Stacked device

Abstract

Provided is a stacked device capable of removing common mode noise. A stacked device (1) comprises: a common mode choke coil (50) provided to a first signal path (R1) and a second signal path (R2); a first capacitive element (61) and a third coil (71) which are provided to a first ground connection path (Rg1); and a second capacitive element (62) and a fourth coil (72) which are provided to a second ground connection path (Rg2). The third coil (71) and the fourth coil (72) form a predetermined choke coil and are configured so that in-phase currents flowing through each coil flow in opposite directions when considering that the currents are [sy1.1]flowing in the clockwise direction or the counterclockwise direction.

Description

Stacked device

[0001] The present disclosure relates to a stacked device.

[0002] Conventionally, a filter for removing common mode noise included in a differential signal is known. Patent Document 1 discloses an electronic component for removing common mode noise.

[0003] Japanese Patent No. 5029726

[0004] In conventional electronic components, common mode noise may not be sufficiently removed.

[0005] The present disclosure provides a stacked device capable of removing common mode noise.

[0006] A stacked device according to one aspect of the present disclosure includes an insulator formed by stacking a plurality of insulating layers, one first terminal and the other first terminal provided on an outer surface of the insulator, one second terminal and the other second terminal provided on the outer surface of the insulator, and a plurality of paths provided inside the insulator. The plurality of paths include a first signal path connecting one first terminal and the other first terminal, a second signal path connecting one second terminal and the other second terminal, a first ground connection path connecting the first signal path and the ground, and a second ground connection path connecting the second signal path and the ground. The first signal path has a first coil, and the second signal path has a second coil that forms a common mode choke coil together with the first coil. The first ground connection path has a first capacitor element and a third coil connected in series. The second ground connection path has a second capacitor element and a fourth coil connected in series. The third coil and the fourth coil form a predetermined choke coil, and are configured such that when the in-phase current flowing through each coil flows in either the clockwise direction or the counterclockwise direction, it flows in the opposite direction.

[0007] According to a stacked device according to one aspect of the present disclosure, common mode noise can be removed.

[0008] This figure shows a communication line equipped with the noise filter of Comparative Example 1. This figure shows a communication line equipped with the stacked device of the present disclosure. This figure shows the equivalent circuit of the stacked device according to Embodiment 1. This is an external view of the stacked device according to Embodiment 1. This figure shows the internal conductor of the stacked device according to Embodiment 1. This is an exploded perspective view of the internal conductor of the stacked device according to Embodiment 1. This figure schematically shows a cross-section of the stacked device according to Embodiment 1. This figure shows the equivalent circuit of the noise filter of Comparative Example 1. This figure shows the internal conductor of the noise filter of Comparative Example 1. This figure shows the common-mode signal pass characteristics of the noise filter of Comparative Example 1 and the stacked device of Embodiment 1. This figure shows the equivalent circuit of the stacked device of Comparative Example 2. This figure shows the internal conductor of the stacked device of Comparative Example 2. This figure shows the differential-mode signal pass characteristics of the stacked device of Comparative Example 2. This figure shows the equivalent circuit of the stacked device according to Embodiment 2. This figure shows the internal conductor of the stacked device according to Embodiment 2. This is an exploded perspective view of the internal conductor of the stacked device according to Embodiment 2.

[0009] (Background to this disclosure) The background to this disclosure will be explained with reference to Figures 1 and 2.

[0010] Figure 1 shows a communication line equipped with the noise filter 101 of Comparative Example 1.

[0011] As shown in Figure 1, the noise filter 101 is installed on the differential signal line connecting the transmitting IC (transmitting integrated circuit) and the receiving IC (receiving integrated circuit). The noise filter 101 is designed to have a high impedance with respect to the frequency of common-mode noise, and when common-mode noise is input, it reflects that common-mode noise. For example, in the communication line shown in Figure 1, the reflected common-mode noise returns to the transmitting IC, is reflected again by the transmitting IC, and returns to the noise filter 101. This repetition causes multiple reflections, which leads to a problem of degraded communication quality.

[0012] Figure 2 shows a communication line on which the stacked device 1 of this disclosure is provided.

[0013] As shown in Figure 2, the stacked device 1 is provided on a differential signal line connecting the transmitting IC and the receiving IC. For example, the transmitting IC is a transceiver IC (transceiver integrated circuit) provided in the master circuit, and the receiving IC is a transceiver IC provided in the slave circuit. The stacked device 1 of this disclosure has a configuration that allows common-mode noise to escape to ground, thereby suppressing the occurrence of multiple reflections and preventing deterioration of communication quality. In other words, the stacked device 1 of this disclosure is configured to sufficiently remove common-mode noise.

[0014] The embodiments described below will be explained with reference to the drawings. Each embodiment described below is a specific example of the present disclosure. The numerical values, shapes, materials, components, arrangement positions of components, connection configurations, steps, and the order of steps shown in the following embodiments are examples and are not intended to limit the present disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0015] Furthermore, in this specification, terms indicating relationships between elements such as parallelism, terms indicating the shape of elements such as rectangular prisms, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0016] Furthermore, each figure is a schematic diagram that has been appropriately emphasized, omitted, or had its proportions adjusted to illustrate this disclosure, and is not necessarily a strict representation; it may differ from the actual shape, positional relationships, and proportions. In all figures, substantially identical components are denoted by the same reference numerals, and redundant explanations may be omitted or simplified.

[0017] Furthermore, in this specification, the terms "top surface" and "bottom surface" in the configuration of a stacked device do not refer to the top surface (vertically upward surface) and bottom surface (vertically downward surface) in absolute spatial perception, but rather are used as terms defined by the relative positional relationship of the components of the stacked device.

[0018] (Embodiment 1) [Equivalent Circuit of a Stacked Device] The equivalent circuit of the stacked device 1 according to Embodiment 1 will be described with reference to Figure 3.

[0019] Figure 3 is a diagram showing the equivalent circuit of the stacked device 1 according to Embodiment 1.

[0020] As shown in Figure 3, the stacked device 1 includes a pair of first terminals, one first terminal P1a and the other first terminal P1b; a pair of second terminals, one second terminal P2a and the other second terminal P2b; and a first ground terminal G1 and a second ground terminal G2.

[0021] Furthermore, the stacked device 1 includes a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, and a second signal path R2 connecting one second terminal P2a and the other second terminal P2b. Furthermore, the stacked device 1 includes a first ground connection path Rg1 connecting the first signal path R1 and the first ground terminal G1, and a second ground connection path Rg2 connecting the second signal path R2 and the second ground terminal G2.

[0022] When the stacked device 1 is mounted on the substrate of an electronic device, the first ground terminal G1 and the second ground terminal G2 are set to ground potential. Differential signals are input from one terminal of each of the pair of first terminals P1a and P1b and the pair of second terminals P2a and P2b, and differential signals are output from the other terminal of each, and differential signals are transmitted to the first signal path R1 and the second signal path R2.

[0023] In this example, when viewed from the center of the stacked device 1, the first terminal P1a and the second terminal P2a are connected to the transmitting IC, and the first terminal P1b and the second terminal P2b are connected to the receiving IC. In other words, the first terminal P1a and the second terminal P2a become input terminals, and the first terminal P1b and the second terminal P2b become output terminals.

[0024] Common mode choke coils 50 are provided in the first signal path R1 and the second signal path R2. The common mode choke coil 50 consists of a first coil 51 provided on the first signal path R1 and a second coil 52 provided on the second signal path R2. The first coil 51 consists of two coils 51a and 51b connected in series, and the second coil 52 consists of two coils 52a and 52b connected in series.

[0025] The first coil 51 and the second coil 52 are configured such that the in-phase current flowing through each coil flows in the same direction, whether clockwise or counterclockwise. For example, when the in-phase current flows clockwise through the first coil 51, it flows clockwise through the second coil 52, and when it flows counterclockwise through the first coil 51, it flows counterclockwise through the second coil 52.

[0026] The first coil 51 and the second coil 52 are arranged to be electromagnetically coupled when a differential signal is transmitted to the first signal path R1 and the second signal path R2. In the stacked device 1, the electromagnetic coupling of the first coil 51 and the second coil 52 makes it possible to remove common-mode noise of a specific frequency contained in the differential signal.

[0027] The first ground connection path Rg1 is a path that connects the first signal path R1 to the ground. One end of the first ground connection path Rg1 is connected to the first node n1 located on the first signal path R1 between one of the first terminals P1a and the first coil 51. The other end of the first ground connection path Rg1 is connected to the first ground terminal G1.

[0028] The second ground connection path Rg2 is a path that connects the second signal path R2 to the ground. One end of the second ground connection path Rg2 is connected to the second node n2, which is located on the second signal path R2 between one of the second terminals P2a and the second coil 52. The other end of the second ground connection path Rg2 is connected to the second ground terminal G2.

[0029] A first capacitive element 61 and a third coil 71 are provided in series on the first ground connection path Rg1. The first capacitive element 61 is connected to the first signal path R1, and the third coil 71 is provided on the path connecting the first capacitive element 61 and the first ground terminal G1.

[0030] A second capacitor 62 and a fourth coil 72 are provided in series on the second ground connection path Rg2. The second capacitor 62 is connected to the second signal path R2, and the fourth coil 72 is provided on the path connecting the second capacitor 62 and the second ground terminal G2.

[0031] The third coil 71 and the fourth coil 72 are configured such that the in-phase current flowing through each coil flows in opposite directions, either clockwise or counterclockwise. For example, when the in-phase current flows clockwise through the third coil 71, it flows counterclockwise through the fourth coil 72, and when it flows counterclockwise through the third coil 71, it flows clockwise through the fourth coil 72.

[0032] The third coil 71 and the fourth coil 72 described above form a predetermined choke coil 70 that suppresses the passage of differential mode signals and allows common mode noise to pass through. In this example, the predetermined choke coil 70 is a differential mode choke coil and is provided in the first ground connection path Rg1 and the second ground connection path Rg2.

[0033] The stacked device 1 of this embodiment includes a common mode choke coil 50, a first capacitive element 61, a third coil 71, a second capacitive element 62, and a fourth coil 72. The common mode choke coil 50 is provided in the first signal path R1 and the second signal path R2. The first capacitive element 61 is connected to the first signal path R1. The third coil 71 is provided in the path connecting the first capacitive element 61 and the first ground terminal G1. The second capacitive element 62 is connected to the second signal path R2. The fourth coil 72 is provided in the path connecting the second capacitive element 62 and the second ground terminal G2, and together with the third coil 71 constitutes a predetermined choke coil 70. The third coil 71 and the fourth coil 72 are configured such that the in-phase current flowing through each coil flows in opposite directions, whether clockwise or counterclockwise.

[0034] With this stacked device 1, common-mode noise at a predetermined frequency can be removed not only by the common-mode choke coil 50 but also by the differential-mode choke coil 70.

[0035] [Structure of the stacked device] The structure of the stacked device 1 according to Embodiment 1 will be described with reference to Figures 4 to 7.

[0036] Figure 4 is an external view of the multilayer device 1. Figure 5 shows the internal conductor of the multilayer device 1. Figure 6 is an exploded perspective view of the internal conductor of the multilayer device 1. Figure 7 is a schematic cross-section of the multilayer device 1.

[0037] In Figure 5, the insulator 10 of the laminated device 1 is shown with a dashed line, and the internal conductor and external terminals of the insulator 10 are shown with solid lines. Figure 7(a) is a schematic diagram of the cross-section along line VIIa-VIIa in Figure 4, and (b) is a schematic diagram of the cross-section along line VIIb-VIIb in Figure 4. In Figure 7, the thickness of the insulating layer and electrodes are shown as thicker than their actual thickness.

[0038] The multilayer device 1 is a surface-mount type common-mode noise filter. The dimensions of the multilayer device 1 are, for example, 3.2 mm in length, 2.5 mm in width, and 2.5 mm in height, or 2.5 mm in length, 2.0 mm in width, and 1.2 mm in height.

[0039] The laminated device 1 shown in Figures 4 to 7 comprises an insulator 10 made of an insulating material, one first terminal P1a and the other first terminal P1b provided on the outer surface of the insulator 10, one second terminal P2a and the other second terminal P2b provided on the outer surface of the insulator 10, a first ground terminal G1 and a second ground terminal G2 provided on the outer surface of the insulator 10, and a plurality of paths provided inside the insulator 10. The insulator 10 may be provided with a mark indicating that it is an input terminal (for example, a mark indicating pin 1).

[0040] The insulator 10 is formed, for example, by laminating a plurality of insulating layers 15 (see Figure 7). The insulating layers 15 are made of a magnetic material or a non-magnetic material such as glass. The insulator 10 may also be formed by laminating a plurality of magnetic insulating layers 15 and non-magnetic insulating layers 15. The non-magnetic insulating layers 15 may be dielectric layers. The thickness of the insulating layers 15 is appropriately selected from, for example, a range of 10 μm to 100 μm. Note that in Figure 7, some parts of the insulating layers 15 are omitted from the illustration. Also, in Figure 7, the interface of the insulating layers 15 is shown with a dashed line, but in reality, the interface of the insulating layers 15 is not visible.

[0041] The insulator 10 has a rectangular parallelepiped shape and includes a bottom surface 18, a top surface 19 facing away from the bottom surface 18, and a plurality of sides connecting the bottom surface 18 and the top surface 19. The plurality of sides include a first side surface 11 and a second side surface 12 facing away from each other, and a third side surface 13 and a fourth side surface 14 facing away from each other. The bottom surface 18 and the top surface 19 are parallel to each other, the first side surface 11 and the second side surface 12 are parallel to each other, and the third side surface 13 and the fourth side surface 14 are parallel to each other. The first side surface 11 and the second side surface 12 are perpendicular to the third side surface 13 and the fourth side surface 14, respectively. The bottom surface 18 and the top surface 19 are perpendicular to the first side surface 11, the second side surface 12, the third side surface 13 and the fourth side surface 14, respectively. The corner portions (ridge portions) where each surface of the insulator 10 intersect may be rounded.

[0042] Here, the direction in which the first side surface 11 and the second side surface 12 are facing away from each other is called the first direction d1, and the direction from the first side surface 11 to the second side surface 12 is the positive direction of the first direction d1 (the positive side of the first direction d1). The direction in which the third side surface 13 and the fourth side surface 14 are facing away from each other is called the second direction d2, and the direction from the third side surface 13 to the fourth side surface 14 is the positive direction of the second direction d2 (the positive side of the second direction d2). The direction in which the bottom surface 18 and the top surface 19 are facing away from each other is called the third direction d3, and the direction from the bottom surface 18 to the top surface 19 is the positive direction of the third direction d3 (the positive side of the third direction d3). In the drawings from Figure 4 onward, the direction in which the arrows for the first direction d1, second direction d2, and third direction d3 point is the positive direction, and the direction opposite to the arrow is the negative direction (the negative side). In this example, the stacking direction of the multiple insulating layers 15 is the same as the third direction d3. Furthermore, the direction along the coil axis of each coil, as mentioned above, is also the same as the third direction d3. In the following, the negative side of the first direction d1 may be referred to as "one side," and the positive side, which is opposite the negative side, may be referred to as "the other side."

[0043] As shown in FIGS. 4 and 5, one of the first terminals P1a and one of the second terminals P2a are provided on a part of the first side surface 11 which is the outer surface of the insulator 10, respectively. The other first terminal P1b and the other second terminal P2b are provided on a part of the second side surface 12 which is the outer surface of the insulator 10, respectively. The first ground terminal G1 is provided on a part of the third side surface 13 which is the outer surface of the insulator 10. The second ground terminal G2 is provided on a part of the fourth side surface 14 which is the outer surface of the insulator 10. In addition, these external terminals may be provided on a part of the bottom surface 18 and the top surface 19, respectively.

[0044] As shown in FIGS. 5 and 6, the plurality of paths provided inside the insulator 10 include a first signal path R1, a second signal path R2, a first ground connection path Rg1, and a second ground connection path Rg2. The first signal path R1, the second signal path R2, the first ground connection path Rg1, and the second ground connection path Rg2 are formed by connection electrodes, routing wirings, land electrodes, via conductors, opposing electrodes, coil wirings, etc.

[0045] One end of the first signal path R1 is connected to one of the first terminals P1a, and the other end of the first signal path R1 is connected to the other first terminal P1b. The first signal path R1 has a first coil 51, and the first coil 51 is composed of two spiral coils 51a and 51b.

[0046] One end of the second signal path R2 is connected to one of the second terminals P2a, and the other end of the second signal path R2 is connected to the other second terminal P2b. The second signal path R2 has a second coil 52 which constitutes a common mode choke coil 50 together with the first coil 51. The second coil 52 is composed of two spiral coils 52a and 52b.

[0047] The common mode choke coil 50 located on the first signal path R1 and the second signal path R2 is composed of a plurality of common mode choke coils 50a, 50b. The plurality of common mode choke coils 50a, 50b are arranged side by side along the stacking direction (third direction d3) in which a plurality of insulating layers 15 are stacked.

[0048] The common mode choke coil 50a is formed by coils 51a and 52a, and the common mode choke coil 50b is formed by coils 51b and 52b. Coils 51a and 52a are each spiral planar coils, and at least a part of each is arranged facing each other in the direction along the coil axis (third direction d3). Coils 51b and 52b are also each spiral planar coils, and at least a part of each is arranged facing each other in the direction along the coil axis (third direction d3).

[0049] The first coil 51 and the second coil 52 are configured such that when viewing the direction in which the in-phase currents flowing through the respective coils flow, either clockwise or counterclockwise, they flow in the same direction. In this example, the first coil 51 and the second coil 52 have the same winding direction when viewed from the direction along the coil axis (third direction d3) of each coil.

[0050] The first ground connection path Rg1 and the second ground connection path Rg2 are provided at predetermined positions outside the region where the plurality of common mode choke coils 50a and 50b face each other in the stacking direction (third direction d3). In this example, the first ground connection path Rg1 and the second ground connection path Rg2 are arranged at positions facing the top surface 19 when viewed from the common mode choke coil 50 (the plus side in the third direction d3 when viewed from the common mode choke coil 50), and are arranged at positions facing the third side surface 13 when viewed from the common mode choke coil 50 (the minus side in the first direction d1 when viewed from the common mode choke coil 50).

[0051] The first ground connection path Rg1 has a first capacitor element 61 connected to the first signal path R1, and a third coil 71 provided in a path connecting the first capacitor element 61 and the first ground terminal G1, and further has a first lead-out line 81 provided in a path connecting the third coil 71 and the first ground terminal G1.

[0052] The second ground connection path Rg2 includes a second capacitive element 62 connected to the second signal path R2, a fourth coil 72 provided in the path connecting the second capacitive element 62 and the second ground terminal G2, and further includes a second lead line 82 provided in the path connecting the fourth coil 72 and the second ground terminal G2.

[0053] The first capacitance element 61 has flat counter electrodes 61p1 and 61p2. The area of ​​each of the counter electrodes 61p1 and 61p2 is the same. Counter electrode 61p1 is connected to a first node n1 on a first signal path R1 located between one first terminal P1a and the first coil 51. Counter electrode 61p2 is positioned to face counter electrode 61p1 via an insulating layer 15. The first capacitance element 61 is formed by the opposing surfaces of counter electrodes 61p1 and 61p2.

[0054] The second capacitance element 62 has flat counter electrodes 62p1 and 62p2. The area of ​​each of the counter electrodes 62p1 and 62p2 is the same. Counter electrode 62p1 is connected to a second node n2 on a second signal path R2 located between one second terminal P2a and the second coil 52. Counter electrode 62p2 is positioned to face counter electrode 62p1 via an insulating layer 15. The second capacitance element 62 is formed by the opposing surfaces of counter electrodes 62p1 and 62p2.

[0055] The first capacitance element 61 and the second capacitance element 62 have the same capacitance. The first capacitance element 61 and the second capacitance element 62 are arranged adjacent to each other in the second direction d2. In the laminated device 1, the counter electrodes 61p1 and 62p1 are formed on the same insulating layer among the plurality of insulating layers 15. The counter electrodes 61p2 and 62p2 are formed on a different insulating layer from the insulating layer on which the counter electrodes 61p1 and 62p1 are formed. In this example, the insulating layer on which the counter electrodes 61p2 and 62p2 are formed is laminated on the insulating layer on which the counter electrodes 61p1 and 62p1 are formed.

[0056] The third coil 71 is spiral-shaped and has one end 71e1 located near the center of the coil, and the other end 71e2 located further from the center than the first end 71e1. The first end 71e1 of the third coil 71 is connected to the first capacitive element 61, and the other end 71e2 of the third coil 71 is electrically connected to the first ground terminal G1. Specifically, the first end 71e1 of the third coil 71 is connected to the counter electrode 61p2, and the other end 71e2 of the third coil 71 is connected to the first ground terminal G1 via an L-shaped first lead line 81. The other end 71e2 of the third coil 71 is also connected to the second ground terminal G2 via an L-shaped second lead line 82. The third coil 71 is formed of one layer, but it may be formed of multiple layers.

[0057] The fourth coil 72 is spiral-shaped and has one end 72e1 located near the center of the coil, and the other end 72e2 located further from the center than the first end 72e1. The first end 72e1 of the fourth coil 72 is connected to the second capacitive element 62, and the other end 72e2 of the fourth coil 72 is electrically connected to the second ground terminal G2. Specifically, the first end 72e1 of the fourth coil 72 is connected to the counter electrode 62p2, and the other end 72e2 of the fourth coil 72 is connected to the second ground terminal G2 via an L-shaped second lead line 82. The other end 72e2 of the fourth coil 72 is also connected to the first ground terminal G1 via an L-shaped first lead line 81. The fourth coil 72 is formed of one layer, but it may be formed of multiple layers.

[0058] The third coil 71 and the fourth coil 72 are formed on the positive side of the third direction d3 compared to the first capacitive element 61 and the second capacitive element 62. The third coil 71 and the fourth coil 72 are each spiral planar coils, and at least a portion of each is arranged facing the direction along the coil axis (third direction d3). In this example, a portion of the third coil 71 is arranged to face a portion of the fourth coil 72 via the insulating layer 15.

[0059] The third coil 71 and the fourth coil 72 are configured such that the in-phase current flowing through each coil flows in opposite directions, whether clockwise or counterclockwise. In this example, the third coil 71 and the fourth coil 72 have opposite winding directions when viewed from the direction along the coil axis of each coil (third direction d3). Specifically, when viewed from the direction of the third direction d3 from negative to positive and the winding direction from the center of the coil outwards, the third coil 71 is left-handed and the fourth coil 72 is right-handed.

[0060] In the stacked device 1 of this embodiment, for example, when common-mode noise is input, a current in phase flows through the first coil 51 and the second coil 52, causing the first coil 51 and the second coil 52 to magnetically couple and remove the common-mode noise. Furthermore, even if the common-mode noise is reflected by the first coil 51 and the second coil 52, the common-mode noise passes through the third coil 71 and the fourth coil 72 and flows to ground, thus reliably removing the common-mode noise. Also, for example, when a differential-mode signal is input, a current in opposite phase flows through the first coil 51 and the second coil 52, causing the first coil 51 and the second coil 52 to couple in a way that cancels out the magnetisms, and the differential-mode signal passes through the first coil 51 and the second coil 52 without being removed. In the case of a differential mode signal, the third coil 71 and the fourth coil 72 are coupled in opposite directions, so they reinforce each other's magnetic field, and the differential mode signal cannot pass through the third coil 71 and the fourth coil 72. This prevents the differential mode signal from flowing into ground.

[0061] As described above, the stacked device 1 includes a common mode choke coil 50, a first capacitive element 61, a third coil 71, a second capacitive element 62, and a fourth coil 72. The common mode choke coil 50 is provided in the first signal path R1 and the second signal path R2. The first capacitive element 61 is connected to the first signal path R1. The third coil 71 is provided in the path connecting the first capacitive element 61 and the first ground terminal G1. The second capacitive element 62 is connected to the second signal path R2. The fourth coil 72 is provided in the path connecting the second capacitive element 62 and the second ground terminal G2, and together with the third coil 71 constitutes a predetermined choke coil 70. The third coil 71 and the fourth coil 72 are configured such that the in-phase current flowing through each coil flows in opposite directions, whether clockwise or counterclockwise.

[0062] With this stacked device 1, common-mode noise at a predetermined frequency can be removed not only by the common-mode choke coil 50 but also by the differential-mode choke coil 70. This makes it possible to sufficiently remove common-mode noise.

[0063] The stacked device 1 of Embodiment 1 is equipped with a continuity check line 85 as one of several paths. The continuity check line 85 is a line for checking the continuity between the first ground terminal G1 and the internal conductor, or between the second ground terminal G2 and the internal conductor. In this example, the continuity check line 85 is composed of a first lead line 81 and a second lead line 82. The first lead line 81 and the second lead line 82 are connected at a connection point 83, electrically connecting the first ground terminal G1 and the second ground terminal G2. In this example, the other end 71e2 of the third coil 71 is connected to the first ground terminal G1 via the connection point 83 and the first lead line 81, and the other end 72e2 of the fourth coil 72 is connected to the second ground terminal G2 via the connection point 83 and the second lead line 82.

[0064] For example, a continuity check can be performed by touching the measuring probe to the first ground terminal G1 and the second ground terminal G2, respectively. If the continuity check is OK, it can be determined that the first ground terminal G1 and the internal conductor are electrically connected, and the second ground terminal G2 and the internal conductor are electrically connected. On the other hand, if the continuity check is NG, it can be inferred that the first ground terminal G1 and the internal conductor are not electrically connected, or the second ground terminal G2 and the internal conductor are not electrically connected, or both.

[0065] [Effects, etc.] The effects of the stacked device 1 having the above configuration will be explained in comparison with the comparative example.

[0066] First, the configuration of the noise filter 101 in Comparative Example 1 will be described.

[0067] Figure 8 shows the equivalent circuit of the noise filter 101 of Comparative Example 1. Figure 9 shows the internal conductor of the noise filter 101 of Comparative Example 1. Note that in Figure 9, the insulator 10 and external terminals are omitted from the illustration, and only the internal conductor is shown.

[0068] The noise filter 101 of Comparative Example 1 is the same as the stacked device 1 of Embodiment 1 in that it includes a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, and a second signal path R2 connecting one second terminal P2a and the other second terminal P2b. On the other hand, the noise filter 101 of Comparative Example 1 differs from the stacked device 1 of Embodiment 1 in that it does not include a first ground terminal G1 and a second ground terminal G2, nor a first ground connection path Rg1 and a second ground connection path Rg2.

[0069] Figure 10 shows the common-mode signal pass characteristics of the noise filter 101 of Comparative Example 1 and the stacked device 1 of Embodiment 1.

[0070] This figure shows the S-parameters (Scc21), which are the characteristics when a common-mode high-frequency signal is input to one first terminal P1a and one second terminal P2a. Note that the first ground terminal G1 and the second ground terminal G2 of the multilayer device 1 are set to ground potential. In this example, it is determined that the common-mode signal is sufficiently attenuated when the attenuation is greater than 20 dB.

[0071] As shown in Figure 10, the noise filter 101 of Comparative Example 1 can block the passage of common-mode signals with a bandwidth of 0.93 GHz, which is in the frequency range of 0.12 GHz to 1.05 GHz.

[0072] In the multilayer device 1 of this embodiment, as shown in Figure 10, another attenuation band is formed at a higher frequency than the attenuation band formed by the common mode choke coil 50. Therefore, the multilayer device 1 can block the passage of common mode signals with a bandwidth of 1.95 GHz, which is in the frequency range of 0.15 GHz to 2.10 GHz. In this way, the multilayer device 1 of this embodiment can widen the stopband that blocks the passage of common mode signals compared to the noise filter 101 of Comparative Example 1.

[0073] Next, the configuration of the stacked device 102 of Comparative Example 2 will be described.

[0074] Figure 11 shows the equivalent circuit of the multilayer device 102 of Comparative Example 2. Figure 12 shows the internal conductor of the multilayer device 102 of Comparative Example 2. Note that in Figure 12, the insulator 10 and external terminals are omitted from the illustration, and only the internal conductor is shown.

[0075] The stacked device 102 of Comparative Example 2 is the same as the stacked device 1 of Embodiment 1 in that it includes a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, and a second signal path R2 connecting one second terminal P2a and the other second terminal P2b. On the other hand, the stacked device 102 of Comparative Example 2 includes a first ground connection path Rg101 and a second ground connection path Rg102, but differs from the stacked device 1 of Embodiment 1 in that a capacitive element is not provided in the first ground connection path Rg101 and a capacitive element is not provided in the second ground connection path Rg102.

[0076] Figure 13 shows the pass characteristics of the differential mode signal of the stacked device 102 of Comparative Example 2.

[0077] This figure shows the S-parameters (Sdd21), which are the characteristics when an out-of-phase high-frequency signal is input to one of the first terminals P1a and the other of the second terminals P2a.

[0078] As shown in Figure 13, the stacked device 102 of Comparative Example 2 exhibits a large insertion loss of differential mode signals in the frequency band below 0.1 GHz. This is thought to be because, in the stacked device 102 of Comparative Example 2, signals in the low frequency band, i.e., signals with properties similar to DC currents, flow into the ground via the first ground connection path Rg101 and the second ground connection path Rg102.

[0079] In contrast, in the multilayer device 1 of this embodiment, a capacitive element that blocks the passage of DC current, in other words, a capacitor having a pair of counter electrodes, is provided in each of the first ground connection path Rg1 and the second ground connection path Rg2, thereby suppressing the inflow of signals with frequencies around 0.1 GHz into the ground. Therefore, in the multilayer device 1 of this embodiment, even with differential mode signals in the low frequency band, the insertion loss of the differential mode signal can be suppressed, making it possible to use it in a wide frequency band.

[0080] (Embodiment 2) [Equivalent Circuit of a Multilayer Device] The equivalent circuit of the multilayer device 1A according to Embodiment 2 will be described with reference to Figure 14. In Embodiment 2, the winding directions of the third coil 71 and the fourth coil 72 are the same, and the connection of one end 72e1 and the other end 72e2 of the fourth coil 72 to the second capacitance element 62 and the second ground terminal G2 is reversed compared to Embodiment 1.

[0081] Figure 14 shows the equivalent circuit of the stacked device 1A according to Embodiment 2.

[0082] As shown in Figure 14, the stacked device 1A includes a pair of first terminals, one first terminal P1a and the other first terminal P1b; a pair of second terminals, one second terminal P2a and the other second terminal P2b; a first ground terminal G1 and a second ground terminal G2. The stacked device 1A also includes a first signal path R1 connecting one first terminal P1a and the other first terminal P1b; a second signal path R2 connecting one second terminal P2a and the other second terminal P2b; a first ground connection path Rg1 connecting the first signal path R1 and the first ground terminal G1; and a second ground connection path Rg2 connecting the second signal path R2 and the second ground terminal G2.

[0083] The configurations of the first signal path R1 and the second signal path R2 are the same as in Embodiment 1. The configurations of the first coil 51 and the second coil 52 are also the same as in Embodiment 1.

[0084] In Embodiment 2, the configurations of the first ground connection path Rg1 and the second ground connection path Rg2 are the same as in Embodiment 1. In Embodiment 2, the configurations of the first capacitance element 61 and the second capacitance element 62 are the same as in Embodiment 1, while the configurations of the third coil 71, the first lead line 81, the fourth coil 72, and the second lead line 82 differ from those in Embodiment 1.

[0085] In the stacked device 1A of Embodiment 2, the winding directions of the third coil 71 and the fourth coil 72 are the same, one end 72e1 of the fourth coil 72 is electrically connected to the second ground terminal G2, and the other end 72e2 is connected to the second capacitive element 62. In this respect, Embodiment 2 differs from Embodiment 1, but in terms of current flow, Embodiment 2 has the same configuration as Embodiment 1.

[0086] In other words, in the stacked device 1A of Embodiment 2, the third coil 71 and the fourth coil 72 are configured such that the in-phase current flowing through each coil flows in opposite directions, whether clockwise or counterclockwise. For example, when the in-phase current flowing through the third coil 71 flows clockwise, it flows counterclockwise through the fourth coil 72, and when the current flowing through the third coil 71 flows counterclockwise, it flows clockwise through the fourth coil 72.

[0087] The third coil 71 and the fourth coil 72 described above form a predetermined choke coil 70A that suppresses the passage of differential mode signals and allows common mode noise to pass through. In this example, the predetermined choke coil 70A functions substantially as a differential mode choke coil and is provided in the first ground connection path Rg1 and the second ground connection path Rg2.

[0088] In the stacked device 1A of Embodiment 2, common-mode noise at a predetermined frequency can be removed not only by the common-mode choke coil 50 but also by the differential-mode choke coil 70A. This makes it possible to sufficiently remove common-mode noise.

[0089] [Structure of the stacked device] The structure of the stacked device 1A according to Embodiment 2 will be described with reference to Figures 15 and 16.

[0090] Figure 15 shows the internal conductor of the multilayer device 1A. Figure 16 is an exploded perspective view of the internal conductor of the multilayer device 1A. In Figure 15, the insulator 10 of the multilayer device 1A is shown with a dashed line, and the internal conductor and external terminals of the insulator 10 are shown with solid lines.

[0091] As described above, the stacked device 1A includes one first terminal P1a and the other first terminal P1b, one second terminal P2a and the other second terminal P2b, a first ground terminal G1 and a second ground terminal G2. The stacked device 1A also includes a first signal path R1, a second signal path R2, a first ground connection path Rg1, and a second ground connection path Rg2.

[0092] The configurations of the first signal path R1 and the second signal path R2 are the same as in Embodiment 1. The configurations of the first coil 51 and the second coil 52 are also the same as in Embodiment 1.

[0093] The first ground connection path Rg1 includes a first capacitance element 61, a third coil 71, and a first lead line 81. The second ground connection path Rg2 includes a second capacitance element 62, a fourth coil 72, and a second lead line 82. The configuration of the first capacitance element 61 and the second capacitance element 62 is the same as in Embodiment 1.

[0094] The third coil 71 is spiral-shaped and has one end 71e1 located near the center of the coil, and the other end 71e2 located further from the center of the coil than the first end 71e1. The first end 71e1 of the third coil 71 is connected to the first capacitive element 61, and the other end 71e2 of the third coil 71 is electrically connected to the first ground terminal G1. Specifically, the other end 71e2 of the third coil 71 is connected to the first ground terminal G1 via an L-shaped first lead line 81.

[0095] The fourth coil 72 is spiral-shaped and has one end 72e1 located near the center of the coil, and the other end 72e2 located further from the center of the coil than the first end 72e1. The first end 72e1 of the fourth coil 72 is electrically connected to the second ground terminal G2, and the other end 72e2 of the fourth coil 72 is connected to the second capacitive element 62. Specifically, the first end 72e1 of the fourth coil 72 is connected to the second ground terminal G2 via the second lead line 82.

[0096] The third coil 71 and the fourth coil 72 are formed on the positive side of the third direction d3 compared to the first capacitive element 61 and the second capacitive element 62. The third coil 71 and the fourth coil 72 are each spiral planar coils, and at least a portion of each is arranged facing the direction along the coil axis (third direction d3). In this example, a portion of the third coil 71 is arranged to face a portion of the fourth coil 72 via the insulating layer 15.

[0097] The third coil 71 and the fourth coil 72 are configured such that the in-phase currents flowing through them flow in opposite directions, either clockwise or counterclockwise. In this example, the third coil 71 and the fourth coil 72 have the same winding direction when viewed from the direction along the coil axis of each coil (third direction d3). Specifically, when viewed from the negative to positive direction of the third direction d3 and the winding direction outward from the center of the coil, the third coil 71 is left-handed and the fourth coil 72 is also left-handed.

[0098] The stacked device 1A of this embodiment also includes a common mode choke coil 50, a first capacitive element 61, a third coil 71, a second capacitive element 62, and a fourth coil 72. The common mode choke coil 50 is provided in the first signal path R1 and the second signal path R2. The first capacitive element 61 is connected to the first signal path R1. The third coil 71 is provided in the path connecting the first capacitive element 61 and the first ground terminal G1. The second capacitive element 62 is connected to the second signal path R2. The fourth coil 72 is provided in the path connecting the second capacitive element 62 and the second ground terminal G2, and together with the third coil 71 constitutes a predetermined choke coil 70A. The third coil 71 and the fourth coil 72 are configured so that the in-phase current flowing through each coil flows in opposite directions, whether clockwise or counterclockwise.

[0099] With this multilayer device 1A, common-mode noise at a predetermined frequency can be removed not only by the common-mode choke coil 50 but also by the differential-mode choke coil 70A. This makes it possible to sufficiently remove common-mode noise.

[0100] (Summary) Examples of stacked devices 1 or 1A according to one aspect of this disclosure are given below.

[0101] The laminated device 1 (or 1A) of Example 1 comprises an insulator 10 formed by laminating a plurality of insulating layers 15, one first terminal P1a and the other first terminal P1b provided on the outer surface of the insulator 10, one second terminal P2a and the other second terminal P2b provided on the outer surface of the insulator 10, and a plurality of paths provided inside the insulator 10. The plurality of paths include a first signal path R1 connecting one first terminal P1a and the other first terminal P1b, a second signal path R2 connecting one second terminal P2a and the other second terminal P2b, a first ground connection path Rg1 connecting the first signal path R1 and ground, and a second ground connection path Rg2 connecting the second signal path R2 and ground. The first signal path R1 has a first coil 51, and the second signal path R2 has a second coil 52 that together with the first coil 51 constitute a common mode choke coil 50. The first ground connection path Rg1 has a first capacitance element 61 and a third coil 71 connected in series. The second ground connection path Rg2 has a second capacitance element 62 and a fourth coil 72 connected in series. The third coil 71 and the fourth coil 72 form a predetermined choke coil 70 (or 70A), and are configured such that the in-phase currents flowing through each coil flow in opposite directions, whether clockwise or counterclockwise.

[0102] With this multilayer device 1 or 1A, common-mode noise at a predetermined frequency can be removed not only by the common-mode choke coil 50 but also by the differential-mode choke coil 70 (or 70A). This makes it possible to sufficiently remove common-mode noise. For example, the multilayer device 1 or 1A can widen the stopband that blocks the passage of common-mode signals compared to the noise filter 101 of Comparative Example 1. Furthermore, the multilayer device 1 or 1A can suppress the increase in insertion loss of differential-mode signals in the low-frequency band compared to the multilayer device 102 of Comparative Example 2, and can be used in a wide frequency band.

[0103] The laminated device 1 in Example 2 is the laminated device described in Example 1, wherein the third coil 71 and the fourth coil 72 may have opposite winding directions when viewed from the direction along the coil axis of each coil.

[0104] This stacked device 1 can effectively remove common-mode noise.

[0105] The laminated device 1 in Example 3 is the laminated device described in Example 2, wherein the outer surface of the insulator 10 is provided with a first ground terminal G1 and a second ground terminal G2, which serve as the ground. The first capacitive element 61 is connected to the first signal path R1. The second capacitive element 62 is connected to the second signal path R2. The third coil 71 and the fourth coil 72 are each spiral coils, with one end located near the center of the coil and the other end located further from the center of the coil than the other end. One end 71e1 of the third coil 71 is connected to the first capacitive element 61, and the other end 71e2 of the third coil 71 may be electrically connected to the first ground terminal G1. One end 72e1 of the fourth coil 72 is connected to the second capacitive element 62, and the other end 72e2 of the fourth coil 72 may be electrically connected to the second ground terminal G2.

[0106] This configuration provides a stacked device 1 that can sufficiently remove common-mode noise.

[0107] The stacked device 1A in Example 4 is the stacked device described in Example 1, wherein the third coil 71 and the fourth coil 72 may have the same winding direction when viewed from the direction along the coil axis of each coil.

[0108] This stacked device 1A can effectively remove common-mode noise.

[0109] The laminated device 1A in Example 5 is the laminated device described in Example 4, wherein the outer surface of the insulator 10 is provided with a first ground terminal G1 and a second ground terminal G2, which serve as the ground. The first capacitive element 61 is connected to the first signal path R1. The second capacitive element 62 is connected to the second signal path R2. The third coil 71 and the fourth coil 72 are each spiral coils, with one end located at the center of the coil and the other end located further from the center of the coil than the other end. One end 71e1 of the third coil 71 is connected to the first capacitive element 61, and the other end 71e2 of the third coil 71 may be electrically connected to the first ground terminal G1. One end 72e1 of the fourth coil 72 is electrically connected to the second ground terminal G2, and the other end 72e2 of the fourth coil 72 may be connected to the second capacitive element 62.

[0110] This configuration provides a stacked device 1A that can sufficiently remove common-mode noise.

[0111] The stacked devices 1 and 1A in Example 6 are stacked devices described in any of Examples 2 to 5, wherein the third coil 71 and the fourth coil 72 are each spiral-shaped planar coils, and at least a portion of each may be arranged facing each other in a direction along the coil axis.

[0112] This configuration provides stacked devices 1 and 1A that can sufficiently remove common-mode noise.

[0113] The laminated devices 1 and 1A of Example 7 are laminated devices described in any of Examples 2 to 6, wherein the common mode choke coil 50 is composed of a plurality of common mode choke coils 50a and 50b, and the plurality of common mode choke coils 50a and 50b may be arranged along the lamination direction in which the plurality of insulating layers 15 are laminated.

[0114] With this configuration, any desired inductor component can be formed by multiple common-mode choke coils 50a and 50b. This makes it possible to change the stopband of the common-mode signal according to the requirements of the multilayer devices 1 and 1A.

[0115] The stacked device 1 in Example 8 is the stacked device described in Example 3, and the multiple paths may further include a continuity check line 85 that electrically connects the first ground terminal G1 and the second ground terminal G2.

[0116] By providing the continuity check line 85 in the stacked device 1 in this way, it is possible to easily confirm whether the first ground terminal G1 and the first ground connection path Rg1 are electrically connected, and whether the second ground terminal G2 and the second ground connection path Rg2 are electrically connected.

[0117] The laminated devices 1 and 1A of Example 9 are the laminated devices described in Example 3 or 5, wherein the insulator 10 is rectangular parallelepiped and has a bottom surface 18, a top surface 19, and four sides. The four sides include a first side surface 11 and a second side surface 12 facing away from each other, and a third side surface 13 and a fourth side surface 14 facing away from each other. One first terminal P1a and one second terminal P2a may be formed on the first side surface 11, the other first terminal P1b and the other second terminal P2b may be formed on the second side surface 12, a first ground terminal G1 may be formed on the third side surface 13, and a second ground terminal G2 may be formed on the fourth side surface 14.

[0118] This configuration makes it possible to provide rectangular parallelepiped surface-mount stacked devices 1 and 1A.

[0119] (Other Forms, etc.) Although the embodiments and variations of the stacked devices described above have been explained, the disclosure is not limited to the embodiments and variations described above. Without departing from the spirit of the disclosure, various modifications that a person skilled in the art could conceive of are applied to the embodiments and variations, as well as other forms constructed by combining some of the components of the embodiments and variations with other components, are also included in the scope of the disclosure.

[0120] The above example shows one end of the first ground connection path Rg1 connected to the first node n1 and one end of the second ground connection path Rg2 connected to the second node n2, but it is not limited to this. For example, one end of the first ground connection path Rg1 may be connected to the first signal path R1 between the first coil 51 and the other first terminal P1b, and one end of the second ground connection path Rg2 may be connected to the second signal path R2 between the second coil 52 and the other second terminal P2b.

[0121] For example, the continuity check line 85 shown in Embodiment 1 is preferably positioned so as not to overlap with the common mode choke coil 50 when viewed from the third direction d3, in order to minimize its influence on the electromagnetic coupling of the common mode choke coil 50. For example, the continuity check line 85 may be provided outside the common mode choke coil 50 when viewed from the third direction d3.

[0122] In the above embodiment, the third coil 71 and the fourth coil 72 are shown as spiral-shaped coils, but the embodiment is not limited to this. For example, the third coil and the fourth coil may be meander-shaped coils.

[0123] In the above embodiment, an example was shown in which the common mode choke coil 50 is composed of two sets of common mode choke coils 50a and 50b, but it is not limited to this. For example, the common mode choke coil may be composed of one set of common mode choke coils, or it may be composed of three or more sets of common mode choke coils.

[0124] In the above embodiment, an example was shown in which the ground is configured with two ground terminals (first ground terminal G1 and second ground terminal G2), but it is not limited to this. For example, the ground may be configured with one ground terminal. In that case, it is not necessary to provide a mark on the insulator to distinguish between input and output.

[0125] In the above embodiment 1, an example was shown in which the capacitive element is connected to the signal path and the coil is connected to the ground terminal in the ground connection path. However, the embodiment is not limited to this, and the coil may be connected to the signal path and the capacitive element may be connected to the ground terminal. Specifically, the first capacitive element 61 may be connected to the first ground terminal G1, and the second capacitive element 62 may be connected to the second ground terminal G2. The third coil 71 and the fourth coil 72 are each spiral coils and may have one end located near the center of the coil and the other end located further from the center of the coil than the other end. One end of the third coil 71 may be connected to the first signal path R1, and the other end of the third coil 71 may be connected to the first capacitive element 61. One end of the fourth coil 72 may be connected to the second signal path R2, and the other end of the fourth coil 72 may be connected to the second capacitive element 62.

[0126] In the above embodiment 2, an example was shown in which the capacitive element is connected to the signal path and the coil is connected to the ground terminal in the ground connection path. However, the invention is not limited to this, and the coil may be connected to the signal path and the capacitive element may be connected to the ground terminal. Specifically, the first capacitive element 61 may be connected to the first ground terminal G1, and the second capacitive element 62 may be connected to the second ground terminal G2. The third coil 71 and the fourth coil 72 are each spiral coils and may have one end located near the center of the coil and the other end located further from the center of the coil than the other end. One end of the third coil 71 may be connected to the first signal path R1, and the other end of the third coil 71 may be connected to the first capacitive element 61. One end of the fourth coil 72 may be connected to the second capacitive element 62, and the other end of the fourth coil 72 may be connected to the second signal path R2.

[0127] In the above embodiment, an example of using a stacked device in a differential communication line was described, but it is not limited to that, and the stacked device of this embodiment can also be applied to lines consisting of a power supply and ground line pair.

[0128] The stacked device relating to this disclosure is useful as a common-mode noise filter that suppresses the passage of common-mode signals.

[0129] 1, 1A Multilayer device 10 Insulator 11 First side 12 Second side 13 Third side 14 Fourth side 15 Insulating layer 18 Bottom surface 19 Top surface 50, 50a, 50b Common mode choke coil 51 First coil 51a, 51b Coil 52 Second coil 52a, 52b Coil 61 First capacitance element 61p1, 61p2 Counter electrode 62 Second capacitance element 62p1, 62p2 Counter electrode 70, 70A Predetermined choke coil (differential mode choke coil) 71 Third coil 71e1 One end 71e2 Other end 72 Fourth coil 72e1 One end 72e2 Other end 81 First lead line 82 Second lead line 83 Connection point 85 Continuity check line P1a, P1b Terminal 1 P2a, P2b Terminal 2 G1 First ground terminal G2 Second ground terminals Rg1, Rg101 First ground connection path Rg2, Rg102 Second ground connection path d1 First direction d2 Second direction d3 Third direction n1 First node n2 Second node R1 First signal path R2 Second signal path

Claims

1. An insulator formed by laminating multiple insulating layers; one first terminal and the other first terminal provided on the outer surface of the insulator; one second terminal and the other second terminal provided on the outer surface of the insulator; and a plurality of paths provided inside the insulator, wherein the plurality of paths include: a first signal path connecting the one first terminal and the other first terminal; a second signal path connecting the one second terminal and the other second terminal; a first ground connection path connecting the first signal path and ground; and a second ground connection path connecting the second signal path and ground, wherein the first signal path includes a first coil; the second signal path includes a second coil that, together with the first coil, constitutes a common mode choke coil; the first ground connection path includes a first capacitance element and a third coil connected in series; and the second ground connection path includes a second capacitance element and a fourth coil connected in series. The third coil and the fourth coil form a predetermined choke coil, and the laminated device is configured such that the in-phase currents flowing through each coil flow in opposite directions, when considering whether they flow clockwise or counterclockwise.

2. The laminated device according to claim 1, wherein the third coil and the fourth coil have opposite winding directions when viewed from the direction along the coil axis of each coil.

3. The laminated device according to claim 2, wherein the outer surface of the insulator is provided with a first ground terminal and a second ground terminal which serve as the ground, the first capacitive element is connected to the first signal path, the second capacitive element is connected to the second signal path, the third coil and the fourth coil are each spiral coils, having one end located near the center of the coil and the other end located further from the center of the coil than the one end, the one end of the third coil is connected to the first capacitive element, the other end of the third coil is electrically connected to the first ground terminal, the one end of the fourth coil is connected to the second capacitive element, and the other end of the fourth coil is electrically connected to the second ground terminal.

4. The laminated device according to claim 1, wherein the third coil and the fourth coil have the same winding direction when viewed from a direction along the coil axis of each coil.

5. The stacked device according to claim 4, wherein the outer surface of the insulator is provided with a first ground terminal and a second ground terminal which serve as the ground, the first capacitive element is connected to the first signal path, the second capacitive element is connected to the second signal path, the third coil and the fourth coil are each spiral coils, having one end located near the center of the coil and the other end located further from the center of the coil than the one end, the one end of the third coil is connected to the first capacitive element, the other end of the third coil is electrically connected to the first ground terminal, the one end of the fourth coil is electrically connected to the second ground terminal, and the other end of the fourth coil is connected to the second capacitive element.

6. The laminated device according to any one of claims 2 to 5, wherein the third coil and the fourth coil are each spiral-shaped planar coils, and at least a portion of each is arranged facing each other in a direction along the coil axis.

7. The laminated device according to any one of claims 1 to 5, wherein the common mode choke coil is composed of a plurality of common mode choke coils, and the plurality of common mode choke coils are arranged along the lamination direction in which the plurality of insulating layers are laminated.

8. The laminated device according to claim 3, wherein the plurality of paths further have a continuity check line that electrically connects the first ground terminal and the second ground terminal.

9. The laminated device according to claim 3 or 5, wherein the insulator is rectangular parallelepiped and has a bottom surface, a top surface and four sides, the four sides having a first side and a second side facing each other, and a third side and a fourth side facing each other, one first terminal and one second terminal formed on the first side, the other first terminal and the other second terminal formed on the second side, the first ground terminal formed on the third side, and the second ground terminal formed on the fourth side.

Images