Feedforward equalizer and feedforward transmitter capable of removing reflected wave of channel

Abstract

This feedforward equalizer comprises: a signal delay unit for delaying a data signal to be applied to a memory unit including a plurality of dual in-line memory modules (DIMMs) and at least one reflected wave removal signal; and a control unit for controlling the operation of the signal delay unit. After the data signal is applied to the memory unit, the control unit controls the signal delay unit to apply the at least one reflected wave removal signal for removing a reflected wave according to the application of the data signal to the memory unit.

Description

Feedforward equalizer and feedforward transmitter capable of eliminating channel reflections

[0001] The present invention relates to a feedforward equalizer and a feedforward transmitter capable of eliminating reflected waves in a channel, and more specifically, to a feedforward equalizer and a feedforward transmitter capable of eliminating reflected waves generated when communicating using a Dual In-line Memory Module (DIMM) in a channel environment with high reflectivity.

[0002] Conventional reflection cancellation technology has the following problems with existing memory interfaces. It is difficult to be compatible with memory interface structures using the existing Pulse-amplitude modulation (PAM) signal method, and when using a Decision Feedback Equalizer (DFE) to cancel reflections, it cannot effectively cancel reflections occurring within a Unit Interval (UI), and design complexity increases because a large number of taps must be used. Therefore, a reflection cancellation technology at the transmitter end capable of solving these problems is being researched.

[0003] The present invention aims to provide a feedforward equalizer and a feedforward transmitter capable of reducing signal distortion and increasing reliability during signal transmission by eliminating reflected waves generated when communicating in a channel environment with high reflectivity.

[0004] The present invention aims to provide a feedforward equalizer and a feedforward transmitter compatible with existing memory using a pulse amplitude modulation (PAM)-based signal method by adding only a partial circuit for removing reflected waves in a time delay circuit, a logic circuit for removing reflected waves, and an output driver.

[0005] The present invention aims to provide a feedforward equalizer and a feedforward transmitter capable of increasing the eye margin by eliminating reflected waves within a unit interval (UI).

[0006] The present invention aims to provide a feedforward equalizer and a feedforward transmitter that can reduce the occupied area and increase power efficiency by having a relatively simple structure.

[0007] A feedforward equalizer according to one embodiment of the present invention includes: a signal delay unit that delays a data signal applied to a memory unit comprising a plurality of dual in-line memory modules (DIMM) and at least one reflected wave removal signal; and a control unit that controls the operation of the signal delay unit, wherein the control unit controls the signal delay unit to apply the at least one reflected wave removal signal to the memory unit for removing reflected waves resulting from the application of the data signal after the data signal is applied to the memory unit.

[0008] In some embodiments, the signal delay unit includes a DFF delay unit comprising a D flip-flop (DFF); and a voltage-controlled delay line (VCDL) delay unit comprising at least one P-type metal-oxide-semiconductor (PMOS) transistor and at least one N-type metal-oxide-semiconductor (NMOS) transistor, wherein the DFF delay unit delays the reflected wave removal signal by an integer multiple of a first delay time unit compared to the data signal, and the VCDL delay unit delays the reflected wave removal signal by an integer multiple of a second delay time unit compared to the data signal, and the first delay time unit may be greater than the second delay time unit.

[0009] In some embodiments, the first delay time unit is equal to the unit interval (UI) of the data signal, and the second delay time unit may be smaller than the unit interval of the data signal.

[0010] In some embodiments, the reflected wave removal signal may include a first reflected wave removal signal having an absolute value smaller than the size of the data signal; and a second reflected wave removal signal applied to the memory unit after the first reflected wave removal signal is applied to the memory unit, and having an absolute value smaller than the size of the first reflected wave removal signal.

[0011] In some embodiments, one of the data signal and the first reflected wave removal signal may have a positive value, and the other of the data signal and the first reflected wave removal signal may have a negative value, and one of the first reflected wave removal signal and the second reflected wave removal signal may have a positive value, and the other of the first reflected wave removal signal and the second reflected wave removal signal may have a negative value.

[0012] In some embodiments, the absolute value of the magnitude of the at least one reflected wave removal signal decreases over time, the at least one reflected wave removal signal alternates between positive and negative values, and the time interval between the at least one reflected wave removal signals may be the same.

[0013] In some embodiments, the memory unit comprises: a memory module unit comprising at least one Dynamic Random Access Memory (DRAM) chip and a first DIMM having one end connected to an input channel through a first channel, and a second DIMM having at least one DRAM chip and one end connected to the input channel through a second channel; and a switch unit comprising a first switch unit connecting the first DIMM and the first channel, and a second switch unit connecting the second DIMM and the second channel, wherein either of the first switch unit and the second switch unit may be set to an open state, and the other of the first switch unit and the second switch unit may be set to a connected state.

[0014] In some embodiments, the reflected wave removal signal can remove reflected waves transmitted to the first DIMM or the second DIMM connected to the other of the first switch unit and the second switch unit having the connection state due to an impedance imbalance between the input channel, the first channel, and the second channel resulting from either the first switch unit and the second switch unit being set to the open state.

[0015] In some embodiments, the magnitude of the at least one reflected wave removal signal can be calculated based on the characteristic impedances of the input channel, the first channel, and the second channel.

[0016] A feedforward transmitter according to one embodiment of the present invention includes the feedforward equalizer.

[0017] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention can reduce signal distortion and increase reliability during signal transmission by eliminating reflected waves generated when communicating in a high-channel environment.

[0018] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention are compatible with existing memory using a pulse amplitude modulation (PAM)-based signal method by adding only a partial circuit for removing reflected waves in a time delay circuit, a logic circuit for removing reflected waves, and an output driver.

[0019] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention can increase the eye margin by removing reflected waves within a unit interval (UI).

[0020] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention can reduce the area occupied and increase power efficiency by having a relatively simple structure.

[0021] FIG. 1 is a block diagram schematically illustrating the structure of a feedforward transmitter and a memory unit of a signal processing device according to one embodiment of the present invention.

[0022] FIG. 2 is a diagram schematically illustrating a signal processing device according to one embodiment of the present invention.

[0023] FIG. 3 is a circuit diagram schematically illustrating a D flip-flop (DFF, D Flip-Flop) delay section of a signal processing device according to one embodiment of the present invention.

[0024] FIG. 4 is a circuit diagram schematically illustrating a voltage-controlled delay line (VCDL) delay section of a signal processing device according to one embodiment of the present invention.

[0025] FIG. 5 is a perspective view schematically illustrating a signal processing device according to one embodiment of the present invention.

[0026] FIG. 6 is a circuit diagram schematically illustrating the structure of a signal processing device according to one embodiment of the present invention.

[0027] FIGS. 7a to 7c are circuit diagrams for explaining reflected waves according to data signal transmission of a signal processing device according to an embodiment of the present invention.

[0028] FIG. 8 is a graph showing a reflected wave according to the transmission of a data signal by a signal processing device according to one embodiment of the present invention.

[0029] FIG. 9 is a diagram illustrating the transmission of a data signal and a reflected wave removal signal of a signal processing device according to an embodiment of the invention.

[0030] FIG. 10 is a non-return to zero (NRZ) eye diagram comparing data eyes at the receiving end of a signal processing device according to the prior art and a signal processing device according to an embodiment of the present invention.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0032] It should be noted that the drawings are schematic and not drawn to scale. The relative dimensions and proportions of parts in the drawings are exaggerated or reduced in size for clarity and convenience in the drawings, and any dimensions are merely illustrative and not limiting. Additionally, the same reference numerals are used to denote similar features for the same structure, element, or part appearing in two or more drawings.

[0033] The embodiments of the present invention specifically illustrate ideal embodiments of the present invention. As a result, various variations of the illustration are expected. Accordingly, the embodiments are not limited to the specific form of the illustrated area and include, for example, variations in form resulting from manufacturing.

[0034] Furthermore, all technical and scientific terms used in this specification, unless otherwise defined, have the meaning generally understood by those skilled in the art to which the present invention pertains. All terms used in this specification are selected for the purpose of further clarifying the present invention and are not selected to limit the scope of rights according to the present invention.

[0035] Additionally, expressions used in this specification, such as 'comprising,' 'having,' 'having,' etc., should be understood as open-ended terms implying the possibility of including other embodiments, unless otherwise stated in the phrase or sentence containing such expressions.

[0036] Additionally, singular expressions described in this specification may include the meaning of the plural form unless otherwise stated, and this applies likewise to singular expressions described in the claims.

[0037] Additionally, while terms such as first, second, third, etc. may be used in this specification to describe various components, these components are not limited by said terms. These terms are used for the purpose of distinguishing one component from other components. For example, without departing from the scope of the present invention, the first component may be named the second or third component, and similarly, the second or third component may be named alternately.

[0038] As used in the present invention, the term “part” refers to software or hardware components such as FPGAs (field-programmable gate arrays) and ASICs (application-specific integrated circuits). However, “part” is not limited to hardware and software. “Part” may be configured to reside in an addressable storage medium or configured to run on one or more processors. Accordingly, by example, “part” includes components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. Components and functions provided within “part” may be combined into a smaller number of components and “parts” or separated into additional components and “parts.”

[0039] Hereinafter, a signal processing device (1) according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

[0040] FIG. 1 is a block diagram schematically illustrating the structure of a signal processing device according to one embodiment of the present invention. FIG. 2 is a diagram schematically illustrating a signal processing device according to one embodiment of the present invention.

[0041] Referring to FIGS. 1 and 2, a signal processing device (1) according to one embodiment of the present invention includes a feedforward transmitter (10), a memory unit (20), and a control unit (30).

[0042] In one embodiment, the feedforward transmitter (10) may include a pseudo-random binary sequence (hereinafter referred to as "PRBS") generator (110), a feedforward equalizer (120), a multiplexer (130), and an output unit (150). For example, the feedforward transmitter (10) may output a signal generated by the PRBS generator (110) based on an input clock signal (CLK) to a memory unit (20) through the feedforward equalizer (120), the multiplexer (130), and the output unit (150). For example, the clock signal (CLK) may be divided through a divider (DIV4) and input to at least one of the PRBS generator (110), the feedforward equalizer (120), the multiplexer (130), and the output unit (150). For example, the clock signal (CLK) may have a clock frequency, i.e., a half rate, which is half the frequency of the data signal, but the present invention is not limited thereto and may have various frequencies including a full rate.

[0043] The PRBS generation unit (110) can generate a PRBS signal that mimics (e.g., simulates) the data to be transmitted. For example, the PRBS generation unit (110) can generate a PRBS signal that mimics a data signal input from a source, user, etc. Here, the PRBS signal may also be referred to as a data signal. However, embodiments of the present invention are not limited thereto, and the PRBS generation unit (110) may output an input data signal together with the PRBS signal. The method by which the PRBS generation unit (110) generates the PRBS signal is not particularly limited and may generate the PRBS signal according to any known method. The data signal generated by the PRBS generation unit (110) may be a pulse signal. For example, the data signal (DATA) may be a pulse-amplitude modulation (hereinafter "PAM") signal, but the present invention is not limited thereto and may include various known signals as long as they do not contradict the purpose of the present invention. The data signal generated in the PRBS generation unit (110) can be output to the feedforward equalization unit (120).

[0044] The feedforward equalization unit (120) may include a reflection cancellation (RC) signal generation unit (121), a signal delay unit (122), and a signal control unit (127). Here, the feedforward equalization unit (120) may correspond to a "feedforward equalizer".

[0045] The RC signal generation unit (121) can generate at least one reflected wave removal signal based on a data signal input from the PRBS generation unit (110). For example, the RC signal generation unit (121) can generate at least one reflected wave removal signal based on properties such as the data signal input from the PRBS generation unit (110) and the characteristic impedance of the memory unit (20). For example, the RC signal generation unit (121) can generate at least one reflected wave removal signal to remove reflected waves resulting from applying the data signal to the memory unit (20). For example, each of the at least one reflected wave removal signal may be a pulse signal. For example, the at least one reflected wave removal signal generated by the RC signal generation unit (121) and output to the memory unit (20) can cancel out the reflected waves resulting from applying the data signal to the memory unit (20) to remove the reflected waves.

[0046] In one embodiment, the RC signal generator (121) can generate a reflection wave removal signal having an absolute value equal to the absolute value of the reflection wave magnitude and an amplitude having a sign opposite to the sign of the reflection wave. For example, at least one reflection wave removal signal generated by the RC signal generator (121) may include a first reflection wave removal signal having an absolute value smaller than the magnitude (e.g., amplitude) of the data signal and a second reflection wave removal signal having an absolute value smaller than the magnitude of the first reflection wave removal signal. For example, the RC signal generator (121) may generate the first reflection wave removal signal and the second reflection wave removal signal sequentially so that the second reflection wave removal signal is applied to the memory unit (20) after the first reflection wave removal signal is applied to the memory unit (20). For example, one of the data signal and the first reflection wave removal signal may have a positive value, and the other of the data signal and the first reflection wave removal signal may have a negative value. For example, one of the first reflected wave removal signal and the second reflected wave removal signal may have a positive value, and the other of the first reflected wave removal signal and the second reflected wave removal signal may have a negative value. For example, if the data signal has a positive value, the first reflected wave removal signal may have a negative value and the second reflected wave removal signal may have a positive value, and if the data signal has a negative value, the first reflected wave removal signal may have a positive value and the second reflected wave removal signal may have a negative value. For example, the RC signal generator (121) generates a plurality of reflected wave removal signals, and the absolute value of the magnitude of the plurality of reflected wave removal signals may decrease over time. For example, the plurality of reflected wave removal signals generated sequentially by the RC signal generator (121) may alternate positive and negative values. For example, the time interval between the plurality of reflected wave removal signals generated by the RC signal generator (121) may be the same.The RC signal generation unit (121) can output at least one generated reflection wave removal signal and a data signal input from the PRBS generation unit (110) to the multiplexer (130).

[0047] The multiplexer (130) receives a data signal and at least one reflected wave removal signal and can multiplex the data signal and at least one reflected wave removal signal. For example, the multiplexer (130) can primarily serialize the data signal and at least one reflected wave removal signal into high-speed signals and output them. The multiplexer (130) may include an 8:2 multiplexer, but the present invention is not limited thereto. The multiplexer (130) can output the serialized data signal and at least one reflected wave removal signal to the signal delay unit (122) of the feedforward equalizer (120).

[0048] In one embodiment, the signal delay unit (122) can delay and output at least one of a data signal applied from the multiplexer (130) and at least one reflected wave removal signal. In one embodiment, the signal delay unit (122) may include a D flip-flop (D Flip-Flop, hereinafter "DFF") delay unit (123), a first voltage-controlled delay line (Voltage-Controlled Delay Line, hereinafter "VCDL") delay unit (124), and a second VCDL delay unit (125).

[0049] FIG. 3 is a circuit diagram schematically illustrating a DFF delay unit (123) according to one embodiment of the present invention.

[0050] Referring to FIG. 3, the DFF delay unit (123) includes a plurality of D flip-flops (DFF, D Flip-Flop) and can delay and output at least one of a data signal and at least one reflected wave removal signal according to a clock signal (CLK). For example, the DFF delay unit (123) can output the output of the Nth flip-flop through an output selector.

[0051] For example, the DFF delay unit (123) may cause at least one of the data signal and at least one reflection removal signal to be delayed by a first delay time unit or an integer multiple of the first delay time unit, wherein the first delay time unit may be a unit interval (UI) of the data signal. Here, the unit interval (UI) may mean the minimum time during which a change in the signal state can occur. For example, when the data signal is a pulse signal, the unit interval (UI) may mean the time during which one pulse is sustained. However, embodiments of the present invention are not limited thereto, and the unit interval (UI) may also mean the period of the data signal. For example, the DFF delay unit (123) may delay the data signal to control the application timing and period of the data signal, and may delay at least one reflection removal signal to control the application timing of at least one reflection removal signal. For example, the delay time during which the DFF delay unit (123) delays the data signal may be the same as or different from the delay time during which the at least one reflection removal signal is delayed.

[0052] FIG. 4 is a circuit diagram schematically illustrating a first VCDL delay unit (124) or a second VCDL delay unit (125) according to an embodiment of the present invention.

[0053] Referring to FIG. 4, the first VCDL delay unit (124) or the second VCDL delay unit (125) may include a plurality of P-type metal-oxide-semiconductor (hereinafter "PMOS") transistors and N-type metal-oxide-semiconductor (hereinafter "NMOS") transistors to delay and output a data signal or at least one reflected wave removal signal. For example, the first VCDL delay unit (124) or the second VCDL delay unit (125) may have a voltage (V) applied to the PMOS transistor or NMOS gate. P , V N Depending on ), a delay can be generated by adjusting the rising and falling transition times of at least one of the data signal or at least one reflected wave removal signal.

[0054] In one embodiment, a data signal is input to a first VCDL delay unit (124), and at least one reflected wave removal signal may be input to a second VCDL delay unit (125). For example, the first VCDL delay unit (124) may cause the data signal to be delayed by a time smaller than the unit interval (UI) of the data signal (coarse tuning). For example, the first VCDL delay unit (124) may output the data signal by delaying it by a predetermined delay time unit or an integer multiple of the predetermined delay time unit, wherein the predetermined delay time unit may be smaller than the first delay time unit in which the data signal is delayed by the DFF delay unit (123). For example, the integer multiple of the predetermined delay time unit in which the data signal is delayed by the first VCDL delay unit (124) may be smaller than the unit interval (UI) of the data signal. For example, the data signal may pass through the DFF delay unit (123) and the first VCDL delay unit (124) and be delayed by the sum of the time delayed by the DFF delay unit (123) and the time delayed by the first VCDL delay unit (124).

[0055] In one embodiment, the second VCDL delay unit (125) can cause at least one reflected wave signal to be delayed by a time smaller than the unit interval (UI) of the data signal (coarse tuning). For example, the second VCDL delay unit (125) can delay at least one reflected wave signal by a second delay time unit or an integer multiple of the second delay time unit and output it, wherein the second delay time unit may be smaller than the first delay time unit in which at least one reflected wave removal signal is delayed by the DFF delay unit (123). For example, the integer multiple of the second delay time unit in which at least one reflected wave removal signal is delayed by the second VCDL delay unit (125) may be smaller than the unit interval (UI) of the data signal. For example, at least one reflected wave removal signal may pass through the DFF delay unit (123) and the second VCDL delay unit (125) and be delayed by the sum of the time delayed by the DFF delay unit (123) and the time delayed by the second VCDL delay unit (125). For example, the DFF delay unit (123) and the second VCDL delay unit (125) may control the application time and period at which at least one reflected wave removal signal is input to the memory unit (20).

[0056] The time at which the data signal is delayed by the DFF delay unit (123) and the first VCDL delay unit (124) may be the same as or different from the time at least one reflected wave removal signal is delayed by the DFF delay unit (123) and the second VCDL delay unit (125). Additionally, the time at least one reflected wave removal signal is delayed by the DFF delay unit (123) and the second VCDL delay unit (125) may be the same as or different from each other.

[0057] A multiplexer may be placed between the DFF delay unit (123) and the first VCDL delay unit (124), and between the DFF delay unit (123) and the second VCDL delay unit (125). For example, a data signal output from the DFF delay unit (123) may be multiplexed through a multiplexer, serialized, and output to the first VCDL delay unit (124), and a reflected wave removal signal output from the DFF delay unit (123) may be multiplexed through a multiplexer, serialized, and output to the second VCDL delay unit (125). Here, the multiplexer may include a 2:1 multiplexer, but the present invention is not limited thereto.

[0058] In one embodiment, the signal control unit (127) may include a memory (not shown) and a processor (not shown).

[0059] For example, the memory of the signal control unit (127) may include a computer storage medium and / or a communication medium capable of storing computer-readable instructions that can be executed by a processor. The computer storage medium may include a storage unit of the type such as volatile memory, non-volatile memory, and / or other permanent and / or auxiliary computer storage media, removable and non-removable computer storage media, implemented by any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. The communication medium may implement computer-readable instructions, data structures, program modules, or other data as modulated data signals such as carrier waves or other transmission mechanisms. Additionally, instructions that can be executed by a processor may be loaded from a computer-readable recording medium separate from the memory.

[0060] Additionally, the processor of the signal control unit (127) can execute instructions stored in memory or other storage devices. For example, the processor can realize the control or function of the entire feedforward equalization unit (120) by executing instructions stored in the non-volatile memory of the memory or other storage devices or other permanent and / or auxiliary computer storage media, reading out a program or data according to the instructions onto the volatile memory of the memory, and executing processing.

[0061] In one embodiment, the signal control unit (127) can control the operation of the RC signal generation unit (121) and the signal delay unit (122) according to the execution of instructions of the processor.

[0062] For example, the signal control unit (127) can calculate the respective magnitude (e.g., amplitude) of at least one reflected wave removal signal to be generated by the RC signal generation unit (121) based on properties such as the data signal input from the PRBS generation unit (110) and the characteristic impedance of the memory unit (20). To this end, the signal control unit (127) can calculate the characteristics of at least one reflected wave removal signal (e.g., number of pulses, magnitude, amplitude, period, frequency, etc.) and the delay time at which the signal delay unit (122) delays the data signal and at least one reflected wave removal signal, respectively, based on information regarding the characteristics of the data signal (e.g., number of pulses, magnitude, amplitude, period, frequency, etc.) and the characteristics of the memory unit (20) (e.g., characteristic impedance and channel delay time) that are pre-set or measured, or based on user input. However, embodiments of the present invention are not limited thereto, and the signal control unit (127) may transmit a test signal to the memory unit (20) and measure the reflected wave accordingly to measure or calculate the characteristics of at least one reflected wave removal signal required (e.g., number of pulses, magnitude, amplitude, period, frequency, etc.) and the delay time required for the signal delay unit (122) to delay the data signal and at least one reflected wave removal signal, respectively.

[0063] For example, the signal control unit (127) can control the RC signal generation unit (121) to generate a reflected wave removal signal having an absolute value equal to the absolute value of the reflected wave and an amplitude having a sign opposite to that of the reflected wave. For example, the signal control unit (127) can control the RC signal generation unit (121) so that at least one reflected wave removal signal includes a first reflected wave removal signal having an absolute value smaller than the size of the data signal and a second reflected wave removal signal having an absolute value smaller than the size of the first reflected wave removal signal. For example, the signal control unit (127) can control the RC signal generation unit (121) so that one of the data signal and the first reflected wave removal signal has a positive value, and the other of the data signal and the first reflected wave removal signal has a negative value. For example, the signal control unit (127) can control the RC signal generation unit (121) such that one of the first reflected wave removal signal and the second reflected wave removal signal has a positive value, and the other of the first reflected wave removal signal and the second reflected wave removal signal has a negative value. For example, the signal control unit (127) can control the RC signal generation unit (121) such that a plurality of reflected wave removal signals are generated and the absolute value of the magnitude of the plurality of reflected wave removal signals decreases over time. For example, the signal control unit (127) can control the RC signal generation unit (121) such that the plurality of reflected wave removal signals alternately have positive and negative values.

[0064] For example, the signal control unit (127) can calculate the time for which a data signal is delayed through the signal delay unit (122) and the time for which at least one reflected wave removal signal is delayed through the signal delay unit (122), and perform control accordingly. For example, the signal control unit (127) can control the operation of the RC signal generation unit (121) and the signal delay unit (122) to adjust the time for which the data signal and at least one reflected wave removal signal are each delayed. For example, the signal control unit (127) can control the RC signal generation unit (121) and the signal delay unit (122) so that after the data signal is applied to the memory unit (20), at least one reflected wave removal signal for removing reflected waves resulting from the application of the data signal is applied to the memory unit (20). For example, the signal control unit (127) can control the RC signal generation unit (121) and the signal delay unit (122) so that the second reflection wave removal signal is applied to the memory unit (20) after the first reflection wave removal signal is applied to the memory unit (20). For example, the signal control unit (127) can control the RC signal generation unit (121) and the signal delay unit (122) so that the time interval between the plurality of reflection wave removal signals applied to the memory unit (20) is the same.

[0065] Although FIG. 1 illustrates that the signal control unit (125) is included in the feedforward equalization unit (120), the present invention is not limited thereto. For example, the signal control unit (125) may be provided in the feedforward transmitter (10) outside the feedforward equalization unit (120), may be provided outside the feedforward transmitter (10), or may be provided in the memory unit (20) or the control unit (30). That is, the signal control unit (125) is not particularly limited in its location and configuration as long as it can control the generation of the reflected wave removal signal and the delay of the data signal and the reflected wave removal signal.

[0066] The data signal and reflected wave removal signal output from the feedforward equalization unit (120) are output to the memory unit (20) through the output unit (150) including the output driver and the transmitting unit (TX).

[0067] FIG. 5 is a perspective view illustrating a signal processing device (1) according to one embodiment of the present invention. FIG. 6 is a circuit diagram schematically illustrating the structure of a signal processing device (1) according to one embodiment of the present invention.

[0068] In FIG. 5, the feedforward transmitter (10) and memory unit (20) of the signal processing device (1) according to one embodiment of the present invention are shown as being placed on a single substrate (e.g., a printed circuit board (PCB), but the present invention is not limited thereto. For example, the feedforward transmitter (10) may be provided on the central processing unit (CPU) of the signal processing device (1) or on a separate substrate.

[0069] Referring to FIGS. 1, 5 and 6, the memory unit (20) may include a memory module unit (210), a channel unit (220), and a switch unit (230).

[0070] The memory module section (210) may include at least one Dual In-line Memory Module (hereinafter "DIMM") disposed on a substrate. For example, the memory module section (210) may include a first DIMM (211), a second DIMM (212), and a third DIMM (213). Each of the first DIMM (211), the second DIMM (212), and the third DIMM (213) may include at least one Dynamic Random Access Memory (hereinafter "DRAM") chip (215). For example, for convenience of explanation, FIG. 5 is illustrated as having a memory module (210) that includes three first to third DIMMs (211, 212, 213) each containing eight DRAM chips (215), and FIG. 6 is illustrated as having a memory module (210) that includes two first and second DIMMs (211, 212), but the present invention is not limited thereto, and the memory module (210) may include fewer or more DIMMs and DRAM chips.

[0071] Referring to FIG. 6, the channel section (220) may include an input channel (221), a first channel (222), and a second channel (223). For example, the input channel (221) may be connected to the transmitting end (TX) of the feedforward transmitter (10) to receive input from the feedforward transmitter (10) and transmit it to the first and second DIMMs (211, 212). The first channel (222) is positioned between the input channel (221) and the first DIMM (211), and the second channel (223) is positioned between the input channel (221) and the second DIMM (212). That is, a signal processing device (1) according to one embodiment of the present invention may have a multi-drop bus structure in which communication between a feedforward transmitter (10) and a plurality of DIMMs (211, 212) of a memory unit (20) shares a single transmission line, for example, an input channel (221). Referring to FIG. 6, one end of the first DIMM (211) is connected to the input channel (221) through the first channel (222), and the other end may be connected to the first output terminal, and one end of the second DIMM (212) is connected to the input channel (221) through the second channel (223), and the other end may be connected to the second output terminal.

[0072] Referring to FIG. 6, the switch unit (230) includes a first switch unit (231) positioned between a first channel (222) and a first DIMM (211), and a second switch unit (232) positioned between a second channel (223) and a second DIMM (212). The first switch unit (231) allows the first channel (222) and the first DIMM (211) to be connected in a connected state and disconnects the first channel (222) and the first DIMM (211) in an open state. The second switch unit (232) allows the second channel (223) and the second DIMM (212) to be connected in a connected state and disconnects the second channel (223) and the second DIMM (212) in an open state.

[0073] FIG. 6 illustrates a case where a feedforward transmitter (10) and a second DIMM (212) communicate. For communication between the feedforward transmitter (10) and the second DIMM (212), the first switch unit (231) is set to an open state and the second switch unit (232) is set to a connected state so that a data signal is transmitted to the second DIMM (212) through the input channel (221) and the second channel (223). At this time, a reflected wave is generated because the matching condition is not satisfied due to the discontinuity of impedance at the intersection (STUB) of the input channel (221), the first channel (222), and the second channel (223). That is, in order to satisfy the impedance matching condition, the impedance within the channel must be constant and continuous, but if a discontinuity occurs, a reflected wave is generated at that point. In one example of FIG. 6, there are two impedance discontinuities at the intersection (STUB) of the input channel (221), the first channel (222), and the second channel (223), and at the end of the first switch unit (231) which is in an open state, and a reflected wave is generated at that point, so that the second DIMM (212) receives not only the data signal (main) but also the reflected wave. FIG. 6 describes a situation in which the feedforward transmitter (10) and the second DIMM (212) communicate, but the first switch unit (231) may be in a connected state and the second switch unit (232) may be in an open state so that the feedforward transmitter (10) and the first DIMM (211) communicate. Additionally, when the signal processing device (10) includes a plurality of DIMMs, the switch connecting the channel section (220) to the DIMM communicating with the feedforward transmitter (10) is set to a connected state, and the switch connecting the channel section (220) to the remaining DIMMs excluding the DIMM may be set to an open state.

[0074] Referring again to FIG. 1, the control unit (30) can control the operation of the feedforward transmitter (10) and the memory unit (20). Although FIG. 1 shows the control unit (30) as being separate from the feedforward transmitter (10) and the memory unit (20), the present invention is not limited thereto and may be included in at least one of the feedforward transmitter (10) and the memory unit (20), or may be integrated with the signal control unit (127) of the feedforward equalization unit (120) to form a single component. The control unit (30) includes a memory (not shown) and a processor (not shown) to control the operation of the feedforward transmitter (10) and the memory unit (20), and may be electrically connected to the feedforward transmitter (10) and the memory unit (20) or transmit and receive signals through a network, communication, etc. Since the configuration of the memory and processor of the control unit (30) is the same as previously described in relation to the memory and processor of the signal control unit (127), a description thereof is omitted.

[0075] For example, the control unit (30) can calculate the frequency of the clock signal (CLK), the generation of the data signal by the PRBS generation unit (110), the characteristics of at least one reflected wave removal signal generated by the RC signal generation unit (121) (e.g., number of pulses, size, amplitude, period, frequency, etc.), the delay time in which the DFF delay unit (123), the first VCDL delay unit (124), and the second VCDL delay unit (125) each delay the data signal and at least one reflected wave removal signal, respectively, and set and control the path through which the data signal passes the DFF delay unit (123) and the first VCDL delay unit (124), the path through which at least one reflected wave removal signal passes the DFF delay unit (123) and the second VCDL delay unit (125), and the connection status of the first switch unit (231) and the second switch unit (232). For example, the control unit (30) can set the switch unit connected to the DIMM communicating with the feedforward transmitter (10) to a connected state, and set the switch unit connected to the other DIMM to an open state.

[0076] Additionally, although not shown, a signal processing device (10) according to one embodiment of the present invention may additionally include any modulation unit, encoding unit, filter, multiplexer, operation unit, delay unit, etc., which adjust the characteristics of a data signal and a plurality of reflected wave removal signals, perform modulation, encoding, operation, etc., and selectively apply a signal or control the timing of the application of a signal, depending on the purpose of use and environment of use of the signal processing device (10).

[0077] Hereinafter, a reflected wave resulting from the transmission of a data signal by a signal processing device (1) according to an embodiment of the present invention will be described with reference to FIGS. 7a to 8. FIGS. 7a to 7c are circuit diagrams for explaining a reflected wave resulting from the transmission of a data signal by a signal processing device according to an embodiment of the present invention. FIG. 8 is a graph showing a reflected wave resulting from the transmission of a data signal by a signal processing device according to an embodiment of the present invention.

[0078] Referring to FIGS. 7a to 7c, in a signal processing device (1) according to one embodiment of the present invention, a feedforward transmitter (10) and a second DIMM (212) communicate, and a first switch unit (231) is set to an open state and a second switch unit (232) is set to a connected state. In one embodiment, the characteristic impedance (Z0) of the channel unit (220) of the memory unit (20) is approximately 0.1 to 500 Ω, for example, 50 Ω, and the data signal input from the feedforward transmitter (10) to the memory unit (20) is a pulse signal, and it is assumed that the lengths of the input channel (221), the first channel (222), and the second channel (223) are the same, but the present invention is not limited thereto. For example, as long as it does not deviate from the purpose of the present invention, the lengths of the input channel (221), the first channel (222), and the second channel (223) may be different from each other. For example, the time delay occurring when a signal passes through each of the input channel (221), the first channel (222), and the second channel (223) may be the same as the unit channel delay, but the present invention is not limited thereto.

[0079] FIG. 7a illustrates a situation in which a reflected wave is generated due to impedance discontinuity after a data signal is applied at the crossover section (STUB). Referring to FIG. 7a and 8, the data signal passes through the input channel (221) from the transmitting end (TX) of the feedforward transmitter (10) to reach the crossover section (STUB), and the data signal reaching the crossover section (STUB) is transmitted to the first DIMM (211) and the second DIMM (212), and a reflected wave may be generated due to impedance discontinuity at the crossover section (STUB). The reflected wave has an amplitude corresponding to the product of the amplitude of the input data signal and the reflection coefficient (Γ) and may be reflected to the transmitting end (TX) of the feedforward transmitter (10). Here, the reflection coefficient (Γ) can be calculated based on the characteristic impedance (Z0) value of the channel section (220). For example, the reflection coefficient (Γ) of the reflected wave generated by the impedance discontinuity at the crossover (STUB) and reflected to the transmitting end (TX) can be expressed by the following Equation 1. That is, the reflection coefficient (Γ) due to the impedance discontinuity at the crossover (STUB) is approximately -1 / 3, and when the data signal is positive, a reflected wave of negative value is generated.

[0080] [Equation 1]

[0081] Γ={(Z0 / 2)-Z0} / {(Z0 / 2)+Z0}=-1 / 3

[0082] Referring to FIG. 8, a data signal applied from the transmitting end (TX) of a feedforward transmitter (10) and reaching the crossover (STUB) is transmitted to the second DIMM (212) at time point (①). Additionally, a reflected wave generated due to impedance discontinuity at the crossover (STUB) is transmitted to the transmitting end (TX) at time point (①). The time point (①) at which the data signal is transmitted to the second DIMM (212) may be the same as the time point (①) at which the reflected wave from the crossover (STUB) is transmitted to the transmitting end (TX), but the present invention is not limited thereto.

[0083] FIG. 7b illustrates a situation in which a reflected wave is generated due to the first switch unit (231) being in an open state. Referring to FIG. 7b, a data signal transmitted from the crossover unit (STUB) to the first DIMM (211) can generate a reflected wave that is reflected from the first switch unit (231) to the crossover unit (STUB) due to the first switch unit (231) being in an open state. The reflected wave has an amplitude corresponding to the product of the amplitude of the data signal transmitted to the first DIMM (211) and the reflection coefficient (Γ), and the reflection coefficient (Γ) can be calculated based on the characteristic impedance (Z0) value of the channel unit (220). For example, the reflection coefficient (Γ) resulting from the first switch part (231) having an impedance of infinity (inf) in an open state can be expressed by the following Equation 2, and the reflection coefficient (Γ) is a value approximately 1, so that when the data signal is a positive value, a positive reflected wave is generated.

[0084] [Equation 2]

[0085] Γ=(inf-Z0) / (inf+Z0)≈1

[0086] Referring to FIG. 8, the reflected wave of the data signal transmitted to the first DIMM (211) due to the first switch part (231) in an open state is reflected to the intersection part (STUB) at the time point (②).

[0087] FIG. 7c illustrates a situation in which a reflected wave reflected from the first switch unit (231) to the crossover unit (STUB) passes through the crossover unit (STUB) and is transmitted to the transmitting end (TX) and the second DIMM (212) of the feedforward transmitter (10). Referring to FIG. 7c, the reflected wave reflected from the first switch unit (231) to the crossover unit (STUB) is divided and transmitted to the transmitting end (TX) and the second DIMM (212) of the feedforward transmitter (10), and due to the impedance discontinuity at the crossover unit (STUB), a reflected wave that is reflected back to the first DIMM (211) can be generated. The reflected wave reflected back to the first DIMM (211) has an amplitude corresponding to the product of the amplitude of the reflected wave reflected from the first switch section (231) to the cross section (STUB) and the reflection coefficient (Γ), and the reflection coefficient (Γ) can be calculated based on the characteristic impedance (Z0) value of the channel section (220). For example, the reflection coefficient (Γ) of the cross section (STUB) can be expressed by the following Equation 3, and is approximately -1 / 3, so that when the reflected wave reflected from the first switch section (231) to the cross section (STUB) is a positive value, a reflected wave of a negative value is generated.

[0088] [Equation 3]

[0089] Γ={(Z0 / 2)-Z0} / {(Z0 / 2)+Z0}=-1 / 3

[0090] Referring to FIG. 8, the reflected wave that is reflected from the first switch unit (231) and reaches the intersection unit (STUB) at the point in time (②) is transmitted to the transmitting unit (TX) and the second DIMM (212) at the point in time (③).

[0091] As such, the reflected wave appears repeatedly thereafter due to the impedance discontinuity caused by the STUB and the first DIMM (211) in an open state, but because the reflection coefficient (Γ) at the STUB is less than 1, the amplitude of the reflected wave can gradually decrease and disappear. Referring to FIG. 8, the absolute value of the reflected wave received at the second DIMM (212) can gradually decrease over time.

[0092] Referring to FIG. 8, from the perspective of the second DIMM (212) communicating with the feedforward transmitter (10), a data signal is received at time point (①) and a reflected wave is received at time point (③), and thereafter, the reflected waves received by the second DIMM (212) appear repeatedly. For example, the reflected waves received by the second DIMM (212) have amplitudes that decrease over time, alternate positive and negative values, and the time interval between each reflected wave being received may be the same. For example, the time interval between the data signal received by the second DIMM (212) and the first reflected wave may be the same as the time interval between the first reflected wave and the second reflected wave received by the second DIMM (212).

[0093] FIG. 9 is a diagram illustrating the transmission of a data signal and a reflected wave removal signal of a signal processing device according to an embodiment of the invention.

[0094] In one embodiment, referring to FIGS. 8 and 9, when a feedforward transmitter (10) and a second DIMM (212) communicate, a data signal transmitted from the transmitting end (TX) of the feedforward transmitter (10) can reach the receiving end, the second DIMM (212), at time point (①) after two unit channel delays. Thereafter, a reflected wave caused by the open state of the first DIMM (211) can reach the second DIMM (212) at time point (③) after two unit channel delays. Therefore, if a reflected wave removal signal corresponding to the reflected wave is transmitted from the transmitting end (TX) after two unit channel delays following the transmission of the data signal to be transmitted, the time at which the reflected wave and the reflected wave removal signal reach the second DIMM (212) is the same, and when added together, the reflected wave can have the effect of canceling out. To this end, the reflected wave cancellation signal may have an absolute value equal to the absolute value of the reflected wave and an amplitude having a sign opposite to that of the reflected wave.

[0095] Since the reflected wave removal signal generates another reflected wave corresponding to it, the feedforward transmitter (10) can transmit multiple reflected wave removal signals according to a predetermined time interval when sending a single data signal. In this case, since the reflection coefficient at the crossover section (STUB) is less than 1, the reflected wave becomes smaller as the process is repeated, so the reflected wave can be sufficiently removed when multiple reflected wave removal signals are transmitted. For example, to remove the reflected wave that occurs repeatedly when sending a single data signal, a total of six pulse-shaped reflected wave removal signals can be transmitted according to a predetermined time interval, but the present invention is not limited thereto, and fewer or more reflected wave removal signals than six can be transmitted. For example, the reflected wave can be removed by determining the channel delay time of the channel section (220), transmitting a single signal, and then inputting the reflected wave removal signal from the feedforward transmitter (10) to the memory section (20) after that amount of time. For example, referring to FIG. 8, multiple reflected wave removal signals can each be transmitted at two unit channel delay intervals.

[0096] In one embodiment of the present invention, by utilizing the characteristic of such reflected waves, it is possible to anticipate that reflected waves will occur and transmit a reflected wave removal signal capable of canceling the reflected waves at the feedforward transmitter (10) together with a data signal, thereby removing the reflected waves received at the first DIMM (211) or the second DIMM (212). In one embodiment, the signal control unit (127) or control unit (30) of FIG. 1 may calculate the characteristics of at least one reflected wave removal signal (e.g., number of pulses, size, amplitude, period, frequency, etc.) and the delay time for the signal delay unit (122) to delay the data signal and at least one reflected wave removal signal based on information such as the characteristics of the data signal (e.g., size, amplitude, period, frequency, etc.) and the characteristics of the memory unit (20) (e.g., characteristic impedance (Z0) of at least one of the input channel, first channel and second channel or a combination thereof, channel delay time, reflection coefficient (Γ) of the reflected wave at each time point), as described with reference to FIG. 7a to 8, and the delay time for the data signal and at least one reflected wave removal signal to be delayed accordingly, and control the feedforward transmitter (10) so that the feedforward transmitter (10) can generate and transmit a reflected wave removal signal capable of canceling out the reflected wave. The signal control unit (127) or the control unit (30) may calculate the characteristics of at least one reflected wave removal signal and the delay time for the signal delay unit (122) to delay the data signal and at least one reflected wave removal signal based on information that is previously input or set (e.g., characteristics of the data signal, characteristics of the memory unit (20)) or user input.However, the embodiments of the present invention are not limited thereto, and the signal control unit (127) or the control unit (30) may directly measure the characteristics of the memory unit (20), or transmit a test signal to obtain information thereon and measure the reflected wave accordingly, and based thereon, may calculate the characteristics of at least one reflected wave removal signal and the delay time for the signal delay unit (122) to delay the data signal and at least one reflected wave removal signal.

[0097] FIG. 10 is a non-return to zero (NRZ) eye diagram comparing data eyes at the receiving end of a signal processing device according to the prior art and a signal processing device according to an embodiment of the present invention. FIG. 10(a) is an NRZ eye diagram of a signal processing device according to the prior art, and FIG. 10(b) is an NRZ eye diagram at the receiving end of a signal processing device according to an embodiment of the present invention. FIG. 10(a) and FIG. 10(b) show the results of measuring data eyes at the receiving end after channel passing when operating at a data transmission speed of 8 Gb / s.

[0098] Referring to FIG. 10(a), it can be seen that the data eye at the receiving end of a signal processing device according to the prior art is substantially closed. However, referring to FIG. 10(b), in a signal processing device including a feedforward transmitter according to an embodiment of the present invention that transmits a reflection removal signal to remove a reflection wave, it can be seen that the reflection wave is effectively removed and the eye margin can be secured.

[0099] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention can reduce signal distortion and increase reliability during signal transmission by eliminating reflected waves generated when communicating using a Dual In-line Memory Module (DIMM) in a high-channel environment.

[0100] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention are compatible with existing memory using a PAM-based signal method by adding only a time delay circuit, a logic circuit for removing reflected waves, and a partial circuit for removing reflected waves in the output driver.

[0101] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention can increase the eye margin by removing reflected waves within a unit interval (UI).

[0102] A feedforward equalizer and a feedforward transmitter according to one embodiment of the present invention can reduce the area occupied and increase power efficiency by having a relatively simple structure.

[0103] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features.

[0104] Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting, and the scope of the invention is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalents thereof should be interpreted as being included within the scope of the invention.

[0105] This invention was carried out with funding from the government (Ministry of Science and ICT) under No. RS-2024-00423344, “[N01250110](Integrated EZ) Efficient power management and noise-robust communication circuit for artificial intelligence semiconductor systems”.

[0106] [Explanation of the symbol]

[0107] 1: Signal processing unit

[0108] 10: Feedforward transmitter

[0109] 120: Feedforward lighting unit

[0110] 121: RC signal generator

[0111] 122: Signal delay section

[0112] 123: DFF delay section

[0113] 124: 1st VCDL delay section

[0114] 125: 2nd VCDL delay section

[0115] 127: Signal control unit

[0116] 20: Memory section

[0117] 210: Memory Module

[0118] 220: Channel Department

[0119] 230: Switch section

[0120] 30: Control unit

Claims

1. A signal delay unit that delays a data signal applied to a memory unit including a plurality of dual in-line memory modules (DIMM) and at least one reflected wave removal signal; and It includes a control unit that controls the operation of the above signal delay unit, and The above control unit is, A feedforward equalizer that controls the signal delay unit to apply the at least one reflection wave removal signal to the memory unit for removing a reflection wave resulting from the application of the data signal after the data signal is applied to the memory unit.

2. In Paragraph 1, The above signal delay unit A DFF delay unit including a D flip-flop (DFF, D Flip-Flop); and A voltage-controlled delay line (VCDL) delay section comprising at least one P-type metal-oxide-semiconductor (PMOS) transistor and at least one N-type metal-oxide-semiconductor (NMOS) transistor, and The above DFF delay unit delays the reflected wave removal signal by an integer multiple of a first delay time unit compared to the data signal, and the above VCDL delay unit delays the reflected wave removal signal by an integer multiple of a second delay time unit compared to the data signal, A feedforward equalizer in which the first delay time unit is larger than the second delay time unit.

3. In Paragraph 2, The above first delay time unit is equal to the unit interval (UI, Unit Interval) of the data signal, and A feedforward equalizer in which the second delay time unit is smaller than the unit interval of the data signal.

4. In Paragraph 1, The above reflected wave removal signal is A first reflected wave removal signal having an absolute value smaller than the magnitude of the above data signal; and A feedforward equalizer comprising a second reflection removal signal that is applied to the memory unit after the first reflection removal signal is applied to the memory unit and has an absolute value smaller than the magnitude of the first reflection removal signal.

5. In Paragraph 4, One of the data signal and the first reflected wave removal signal has a positive value, and the other of the data signal and the first reflected wave removal signal has a negative value, A feedforward equalizer in which one of the first reflected wave removal signal and the second reflected wave removal signal has a positive value, and the other of the first reflected wave removal signal and the second reflected wave removal signal has a negative value.

6. In Paragraph 1, The absolute value of the magnitude of at least one reflected wave removal signal decreases over time, and The above at least one reflected wave removal signal has alternating positive and negative values, A feedforward equalizer in which the time interval between at least one reflected wave removal signal is the same.

7. In Paragraph 1, The above memory unit is, A memory module comprising: a first DIMM including at least one Dynamic Random Access Memory (DRAM) chip, one end of which is connected to an input channel through a first channel; and a second DIMM including at least one DRAM chip, one end of which is connected to the input channel through a second channel; and A switch unit comprising a first switch unit connecting the first DIMM and the first channel, and a second switch unit connecting the second DIMM and the second channel, A feedforward equalizer in which either of the first switch unit and the second switch unit is set to an open state, and the other of the first switch unit and the second switch unit is set to a connected state.

8. In Paragraph 7, The above-mentioned reflected wave removal signal is a feedforward equalizer intended to remove reflected waves transmitted to the first DIMM or the second DIMM connected to the other of the first switch unit and the second switch unit having the above-mentioned connection state due to an impedance imbalance between the input channel, the first channel, and the second channel resulting from either the first switch unit and the second switch unit being set to the above-mentioned open state.

9. In Paragraph 7, A feedforward equalizer in which the magnitude of at least one reflected wave removal signal is calculated based on the characteristic impedances of the input channel, the first channel, and the second channel.

10. A feedforward transmitter comprising a feedforward equalizer according to any one of paragraphs 1 through 9.

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