Method for sending indicator light signals, and storage medium and integrated hard disk

Abstract

Provided in the embodiments of the present application are a method for sending indicator light signals, and a storage medium, an integrated hard disk and a computer program product. The method is applied to the integrated hard disk, and the integrated hard disk comprises a motherboard, a backplane and a hard disk interface card, wherein transmission channels of a virtual pin port of a central processing unit on the motherboard have been expanded to N transmission channels by means of a channel expansion component, and the N transmission channels are correspondingly connected to N first connectors on the motherboard on a one-to-one basis. The method comprises: respectively sending N enable signals to first-type pins of N first connectors, so as to forward the N enable signals to a logic control device by means of first-type pins of N second connectors that are correspondingly connected to the N first connectors on a one-to-one basis; and respectively sending N indicator light signals to second-type pins of the N first connectors by means of N transmission channels, so as to forward the N indicator light signals to the logic control device by means of second-type pins of the N second connectors.

Description

Indicator light signal transmission method, storage medium, and integrated hard disk

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411967263.X, filed on December 30, 2024, entitled “Method for transmitting indicator light signals, storage medium, integrated hard disk and computer program product”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a method for transmitting indicator light signals, a storage medium, an integrated hard disk, and a computer program product. Background Technology

[0004] In the design of modern computing systems, indicator lights serve as a crucial visual feedback method for hardware status and fault diagnosis, helping technicians quickly determine the system's operating status, identify potential hardware faults, and perform necessary maintenance. However, existing indicator light control logic is often tightly bound to a specific type of Central Processing Unit (CPU). This means that when the CPU model or version changes, the original indicator light control logic may no longer be applicable, requiring developers to redesign the indicator light control logic based on the changed CPU.

[0005] In related technologies, when the CPU type changes, the lighting control logic needs to be redesigned, resulting in high design costs. No effective solution has yet been proposed. Summary of the Invention

[0006] This application provides a method for sending indicator light signals, a storage medium, an integrated hard disk, and a computer program product, to at least solve the problem in related technologies that require redesigning the lighting control logic when the CPU type changes, resulting in high design costs.

[0007] According to one embodiment of this application, a method for transmitting indicator light signals is provided, applied to an integrated hard disk. The integrated hard disk includes: a motherboard, a backplane connected to the motherboard, and the transmission channels of the virtual pin interface of the central processing unit on the motherboard are expanded to N through a channel expansion component. The N transmission channels are connected one-to-one with N first connectors on the motherboard. The method includes: transmitting N enable signals to the first type pins of the N first connectors respectively, so as to forward the N enable signals to a logic controller through the first type pins of N second connectors connected one-to-one with the N first connectors, wherein the second connectors and the logic controller are both disposed on the backplane; transmitting N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, so as to forward the N indicator light signals to the logic controller through the second type pins of the N second connectors, wherein the low-level first enable signal among the N enable signals is used to instruct the logic controller to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic controller to block the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1.

[0008] In one exemplary embodiment, a first type of pin of the first connector is connected to a first type of pin of the second connector, and a second type of pin of the first connector is connected to a second type of pin of the second connector.

[0009] In an exemplary embodiment, before sending N indicator signals to the second type pins of N first connectors via N transmission channels, the method further includes: when the central processing unit is connected to the backplane via a hard disk interface card, forwarding N enable signals to the logic controller via the first type pins of the N second connectors and the first type pins of the N third connectors, wherein the N third connectors are located on the hard disk interface card, the first type pins of the N third connectors are set as ground pins, and the hard disk interface card is connected to both the motherboard and the backplane; when the first type pins of the N third connectors are set as ground pins, the hard disk interface card is prohibited from adjusting the level state of the received N enable signals.

[0010] In one exemplary embodiment, before forwarding N enable signals to the logic controller via the first type pins of N second connectors and the first type pins of N third connectors, the method further includes: forwarding N indicator light signals and N enable signals to the same fourth connector via the N first connectors, wherein the fourth connector, the N third connectors, and the controller are all disposed on a hard disk interface card, and the fourth connector and the N third connectors are connected through the controller; forwarding the N indicator light signals and N enable signals to the controller via the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected through the first interface bus; the controller is configured to forward the N indicator light signals and N enable signals to the N third connectors.

[0011] In an exemplary embodiment, after forwarding N indicator signals and N enable signals to the controller via the fourth connector and the first interface bus, the method further includes: forwarding the N indicator signals to N third connectors via the controller and N second interface buses, so as to forward the N indicator signals to the logic controller via the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

[0012] In one exemplary embodiment, N second interface buses correspond one-to-one with N third interface buses on the motherboard, and the N third interface buses are respectively connected to the central processing unit and N first connectors.

[0013] In an exemplary embodiment, before sending the N enable signals to the first type of pins of the N first connectors, the method further includes: if the state of the virtual machine device queue corresponding to the fourth interface bus among the N third interface buses is open, controlling the enable signal corresponding to the fourth interface bus to be a first enable signal, wherein the addresses of the N third interface buses are consistent with the addresses of the N second interface buses; and / or, if the state of the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is closed, controlling the enable signal corresponding to the fifth interface bus to be a second enable signal, wherein the N third interface buses are respectively connected to the central processing unit and the N first connectors.

[0014] In an exemplary embodiment, before sending the N enable signals to the first type pins of the N first connectors respectively, the method further includes: obtaining the first device address of the hard disk interface card and determining the second device addresses of the N target hard disks corresponding to the N third interface buses, wherein the hard disk interface card is connected to the central processing unit and to the backplane; and setting the second device address to the first device address through a write operation.

[0015] In one exemplary embodiment, setting a second device address to a first device address via a write operation includes: determining the target location of a first character that is inconsistent between the second device address and the first device address; obtaining the second character corresponding to the target location from the first device address; and modifying the first character at the target location in the second device address to the second character, so as to modify the second device address to be consistent with the first device address.

[0016] In one exemplary embodiment, the channel addresses of the N target hard disks are all different.

[0017] In an exemplary embodiment, after forwarding N indicator light signals to the logic controller via the second type pins of the N second connectors, the method further includes: if a first target hard drive among the N target hard drives fails, receiving an interrupt request issued by the first target hard drive via the second connector corresponding to the first target hard drive through the sixth interface bus corresponding to the first target hard drive, wherein the N target hard drives are disposed on a backplane; generating an interrupt command based on the interrupt request, and sending the interrupt command via the sixth interface bus to the second type pin of the first connector corresponding to the sixth interface bus, so as to send the interrupt command to the logic controller via the second type pin of the second connector corresponding to the sixth interface bus to shut down the first target hard drive.

[0018] In one exemplary embodiment, N indicator lights are used to indicate the operating status of the corresponding target hard drive.

[0019] In an exemplary embodiment, after shutting down the first target hard disk, the method further includes: if the difference between the time when the first target hard disk was shut down and the current time is greater than a preset time, sending a startup command to the logic controller through the second type pin of the first connector corresponding to the sixth interface bus and the second type pin of the second connector corresponding to the sixth interface bus to restart the first target hard disk.

[0020] In one exemplary embodiment, before sending the N enable signals to the first type of pins of the N first connectors respectively, the method further includes: sending a target address via an integrated circuit interconnect bus to determine a target I / O expander communicating with a central processing unit from a plurality of I / O expanders, wherein the plurality of I / O expanders are connected to the central processing unit; sending a register address to the target I / O expander to determine a target register controlling the N enable signals, wherein the target register exists in the internal storage space of the target I / O expander; writing 0 to a target location in the target register to control the first enable signal to be low, and writing 1 to the target location to control the second enable signal to be high.

[0021] In an exemplary embodiment, after forwarding N indicator light signals to a logic controller via the second type of pins of the N second connectors, the method further includes: if a first enable signal exists among the N enable signals, lighting the indicator light corresponding to the first enable signal via the logic controller; and if a second enable signal exists among the N enable signals, turning off the indicator light corresponding to the second enable signal via the logic controller.

[0022] According to another embodiment of this application, an integrated hard disk is also provided, comprising: a motherboard, on which a central processing unit (CPU) and N first connectors are disposed, wherein the transmission channels of the virtual pin interface of the CPU are expanded to N through a channel expansion component, and the N transmission channels are connected one-to-one with the N first connectors on the motherboard; a backplane, on which N second connectors and logic controllers are disposed; wherein the CPU is configured to send N enable signals to the first type pins of the N first connectors respectively, so as to enable the N signals through the first type pins of the N second connectors connected one-to-one with the N first connectors. The signal is forwarded to the logic controller, wherein N second connectors and the logic controller are disposed on the backplane; and N indicator light signals are sent to the second type pins of N first connectors through N transmission channels, so as to forward the N indicator light signals to the logic controller through the second type pins of N second connectors. Among the N enable signals, the low-level first enable signal is used to instruct the logic controller to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal is used to instruct the logic controller to shield the indicator light signal corresponding to the second enable signal. N is an integer greater than 1.

[0023] In one exemplary embodiment, a first type of pin of the first connector is connected to a first type of pin of the second connector, and a second type of pin of the first connector is connected to a second type of pin of the second connector.

[0024] In one exemplary embodiment, the integrated hard disk further includes: a hard disk interface card connected to both the motherboard and the backplane; and a central processing unit (CPU), configured to forward N enable signals to a logic controller via first-type pins of N second connectors and first-type pins of N third connectors when the CPU is connected to the backplane through the hard disk interface card. The N third connectors are located on the hard disk interface card, and the first-type pins of the N third connectors are configured as ground pins. When the first-type pins of the N third connectors are configured as ground pins, the hard disk interface card is prohibited from adjusting the level of the received N enable signals.

[0025] According to another embodiment of this application, a computer non-volatile readable storage medium is also provided, wherein a computer program is stored in the computer non-volatile readable storage medium, and the computer program is configured to execute the steps in any of the above method embodiments when running.

[0026] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0027] In this application, N enable signals are emitted through the first type pins of N first connectors on the motherboard, and then through the first type pins of N second connectors on the backplane, ultimately reaching the logic controller on the backplane. Each second connector is connected to a corresponding first connector. N indicator light signals are sent to the second type pins of the N first connectors via N transmission channels. These indicator light signals are then forwarded to the logic controller on the backplane via the second type pins of the N second connectors. When the first enable signal is low, the logic controller interprets the indicator light signal corresponding to the first enable signal; when the second enable signal is high, the logic controller blocks the indicator light signal corresponding to the second enable signal. Therefore, this solves the problem in related technologies where a change in CPU type necessitates a redesign of the LED control logic, leading to higher design costs. This significantly enhances system compatibility. Attached Figure Description

[0028] Figure 1 is a hardware structure block diagram of a method for transmitting indicator light signals according to an embodiment of this application;

[0029] Figure 2 is a flowchart of a method for transmitting indicator light signals according to an embodiment of this application;

[0030] Figure 3 is a first schematic diagram of a method for transmitting indicator light signals according to an embodiment of this application;

[0031] Figure 4 is a second schematic diagram of a method for transmitting indicator light signals according to an embodiment of this application;

[0032] Figure 5 is a third schematic diagram of a method for transmitting indicator light signals according to an embodiment of this application;

[0033] Figure 6 is a fourth schematic diagram of a method for transmitting indicator light signals according to an embodiment of this application;

[0034] Figure 7 is a structural block diagram of an integrated hard disk for transmitting indicator light signals according to an embodiment of this application. Detailed Implementation

[0035] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0037] The methods and embodiments provided in this application can be executed in an integrated hard disk or similar computing device. Taking an integrated hard disk as an example, FIG1 is a hardware structure block diagram of a method for sending indicator light signals according to an embodiment of this application. As shown in FIG1, the integrated hard disk may include one or more (only one is shown in FIG1) processors 102 (processors 102 may include, but are not limited to, processing devices such as microprocessors or programmable logic devices) and a memory 104 configured to store data. The integrated hard disk may also include a transmission device 106 configured to implement communication functions and an input / output device 108. Those skilled in the art will understand that the structure shown in FIG1 is only illustrative and does not limit the structure of the integrated hard disk. For example, the integrated hard disk may also include more or fewer components than shown in FIG1, or have a different configuration than shown in FIG1.

[0038] The memory 104 may be configured to store computer programs, such as application software programs and modules, like the computer program corresponding to the indicator light signal transmission method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the aforementioned indicator light signal transmission method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to an integrated hard disk via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0039] The transmission device 106 is configured to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider with integrated hard drives. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module configured to communicate with the Internet wirelessly.

[0040] This embodiment provides a method for transmitting indicator light signals, applied to the aforementioned integrated hard disk. Figure 2 is a flowchart of the method for transmitting indicator light signals according to an embodiment of this application. As shown in Figure 2, the process includes the following steps:

[0041] Step S202: Send N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic controller through the first type pins of N second connectors that are connected one-to-one with the N first connectors. The second connectors and the logic controller are both located on the backplane.

[0042] In this embodiment, there is a one-to-one correspondence between the N enable signals and the N first connectors, with each first connector having a first type of pin. That is, the N enable signals are sent to the first type of pins present in all N first connectors. Furthermore, the N enable signals are sent to the first type of pins of the N second connectors via these first type of pins. It should be clarified that the one-to-one correspondence between the N first connectors and the N second connectors in this embodiment can be understood as follows: assuming there are two first connectors, A and B, the first type of pins of first connector A corresponds to the first type of pins of second connector A', and the second type of pins of first connector A corresponds to the second type of pins of second connector A'. Similarly, the first type of pins of first connector B corresponds to the first type of pins of second connector B', and the second type of pins of first connector B corresponds to the second type of pins of second connector B'.

[0043] Step S204: N indicator light signals are sent to the second type pins of N first connectors through N transmission channels, so as to forward the N indicator light signals to the logic controller through the second type pins of N second connectors. Among the N enable signals, the low-level first enable signal is used to instruct the logic controller to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal is used to instruct the logic controller to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1.

[0044] In this system, there is a one-to-one correspondence between the N transmission channels and the N first connectors, and each first connector has a second type of pin. That is, the N indicator light signals are sent through the N transmission channels to the second type of pins present in all N first connectors. Furthermore, the N indicator light signals are sent to the second type of pins of the N second connectors via the second type of pins.

[0045] Through the above steps, N enable signals are sent to the first type pins of N first connectors, and then forwarded to the logic controller via the first type pins of N second connectors that correspond one-to-one with the N first connectors. Both the second connectors and the logic controller are located on a backplane. N indicator light signals are sent to the second type pins of the N first connectors via N transmission channels, and then forwarded to the logic controller via the second type pins of the N second connectors. Among the N enable signals, the low-level first enable signal instructs the logic controller to interpret the indicator light signal corresponding to the first enable signal, and the high-level second enable signal instructs the logic controller to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1. Therefore, this solves the problem in related technologies where a change in CPU type requires redesigning the lighting control logic, leading to higher design costs, and greatly enhances system compatibility.

[0046] In an exemplary embodiment, before sending N indicator signals to the second type pins of N first connectors via N transmission channels, the method further includes: when the central processing unit is connected to the backplane via a hard disk interface card, forwarding N enable signals to the logic controller via the first type pins of the N second connectors and the first type pins of the N third connectors, wherein the N third connectors are located on the hard disk interface card, the first type pins of the N third connectors are set as ground pins, and the hard disk interface card is connected to both the motherboard and the backplane; when the first type pins of the N third connectors are set as ground pins, the hard disk interface card is prohibited from adjusting the level state of the received N enable signals.

[0047] In a scenario where the CPU establishes a connection with the backplane via a hard disk interface card, N enable signals are first issued by the CPU, pass through N first connectors on the motherboard, then through the first type of pins of the N third connectors on the hard disk interface card, and finally reach the first type of pins of the N second connectors on the backplane. This allows the enable signals to be forwarded to the Complex Programmable Logic Device (CPLD) on the backplane. It is important to note that in this embodiment, the first type of pins of the N third connectors are pre-set to ground (GND) pins to ensure that the level of the N enable signals is not modified by any device on the hard disk interface card during the forwarding process. Therefore, regardless of whether the original state of the enable signal is high or low, it can remain unchanged and directly reach the logic controller on the backplane via the hard disk interface card. When the enable signal is low, the logic controller begins to interpret the corresponding indicator light signal; while a high-level enable signal instructs the logic controller to disable the corresponding indicator light signal, i.e., not to perform any lighting operation.

[0048] By setting the first type pin of the third connector in the hard drive interface card as a ground pin, the enable signal level is prevented from changing during transmission, thus achieving stable forwarding of the enable signal. This design not only simplifies the lighting control logic but also reduces the complexity of hardware design and maintenance.

[0049] In one exemplary embodiment, before forwarding N enable signals to the logic controller via the first type pins of N second connectors and the first type pins of N third connectors, the method further includes: forwarding N indicator light signals and N enable signals to the same fourth connector via the N first connectors, wherein the fourth connector, the N third connectors, and the controller are all disposed on a hard disk interface card, and the fourth connector and the N third connectors are connected through the controller; forwarding the N indicator light signals and N enable signals to the controller via the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected through the first interface bus; the controller is configured to forward the N indicator light signals and N enable signals to the N third connectors.

[0050] As shown in Figure 6, N indicator light signals and N enable signals from the CPU are received by N first connectors on the motherboard. Then, these N indicator light signals and N enable signals are forwarded to the fourth connector on the hard drive interface card (equivalent to the HSCON connector in Figure 6). The fourth connector not only receives all signals forwarded from the first connectors but also forwards the received N indicator light signals and N enable signals to the controller via the first interface bus (equivalent to the PCIe (Peripheral Component Interconnect Express) connecting the HSCON (High Speed ​​Connector) and the controller on the Tri-mode card in Figure 6). The controller receives the N indicator light signals and N enable signals from the fourth connector via the first interface bus and forwards them to the third connector via the second interface bus (equivalent to the PCIe connecting the controller and the MCIO (Multipurpose Card Input / Output) connector on the Tri-mode card in Figure 6).

[0051] It should be clarified that the second interface bus corresponds one-to-one with the third interface bus on the motherboard. Assuming there are two third interface buses on the motherboard, namely PCIE_PEx_[0:7] and PCIE_PEx_[8:15], then the Tri-mode card (equivalent to the hard disk interface card in this embodiment) also has two corresponding second interface buses, PCIE_PEx_[0:7] and PCIE_PEx_[8:15], to ensure that the N indicator light signals and N enable signals are not confused when transmitted to the third connector through the second interface bus.

[0052] In this embodiment, the Tri-mode card efficiently and accurately forwards N indicator light signals and N enable signals from the CPU through a fourth connector, ensuring that these indicator light signals and enable signals can stably reach the N third connectors on the hard disk interface card and be correctly processed and applied.

[0053] In an exemplary embodiment, after forwarding N indicator signals and N enable signals to the controller via the fourth connector and the first interface bus, the method further includes: forwarding the N indicator signals to N third connectors via the controller and N second interface buses, so as to forward the N indicator signals to the logic controller via the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

[0054] As shown in Figure 6, when N indicator light signals arrive at the third connector (equivalent to the MCIO connector on the Tri-mode card in Figure 6), the N indicator light signals are transferred to the second type pins (A8 / A9) of the second connector (MCIO connector on the backplane) via the second type pins (B8 / B9) of the third connector. Then, through cable connections, these signals are stably transmitted to the corresponding second type pins of the N second connectors on the backplane. Finally, the N indicator light signals are forwarded to the logic controller (CPLD) via the second connectors. The logic controller processes and interprets the signals to control the display status of the LED (Light Emitting Diode) indicator lights on the backplane.

[0055] In this embodiment, by forwarding N indicator light signals to the same controller, and then transmitting them to N third connectors through N second interface buses, and forwarding the N indicator light signals to the logic controller through the second type pins of the third connectors and the second type pins of the second connectors, the complex signal paths and hardware matching requirements of traditional designs are avoided, reducing design costs and maintenance difficulties.

[0056] In an exemplary embodiment, before sending the N enable signals to the first type of pins of the N first connectors, the method further includes: if the state of the virtual machine device queue corresponding to the fourth interface bus among the N third interface buses is open, controlling the enable signal corresponding to the fourth interface bus to be a first enable signal, wherein the addresses of the N third interface buses are consistent with the addresses of the N second interface buses; and / or, if the state of the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is closed, controlling the enable signal corresponding to the fifth interface bus to be a second enable signal, wherein the N third interface buses are respectively connected to the central processing unit and the N first connectors.

[0057] In some embodiments, assuming that the VMD (Virtual Machine Device Queue) state corresponding to 3 out of the N third interface buses (i.e., the fourth interface bus) is enabled, the enable signal corresponding to these 3 interface buses is the first enable signal (i.e., the enable signal in a low-level state). Assuming that the VMD state corresponding to 5 out of the N third interface buses (i.e., the fifth interface bus) is disabled, the enable signal corresponding to these 5 interface buses is the second enable signal (i.e., the enable signal in a high-level state).

[0058] It should be clarified that the addresses of the N third interface buses are consistent with the addresses of the N second interface buses. This means that during the transmission of the enable signal, a mapping relationship is formed between the N third interface buses and the N second interface buses, ensuring that the enable signal is accurately transmitted between the CPU and the backplane.

[0059] In this embodiment, by monitoring and responding to the state of the VMD, the high and low levels of the enable signal are intelligently adjusted, and the indicator light signals are controlled to turn on and off according to the high and low levels of the enable signal, thus avoiding accidental activation of the lights when the VMD is off and improving the accuracy of the indicator signals.

[0060] In an exemplary embodiment, before sending the N enable signals to the first type of pins of the N first connectors respectively, the method further includes: obtaining the first device address of the hard disk interface card and determining the second device addresses of the N target hard disks corresponding to the N third interface buses; and setting the second device address to the first device address through a write operation.

[0061] In some embodiments, the VPP (Virtual Pin Port) slave address (i.e., the second device address) of all PCIe Ports (i.e., the third interface bus) is set to be consistent with the slave address (i.e., the first device address) of the Tri-mode card. For example, the VPP slave address of the PCIe Port and the slave address of the Tri-mode card are both set to 0x40. In some embodiments, the VPP_CH1 channel address corresponding to PCIE_PEx_[0:7] is set to 0xE0, and the VPP slave address is 0x40. The VPP_CH2 channel address corresponding to PCIE_PEx_[8:15] is set to 0xE0, and the VPP slave address can also be 0x40. The purpose of this is that although the devices under each PCIe Port share the same VPP slave address (0x40), the CPU can still precisely control the LED lighting behavior of each target device due to the different channel addresses.

[0062] This design strategy not only simplifies the hardware chain but also improves the system's compatibility with different device configurations, ensuring that the lighting control logic remains consistent between the CPU direct-connect backplane and the Tri-mode card direct-connect backplane without requiring additional hardware or software adjustments.

[0063] In one exemplary embodiment, setting a second device address to a first device address via a write operation includes: determining the target location of a first character that is inconsistent between the second device address and the first device address; obtaining the second character corresponding to the target location from the first device address; and modifying the first character at the target location in the second device address to the second character, so as to modify the second device address to be consistent with the first device address.

[0064] In some embodiments, it is checked whether the second device address is exactly the same as the first device address. If the second device address is not exactly the same as the first device address, the location of the first different character in the two addresses is determined, i.e., the target location. For example, if the first device address is "0x12345678" and the second device address is "0x1234567A", then the different character is "A", and the target location is the last character of the address. The character at the target location is extracted from the first device address; in the example above, the extracted character is "8". Next, the different character at the target location in the second device address, which is "A" in this example, is changed to the character "8" obtained from the first device address to ensure that the second device address and the first device address are identical.

[0065] In this embodiment, the address consistency design enables the system to be seamlessly compatible with different types of CPUs and Tri-mode cards, and the consistent device address simplifies the transmission path of the lighting signal, reduces communication latency and errors, and ensures the accurate transmission of the lighting signal.

[0066] In an exemplary embodiment, after forwarding N indicator light signals to the logic controller via the second type pins of the N second connectors, the method further includes: if a first target hard drive among the N target hard drives fails, receiving an interrupt request issued by the first target hard drive via the second connector corresponding to the first target hard drive through the sixth interface bus corresponding to the first target hard drive, wherein the N target hard drives are disposed on a backplane; generating an interrupt command based on the interrupt request, and sending the interrupt command via the sixth interface bus to the second type pin of the first connector corresponding to the sixth interface bus, so as to send the interrupt command to the logic controller via the second type pin of the second connector corresponding to the sixth interface bus to shut down the first target hard drive.

[0067] It should be clarified that in this embodiment, N target hard drives are set on the backplane, and the indicator light signals are used to reflect the operating status of the target hard drives. For example, an indicator light on means that the target hard drive is in normal working condition, and an indicator light off means that the target hard drive has malfunctioned.

[0068] In an exemplary embodiment, after shutting down the first target hard disk, the method further includes: if the difference between the time when the first target hard disk was shut down and the current time is greater than a preset time, sending a startup command to the logic controller through the second type pin of the first connector corresponding to the sixth interface bus and the second type pin of the second connector corresponding to the sixth interface bus to restart the first target hard disk.

[0069] In some embodiments, assuming that 3 out of N target hard drives (i.e., the first target hard drive) fail, these 3 target hard drives will send interrupt requests to the CPU. These 3 target hard drives send the interrupt requests to their corresponding second connectors via their three interface buses (i.e., the sixth interface bus). Since the second connector is connected to the first connector, the interrupt requests are transmitted to the CPU through the first connector. Upon receiving the interrupt requests, the CPU generates an interrupt command and then sends the interrupt command to the logic controller via the sixth interface bus, the second type of pin of the first connector corresponding to the sixth interface bus, and the second type of pin of the second connector corresponding to the sixth interface bus. Upon receiving the interrupt command, the logic controller will immediately shut down the first target hard drives to prevent the failed hard drives from affecting the overall system performance.

[0070] Assuming the hard drive failure is temporary or a software-related issue, a restart attempt is needed. Therefore, if the difference between the hard drive's shutdown time and the current time exceeds a preset time, a boot command is sent to the logic controller via the sixth interface bus, using the second type pins of the first and second connectors. This preset time threshold ensures the CPU has sufficient time for fault diagnosis and status assessment before attempting to restart the hard drive, avoiding instability and resource waste caused by frequent restarts. Upon receiving the boot command, the logic controller immediately executes the restart operation for the first target hard drive. This process may involve resetting the hard drive's hardware state, refreshing firmware configuration, or re-establishing data communication links, all aimed at attempting to restore the hard drive to its normal operating state.

[0071] In this embodiment, an interrupt command is rapidly generated based on the interrupt request issued by the first target hard drive, enabling rapid fault response. When the difference between the shutdown time of the first target hard drive and the current time exceeds a preset time, a boot command can be automatically sent through the same communication path to restart the first target hard drive. This recovery mechanism ensures that the system can attempt to restore the normal operation of the hard drive without manual intervention, enhancing the system's self-healing capability and availability.

[0072] In one exemplary embodiment, before sending the N enable signals to the first type of pins of the N first connectors, the method further includes: sending a target address via an integrated circuit interconnect bus to determine a target IO expander communicating with a central processing unit from a plurality of IO (Input / Output) expanders, wherein the plurality of IO expanders are connected to the central processing unit; sending a register address to the target IO expander to determine a target register controlling the N enable signals, wherein the target register exists in the internal storage space of the target IO expander; writing 0 to a target location in the target register to control the first enable signal to be low, and writing 1 to the target location to control the second enable signal to be high.

[0073] The CPU sends target address signals via the I2C bus (Inter-Integrated Circuit). The I2C bus is a two-wire serial bus used for communication between a microcontroller and multiple peripheral devices. In this scenario, since multiple I / O expanders are connected to the CPU, the CPU needs to send specific address signals to determine the target I / O expander with which it needs to communicate. Once the target I / O expander is determined, the CPU sends a register address signal to that expander via the I2C bus. I / O expanders typically include multiple registers configured to store and control different I / O signal states. By sending a specific register address, the CPU can accurately locate the target register controlling N enable signals. This step ensures that subsequent write operations directly affect the register managing the enable signals, thus achieving precise signal control. After the target register is successfully located, the CPU performs a write operation to control either the first enable signal to be low (0) or the second enable signal to be high (1). This operation is performed directly at the target location in the target register; by changing the specific location in the register, the state of the enable signals can be adjusted instantly. For example, if a bit in the target register is set to 0, the associated first enable signal will be pulled low; conversely, if the bit is set to 1, the second enable signal will be pulled high.

[0074] In this embodiment, the CPU can intelligently select and communicate with multiple I / O expanders through address communication via the I2C bus. Even if there are more I / O expanders or enable signals, the control logic can be easily expanded and adapted through dynamic address sending and register positioning.

[0075] In an exemplary embodiment, after forwarding N indicator light signals to a logic controller via the second type of pins of the N second connectors, the method further includes: if a first enable signal exists among the N enable signals, lighting the indicator light corresponding to the first enable signal via the logic controller; and if a second enable signal exists among the N enable signals, turning off the indicator light corresponding to the second enable signal via the logic controller.

[0076] When a first enable signal is present among the N enable signals (i.e., the first enable signal is low), it is considered an enable or activation signal. In this case, the logic controller (e.g., a CPLD) detects the presence of the first enable signal and interprets it as a command to light up the indicator light. Therefore, the indicator light corresponding to the first enable signal will be lit. Conversely, when a second enable signal is present among the N enable signals (i.e., the second enable signal is high), it is considered a disable or mask signal. When the logic controller detects the second enable signal, it interprets it as a command to turn off the indicator light. Therefore, the indicator light corresponding to the second enable signal will be turned off.

[0077] In this embodiment, by distinguishing different enable signal states, the logic controller can accurately control the indicator lights to turn on or off, which not only improves the user interface's friendliness and the accuracy of information, but also simplifies hardware design and software control, reduces costs, and enhances the overall performance and reliability of the system.

[0078] To better understand the process of sending the indicator light signal, the following description, in conjunction with optional embodiments, further illustrates the method of sending the indicator light signal, but is not intended to limit the technical solution of the embodiments of this application.

[0079] Figure 3 is a first schematic diagram of a method for transmitting indicator light signals according to an embodiment of this application. As shown in Figure 3, the method includes the following steps:

[0080] In related technologies, the CPU, as the master device, can communicate with multiple slave devices to control the LED indicators of various Peripheral Component Interconnect Express Ports (PCIe Ports). The core of this design is that each CPU is equipped with only one set of Virtual Pin Port (VPP) buses, and this VPP bus needs to cover the management of indicator signals for all PCIe Ports under the CPU. Therefore, when designing the motherboard, this VPP bus is connected to a separate connector to facilitate signal transmission and management.

[0081] To differentiate between different PCIe ports, the motherboard introduces the concept of Strap Pins (configuration pins). Strap Pins are specific pins on the PCIe connector used to identify different PCIe ports, enabling precise control of indicator light signals in complex system environments. However, the validity of the VPP signal is affected by the Virtual Machine Device Queues (VMD) status. When the VMD is off, the VPP signal may transmit incorrect indicator light signals, leading to inconsistent LED status and hindering system status monitoring.

[0082] To solve the above technical problems, the CPU obtains the VMD status information corresponding to the PCIe Port and transmits this VMD status information to the CPLD on the backplane via the I2C bus. The CPLD is the indicator light management unit on the backplane. The information transmission between the CPU and the CPLD ensures that the CPLD can accurately parse the VPP indicator light signal and execute the correct LED control instructions according to the VMD status.

[0083] In some embodiments, in the backplane design, the VPP Header and the Multi-purpose Card I / O (MCIO) connector are connected to the corresponding connectors on the motherboard via cables to transmit VPP indicator signals and PCIe signals. Simultaneously, the I2C Header is also connected to the I2C bus on the motherboard via a cable to receive VMD status information transmitted by the CPU. Upon receiving the VPP signal, the CPLD first uses the Strap Pin connected to the MCIO connector to identify which PCIe Port's information it is receiving, and then parses the VMD status of the corresponding PCIe Port from the I2C bus. Based on the VMD status determination, if VMD is enabled, the CPLD extracts the indicator signal of the VPP address corresponding to that PCIe Port from the VPP signal and controls the corresponding hard drive's LED indicator status through the General Purpose Input / Output (GPIO) interface, achieving accurate indicator control.

[0084] In this design, the Strap Pin, PCIe Port, VPP address, and VMD status are closely linked. The backplane CPLD must first obtain the PCIe Port information through the Strap Pin, then parse the corresponding VMD status from the I2C bus, and obtain the VPP address. Finally, it ensures that the indicator light signal parsed from the VPP signal is correct, thereby accurately controlling the LED indicator status of the hard drive.

[0085] Figure 4 is a second schematic diagram of a method for transmitting indicator light signals according to an embodiment of this application. As shown in Figure 4, the method includes the following steps:

[0086] The Tri-mode card, as a multi-functional interface card, uses VPP signals to control the indicator light status of hard drives, thus providing a direct indication of the hard drive's operating status. The Tri-mode card connects to the hard drive. The Tri-mode card integrates the VPP signals into each MCIO connector, with each connector containing two sets of VPP indicator signals. These two sets of signals carry the indicator light signals for all hard drives connected to that MCIO connector. This means that regardless of the number of hard drives connected to the connector, only one set of VPP signals needs to be analyzed to obtain the indicator light control commands for all hard drives, thereby achieving unified control and indicator light operation for all hard drives connected to the entire connector.

[0087] In some embodiments, the MCIO connector of the Tri-mode card is directly connected to the MCIO connector on the backplane via a cable. In the backplane design, the first set of VPP signals from the MCIO connector is routed to the CPLD. This allows the CPLD to receive and analyze the first set of VPP signals from the Tri-mode card, extracting the indicator light signals used to control the two hard drives. Based on the analyzed information, the CPLD controls the LEDs on the corresponding hard drives via its output GPIO signals, providing visual feedback on the hard drive status.

[0088] Figure 5 is a third schematic diagram of a method for transmitting indicator light signals according to an embodiment of this application. As shown in Figure 5, the method includes the following steps:

[0089] In this embodiment, the CPU's original VPP signal (equivalent to the indicator light signal in this embodiment) is connected to an I2C switch (equivalent to the channel expansion component in this embodiment). Through the I2C switch, the original single VPP signal is expanded into two independent transmission channels: VPP_CH1 and VPP_CH2. Each transmission channel has a specific function: VPP_CH1 is responsible for transmitting the indicator light signal of the PCIe x8 port [0:7] (equivalent to the first of the two third interface buses in this embodiment), while VPP_CH2 is responsible for transmitting information from the PCIe x8 port [8:15] (equivalent to the second of the two third interface buses in this embodiment). This design means that the indicator light commands for each PCIe x8 port are transmitted and controlled independently, improving the accuracy and flexibility of indicator light control.

[0090] Meanwhile, to ensure compatibility with the Tri-mode card (equivalent to the hard drive interface card in this embodiment), two sets of VPP signals (VPP_CH1 and VPP_CH2) are connected to the B8 / B9 pins of the MCIO connector (equivalent to the second type of pins in this embodiment). These are specific points on the Tri-mode card used to receive indicator light signals. This ensures that the VPP signal reception method and pin definitions remain consistent whether the CPU is directly connected to the backplane or connected via the Tri-mode card. Furthermore, the VPP slave addresses of all PCIe ports are set to the same value as the slave address of the Tri-mode card; for example, both the PCIe port VPP slave address and the Tri-mode card slave address are set to 0x40. In some embodiments, in the Basic Input / Output System (BIOS), the VPP_CH1 channel address corresponding to PCIE_PEx_[0:7] is set to 0xE0, and the VPP slave device address is 0x40. The VPP_CH2 channel address corresponding to PCIE_PEx_[8:15] is also set to 0xE0, and the VPP slave device address can also be 0x40. The purpose of this is that although devices under each PCIe Port share the same VPP slave device address (0x40), the CPU can still precisely control the LED behavior of each device due to the different channel addresses. This design strategy not only simplifies the hardware link but also improves the system's compatibility with different device configurations, ensuring that the LED control logic remains consistent between the CPU direct-connect backplane and the Tri-mode card direct-connect backplane without additional hardware or software adjustments.

[0091] In this embodiment, the IO Expander (equivalent to the IO expander in this embodiment) and the CPU are connected via an I2C bus (equivalent to the integrated circuit interconnect bus in this embodiment). The IO Expander expands two enable signals: FM_VPP_CH1_EN_N and FM_VPP_CH2_EN_N. These two enable signals are connected to the B28 pins of the two MCIO connectors (equivalent to the first type of pins in this embodiment) to control the enabled or disabled state of the corresponding VPP channels (VPP_CH1 and VPP_CH2). Taking VPP_CH1 as an example, when the VMD state corresponding to PCIE_PEx_[0:7] is enabled, the CPU will set FM_VPP_CH1_EN_N to a low level via the I2C bus, thereby allowing the CPLD on the backplane to parse the indicator light signal of VPP_CH1. When the VMD state is disabled, the CPU sets FM_VPP_CH1_EN_N to a high level, which means that the CPLD needs to shield the indicator light signal of VPP_CH1 to avoid triggering the indicator light behavior under inappropriate conditions. Similarly, the control logic of VPP_CH2 is consistent with that of VPP_CH1, ensuring the consistency and effectiveness of the control of all PCIe port indicator lights.

[0092] In terms of hardware connection, the MCIO connector on the backplane (equivalent to the second connector in this embodiment) is connected to the MCIO connector on the motherboard (equivalent to the first connector in this embodiment) via a cable. In some embodiments, when the backplane is connected to the motherboard, the B8 / B9 pin of the motherboard MCIO connector transmits the VPP signal to the A8 / A9 pin of the backplane MCIO connector (equivalent to the second type of pin in this embodiment), and then connects the CPLD (equivalent to the logic controller in this embodiment) on the backplane to the A8 / A9 pin and the A28 pin via a cable. The CPLD determines whether to parse the VPP signal on the A8 / A9 pin and whether to perform indicator light control based on the state of the FM_VPPx_EN_N signal received from the A28 pin (equivalent to the first type of pin in this embodiment). If the FM_VPPx_EN_N signal is low, the CPLD parses the VPP signal and performs the corresponding indicator light behavior; conversely, if the signal is high, the CPLD will not parse the VPP signal to avoid misoperation or incorrect indicator light indication.

[0093] The above design not only enables the CPU to control complex indicator lights on the direct-connected backplane, but also ensures the consistency and compatibility of the indicator light control scheme when replacing or using different types of CPUs or Tri-mode cards by unifying the pin definitions and control logic with the Tri-mode card.

[0094] Figure 6 is a fourth schematic diagram of an indicator light signal transmitting device according to an embodiment of this application. As shown in Figure 6, it includes the following steps:

[0095] In this embodiment, the motherboard is connected to the HSCONN of the Tri-mode card (equivalent to the fourth connector in this embodiment) via a cable to transmit N enable signals and N indicator light signals to the Tri-mode card. The HSCONN transmits the N enable signals and N indicator light signals to the Tri-mode card's controller via the PCIe bus. The controller then forwards the N enable signals and N indicator light signals to the Tri-mode card's MCIO connector (equivalent to the third connector in this embodiment). It is worth noting that each MCIO connector in the Tri-mode card integrates two sets of VPP signals (B8 / B9 and B26 / B27), but both sets of signals include the indicator light signals for all connected target hard drives. Therefore, only one set of VPP signals needs to be parsed to control the indicator light status of all target hard drives connected to that connector.

[0096] In this embodiment, the VPP signal of pins B8 / B9 is selected as the target for analyzing the indicator light behavior. When the Tri-mode card is connected to the backplane, the MCIO connector on the backplane is connected to the MCIO connector on the motherboard via a cable design with pins on the A and B sides reversed. This ensures that the VPP signal of pins B8 / B9 of the Tri-mode card can pass smoothly through the cable and ultimately reach pins A8 / A9 of the MCIO connector on the backplane, and then be transmitted to the CPLD for signal analysis. The CPLD, as the control center on the backplane, is responsible for receiving and analyzing these VPP signals, resolving the indicator light signal of address 0x40, thereby precisely controlling the LED indicators of each hard drive.

[0097] Meanwhile, pin B28 of the Tri-mode card's MCIO connector serves as a ground signal, connected via a cable to pin A28 of the backplane's MCIO connector. In this design, the ground signal on pin B28 stably pulls the enable signal FM_VPPx_EN_N low. This effectively tells the CPLD on the backplane to always resolve the VPP signal from pins A8 / A9, regardless of the VMD's state. In this way, even in a Tri-mode card environment, the CPLD can stably and accurately resolve the VPP signal and control the hard drive's LED display status information.

[0098] In summary, the design presented in this embodiment achieves compatible transmission and parsing of VPP indicator signals between the Tri-mode card and the backplane. It not only simplifies the complexity of hardware and software design but also ensures that the indicator light control system on the backplane accurately reflects the working status of the hard drive under the Tri-mode card regardless of CPU type changes, effectively overcoming the problem of redesigning indicator light control logic due to CPU type changes in related technologies.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0100] Figure 7 is a structural block diagram of an integrated hard disk for transmitting indicator light signals according to an embodiment of this application. As shown in Figure 7, the integrated hard disk includes:

[0101] The motherboard 700 has a central processing unit 704 and N first connectors 706. The transmission channels of the virtual pin interface of the central processing unit 704 have been expanded to N through the channel expansion component. The N transmission channels are connected one-to-one with the N first connectors 706 on the motherboard.

[0102] Backplane 702, on which N second connectors 710 and logic controllers 708 are provided;

[0103] The central processing unit 704 is configured to send N enable signals to the first type pins of N first connectors 706 respectively, so as to forward the N enable signals to the logic controller 708 through the first type pins of N second connectors 710 connected one-to-one with the N first connectors 706. The N second connectors 710 and the logic controller 708 are disposed on the backplane 702. It also sends N indicator light signals to the second type pins of the N first connectors 706 respectively through N transmission channels, so as to forward the N indicator light signals to the logic controller 708 through the second type pins of the N second connectors 710. In the N enable signals, the low-level first enable signal is used to instruct the logic controller 708 to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal is used to instruct the logic controller 708 to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1.

[0104] The integrated hard drive also includes: a hard drive interface card 712 connected to both the motherboard 700 and the backplane 702; and a central processing unit 704, configured to forward N enable signals to a logic controller 708 via a fourth connector 716, the first type pins of N second connectors 710, and the first type pins of N third connectors 714 when the central processing unit 704 is connected to the backplane 702 through the hard drive interface card 712. The N third connectors 714 are located on the hard drive interface card 712, and the first type pins of the N third connectors 714 are set as ground pins. When the first type pins of the N third connectors 714 are set as ground pins, the hard drive interface card 712 is prohibited from adjusting the level of the received N enable signals.

[0105] In this embodiment, N enable signals are respectively sent to the first type pins of N first connectors, so that the N enable signals are forwarded to the logic controller through the first type pins of N second connectors that correspond one-to-one with the N first connectors. Both the second connectors and the logic controller are located on a backplane. N indicator light signals are respectively sent to the second type pins of the N first connectors through N transmission channels, so that the N indicator light signals are forwarded to the logic controller through the second type pins of the N second connectors. Among the N enable signals, the low-level first enable signal instructs the logic controller to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal instructs the logic controller to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1. This technical solution solves the problem in related technologies where a change in CPU type necessitates a redesign of the lighting control logic, leading to high design costs.

[0106] In an exemplary embodiment, the hard disk interface card 712 is further configured to forward N enable signals to a logic controller via the first type pins of N second connectors and the first type pins of N third connectors when the central processing unit is connected to the backplane through the hard disk interface card. The N third connectors are located on the hard disk interface card, and the first type pins of the N third connectors are set as ground pins. The hard disk interface card is connected to both the motherboard and the backplane. When the first type pins of the N third connectors are set as ground pins, the hard disk interface card is prohibited from adjusting the level of the received N enable signals.

[0107] In one exemplary embodiment, the central processing unit 704 is further configured to forward N indicator light signals and N enable signals to the same fourth connector via N first connectors, wherein the fourth connector, the N third connectors, and the controller are all located on a hard disk interface card, and the fourth connector and the N third connectors are connected through the controller; the N indicator light signals and N enable signals are forwarded to the controller via the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected through the first interface bus; the controller is configured to forward the N indicator light signals and N enable signals to the N third connectors.

[0108] In one exemplary embodiment, the hard disk interface card 712 is further configured to forward N indicator light signals to N third connectors via a controller and N second interface buses, so as to forward the N indicator light signals to a logic controller via the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

[0109] In one exemplary embodiment, the central processing unit 704 is further configured to, when the state of the virtual machine device queue corresponding to the fourth interface bus among the N third interface buses is open, control the enable signal corresponding to the fourth interface bus to be a first enable signal, wherein the addresses of the N third interface buses are the same as the addresses of the N second interface buses; and / or, when the state of the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is closed, control the enable signal corresponding to the fifth interface bus to be a second enable signal, wherein the N third interface buses are respectively connected to the central processing unit and the N first connectors.

[0110] In one exemplary embodiment, the central processing unit 704 is further configured to obtain the first device address of the hard disk interface card and determine the second device addresses of the N target hard disks corresponding to the N third interface buses; and set the second device address to the first device address through a write operation.

[0111] In an exemplary embodiment, the central processing unit 704 is further configured to determine the target location of the first character in the second device address that is inconsistent with the first device address; obtain the second character corresponding to the target location from the first device address; and modify the first character at the target location in the second device address to the second character so as to modify the second device address to be consistent with the first device address.

[0112] In an exemplary embodiment, the central processing unit 704 is further configured to, in the event that a first target hard disk among the N target hard disks fails, receive an interrupt request issued by the first target hard disk through a second connector corresponding to the first target hard disk via a sixth interface bus corresponding to the first target hard disk, wherein the N target hard disks are disposed on a backplane; generate an interrupt instruction based on the interrupt request, and send the interrupt instruction to a second type pin of the first connector corresponding to the sixth interface bus via the sixth interface bus, so as to send the interrupt instruction to a logic controller via the second type pin of the second connector corresponding to the sixth interface bus, thereby shutting down the first target hard disk.

[0113] In an exemplary embodiment, the central processing unit 704 is further configured to send a startup command to the logic controller via the second type pin of the first connector corresponding to the sixth interface bus and the second type pin of the second connector corresponding to the sixth interface bus, in order to restart the first target hard disk, if the difference between the time when the first target hard disk was shut down and the current time is greater than a preset time.

[0114] In one exemplary embodiment, the central processing unit 704 is further configured to send a target address via an integrated circuit interconnect bus to determine a target I / O extender communicating with the central processing unit from among a plurality of I / O extenders, wherein the plurality of I / O extenders are connected to the central processing unit; send a register address to the target I / O extender to determine a target register controlling N enable signals, wherein the target register exists in the internal storage space of the target I / O extender; write 0 to a target location in the target register to control a first enable signal to be low, and write 1 to the target location to control a second enable signal to be high.

[0115] In an exemplary embodiment, the central processing unit 704 is further configured to, when a first enable signal exists among the N enable signals, illuminate the indicator light corresponding to the first enable signal via a logic controller; and when a second enable signal exists among the N enable signals, extinguish the indicator light corresponding to the second enable signal via a logic controller.

[0116] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0117] Optionally, in this embodiment, the storage medium may be configured to store program code for performing the following steps:

[0118] S1, send N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic controller through the first type pins of N second connectors that are connected one-to-one with the N first connectors. The second connectors and the logic controller are both located on the backplane.

[0119] S2, N indicator light signals are sent to the second type pins of N first connectors through N transmission channels, so as to forward the N indicator light signals to the logic controller through the second type pins of N second connectors. Among the N enable signals, the low-level first enable signal is used to instruct the logic controller to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal is used to instruct the logic controller to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1.

[0120] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0121] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0122] Optionally, in this embodiment, the computer program described above can be configured to perform the following steps:

[0123] S1, send N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic controller through the first type pins of N second connectors that are connected one-to-one with the N first connectors. The second connectors and the logic controller are both located on the backplane.

[0124] S2, N indicator light signals are sent to the second type pins of N first connectors through N transmission channels, so as to forward the N indicator light signals to the logic controller through the second type pins of N second connectors. Among the N enable signals, the low-level first enable signal is used to instruct the logic controller to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal is used to instruct the logic controller to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1.

[0125] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0126] It is obvious to those skilled in the art that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be integrated on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0127] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for transmitting indicator light signals, characterized in that, This is applied to an integrated hard drive, which includes: a motherboard, a backplane connected to the motherboard, and the transmission channels of the virtual pin interface of the central processing unit on the motherboard are expanded to N through a channel expansion component. Each of the N transmission channels is connected to one of N first connectors on the motherboard, including: N enable signals are sent to the first type pins of N first connectors respectively, so that the N enable signals are forwarded to the logic controller through the first type pins of N second connectors that are connected one-to-one with the N first connectors. The second connectors and the logic controller are both disposed on the backplane. N indicator lights are transmitted to the second type pins of the N first connectors through N transmission channels, and then forwarded to the logic controller through the second type pins of the N second connectors. Among the N enable signals, the low-level first enable signal is used to instruct the logic controller to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal is used to instruct the logic controller to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1.

2. The method for transmitting indicator light signals according to claim 1, characterized in that, The first type of pin of the first connector is connected to the first type of pin of the second connector, and the second type of pin of the first connector is connected to the second type of pin of the second connector.

3. The method for transmitting indicator light signals according to claim 1, characterized in that, Before sending N indicator light signals to the second type of pins of the N first connectors via the N transmission channels, the method further includes: When the central processing unit is connected to the backplane via a hard disk interface card, the N enable signals are forwarded to the logic controller via the first type pins of the N second connectors and the first type pins of the N third connectors. The N third connectors are located on the hard disk interface card, and the first type pins of the N third connectors are set as ground pins. The hard disk interface card is connected to both the motherboard and the backplane. When the first type of pins of the N third connectors are set as ground pins, the hard disk interface card is prohibited from adjusting the level state of the received N enable signals.

4. The method for transmitting indicator light signals according to claim 3, characterized in that, Before forwarding the N enable signals to the logic controller via the first type pins of the N second connectors and the first type pins of the N third connectors, the method further includes: The N indicator lights and the N enable signals are all forwarded to the same fourth connector through the N first connectors. The fourth connector, the N third connectors and the controller are all located on the hard disk interface card. The fourth connector and the N third connectors are connected through the controller. The N indicator lights and the N enable signals are forwarded to the controller via the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected via the first interface bus; the controller is configured to forward the N indicator lights and the N enable signals to the N third connectors.

5. The method for transmitting indicator light signals according to claim 4, characterized in that, After forwarding the N indicator lights and the N enable signals to the controller via the fourth connector and the first interface bus, the method further includes: The controller and N second interface buses forward the N indicator lights to the N third connectors, and the N indicator lights are forwarded to the logic controller via the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

6. The method for transmitting indicator light signals according to claim 5, characterized in that, The N second interface buses correspond one-to-one with the N third interface buses on the motherboard, and the N third interface buses are respectively connected to the central processing unit and the N first connectors.

7. The method for transmitting indicator light signals according to claim 1, characterized in that, Before sending the N enable signals to the first type of pins of the N first connectors respectively, the method further includes: If, among the N third interface buses, the virtual machine device queue corresponding to the fourth interface bus is in an open state, the enable signal corresponding to the fourth interface bus is controlled to be the first enable signal, wherein the addresses of the N third interface buses are consistent with the addresses of the N second interface buses; and / or, When the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is in a closed state, the enable signal corresponding to the fifth interface bus is controlled to be the second enable signal, wherein the N third interface buses are respectively connected to the central processing unit and the N first connectors.

8. The method for transmitting indicator light signals according to claim 1, characterized in that, Before sending the N enable signals to the first type of pins of the N first connectors respectively, the method further includes: Obtain the first device address of the hard disk interface card and determine the second device addresses of the N target hard disks corresponding to the N third interface buses. The hard disk interface card is connected to the central processing unit and the backplane. The second device address is set to the first device address through a write operation.

9. The method for transmitting indicator light signals according to claim 8, characterized in that, Setting the second device address to the first device address via a write operation includes: Determine the target location of the first character in the second device address that is inconsistent with the first device address; Obtain the second character corresponding to the target location from the first device address; The first character at the target location in the second device address is modified to the second character, so that the second device address is consistent with the first device address.

10. The method for transmitting indicator light signals according to claim 8, characterized in that, The channel addresses of the N target hard disks are all different.

11. The method for transmitting indicator light signals according to claim 1, characterized in that, After forwarding the N indicator light signals to the logic controller via the second type of pins of the N second connectors, the method further includes: If the first target hard drive among the N target hard drives fails, the interrupt request sent by the first target hard drive through the second connector corresponding to the first target hard drive is received through the sixth interface bus corresponding to the first target hard drive, wherein the N target hard drives are disposed on the backplane; An interrupt instruction is generated based on the interrupt request, and the interrupt instruction is sent to the second type pin of the first connector corresponding to the sixth interface bus through the sixth interface bus, so as to send the interrupt instruction to the logic controller through the second type pin of the second connector corresponding to the sixth interface bus, so as to shut down the first target hard disk.

12. The method for transmitting indicator light signals according to claim 11, characterized in that, The N indicator lights are used to indicate the operating status of the corresponding target hard drive.

13. The method for transmitting indicator light signals according to claim 11, characterized in that, After shutting down the first target hard drive, the method further includes: If the difference between the time when the first target hard disk was shut down and the current time is greater than a preset time, a startup command is sent to the logic controller through the second type of pin of the first connector corresponding to the sixth interface bus and the second type of pin of the second connector corresponding to the sixth interface bus to restart the first target hard disk.

14. The method for transmitting indicator light signals according to claim 1, characterized in that, Before sending the N enable signals to the first type of pins of the N first connectors respectively, the method further includes: The target address is sent via an integrated circuit interconnect bus to determine the target I / O expander that communicates with the central processing unit from a plurality of I / O expanders, wherein the plurality of I / O expanders are connected to the central processing unit; Send a register address to the target I / O extender to determine the target register that controls the N enable signals, wherein the target register exists in the internal storage space of the target I / O extender; Write 0 to the target position of the target register to control the first enable signal to be low, and write 1 to the target position to control the second enable signal to be high.

15. The method for transmitting indicator light signals according to claim 1, characterized in that, After forwarding the N indicator light signals to the logic controller via the second type of pins of the N second connectors, the method further includes: If the first enable signal is present among the N enable signals, the indicator light corresponding to the first enable signal is illuminated by the logic controller. If the second enable signal is present among the N enable signals, the indicator light corresponding to the second enable signal is turned off by the logic controller.

16. An integrated hard disk, characterized in that, include: The motherboard has a central processing unit and N first connectors. The transmission channels of the virtual pin interface of the central processing unit have been expanded to N through a channel expansion component. The N transmission channels are connected one-to-one with the N first connectors on the motherboard. A backplane, wherein N second connectors and logic control devices are provided on the backplane; The central processing unit is configured to send N enable signals to the first type of pins of N first connectors respectively, so as to forward the N enable signals to the logic controller through the first type of pins of N second connectors that are connected one-to-one with the N first connectors. The N second connectors and the logic controller are disposed on a backplane. The central processing unit also sends N indicator lights to the second type of pins of the N first connectors respectively through the N transmission channels, so as to forward the N indicator lights to the logic controller through the second type of pins of the N second connectors. In this configuration, a low-level first enable signal among the N enable signals is used to instruct the logic controller to parse the indicator light signal corresponding to the first enable signal, and a high-level second enable signal among the N enable signals is used to instruct the logic controller to block the indicator light signal corresponding to the second enable signal. N is an integer greater than 1.

17. The integrated hard disk according to claim 16, characterized in that, The first type of pin of the first connector is connected to the first type of pin of the second connector, and the second type of pin of the first connector is connected to the second type of pin of the second connector.

18. The integrated hard disk according to claim 17, characterized in that, The integrated hard drive further includes: a hard drive interface card connected to both the motherboard and the backplane; and a central processing unit (CPU) configured to forward the N enable signals to the logic controller via the first type pins of the N second connectors and the first type pins of the N third connectors when the CPU is connected to the backplane through the hard drive interface card. The N third connectors are located on the hard drive interface card, and the first type pins of the N third connectors are configured as ground pins. When the first type of pins of the N third connectors are set as ground pins, the hard disk interface card is prohibited from adjusting the level state of the received N enable signals.

19. A computer non-volatile readable storage medium, characterized in that, The computer non-volatile readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 15.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 15.

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