Single-die-pad package structure and method for asynchronous buck chip

Abstract

Disclosed in the present invention are a single-die-pad package structure and method for an asynchronous buck chip. The single-die-pad package structure comprises a lead frame, a single die pad, an integrated control circuit wafer, a silicon die, a ceramic chip capacitor, a multilayer chip inductor, and a Schottky diode. The single die pad and a plurality of pins are arranged on the lead frame, and the single die pad is divided into a first chip region and a second chip region; the integrated control circuit wafer is placed in the first chip region, and the silicon die is placed in the second chip region; and the ceramic chip capacitor and the multilayer chip inductor are bonded and connected to each other and are each placed on the silicon die, and the Schottky diode is placed on the silicon die. Thus, the number of components on a circuit board is reduced, the area of the circuit board is reduced, and the manufacturing cost and PCB debugging difficulty are reduced.

Description

A single-base island packaging structure and method for asynchronous buck converter chips Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to an asynchronous buck chip single-base island packaging structure and method. Background Technology

[0002] An asynchronous Buck circuit is a common switching-mode power supply topology used to convert an input voltage to a stable output voltage lower than the input voltage. It is typically used in power conversion and voltage regulation. With the advancement of semiconductor technology and the development of power electronics, the application of asynchronous Buck circuits has become increasingly widespread.

[0003] Taking an asynchronous Buck circuit for LED driving as an example, it is typically constructed using a driver chip, integrated control circuit wafer, inductors, capacitors, and packaged Schottky diodes and resistors. However, this method significantly increases the number of components on the circuit board, increases the circuit board area, and raises manufacturing costs and PCB debugging difficulty. Summary of the Invention

[0004] In view of the above-mentioned shortcomings in the current semiconductor packaging field, the present invention provides an asynchronous buck chip single-base island packaging structure and method. By dividing the single-base island into a first chip area and a second chip area, the integrated control circuit wafer is placed on the first chip area, the silicon wafer is placed on the second chip area, the ceramic chip capacitor and the multilayer chip inductor are bonded to each other and placed on the silicon wafer respectively, and the Schottky diode is placed on the silicon wafer. This reduces the number of components on the circuit board, reduces the circuit board area, reduces manufacturing costs and PCB debugging difficulty.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] An asynchronous buck converter chip single-base island package structure includes:

[0007] A lead frame includes a single base island and multiple pins, wherein the single base island includes a first chip region and a second chip region;

[0008] An integrated control circuit wafer is placed in the first chip region, and a first conductive medium is provided between the integrated control circuit wafer and the first chip region;

[0009] A silicon wafer is placed in the second chip region. One side of the silicon wafer is a conductive metal layer, and the other side is a silicon surface. A first insulating medium is provided between the silicon surface and the second chip region. A ceramic chip capacitor, a multilayer chip inductor, and a Schottky diode are also provided on the conductive metal layer.

[0010] A molding compound is used to encapsulate the lead frame, integrated control circuit wafer, silicon wafer, ceramic chip capacitor, multilayer chip inductor, and Schottky diode.

[0011] According to one aspect of the invention, the lead frame includes a power input pin, a signal feedback pin, a power ground pin, and a switch output pin, the positions of which are not fixed on the lead frame.

[0012] According to one aspect of the invention, an external capacitor is also included, one end of which is grounded and the other end is connected to the switch output pin of the lead frame.

[0013] According to one aspect of the invention, it further includes a first feedback resistor and a second feedback resistor, one end of the first feedback resistor is connected to the switch output pin of the lead frame, the other end is connected to one end of the second feedback resistor, the other end of the second feedback resistor is grounded, and the connection point of the first feedback resistor and the second feedback resistor is connected to the signal feedback pin of the lead frame.

[0014] According to one aspect of the present invention, the ceramic chip capacitor includes a first capacitor terminal and a second capacitor terminal, and a second insulating medium is disposed between the ceramic chip capacitor and the conductive metal layer; the multilayer chip inductor includes a first inductor terminal and a second inductor terminal, and a third insulating medium is disposed between the multilayer chip inductor and the conductive metal layer, and the second inductor terminal and the first capacitor terminal are bonded; the Schottky diode includes a top anode, a bottom cathode and a semiconductor, and a second conductive medium is disposed between the Schottky diode and the conductive metal layer.

[0015] According to one aspect of the invention, the power ground pin is bonded to the single-base island and to the top anode of the Schottky diode; the switch output pin of the lead frame is bonded to the first inductor terminal of the multilayer surface mount inductor.

[0016] According to one aspect of the present invention, the integrated control circuit wafer includes a power input terminal VIN, a switch output terminal SW, a bootstrap terminal BST, a power ground terminal GND, and a signal feedback terminal FB.

[0017] According to one aspect of the invention, the power input VIN terminal of the integrated control circuit wafer is bonded to the power input pin of the lead frame; the switch output SW terminal is bonded to the bottom cathode of the Schottky diode and the second inductor terminal of the multilayer surface mount inductor; the bootstrap BST terminal is bonded to the second capacitor terminal of the ceramic surface mount capacitor; the signal feedback FB terminal is bonded to the signal feedback pin of the lead frame; and the power ground GND terminal is bonded to the power ground pin of the lead frame.

[0018] According to one aspect of the invention, the back side of the single-base island extends through the molding compound and is provided with a heat dissipation pad structure.

[0019] A single-base island packaging method for an asynchronous buck converter chip includes:

[0020] The lead frame is configured with a single base island and pins, and the single base island is divided into a first chip area and a second chip area;

[0021] A first conductive medium is disposed on the first chip region, and a first insulating medium is disposed on the second chip region;

[0022] An integrated control circuit wafer is disposed on the first conductive medium;

[0023] A silicon wafer is provided, one side of which is a conductive metal layer and the other side is a silicon surface. The silicon surface is attached to the first insulating medium. A ceramic chip capacitor, a multilayer chip inductor, and a Schottky diode are disposed on the conductive metal layer.

[0024] The integrated control circuit wafer is bonded to the silicon wafer, the multilayer chip inductor, and the ceramic chip capacitor, respectively.

[0025] The pins of the lead frame are bonded to the integrated control circuit wafer, the single-base island, the multilayer surface mount inductor, and the Schottky diode, respectively.

[0026] The lead frame, integrated control circuit wafer, silicon wafer, ceramic chip capacitor, multilayer chip inductor, and Schottky diode are encapsulated in a plastic package.

[0027] The advantages of this invention are as follows: By setting a single base island and multiple pins in the lead frame, the single base island is divided into a first chip area and a second chip area. The integrated control circuit wafer is placed on the first chip area, the silicon wafer is placed on the second chip area, the ceramic chip capacitor and the multilayer chip inductor are bonded to each other and placed on the silicon wafer respectively, and the Schottky diode is placed on the silicon wafer. This reduces the number of components on the circuit board, reduces the circuit board area, reduces manufacturing costs and PCB debugging difficulty. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a circuit diagram of an asynchronous buck chip single-base island packaging structure and method according to the present invention;

[0030] Figure 2 is a packaging diagram of an asynchronous buck chip single-base island packaging structure and method according to the present invention;

[0031] Figure 3 is a framework diagram of an asynchronous buck chip single-base island packaging structure and method according to the present invention;

[0032] Figure 4 is a partial vertical cross-sectional view of an asynchronous buck chip single-base island packaging structure and method according to the present invention.

[0033] Explanation of reference numerals in the attached figures:

[0034] 111. Power Input Pin VIN; 112. Single Base Island; 113. Signal Feedback Pin FB; 114. Power Ground Pin GND; 115. Switch Output Pin VOUT; 121. First Conducting Medium; 201. Silicon Wafer; 202. Third Insulating Medium; 203. First Inductor Terminal; 204. Multilayer Surface Mount Inductor; 205. Second Inductor Terminal; 206. First Capacitor Terminal; 207. Ceramic Surface Mount Capacitor; 208. Second Capacitor Terminal; 209. Second Insulating Medium; 210. Schottky Diode; 211. Second Conducting Medium; 212. First Insulating Medium; 220. Conductive Metal Layer; 221. Silicon Surface; 222. Top Anode; 223. Semiconductor; 224. Bottom Cathode; 301. Molded Encapsulation; 302. Lead Frame; 340. Integrated Control Circuit Wafer. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Example 1:

[0037] As shown in Figures 1 to 4, an asynchronous step-down chip single-base island package structure includes: a lead frame 302, an integrated control circuit wafer 340, a silicon wafer 201, a ceramic chip capacitor 207, a multilayer chip inductor 204, a Schottky diode 210, and a molding compound 301. The lead frame 302 includes at least a single-base island 112, a power input pin 111, a signal feedback pin 113, a power ground pin 114, and a switch output pin 115. The positions of the power input pin 111, signal feedback pin 113, power ground pin 114, and switch output pin 115 on the lead frame 302 are not fixed. The single-base island 112 is bonded to the power ground pin 114. The single-base island 112 is a power ground island, and the single-base island 112 includes a first chip region and a second chip region. The integrated control circuit wafer 340 is placed on the first chip area through a first conductive medium 121, including a power input VIN terminal, a switch output SW terminal, a bootstrap BST terminal, a power ground GND terminal, and a signal feedback FB terminal. The silicon wafer 201 is placed on the second chip area through a first insulating medium 212, including a conductive metal layer 220 as the front side and a silicon surface 221 as the back side. For example, one side of a single crystal silicon wafer can be plated with titanium, nickel, and silver from the inside out, with the silicon surface 221 placed on the first insulating medium 212. A ceramic chip capacitor 207, a multilayer chip inductor 204, and a Schottky diode 210 are disposed on the silicon wafer 201. The ceramic chip capacitor 207 is placed on the conductive metal layer 220 of the silicon wafer 201 through a second insulating medium 209, indirectly placed on the single-base island 112 of the lead frame 302, including a first capacitor terminal 206 and a second capacitor terminal 208. The multilayer surface-mount inductor 204 is placed on the conductive metal layer 220 of the silicon wafer 201 via a third insulating medium 202, and indirectly placed on the single-base island 112 of the lead frame 302, including a first inductor terminal 203 and a second inductor terminal 205. The Schottky diode 210 is placed on the conductive metal layer 220 of the silicon wafer 201 via a second conductive medium 211, and indirectly placed on the single-base island 112 of the lead frame 302. The Schottky diode 210 has a vertical structure, including a top anode 222, a semiconductor 223, and a bottom cathode 224 mounted from top to bottom. The top anode 222 is located at the top of the vertical Schottky diode 210 structure, and the bottom cathode 224 is located at the bottom of the vertical Schottky diode 210 structure. The molding compound 301 encapsulates the lead frame 302, the integrated control circuit wafer 340, the silicon wafer 201, the ceramic chip capacitor 207, the multilayer chip inductor 204, and the Schottky diode 210. The power input pin 111, the signal feedback pin 113, the power ground pin 114, and the switch output pin 115 extend outwards along the side of the molding compound 301. A heat dissipation pad structure is provided on the back of the single-base island 112, extending through the molding compound 301.The second inductor terminal 205 of the multilayer surface mount inductor 204 and the first capacitor terminal 206 of the ceramic surface mount capacitor 207 are bonded together. The first inductor terminal 203 of the multilayer surface mount inductor 204 and the switch output pin 115 of the lead frame 302 are bonded together.

[0038] The first conductive medium 121 and the second conductive medium 211 include materials that, under certain conditions, can connect two objects and conduct electricity in the field of semiconductor packaging, such as conductive epoxy resin, conductive wafer bonding film, solder paste, etc. In this example, the first conductive medium 121 and the second conductive medium 211 can be the same or different types of conductive materials. The first insulating medium 212, the second insulating medium 209, and the third insulating medium 202 include materials that, under certain conditions, can connect two objects and insulate them in the field of semiconductor packaging, such as insulating epoxy resin, insulating wafer bonding film, etc. In this example, the first insulating medium 212, the second insulating medium 209, and the third insulating medium 202 can be the same or different types of insulating media, and the thickness and insulating performance of the insulating media can withstand high voltage.

[0039] The power input VIN terminal of the integrated control circuit wafer 340 is bonded to the power input pin 111 of the lead frame 302; the switch output SW terminal of the integrated control circuit wafer 340 is connected to the bottom cathode 224 of the Schottky diode 210, and the corresponding switch output SW terminal of the integrated control circuit wafer 340 is bonded to the conductive metal layer 220 on the front side of the silicon wafer 201. As mentioned above, the bottom cathode 224 of the Schottky diode 210 conducts electricity to the front side 220 of the silicon wafer 201 through the second conductive medium 211. Therefore, the bonding of the SW terminal of the integrated control circuit wafer 340 to the conductive metal layer 220 on the front side of the silicon wafer 201 and the bonding of the switch output SW terminal of the integrated control circuit wafer 340 to the bottom cathode 224 of the Schottky diode 210 have the same effect. Simultaneously, the switch output terminal SW of the integrated control circuit wafer 340 is bonded to the second inductor terminal 205 of the multilayer surface mount inductor 204. Since the second inductor terminal 205 of the multilayer surface mount inductor 204 and the first capacitor terminal 206 of the ceramic surface mount capacitor 207 are bonded together, the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the second inductor terminal 205 of the multilayer surface mount inductor 204 and the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the first capacitor terminal 206 of the ceramic surface mount capacitor 207 have the same effect. The bootstrap terminal BST is bonded to the second capacitor terminal 208 of the ceramic surface mount capacitor 207. The signal feedback terminal FB is bonded to the signal feedback pin 113 of the lead frame 302. The power ground terminal GND is bonded to the power ground pin 114 of the lead frame 302.

[0040] The top anode 222 of the Schottky diode 210 is bonded to the power ground pin 114 of the package frame 302, and indirectly connected to the power ground GND terminal of the integrated control circuit wafer 340. The bottom cathode 224 of the Schottky diode 210 is electrically connected to the conductive metal layer 220 on the front side of the silicon wafer 201 through the second conductive dielectric 211, and is therefore indirectly electrically connected to the switching output SW terminal of the integrated control circuit wafer 340.

[0041] It also includes an external capacitor, a first feedback resistor, and a second feedback resistor. One end of the external capacitor is grounded, and the other end is connected to the switch output pin 115 of the lead frame 302. One end of the first feedback resistor is connected to the switch output pin 115 of the lead frame 302, and the other end is connected to one end of the second feedback resistor. The other end of the second feedback resistor is grounded, and the connection point of the first feedback resistor and the second feedback resistor is connected to the signal feedback pin 113 of the lead frame 302.

[0042] The advantages of this invention are as follows: By setting a single base island and multiple pins in the lead frame, the single base island is divided into a first chip area and a second chip area. The integrated control circuit wafer is placed on the first chip area, the silicon wafer is placed on the second chip area, the ceramic chip capacitor and the multilayer chip inductor are bonded to each other and placed on the silicon wafer respectively, and the Schottky diode is placed on the silicon wafer. This reduces the number of components on the circuit board, reduces the circuit board area, reduces manufacturing costs and PCB debugging difficulty.

[0043] Example 2:

[0044] As shown in Figures 1 to 4, a single-base island packaging method for an asynchronous buck converter chip includes:

[0045] S1: Set the single base island 112 and pins of the lead frame 302, and divide the single base island 112 into the first chip area and the second chip area.

[0046] S2: A first conductive medium 121 is provided on the first chip area, and a first insulating medium 212 is provided on the second chip area.

[0047] S3: An integrated control circuit wafer 340 is disposed on the first conductive medium 121.

[0048] The integrated control circuit wafer 340 is placed on the first chip area through the first conductive medium 121.

[0049] S4: A silicon wafer 201 is provided, one side of which is a conductive metal layer 220 and the other side is a silicon surface 221. The silicon surface 221 is attached to the first insulating medium 212. A ceramic chip capacitor 207, a multilayer chip inductor 204 and a Schottky diode 210 are provided on the conductive metal layer 220.

[0050] The silicon wafer 201 includes a conductive metal layer 220 as the front side and a silicon surface 221 as the back side. For example, one side of a single crystal silicon can be plated with titanium, nickel, and silver from the inside out. The silicon surface 221 is in contact with the first insulating medium 212. The silicon wafer 201 is placed on the second chip area through the first insulating medium 212. A ceramic chip capacitor 207 and a multilayer chip inductor 204 are placed on the silicon wafer 201 through the second insulating medium 209 and the third insulating medium 202, respectively. The ceramic chip capacitor 207 and the multilayer chip inductor 204 are bonded together. A Schottky diode 210 is placed on the silicon wafer 201 through the second conductive medium 211.

[0051] A ceramic chip capacitor 207 is placed on the conductive metal layer 220 of the silicon wafer 201 via a second insulating medium 209, and indirectly placed on the single-base island 112 of the lead frame 302, including a first capacitor terminal 206 and a second capacitor terminal 208. A multilayer chip inductor 204 is placed on the conductive metal layer 220 of the silicon wafer 201 via a third insulating medium 202, and indirectly placed on the single-base island 112 of the lead frame 302, including a first inductor terminal 203 and a second inductor terminal 205. The Schottky diode 210 is placed on the conductive metal layer 220 of the silicon wafer 201 through the second conductive medium 211, and indirectly placed on the single base island 112 of the lead frame 302. The Schottky diode 210 has a vertical structure, including a top anode 222, a semiconductor 223 and a bottom cathode 224 installed from top to bottom. The top anode 222 refers to the top of the vertical Schottky diode 210 structure, and the bottom cathode 224 refers to the bottom of the vertical Schottky diode 210 structure.

[0052] The order of steps S3 and S4 can be interchanged.

[0053] S5: The integrated control circuit wafer 340 is bonded to the silicon wafer 201, the multilayer chip inductor 204, and the ceramic chip capacitor 207 respectively.

[0054] The integrated control circuit wafer 340 includes a power input VIN terminal, a switch output SW terminal, a bootstrap BST terminal, a power ground GND terminal, and a signal feedback FB terminal.

[0055] S6: Bond the pins of the lead frame 302 to the integrated control circuit wafer 340, the single-base island 112, the multilayer surface mount inductor 204, and the Schottky diode 210, respectively.

[0056] The lead frame 302 also includes a power input pin 111, a signal feedback pin 113, a power ground pin 114, and a switch output pin 115. The positions of the power input pin 111, signal feedback pin 113, power ground pin 114, and switch output pin 115 on the lead frame 302 are not fixed. The single-base island 112 is bonded to the power ground pin 114, and the single-base island 112 of the lead frame 302 is a power ground island. The second inductor terminal 205 of the multilayer surface mount inductor 204 and the first capacitor terminal 206 of the ceramic surface mount capacitor 207 are bonded together. The first inductor terminal 203 of the multilayer surface mount inductor 204 and the switch output pin 115 of the lead frame 302 are bonded together.

[0057] The order of steps S5 and S6 can be interchanged.

[0058] S7: Wrap the lead frame 302, integrated control circuit wafer 340, silicon wafer 201, ceramic chip capacitor 207, multilayer chip inductor 204 and Schottky diode 210 with a plastic encapsulation 301.

[0059] The power input pin 111, signal feedback pin 113, power ground pin 114, and switch output pin 115 extend outward along the side of the molding compound 301. A heat dissipation pad structure is provided on the back of the single base island 112, extending through the molding compound 301.

[0060] The first conductive medium 121 and the second conductive medium 211 include materials that, under certain conditions, can connect two objects and conduct electricity in the field of semiconductor packaging, such as conductive epoxy resin, conductive wafer bonding film, solder paste, etc. In this example, the first conductive medium 121 and the second conductive medium 211 can be the same or different types of conductive materials. The first insulating medium 212, the second insulating medium 209, and the third insulating medium 202 include materials that, under certain conditions, can connect two objects and insulate them in the field of semiconductor packaging, such as insulating epoxy resin, insulating wafer bonding film, etc. In this example, the first insulating medium 212, the second insulating medium 209, and the third insulating medium 202 can be the same or different types of insulating media, and the thickness and insulating performance of the insulating media can withstand high voltage.

[0061] The power input VIN terminal of the integrated control circuit wafer 340 is bonded to the power input pin 111 of the lead frame 302; the switch output SW terminal of the integrated control circuit wafer 340 is connected to the bottom cathode 224 of the Schottky diode 210, and the corresponding switch output SW terminal of the integrated control circuit wafer 340 is bonded to the conductive metal layer 220 on the front side of the silicon wafer 201. As mentioned above, the bottom cathode 224 of the Schottky diode 210 conducts electricity to the front side 220 of the silicon wafer 201 through the second conductive medium 211. Therefore, the bonding of the SW terminal of the integrated control circuit wafer 340 to the conductive metal layer 220 on the front side of the silicon wafer 201 and the bonding of the switch output SW terminal of the integrated control circuit wafer 340 to the bottom cathode 224 of the Schottky diode 210 have the same effect. Simultaneously, the switch output terminal SW of the integrated control circuit wafer 340 is bonded to the second inductor terminal 205 of the multilayer surface mount inductor 204. Since the second inductor terminal 205 of the multilayer surface mount inductor 204 and the first capacitor terminal 206 of the ceramic surface mount capacitor 207 are bonded together, the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the second inductor terminal 205 of the multilayer surface mount inductor 204 and the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the first capacitor terminal 206 of the ceramic surface mount capacitor 207 have the same effect. The bootstrap terminal BST is bonded to the second capacitor terminal 208 of the ceramic surface mount capacitor 207. The signal feedback terminal FB is bonded to the signal feedback pin 113 of the lead frame 302. The power ground terminal GND is bonded to the power ground pin 114 of the lead frame 302.

[0062] The top anode 222 of the Schottky diode 210 is bonded to the power ground pin 114 of the package frame 302, and indirectly connected to the power ground GND terminal of the integrated control circuit wafer 340. The bottom cathode 224 of the Schottky diode 210 is electrically connected to the conductive metal layer 220 on the front side of the silicon wafer 201 through the second conductive dielectric 211, and is therefore indirectly electrically connected to the switching output SW terminal of the integrated control circuit wafer 340.

[0063] It also includes an external capacitor, a first feedback resistor, and a second feedback resistor. One end of the external capacitor is grounded, and the other end is connected to the switch output pin 115 of the lead frame 302. One end of the first feedback resistor is connected to the switch output pin 115 of the lead frame 302, and the other end is connected to one end of the second feedback resistor. The other end of the second feedback resistor is grounded, and the connection point of the first feedback resistor and the second feedback resistor is connected to the signal feedback pin 113 of the lead frame 302.

[0064] Advantages of this invention: By setting a single base island and multiple pins in the lead frame, the single base island is divided into a first chip area and a second chip area. A first conductive medium is set on the first chip area, and a first insulating medium is set on the second chip area. An integrated control circuit wafer is set on the first conductive medium, and a silicon wafer is set. One side of the silicon wafer is a conductive metal layer, and the other side is a silicon surface. The silicon surface is attached to the first insulating medium. A ceramic chip capacitor, a multilayer chip inductor, and a Schottky diode are set on the conductive metal layer. The integrated control circuit wafer is bonded to the silicon wafer, the multilayer chip inductor, and the ceramic chip capacitor, respectively. The pins of the lead frame are bonded to the integrated control circuit wafer, the single base island, the multilayer chip inductor, and the Schottky diode, respectively. This reduces the number of components on the circuit board, reduces the circuit board area, lowers manufacturing costs, and reduces the debugging difficulty of the PCB.

[0065] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A single-base island package structure for an asynchronous buck converter chip, characterized in that, include: The lead frame (302) includes a single base island (112) and multiple pins, wherein the single base island (112) includes a first chip region and a second chip region; An integrated control circuit wafer (340) is placed in the first chip region, and a first conductive medium (121) is provided between the integrated control circuit wafer (340) and the first chip region. A silicon wafer (201) is placed in the second chip region. One side of the silicon wafer (201) is configured as a conductive metal layer (220), and the other side is configured as a silicon surface (221). A first insulating medium (212) is provided between the silicon surface (221) and the second chip region. A ceramic chip capacitor (207), a multilayer chip inductor (204), and a Schottky diode (210) are also provided on the conductive metal layer (220). A molding compound (301) is used to encapsulate the lead frame (302), the integrated control circuit wafer (340), the silicon wafer (201), the ceramic chip capacitor (207), the multilayer chip inductor (204), and the Schottky diode (210).

2. The asynchronous buck chip single-base island packaging structure according to claim 1, characterized in that, The lead frame (302) includes a power input pin (111), a signal feedback pin (113), a power ground pin (114), and a switch output pin (115). The positions of the power input pin (111), the signal feedback pin (113), the power ground pin (114), and the switch output pin (115) on the lead frame (302) are not fixed.

3. The asynchronous buck chip single-base island packaging structure according to claim 2, characterized in that, It also includes an external capacitor, one end of which is grounded and the other end is connected to the switch output pin (115) of the lead frame (302).

4. The asynchronous buck chip single-base island packaging structure according to claim 2, characterized in that, It also includes a first feedback resistor and a second feedback resistor. One end of the first feedback resistor is connected to the switch output pin (115) of the lead frame (302), and the other end is connected to one end of the second feedback resistor. The other end of the second feedback resistor is grounded. The connection point of the first feedback resistor and the second feedback resistor is connected to the signal feedback pin (113) of the lead frame (302).

5. The asynchronous buck chip single-base island packaging structure according to claim 2, characterized in that, The ceramic chip capacitor (207) includes a first capacitor terminal (206) and a second capacitor terminal (208), and a second insulating medium (209) is provided between the ceramic chip capacitor (207) and the conductive metal layer (220); the multilayer chip inductor (204) includes a first inductor terminal (203) and a second inductor terminal (205), and a third insulating medium (202) is provided between the multilayer chip inductor (204) and the conductive metal layer (220), and the second inductor terminal (205) and the first capacitor terminal (206) are bonded; the Schottky diode (210) includes a top anode (222), a bottom cathode (224) and a semiconductor (223), and a second conductive medium (211) is provided between the Schottky diode (210) and the conductive metal layer (220).

6. The asynchronous buck chip single-base island package structure according to claim 5, characterized in that, The power ground pin (114) is bonded to the single base island (112) and to the top anode (222) of the Schottky diode (210); the switch output pin (115) of the lead frame (302) is bonded to the first inductor terminal (203) of the multilayer surface mount inductor (204).

7. The asynchronous buck chip single-base island package structure according to claim 6, characterized in that, The integrated control circuit wafer (340) includes a power input VIN terminal, a switch output SW terminal, a bootstrap BST terminal, a power ground GND terminal, and a signal feedback FB terminal.

8. The asynchronous buck chip single-base island package structure according to claim 7, characterized in that, The power input VIN terminal of the integrated control circuit wafer (340) is bonded to the power input pin (111) of the lead frame (302); the switch output SW terminal is bonded to the bottom cathode (224) of the Schottky diode (210) and the second inductor terminal (205) of the multilayer surface mount inductor (204); the bootstrap BST terminal is bonded to the second capacitor terminal (208) of the ceramic surface mount capacitor (207); the signal feedback FB terminal is bonded to the signal feedback pin (113) of the lead frame (302); and the power ground GND terminal is bonded to the power ground pin (114) of the lead frame (302).

9. An asynchronous buck chip single-base island package structure according to any one of claims 1 to 8, characterized in that, The back of the single base island (112) extends through the molding compound (301) and is provided with a heat dissipation pad structure.

10. A method for packaging an asynchronous buck converter chip using a single-base island, characterized in that, include: The lead frame (302) is configured with a single base island (112) and pins, and the single base island (112) is divided into a first chip area and a second chip area; A first conductive medium (121) is disposed on the first chip area, and a first insulating medium (212) is disposed on the second chip area. An integrated control circuit wafer (340) is disposed on the first conductive medium (121); A silicon wafer (201) is provided, one side of which is a conductive metal layer (220) and the other side is a silicon surface (221). The silicon surface (221) is attached to the first insulating medium (212). A ceramic chip capacitor (207), a multilayer chip inductor (204) and a Schottky diode (210) are provided on the conductive metal layer (220). The integrated control circuit wafer (340) is bonded to the silicon wafer (201), the multilayer chip inductor (204), and the ceramic chip capacitor (207), respectively. The pins of the lead frame (302) are bonded to the integrated control circuit wafer (340), the single-base island (112), the multilayer surface mount inductor (204), and the Schottky diode (210), respectively. The lead frame (302), integrated control circuit wafer (340), silicon wafer (201), ceramic chip capacitor (207), multilayer chip inductor (204) and Schottky diode (210) are encapsulated in a plastic package (301).

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