Capacitor-less non-volatile dynamic memory and manufacturing method therefor
By integrating vertical channel transistors and ferroelectric transistors in capacitor-free non-volatile dynamic memory, the energy consumption and storage density problems of DRAM are solved, achieving high-density and high-energy-efficiency storage and reducing costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2025-12-31
- Publication Date
- 2026-07-09
AI Technical Summary
Current DRAM suffers from energy consumption and storage density issues, while traditional semiconductor processes have limited integration density and are expensive.
It employs a capacitor-free non-volatile dynamic memory, including the three-dimensional integration of vertical channel transistors and ferroelectric transistors, utilizing the non-volatility of ferroelectric materials and the vertical channel gate induced by metal, combined with wafer-level three-dimensional integration technology.
It achieves high-density, high-energy-efficiency storage, reduces costs, and increases integration density.
Smart Images
Figure CN2025148096_09072026_PF_FP_ABST
Abstract
Description
A capacitor-free non-volatile dynamic memory and its fabrication method
[0001] This application claims priority to Chinese Patent Application No. 2025100165731, filed on January 6, 2025, entitled "A Capacitorless Non-Volatile Dynamic Memory and a Method for its Fabrication", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This invention relates to the field of semiconductor technology, and in particular to a capacitor-free non-volatile dynamic memory and its fabrication method. Background Technology
[0003] Current DRAM (Dynamic Random Access Memory) suffers from issues related to energy consumption and storage density. Combining DRAM and NVM (Non-volatile Memory) to form NVDRAM (Non-volatile Dynamic Random Access Memory) and integrating it into the memory hierarchy can solve the current DRAM's storage density and energy consumption problems. Meanwhile, ferroelectric materials, after polarization, can retain their polarization state for a long time, making them widely applicable in the field of non-volatile ferroelectric memories.
[0004] In addition, traditional semiconductor processes are mainly based on silicon and are represented by 3D V-cache. They are usually based on advanced bonding technology, which limits integration density and is expensive.
[0005] In view of this, the present invention is proposed. Summary of the Invention
[0006] The purpose of this invention is to provide a capacitor-free non-volatile dynamic memory and its fabrication method, which can achieve high-density and high-energy-efficiency storage, and adopts wafer-level three-dimensional integration, resulting in high integration density and low cost.
[0007] A first aspect of the present invention provides a capacitor-free non-volatile dynamic memory, comprising: a first transistor and a second transistor; the first transistor is a vertical channel transistor (VCT transistor); the second transistor is a ferroelectric transistor; and the second transistor is located above the first transistor.
[0008] Preferably, the channel material of the first transistor is crystalline silicon formed by metal induction from amorphous silicon; preferably, the metal is Ni.
[0009] Preferably, the channel material of the second transistor is indium gallium zinc oxide.
[0010] Preferably, the second transistor is a horizontal transistor with a bottom gate structure.
[0011] Preferably, the first transistor includes: a first source layer, a first drain layer, a first channel layer, a first gate layer, and a first gate dielectric layer; one of the first source layer and the first drain layer is located on the upper surface of the first channel layer, and the other is located on the lower surface of the first channel layer, and the first source layer and the first drain layer are not connected to each other; the first gate layer surrounds the first channel layer, and the first gate dielectric layer is located between the first gate layer and the first channel layer.
[0012] Preferably, one of the first source layer and the first drain layer is made of NiSi2 and the other is made of crystalline silicon; the first gate layer is made of TiN; and the first gate dielectric layer is made of HfO2.
[0013] Preferably, the second transistor includes: a second source layer, a second drain layer, a second channel layer, a second gate layer, a ferroelectric material layer, and a second gate dielectric layer; the ferroelectric material layer, the second gate dielectric layer, and the second channel layer are sequentially disposed on the second gate layer; the second source layer and the second drain layer are respectively located on the upper surface of the second channel layer and are not connected to each other; the second source layer or the second drain layer is connected to the first gate layer.
[0014] Preferably, the materials of the second source layer, the second drain layer and the first gate layer are all TiN; the material of the second gate dielectric layer is HfO2.
[0015] Preferably, the first transistor is a read transistor and the second transistor is a write transistor.
[0016] A second aspect of the present invention provides a method for fabricating a capacitor-free non-volatile dynamic memory, comprising the following steps:
[0017] S1. Fabricate a first transistor on a peripheral circuit; the first transistor is a vertical channel transistor; the channel of the first transistor is formed by metal induction;
[0018] S2. A second transistor is fabricated above the first transistor; the second transistor is a horizontally structured ferroelectric transistor; the channel of the second transistor is made of indium gallium zinc oxide material;
[0019] S3. Interconnect the first transistor with the second transistor.
[0020] The present invention has at least the following beneficial effects:
[0021] The 2T0C non-volatile memory provided by this invention includes a ferroelectric transistor as one of its transistors. By introducing ferroelectric materials, the non-volatile dynamic random access memory can solve the storage density and energy consumption problems of current dynamic random access memory, enabling high-density and high-energy-efficiency storage. In addition, the other transistor uses a vertical channel transistor (VCT transistor) fabrication process in which a metal-induced gate is formed around the channel, resulting in stronger gate control capability. Furthermore, this invention achieves wafer-level three-dimensional integration, which, compared with traditional semiconductor processes, offers high integration density and low cost, and has broad application prospects. Attached Figure Description
[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0023] Figure 1 is a cross-sectional view of the present invention after growing a dielectric layer and an amorphous silicon thin film on the peripheral circuit;
[0024] Figure 2 is a cross-sectional view of the amorphous silicon thin film after etching according to the present invention;
[0025] Figure 3 is a cross-sectional view of the present invention after the deposition of the metal layer;
[0026] Figure 4 is a cross-sectional view after the formation of the first source layer in this invention;
[0027] Figure 5 is a cross-sectional view of the deposition medium layer, Si3N4 layer and medium layer of the present invention;
[0028] Figure 6 is a cross-sectional view after the channel region of the first transistor has been etched in this invention;
[0029] Figure 7 is a cross-sectional view of the channel region after being filled with amorphous silicon according to the present invention;
[0030] Figure 8 is a cross-sectional view of the amorphous silicon after deposition in this invention;
[0031] Figure 9 is a cross-sectional view of the present invention after the formation of the first channel layer and the first drain layer;
[0032] Figure 10 is a cross-sectional view after the formation of the first gate layer and the first gate dielectric layer in this invention;
[0033] Figure 11 is a cross-sectional view of the present invention after the formation of the second gate layer;
[0034] Figure 12 is a cross-sectional view of the present invention after the formation of the ferroelectric material layer, the second gate dielectric layer, and the second channel layer;
[0035] Figure 13 is a cross-sectional view after the formation of the second source layer and the second drain layer in this invention;
[0036] Figure 14 is a cross-sectional view of the capacitor-free non-volatile dynamic memory prepared according to the present invention.
[0037] Figure 15 is an equivalent circuit diagram of the capacitor-free non-volatile dynamic memory prepared according to the present invention.
[0038] Explanation of reference numerals in the attached figures: 1. Peripheral circuit; 2. Dielectric layer; 3. Amorphous silicon thin film; 4. Metal layer; 5. First source layer; 6. Si3N4 layer; 7. Channel region; 8. Amorphous silicon; 9. First channel layer; 10. First drain layer; 11. First gate dielectric layer; 12. First gate layer; 13. Second gate layer; 14. Ferroelectric material layer; 15. Second gate dielectric layer; 16. Second channel layer; 17. Second source layer; 18. Second drain layer; 19. Conductive channel. Detailed Implementation
[0039] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0040] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form includes the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0041] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0042] Example
[0043] This embodiment provides a capacitor-free non-volatile dynamic memory, including: a first transistor and a second transistor; the first transistor is a vertical channel transistor; the second transistor is a ferroelectric transistor; the second transistor is located above the first transistor.
[0044] In this embodiment, the channel material of the first transistor is crystalline silicon formed by metal induction from amorphous silicon.
[0045] In this embodiment, the channel material of the second transistor is indium gallium zinc oxide (IGZO).
[0046] In this embodiment, the second transistor is a horizontal transistor with a bottom gate structure.
[0047] In this embodiment, the first transistor includes: a first source layer 5, a first drain layer 10, a first channel layer 9, a first gate layer 12, and a first gate dielectric layer 11; the first source layer 5 is located on the lower surface of the first channel layer 9, the first drain layer 10 is located on the upper surface of the first channel layer 9, and the first source layer 5 and the first drain layer 10 are not connected to each other; the first gate layer 12 surrounds the first channel layer 9, and the first gate dielectric layer 11 is located between the first gate layer 12 and the first channel layer 9.
[0048] In this embodiment, the material of the first source layer 5 is NiSi2, the material of the first drain layer 10 is crystalline silicon, the material of the first gate layer 12 is TiN, and the material of the first gate dielectric layer 11 is HfO2.
[0049] In this embodiment, the second transistor includes: a second source layer 17, a second drain layer 18, a second channel layer 16, a second gate layer 13, a ferroelectric material layer 14, and a second gate dielectric layer 15; the ferroelectric material layer 14, the second gate dielectric layer 15, and the second channel layer 16 are sequentially disposed on the second gate layer 13; the second source layer 17 and the second drain layer 18 are respectively located on the upper surface of the second channel layer 16 and are not connected to each other; the second source layer 17 or the second drain layer 18 is connected to the first gate layer 12.
[0050] In this embodiment, the materials of the second source layer 17, the second drain layer 18 and the first gate layer 12 are all TiN; the material of the second gate dielectric layer 15 is HfO2.
[0051] In this embodiment, the first transistor is a read transistor and the second transistor is a write transistor.
[0052] This embodiment also provides a method for fabricating a capacitor-free non-volatile dynamic memory, comprising the following steps:
[0053] S1. Fabricate a first transistor on peripheral circuit 1; the first transistor is a vertical channel transistor; the channel of the first transistor is formed by metal induction;
[0054] S2. A second transistor is fabricated above the first transistor; the second transistor is a ferroelectric transistor; the channel of the second transistor is made of indium gallium zinc oxide material;
[0055] S3. Interconnect the first transistor with the second transistor.
[0056] The preparation method of this embodiment will be described in more detail below:
[0057] For step S1, as shown in Figure 1, a SiO2 dielectric layer 2 and an amorphous silicon thin film 3 are sequentially grown on the CMOS peripheral circuit 1 by epitaxy.
[0058] As shown in Figure 2, the amorphous silicon thin film 3 is etched.
[0059] As shown in Figure 3, an atomic layer deposition (ALD) process is used to deposit a Ni metal layer 4, the Ni thickness of which is less than 1 / 2 of that of amorphous silicon, covering the etched amorphous silicon thin film 3 and the SiO2 dielectric layer 2.
[0060] Preferably, a 2nm thick SiO2 layer is deposited before depositing the Ni metal layer 4. The SiO2 layer can effectively control the reaction rate between nickel and silicon, preventing the reaction from being too fast and thus allowing for better control of the reaction. If the SiO2 layer is too thick, it is not conducive to the reaction; if the SiO2 layer is too thin, the effect of controlling the reaction rate is reduced. Therefore, a 2nm thick SiO2 layer is the optimal condition for controlling the reaction rate between nickel and silicon.
[0061] As shown in Figure 4, rapid thermal annealing at 450-575℃ for 5-10 min forms NiSi2, which serves as the first source layer 5, removing unreacted Ni (if a SiO2 layer is deposited, the SiO2 layer is also removed).
[0062] As shown in Figure 5, a SiO2 dielectric layer, a Si3N4 layer, and a SiO2 dielectric layer are deposited sequentially.
[0063] As shown in Figure 6, the via of the bottom first transistor (read transistor) is etched out and used as the channel region 7.
[0064] As shown in Figure 7, doped amorphous silicon 8 is deposited, and then CMP is used to remove part of the surface, fully filling the channel region 7 (doping concentration 1E18~1E19 / cm). 3 ).
[0065] As shown in Figure 8, the concentration of doped amorphous silicon 8 in the deposition is greater than 1E20 / cm. 3 .
[0066] As shown in Figure 9, after recrystallization annealing at 550℃ for 24 hours, amorphous silicon 8 will crystallize into crystalline silicon (c-Si) using NiSi2 as the mother phase under metal induction. Since NiSi2 has a face-centered cubic (FCC) structure, which is very close to the lattice structure of single-crystal silicon with a lattice mismatch of only 0.4%, it can be considered that amorphous silicon 8 crystallizes into c-Si, forming the first channel layer 9 and the first drain layer 10.
[0067] As shown in Figure 10, the Si3N4 layer 6 is removed by phosphoric acid cleaning, and then TiN is deposited by ALD method to form the first gate layer 12 and the first gate dielectric layer 11.
[0068] For step S2, as shown in Figure 11, after depositing the SiO2 dielectric layer, planarization is performed, TiN is deposited, and the second gate layer 13 (bottom gate structure) is etched by photolithography. Since the critical temperature of indium gallium zinc oxide (IGZO) is about 500℃, its performance and stability may be affected when the IGZO material is exposed to high temperature environment. Therefore, the bottom gate structure can better maintain the stability of the transistor.
[0069] As shown in Figure 12, a ferroelectric material layer 14 and a second gate dielectric layer 15 (HfO2) are deposited, and then an IGZO thin film is deposited as the second channel layer 16.
[0070] As shown in Figure 13, TiN metal is deposited and etched to form a second source layer 17 and a second drain layer 18.
[0071] For step S3, as shown in Figure 14, an interlayer dielectric layer is deposited on the top, followed by dielectric CMP, and then contact hole photolithography and etching are performed to deposit silicide, forming contact holes that contact the source layer, drain layer and gate layer respectively. Conductive channels 19 are formed in the contact holes to form the interconnect of the first transistor and the second transistor, thus obtaining the capacitor-free non-volatile dynamic memory, i.e., 2T0C NVDRAM. The equivalent circuit diagram is shown in Figure 15.
[0072] In summary, the 2T0C NVDRAM provided in this embodiment consists of two transistors, namely a write transistor and a read transistor. The write transistor is a ferroelectric transistor (FeFet) and is a horizontal transistor with a bottom gate structure. The read transistor is a vertical transistor located below the write transistor. The channel of the read transistor is formed by metal induction and the channel material is IGZO oxide.
[0073] The 2T0C NVDRAM provided by this invention employs a ferroelectric transistor in one of its transistors. By introducing ferroelectric materials, the non-volatile dynamic random access memory can solve the storage density and energy consumption problems of current dynamic random access memory, enabling high-density and high-energy-efficiency storage. In addition, the other transistor uses a vertical channel transistor (VCT transistor) fabrication process in which a metal-induced gate is formed around the channel, resulting in stronger gate control capability and enabling wafer-level three-dimensional integration. Compared with traditional semiconductor processes, it has high integration density and low cost, and has broad application prospects.
[0074] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A capacitor-free non-volatile dynamic memory, characterized in that, include: A first transistor and a second transistor; the first transistor is a vertical channel transistor; The second transistor is a ferroelectric transistor; The second transistor is located above the first transistor.
2. The capacitor-free non-volatile dynamic memory according to claim 1, characterized in that, The channel material of the first transistor is crystalline silicon formed by metal induction from amorphous silicon.
3. The capacitor-free non-volatile dynamic memory according to claim 1, characterized in that, The channel material of the second transistor is indium gallium zinc oxide.
4. The capacitor-free non-volatile dynamic memory according to claim 1, characterized in that, The second transistor is a horizontal transistor with a bottom gate structure.
5. The capacitor-free non-volatile dynamic memory according to claim 1, characterized in that, The first transistor includes: a first source layer, a first drain layer, a first channel layer, a first gate layer, and a first gate dielectric layer; one of the first source layer and the first drain layer is located on the upper surface of the first channel layer, and the other is located on the lower surface of the first channel layer, and the first source layer and the first drain layer are not connected to each other; the first gate layer surrounds the first channel layer, and the first gate dielectric layer is located between the first gate layer and the first channel layer.
6. The capacitor-free non-volatile dynamic memory according to claim 5, characterized in that, One of the first source layer and the first drain layer is made of NiSi2, and the other is made of crystalline silicon; the first gate layer is made of TiN; and the first gate dielectric layer is made of HfO2.
7. The capacitor-free non-volatile dynamic memory according to claim 5, characterized in that, The second transistor includes: a second source layer, a second drain layer, a second channel layer, a second gate layer, a ferroelectric material layer, and a second gate dielectric layer; the ferroelectric material layer, the second gate dielectric layer, and the second channel layer are sequentially disposed on the second gate layer; the second source layer and the second drain layer are respectively located on the upper surface of the second channel layer and are not connected to each other; the second source layer or the second drain layer is connected to the first gate layer.
8. The capacitor-free non-volatile dynamic memory according to claim 7, characterized in that, The second source layer, the second drain layer, and the first gate layer are all made of TiN; the second gate dielectric layer is made of HfO2.
9. The capacitor-free non-volatile dynamic memory according to claim 1, characterized in that, The first transistor is a read transistor, and the second transistor is a write transistor.
10. A method for fabricating a capacitor-free non-volatile dynamic memory, characterized in that, Includes the following steps: S1. Fabricate a first transistor on a peripheral circuit; the first transistor is a vertical channel transistor; the channel of the first transistor is formed by metal induction; S2. A second transistor is fabricated above the first transistor; the second transistor is a horizontally structured ferroelectric transistor; the channel of the second transistor is made of indium gallium zinc oxide material; S3. Interconnect the first transistor with the second transistor.