Display device and display method

Abstract

A display device according to an embodiment comprises: a pixel array that includes a plurality of pixels arranged in a plurality of rows and a plurality of columns; a scanning circuit that supplies a first scanning signal having a first pulse width, a second scanning signal having the first pulse width, and a third scanning signal having the first pulse width to the pixels of each row in the pixel array; and a light emission control circuit that supplies a light emission control signal to the pixels of each row. The scanning circuit writes image data into the pixels of each row at the beginning of one frame period, and thereafter causes the pixels to emit light in a plurality of subframe periods. The light emission control circuit causes the pixels to emit light and thereafter causes the pixels to not emit light in subframe periods other than the last subframe period, and causes the pixels to emit light, thereafter causes the pixels to not emit light, and thereafter causes the pixels to emit light in the last subframe period.

Description

Display Device and Display Method

[0001] Embodiments of the present disclosure relate to a display device and a display method.

[0002] In recent years, self-emissive display devices have been implemented in televisions, smartphones, smartwatches, digital signage (electronic billboards, electronic advertising boards, etc.) and have become widespread. Examples of self-emissive display devices include a plurality of light-emitting elements two-dimensionally arranged in a display area, and peripheral circuits arranged around the display area for driving pixels. Examples of light-emitting elements are light-emitting diodes (LEDs), micro light-emitting diodes (micro LEDs), or organic light-emitting diodes (OLEDs).

[0003] As a simple brightness adjustment means in a self-emissive display device, there is a PWM (Pulse Width Modulation) method. The PWM method divides the frame period for displaying one image into a plurality of sub-frame periods, and adjusts the brightness of the entire screen by changing the ratio (also referred to as emission duty) of the emission period (also referred to as lighting) and the non-emission period (also referred to as extinguishing) in each sub-frame period. That is, in the PCM method, it is possible to adjust the brightness without changing the image data. Also, it is easier to control the current of the light-emitting element by causing the light-emitting element to emit light in a time-division manner at a higher brightness than to cause the light-emitting element to emit light constantly at a low brightness. Therefore, the PWM method has the merit of being able to display a uniform image with less unevenness. Note that in the PWM method, the non-emission periods of each sub-frame are made the same and the emission periods of each sub-frame are also made the same so as not to generate flicker.

[0004] However, in the PWM method, when there are portions in an image with a brightness different from other portions, ghosts may occur. For example, when displaying a black horizontal band in the center of a white background screen, dark band-shaped ghosts occur at positions away from the black horizontal band. The images causing the occurrence of ghosts are not limited to black horizontal bands. The shape of the ghosts is also not limited to a band shape. For example, when a character area is partially included in a white background, ghosts also occur in areas other than the character area.

[0005] Japanese Patent Publication No. 2024-83973

[0006] The purpose of this disclosure is to provide a display device and display method that prevent the occurrence of ghosting.

[0007] The display device according to the embodiment includes a pixel array containing a plurality of pixels arranged in a plurality of rows and a plurality of columns, a scanning circuit that supplies a first scan signal of a first pulse width, a second scan signal of a first pulse width, and a third scan signal of a first pulse width to the pixels of each row of the pixel array, and a light emission control circuit that supplies a light emission control signal to the pixels of each row. Each of the plurality of pixels includes a self-emissive display element, a capacitor connected to the display element, a first transistor connected to a third node and supplying image data to the third node when activated by the second scan signal, a second transistor connected between the third node and the first node, a third transistor connected between the first node and the gate of the second transistor and whose conduction is controlled by the first scan signal, and a seventh transistor connected to the first node and supplying a reset voltage to the first node when activated by the third scan signal. The capacitor is connected between the gate of the second transistor and the display element. The scanning circuit outputs a signal obtained by shifting the third scanning signal by one horizontal period as the first scanning signal, and a signal obtained by shifting the first scanning signal by one horizontal period as the second scanning signal. The scanning circuit writes image data to the pixels of each row at the beginning of one frame period, and then makes the pixels light up during multiple subframe periods. The light emission control circuit makes the pixels light up during all subframe periods except the last subframe period, then makes the pixels de-illuminate at a timing corresponding to the image data, and then makes the pixels light up during the last subframe period, then makes the pixels de-illuminate at a timing corresponding to the image data, and then makes the pixels light up again.

[0008] A circuit diagram illustrating an example of a display device according to the embodiment. A circuit diagram illustrating an example of a pixel array according to the embodiment. A circuit diagram illustrating an example of a source driver according to the embodiment. A circuit diagram illustrating an example of a pixel according to the embodiment. A schematic diagram illustrating an example of driving a pixel array according to the embodiment. A signal waveform diagram illustrating an example of driving a pixel array according to the embodiment. A diagram illustrating an example of operation during the reset period of the display device according to the embodiment. A diagram illustrating an example of operation during the sampling period of the display device according to the embodiment. A diagram illustrating the operation during the light emission period of the display device according to the embodiment. A diagram illustrating the operation during the non-light emission period of the display device according to the embodiment.

[0009] The embodiments will be described below with reference to the drawings. The following description illustrates devices and methods for realizing the technical concept of the embodiments, and the technical concept of the embodiments is not limited to the structure, shape, arrangement, material, etc. of the components described below. Modifications that a person skilled in the art can easily conceive of are naturally included in the scope of disclosure. In order to make the explanation clearer, the size, thickness, planar dimensions, or shape of each element may be schematically represented in the drawings with changes from the actual elements. Multiple drawings may include elements with different dimensional relationships or ratios. In multiple drawings, the same reference numeral may be used for corresponding elements to omit redundant explanations. Some elements may be given multiple names, but these examples of names are merely illustrative and do not preclude the use of other names for these elements. Elements that do not have multiple names may also be given other names. "Connection" may include not only direct connections but also connections via other elements. If the number of elements is not explicitly stated as multiple, the element may be singular or plural.

[0010] [Display Device] Figure 1 is a circuit diagram illustrating an example of a display device 10 according to the embodiment.

[0011] The display device 10 includes an array substrate 2 and a flexible printed circuit board (FPC substrate) 4.

[0012] The FPC board 4 includes a control circuit 6. The control circuit 6 is connected to a host device (not shown).

[0013] The array substrate 2 is divided into a display area and a peripheral area. The display area is provided with a pixel array 22. The peripheral area is provided with a terminal section 24, a source driver 26, a scanning circuit 28, and a light emission control circuit 30.

[0014] The terminal section 24 is also connected to the source driver 26, the scanning circuit 28, and the light emission control circuit 30. In Figure 1, the control circuit 6 is shown as being connected to the terminal section 24 via a single signal line, but it may be connected via multiple signal lines. In Figure 1, the terminal section 24 is shown as being connected to the source driver 26, the scanning circuit 28, and the light emission control circuit 30, respectively, via a single signal line, but these circuits may be connected via multiple signal lines, respectively. The control circuit 6 supplies timing signals to the source driver 26, the scanning circuit 28, and the light emission control circuit 30, synchronizing the operation timing of the source driver 26, the scanning circuit 28, and the light emission control circuit 30.

[0015] The pixel array 22 has pixels arranged in an array of N rows x M columns. The source driver 26 is positioned above or below the pixel array 22. The source driver 26 supplies image data Data[j] to the j-th column pixel, where j is any positive integer from 1 to M. The image data Data[j] includes the pixel data from the first row of the j-th column to the N-th row of the j-th column.

[0016] The scanning circuit 28 is positioned to the right or left (right in the example in Figure 1) of the pixel array 22. The scanning circuit 28 supplies a scanning signal Scan[k] to the k-th row pixel, where k is any positive integer from 1 to N. Furthermore, the scanning circuit 28 also supplies scanning signals Scan[k+1] and Scan[k+2] to the k-th row pixel. The scanning signal Scan selects a pixel in the k-th row and controls the brightness of the pixel in the selected row.

[0017] The light emission control circuit 30 supplies a light emission control signal EM[k] to the pixel in the k-th row. The light emission control signal EM[k] is a signal that controls the light emission period / non-light emission period of the pixel in the k-th row.

[0018] [Pixel Array] Figure 2 is a circuit diagram illustrating an example of a pixel array 22 according to the embodiment. The pixel array 22 has pixels 34 arranged in an array of N rows and M columns.

[0019] A pixel 34 is the smallest unit that constitutes a part of an image. Each of a group of pixels 34 may correspond to one of a group of subpixels 34 of multiple colors, for example, a red subpixel 34, a green subpixel 34, and a blue subpixel 34. Three subpixels 34 may form one full-color pixel 34. One example of an arrangement of pixels 34 is a stripe arrangement. There are no restrictions on the arrangement of pixels 34. The arrangement of pixels 34 may also be a delta arrangement, a pentile arrangement, or the like.

[0020] The red subpixel 34, green subpixel 34, and blue subpixel 34 are configured to display the smallest units of an image of different colors. Each of the red subpixel 34, green subpixel 34, and blue subpixel 34 includes a light-emitting element that emits the three primary colors of red, green, and blue. Examples of light-emitting elements include LEDs, micro-LEDs, or OLEDs. In the following description, an OLED will be described as a light-emitting element. An OLED emits light when an electric current flows through it.

[0021] The source driver 26 supplies image data Data[j] to the j-th column pixel via the j-th data line. First, image data Data[1] is supplied to the first column pixel 34. Next, image data Data[2] is supplied to the second column pixel 34. Similarly, image data Data[M] is supplied to the M-th column pixel 34.

[0022] The number of data lines is M. The data lines extend in the Y direction. The source driver 26 selects the position of the data lines, i.e., the pixel rows, in the X direction, and is therefore also called the X driver. The image data Data[1] of the first column and the image data Data[1] and Data[M] of the M column do not contain pixel data for the 1st, 2nd, (N-1)th, and Nth rows. The image data Data[1] of the second column and the image data Data[2] and Data[M-1] of the (M-1)th column do not contain pixel data for the 1st and Nth rows.

[0023] The scanning circuit 28 supplies a scanning signal Scan[k] to the pixel in the kth row via the k-th scanning line. The scanning circuit 28 supplies a scanning signal Scan[k+1] to the pixel in the kth row via the (k+1)-th scanning line, and a scanning signal Scan[k+2] to the pixel in the kth row via the (k+2)-th scanning line. First, the scanning signal Scan[1] is supplied to the pixel 34 in the first row. Next, the scanning signal Scan[2] is supplied to the pixel 34 in the second row and the pixel in the first row. Next, the scanning signal Scan[3] is supplied to the pixel 34 in the third row, the pixel 34 in the second row, and the pixel in the first row. Similarly, the scanning signal Scan[N] is supplied to the pixel 34 in the Nth row, the pixel 34 in the (N-1)th row, and the pixel 34 in the (N-2)th row. The scanning signal Scan[N+1] is supplied to the pixel 34 in the (N-1)th row and the pixel 34 in the Nth row. The scanning signal Scan[N+2] is supplied to the pixel 34 of the Nth row.

[0024] The number of scan lines is N+2. The scan lines extend in the X direction. The scanning circuit 28 selects the position of the scan lines, i.e., the pixel row, in the Y direction, and is therefore also called the first Y driver.

[0025] The light emission control circuit 30 supplies a light emission control signal EM[k] to the kth row pixel via the kth light emission control line. First, the light emission control circuit 30 supplies a light emission control signal EM[1] to the first row pixel 34. Next, the light emission control circuit 30 supplies a light emission control signal EM[2] to the second row pixel 34. Similarly, the light emission control circuit 30 supplies a light emission control signal EM[N] to the Nth row pixel 34.

[0026] The number of light emission control lines is N. The light emission control lines extend in the X direction. The light emission control circuit 30 selects the position of the light emission control lines, i.e., the pixel row in the Y direction, and is therefore also called the second Y driver.

[0027] [Source Driver] Figure 3 is a circuit diagram illustrating an example of a source driver 26 according to an embodiment. The source driver 26 includes a plurality of selection circuits 38[1], 38[2], ... 38[M]. Each of the plurality of selection circuits 38[1], 38[2], ... 38[M] is turned on or off based on the selection signals MUXR, MUXG, or MUXB supplied from the control circuit 6. When the selection circuits 38[1], 38[2], ... 38[M] are on, they supply image data Data[1], Data[2], ... Data[M] supplied from the control circuit 6 to the first row of pixels 34, the second row of pixels 34, ... the Mth row of pixels 34. The image data Data includes a data signal Vdata. The data signal Vdata includes red image data Rdata, green image data Gdata, and blue image data Bdata.

[0028] [Pixel] Figure 4 is a circuit diagram illustrating an example of a pixel 34 according to the embodiment. Figure 4 shows the pixel 34 in the jth column and kth row. The pixel 34 includes seven transistors T1, T2, T3, T4, T5, T6, T7, one capacitor 44, and one OLED 42. Transistors T1-T7 may have a channel region made of a group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties. The channel region of transistors T1-T7 may be made of low-temperature polysilicon (LTPS). Transistors T1-T7 may be formed using thin-film transistors (TFTs). TFTs include n-channel TFTs and p-channel TFTs. For example, transistors T1-T3 and T6-T7 may be n-channel TFTs, and transistors T4 and T5 may be p-channel TFTs.

[0029] The terminal to which the drive voltage VDDEL is applied is the drain of transistor T4. The source of transistor T4 is connected to the drain of transistor T2. The connection point between transistors T4 and T2 is called node N1. The source of transistor T2 is connected to the drain of transistor T5. The connection point between transistors T2 and T5 is called node N3. The source of transistor T5 is connected to the anode of OLED42. The connection point between transistor T5 and OLED42 is called node N4. The terminal to which the reference voltage VSSEL is applied is connected to the cathode of OLED42.

[0030] The light emission control signal EM2 is supplied to the gate of transistor T4. The light emission control signal EM1 is supplied to the gate of transistor T5. Both light emission control signals EM1 and EM2 are light emission control signals EM[k] output from the light emission control circuit 30 to the k-th line of light emission control lines. The light emission control signals EM1 and EM2 are generated using a single signal generation circuit within the light emission control circuit 30.

[0031] The reset voltage VSH is applied to the drain of transistor T7. The source of transistor T7 is connected to node N1. The scan signal Scan3 is supplied to the gate of transistor T7. The scan signal Scan3 is the scan signal Scan[k] output from the scan circuit 28 to the k-th scan line.

[0032] Node N1 is connected to the drain of transistor T3. The source of transistor T3 is connected to the gate of transistor T2. The scan signal Scan1 is supplied to the gate of transistor T3. The scan signal Scan1 is the scan signal Scan[k+1] output to the (k+1)th scan line output from the scanning circuit 28. The gate of transistor T2 is connected to node N4 via capacitor 44. The connection point between the gate of transistor T2 and capacitor 44 is called node N2.

[0033] Image data Data[j] is supplied to the drain of transistor T1. The source of transistor T1 is supplied to node N3. The scan signal Scan2 is supplied to the gate of transistor T1. The scan signal Scan2 is the scan signal Scan[k+2] output from the scan circuit 28 to the (k+2)th scan line.

[0034] The initialization voltage Vini is applied to the source of transistor T6. The drain of transistor T6 is connected to node N4. The light emission control signal EM1 is supplied to the gate of transistor T6.

[0035] The reference voltage VSSEL, drive voltage VDDEL, initialization voltage Vini, and reset voltage VSH may be output from the control circuit 6. The reference voltage VSSEL, drive voltage VDDEL, initialization voltage Vini, and reset voltage VSH may be output from other external devices. The reset voltage VSH and initialization voltage VINI are lower than the drive voltage VDDEL. The reference voltage VSSEL is lower than the drive voltage VDDEL. The reset voltage VSH is higher than, for example, the voltage included in the data signal Vdata (e.g., red image data Rdata, green image data Gdata, or blue image data Bdata).

[0036] When transistor T1 conducts, image data Data[j] is supplied to node N3 via transistor T1. Transistor T1 is also called a selection transistor.

[0037] When transistors T2 and T5 conduct, a current based on the image data Data[j] flows through transistor T5 and OLED 42, causing OLED 42 to emit light. Transistor T2 is also called the drive transistor.

[0038] When transistors T3 and T7 conduct, nodes N1 and N2 are connected, a reset voltage VSH is applied to the gate of transistor T2, and the gate voltage of transistor T2 is reset. Also, when transistor T3 conducts, a charge equivalent to the threshold voltage Vth of transistor T2 is stored in capacitor 44.

[0039] When the transistor T4 conducts, the drive voltage VDDEL is applied to the drain of the transistor T2.

[0040] When the transistor T5 conducts, the transistor T2 and the OLED 42 are connected, a current flows through the OLED 42, and the OLED 42 emits light. When the transistor T5 is non-conductive, the transistor T2 and the OLED 42 are non-connected, no current flows through the OLED 42, and the OLED 42 does not emit light.

[0041] When the transistor T6 conducts, the initialization voltage Vini is applied to the node N4, and the transistor T5, the OLED 42, and the capacitor 44 are initialized.

[0042] When the transistor T7 conducts, the transistor T7 applies the reset voltage VSH to the node N1, and the transistors T4, T2, and T3 are reset.

[0043] The capacitor 44 holds a charge (first charge) corresponding to the threshold voltage Vth of the transistor T2. Also, the capacitor 44 holds a charge (second charge) corresponding to the data voltage (Rdata, Gdata, or Bdata) included in the image data Data[j] input to the node N3.

[0044] The OLED 42 has diode characteristics. The OLED 42 emits light based on the current flowing through the OLED �2 (i.e., the drain current of the transistor T2).

[0045] The conduction / non-conduction of the transistor T1 is controlled by the scan signal Scan2. When the level of the scan signal Scan2 is low level, the transistor T1 is non-conductive. When the level of the scan signal Scan2 is high level, the transistor T1 is conductive.

[0046] The conduction / non-conduction of the transistor T3 is controlled by the scan signal Scan1. When the level of the scan signal Scan1 is low level, the transistor T3 is non-conductive. When the level of the scan signal Scan1 is high level, the transistor T3 is conductive.

[0047] The conduction / non-conduction of the transistor T4 is controlled by the light emission control signal EM2. When the level of the light emission control signal EM2 is at a low level, the transistor T4 conducts. When the level of the light emission control signal EM2 is at a high level, the transistor T4 is non-conductive.

[0048] The conduction / non-conduction of the transistors T5 and T6 is controlled by the light emission control signal EM1. When the level of the light emission control signal EM1 is at a low level, the transistor T5 conducts and the transistor T6 is non-conductive. When the level of the light emission control signal EM1 is at a high level, the transistor T5 is non-conductive and the transistor T6 conducts.

[0049] The conduction / non-conduction of the transistor T7 is controlled by the scan signal Scan3. When the level of the scan signal Scan3 is at a low level, the transistor T7 is non-conductive. When the level of the scan signal Scan3 is at a high level, the transistor T7 conducts.

[0050] The configuration of the pixel 34 is not limited to the configuration shown in FIG. 4 and can be changed according to the use and specifications of the display device 10. Even in the configuration shown in FIG. 4, the configurations of the transistors T1 - T7, the connection of the capacitor 44, various voltages, etc. may be set as appropriate. For example, the driving transistor T2 and the transistor T3 may be configured as High Mobility Oxide (HMO) elements, and the other transistors may be configured as Pch or Nch LTPS elements. The driving transistor T2 may be configured as an Nch LTPS element. Also, all the transistors T1 - T7 may be configured as HMO elements. In this case, the transistors T4 and T5 become Nch elements, and the level of the light emission control signal is reversed from the above description.

[0051] [Driving Method] Figure 5 is a diagram illustrating an example of driving the pixel array 22 according to the embodiment. An example of a driving method is the PWM method. In Figure 5, the horizontal direction represents time, and the vertical direction represents the row direction of the pixel array 22. The control circuit 6 writes the image data Data[1]-Data[M] of a certain row to the pixel array 22 by supplying the image data Data[1]-Data[M] of a certain row from the source driver 26 to the pixel array 22 and supplying the scanning signal Scan to the pixel array 22 from the scanning circuit 28 to select pixels of a certain row. Once the control circuit 6 has written the image data Data[j]-Data[M] of a certain row to the pixel array 22 of a certain row, it supplies the light emission control signals EM1 and EM2 of a certain row to the pixel array 22 from the light emission control circuit 30.

[0052] The control circuit 6 writes image data to the pixel array 22 row by row and causes the pixel array 22 to emit light row by row. At the beginning of the display period (1 frame period) of a row, the control circuit 6 writes image data to the pixel array 22 of a row. In the PWM method, 1 frame period is divided into multiple subframe periods. In each subframe period, the control circuit 6 first emits light to the pixels 34 using light emission control signals EM1 and EM2, and then de-emits light from the pixels 34. In each subframe period, the control circuit 6 adjusts the ratio of the illuminated period to the de-emitted period by changing the levels of the light emission control signals EM1 and EM2 output from the light emission control circuit 30 according to the data signal Vdata for one row, thereby adjusting the brightness of the displayed image.

[0053] The control circuit 6, during the last subframe period of a frame, makes the pixel 34 non-emitting, and then makes the pixel 34 emit light again (light emission 2). The non-emitting period of the last subframe period is shorter by the re-emitting period than the non-emitting period determined by the light emission control circuit 30 according to the data signal Vdata for one line. In the last subframe period, the non-emitting period is shorter and the emitting period is longer compared to other subframe periods, and the ratio of the emitting period to the non-emitting period is different from other subframe periods. If the re-emitting period is long, flicker will occur. The setting value for the re-emitting period will be described later.

[0054] After the re-illumination period, the control circuit 6 writes the image data for the next row to the pixel array 22 and displays the next row.

[0055] Figure 6 is a signal waveform diagram illustrating an example of driving the pixel array 22 according to the embodiment. Figure 6 shows the scan signals Scan1, Scan2, Scan3 and light emission control signals EM1, EM2 supplied to the k-th pixel 34. The scan signal Scan3 supplied to the k-th pixel 34 is the scan signal Scan[k]. The scan signal Scan1 is the scan signal Scan[k+1]. The scan signal Scan2 is the scan signal Scan[k+2]. The light emission control signals EM1, EM2 are the light emission control signals EM[k].

[0056] Under the control of the control circuit 6, the scanning circuit 28 raises the level of the scanning signal Scan3 to a high level at a certain timing within a certain horizontal period (referred to as the 1H period) after the start of one frame period, for example, at an intermediate timing. The light emission control circuit 30 outputs high-level light emission control signals EM1 and EM2 at the start of one frame period. Therefore, the pixels 34 are not emitting light. The 1H period corresponds to the time during which image data Data[1]-Data[M], including the data signal Vdata, is input to all pixels 34 connected to a single scan line.

[0057] The scanning circuit 28 raises the level of the scanning signal Scan1 to a high level at the midpoint of the next 1H period, and then lowers the level of the scanning signal Scan3 to a low level. The change in the level of the scanning signal Scan3 to a low level occurs at some point in the latter half of the 1H period. From the midpoint of the next 1H period to some point in the latter half, both the levels of the scanning signals Scan3 and Scan1 are high. The period during which both the levels of the scanning signals Scan3 and Scan1 are high is called the reset period. Details of the reset period will be described later.

[0058] The scanning circuit 28 further raises the level of the scanning signal Scan2 to a high level at the midpoint of the next 1H period, and then lowers the level of the scanning signal Scan1 to a low level. The change in the level of the scanning signal Scan1 to a low level occurs at some point in the latter half of the 1H period. Furthermore, from the midpoint to some point in the latter half of the next 1H period, both the levels of the scanning signals Scan1 and Scan2 remain at a high level. The period during which both the levels of the scanning signals Scan1 and Scan2 are at a high level is called the sampling period. Details of the sampling period will be described later.

[0059] The pulse widths, i.e., the high-level periods, of the scan signals Scan1, Scan2, and Scan3 are equal to each other. Scan signal Scan1 is a signal obtained by shifting scan signal Scan3 by 1H. Scan signal Scan2 is a signal obtained by shifting scan signal Scan1 by 1H.

[0060] Based on the control of the control circuit 6, the light emission control circuit 30 lowers the levels of the light emission control signals EM1 and EM2 to a low level in accordance with the end of the 1H period when the level of the scan signal Scan2 becomes low, causing the pixel 34 to emit light. The timing at which the levels of the light emission control signals EM1 and EM2 change from high to low is the end of the image data writing period and the start of the first subframe period.

[0061] Based on the control of the control circuit 6, the light emission control circuit 30 changes the levels of the light emission control signals EM1 and EM2 from low to high at a timing corresponding to one line of data signal Vdata during each subframe period, thereby making the pixels 34 non-emitting. The ratio of the light emission period to the non-light emission period in the subframe period corresponds to one line of data signal Vdata. The control circuit 6 synchronizes the timing of changing the levels of the light emission control signals EM1 and EM2 from low to high to a 1H period. Therefore, the brightness of the image is adjusted in 1H period units.

[0062] During the last subframe period of a frame, the control circuit 6 changes the levels of the light emission control signals EM1 and EM2 from high to low, causing the pixel 34 to re-emit light (light emission 2). The non-emitting period of the pixel 34 in the last subframe period includes the re-emitting period. Therefore, in the last subframe period, the non-emitting period is shorter and the emitting period is longer compared to other subframe periods. In other words, the ratio of the emitting period to the non-emitting period in the last subframe period is different from the ratio of the emitting period to the non-emitting period in other subframe periods. If the re-emitting period becomes longer, flicker occurs.

[0063] Figures 7, 8, 9, and 10 illustrate an example of the operation of pixel 34 during different periods. Figure 7 shows the state of pixel 34 during the reset period in Figure 6. At the start timing t1 of the reset period, the level of the scan signal Scan3 is high, so transistor T7 is conducting, and the voltage V(N1) at node N1 is the reset voltage VSH. At timing t1, the level of the scan signal Scan1 changes to high, so transistor T3 conducts, and the voltage V(N2) at node N2 also becomes the reset voltage VSH. During the reset period, the level of the light emission control signal EM1 is high, so transistor T6 is conducting, and the voltage V(N4) at node N4 is the initialization voltage Vini. During the reset period, the applied voltage to capacitor 44 is reset to V(N2) - V(N4) = VSH - Vini. Therefore, the applied voltage to capacitor 44 of the previous frame is reset.

[0064] The reset period continues until timing t2, when the level of the scan signal Scan3 becomes low.

[0065] Figure 8 shows the state of pixel 34 during the sampling period in Figure 6. At timing t3, the level of the scan signal Scan2 becomes high, causing transistor T1 to conduct. The charge stored in capacitor 44 is discharged through transistors T3, T2, and T1 to the source line through which the image data Data[j] flows. Discharge stops when the gate-source voltage Vgs of transistor T2 reaches the threshold voltage Vth of transistor T2.

[0066] At the start of discharge, the voltage V(N1) at node N1 and the potential V(N2) at node N2 are the reset voltage VSH. The voltage V(N3) at node N3 is the voltage V(Data) of the image data Data[j]. The voltage V(N4) at node N4 is the initialization voltage Vini. At the stop of discharge, the potential V(N1) at node N1 is (image data V(Data)) + (threshold voltage Vth of transistor T3), which is equal to the potential V(N2) at node N2. The applied voltage to capacitor 44 is V(N2) - V(N4) = V(Data) + Vth - Vini. During the sampling period, a charge corresponding to the image data is charged to capacitor 44.

[0067] The sampling period continues until timing t4, when the level of the scan signal Scan1 becomes low.

[0068] Figure 9 shows the state of the pixel 34 during the light emission period. The levels of the scan signals Scan1, Scan2, and Scan3 are low. Since the levels of the light emission control signals EM1 and EM2 are low, transistors T4 and T5 are in a conduction state. The voltage applied to capacitor 44 is held at V(Data) + Vth - Vini. This voltage is applied to the gate-source voltage Vgs of transistor T2. As a result, a current flows through transistor T2 in which the effect of the variation between pixels 34 in the threshold voltage Vth of transistor T2 is canceled out. This current flows to OLED 42, and OLED 42 emits light.

[0069] Figure 10 shows the state of pixel 34 during the non-emitting period. The levels of the scan signals Scan1, Scan2, and Scan3 are low. The levels of the light emission control signals EM1 and EM2 are high, so transistors T4 and T5 are not conducting. Transistor T2 is floating. Therefore, no current flows to OLED 42, and OLED 42 does not emit light.

[0070] During the non-emitting period, leakage current may occur in transistor T1. Alternatively, a coupling capacitor 46 may form between the source line through which the image data Data[j] flows and node N3. Due to the effects of the leakage current and the coupling capacitor 46, the voltage V(N1) at node N1 or the voltage V(N3) at node N3 may fluctuate during the non-emitting period, which may affect the writing of the next frame. This effect may result in ghosting.

[0071] However, according to the driving method of the embodiment, the last subframe period includes an emission period, a non-emission period, and a re-emission period. The re-emission period cancels out the effects of fluctuations in the voltage V(N1) at node N1 or the voltage V(N3) at node N3. This prevents the occurrence of ghosting in the next frame.

[0072] The effectiveness of canceling out fluctuations in the voltage V(N1) at node N1 or the voltage V(N3) at node N3 depends on the length of the re-emission period. The longer the re-emission period, the greater the effect of canceling out fluctuations in the voltage V(N1) at node N1 or the voltage V(N3) at node N3. However, a longer re-emission period can cause flicker. An example of setting the re-emission period is explained below.

[0073] If the image display cycle is 45 Hz, then one frame duration is 488 hours. If one frame duration is divided into four subframe durations, then one subframe duration is 122 hours. In subframe durations other than the last subframe duration, for example, the emission period is 12 hours and the non-emission period is 110 hours. In the last subframe duration, the non-emission period is 110 hours minus the re-emission period. The re-emission period is set between 1 hour and 20 hours.

[0074] This disclosure is not limited to the embodiments described above, and the components can be modified and implemented in practice without departing from the gist of the invention. Furthermore, various disclosures can be formed by appropriately combining the multiple components disclosed in the embodiments. For example, some components may be deleted from all the components shown in the embodiments. Moreover, components from different embodiments may be combined as appropriate.

[0075] 6...control circuit, 22...pixel array, 26...source driver, 28...scanning circuit, 30...light emission control circuit, 34...pixel 34, 42...OLED, 44...capacitor, T1, T2, T3, T4, T5, T6, T7...transistors

Claims

1. A display device comprising: a pixel array including a plurality of pixels arranged in a plurality of rows and a plurality of columns; a scanning circuit that supplies a first scanning signal of a first pulse width, a second scanning signal of the first pulse width, and a third scanning signal of the first pulse width to the pixels of each row; and a light emission control circuit that supplies a light emission control signal to the pixels of each row, wherein each of the plurality of pixels includes: a self-emissive display element; a capacitor connected to the display element; a first transistor connected to a third node and, when activated by the second scanning signal, supplies image data to the third node; a second transistor connected between the third node and the first node; a third transistor connected between the first node and the gate of the second transistor, whose conduction is controlled by the first scanning signal; and a seventh transistor connected to the first node and, when activated by the third scanning signal, supplies a reset voltage to the first node, wherein the capacitor is connected between the gate of the second transistor and the display element. A display device comprising: a scanning circuit that outputs a signal obtained by shifting the third scanning signal by one horizontal period as the first scanning signal, and a signal obtained by shifting the first scanning signal by one horizontal period as the second scanning signal; the scanning circuit that writes image data to the pixels of each row at the beginning of one frame period; and a light emission control circuit that, in each of one or more subframe periods included in one frame period, excluding the last subframe period, the pixels emit light, and then de-emit light at a timing corresponding to the image data; and in the last subframe period, the pixels emit light, and then de-emit light at a timing corresponding to the image data, and then emit light again.

2. The display device according to claim 1, wherein the second light emission period of the pixel in the last subframe period is 1 to 20 horizontal periods.

3. A display device comprising: a pixel array including a plurality of pixels arranged in a plurality of rows and a plurality of columns; a scanning circuit that supplies a first scan signal of a first pulse width, a second scan signal of the first pulse width, and a third scan signal of the first pulse width to the pixels in each row; and a light emission control circuit that supplies a light emission control signal to the pixels in each row, wherein each of the plurality of pixels includes: a self-emissive display element; a capacitor connected to the display element; a first transistor connected to a third node and, when activated by the second scan signal, supplies image data to the third node; a second transistor connected between the third node and the first node; a third transistor connected between the first node and the gate of the second transistor, whose conduction is controlled by the first scan signal; and a seventh transistor connected to the first node and, when activated by the third scan signal, supplies a reset voltage to the first node, wherein the capacitor is connected between the gate of the second transistor and the display element. The scanning circuit outputs a signal obtained by shifting the third scanning signal by one horizontal period as the first scanning signal, and outputs a signal obtained by shifting the first scanning signal by one horizontal period as the second scanning signal. The scanning circuit writes image data to the pixels of each row at the beginning of one frame period. The light emission control circuit changes the level of the light emission control signal from a first level to a second level at a timing corresponding to the image data in each of the one or more subframe periods in a plurality of subframe periods included in one frame, excluding the last subframe period. In the last subframe period, changes the level of the light emission control signal from a first level to a second level at a timing corresponding to the image data, and then changes the level of the light emission control signal from a second level to a first level. The pixels emit light in each of the one or more subframe periods in a plurality of subframe periods included in one frame, excluding the last subframe period, if the level of the light emission control signal is at the first level.A display device wherein the pixel is non-emitting in each of the one or more subframe periods, excluding the last subframe period, among the multiple subframe periods included in one frame, when the level of the light emission control signal is at the second level.

4. The display device according to claim 3, wherein the light emission control circuit changes the level of the light emission control signal from the second level to the first level, and then maintains the level of the light emission control signal at the first level for a horizontal period of 1 to 20.

5. The display device according to any one of claims 1 to 4, wherein each of the first transistor, the second transistor, the third transistor, and the seventh transistor is a thin-film transistor including a channel region made of a group 14 element, an oxide exhibiting semiconductor properties, or low-temperature polysilicon.

6. The display device according to any one of claims 1 to 4, wherein each of the plurality of pixels further includes a fifth transistor connected between the third node and the display element and whose conduction is controlled by a first light emission control signal, and a fourth transistor connected to the first node and, when conducted by a second light emission control signal, applies a drive voltage to the first node, and a current based on the drive voltage flows to the display element via the fourth transistor, the second transistor and the signal fifth transistor.

7. The display device according to claim 6, wherein each of the fifth transistor and the fourth transistor is a thin-film transistor including a channel region composed of a group 14 element, an oxide exhibiting semiconductor properties, or low-temperature polysilicon.

8. The display device according to claim 6, further comprising a light emission control circuit that outputs the same signal as the first light emission control signal and the second light emission control signal.

9. The display device according to claim 8, wherein the light emission control circuit outputs a first light emission control signal and a second light emission control signal during the output suspension period of the first scan signal, the second scan signal, and the third scan signal.

10. The display device according to any one of claims 1 to 4, wherein the display element includes a light-emitting diode or an organic light-emitting diode.

11. A display method for a display device comprising: a pixel array including a plurality of pixels arranged in a plurality of rows and a plurality of columns; a scanning circuit that supplies a first scanning signal of a first pulse width, a second scanning signal of the first pulse width, and a third scanning signal of the first pulse width to the pixels of each row; and a light emission control circuit that supplies a light emission control signal to the pixels of each row, wherein each of the plurality of pixels includes: a self-emitting display element; a capacitor connected to the display element; a first transistor connected to a third node and, when activated by the second scanning signal, supplies image data to the third node; a second transistor connected between the third node and the first node; a third transistor connected between the first node and the gate of the second transistor, whose conduction is controlled by the first scanning signal; and a seventh transistor connected to the first node and, when activated by the third scanning signal, supplies a reset voltage to the first node, wherein the capacitor is connected between the gate of the second transistor and the display element. A display method comprising: a scanning circuit outputting a signal obtained by shifting the third scanning signal by one horizontal period as the first scanning signal, a signal obtained by shifting the first scanning signal by one horizontal period as the second scanning signal, the scanning circuit writing image data to the pixels of each row at the beginning of one frame period, and then illuminating the pixels during multiple subframe periods, the light emission control circuit illuminating the pixels during subframe periods other than the last subframe period, and then de-illuminating the pixels at a timing corresponding to the image data, and then illuminating the pixels during the last subframe period, and then de-illuminating the pixels at a timing corresponding to the image data, and then illuminating the pixels again.

12. A pixel array comprising: a plurality of pixels arranged in multiple rows and multiple columns; a scanning circuit that supplies a first scan signal of a first pulse width, a second scan signal of the first pulse width, and a third scan signal of the first pulse width to the pixels in each row; and a light emission control circuit that supplies a light emission control signal to the pixels in each row, wherein each of the plurality of pixels includes: a self-emitting display element; a capacitor connected to the display element; a first transistor connected to a third node and, when activated by the second scan signal, supplies image data to the third node; a second transistor connected between the third node and the first node; a third transistor connected between the first node and the gate of the second transistor, whose conduction is controlled by the first scan signal; and a seventh transistor connected to the first node and, when activated by the third scan signal, supplies a reset voltage to the first node, wherein the capacitor is connected between the gate of the second transistor and the display element. A display method for a display device in which the scanning circuit outputs a signal obtained by shifting the third scanning signal by one horizontal period as the first scanning signal, and a signal obtained by shifting the first scanning signal by one horizontal period as the second scanning signal, and the scanning circuit writes image data to the pixels of each row at the beginning of one frame period, wherein the light emission control circuit changes the level of the light emission control signal from a first level to a second level at a timing corresponding to the image data in each of the one or more subframe periods in a plurality of subframe periods included in one frame, excluding the last subframe period, and then changes the level of the light emission control signal from a first level to a second level at a timing corresponding to the image data in the last subframe period, and thereafter changes the level of the light emission control signal from a second level to a first level, the pixel emits light when the level of the light emission control signal is the first level, and the pixel does not emit light when the level of the light emission control signal is the second level.

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