Array substrate, display panel, and display apparatus

Abstract

An array substrate (10), a display panel (100), and a display apparatus (1000). The array substrate (10) comprises a display area (AA) and a peripheral area (AN) surrounding the display area (AA). The array substrate (10) comprises a plurality of pixel circuits (F11), a plurality of virtual pixel circuits (F12) and a common signal bus (M1). The plurality of pixel circuits (F11) are arranged in an array in the display area (AA). The plurality of virtual pixel circuits (F12) are located in the peripheral area (AN). The plurality of virtual pixel circuits (F12) are arranged into at least one group (2), and each group (2) comprises a plurality of virtual pixel circuits (F12) arranged in an extension direction of an edge of the display area (AA). When there are a plurality of groups (2), the plurality of groups (2) are sequentially arranged in a direction gradually away from the display area (AA). The common signal bus (M1) is located in the peripheral area (AN) and extends along the edge of the display area (AA). The orthographic projection of the common signal bus (M1) on a base (1) of the array substrate (10) overlaps the orthographic projections of the virtual pixel circuits (F12) in the at least one group (2) on the base (1). The display panel (100) comprising the array substrate (10) is configured to display images.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) panels are characterized by their small size, low power consumption, no radiation, and relatively low manufacturing cost, and occupy an important position in the current display panel market.

[0003] Electronic paper display (EPD) panels, with their paper-like texture, ultra-low power consumption, no light pollution, and bistable display technology, demonstrate unique advantages in digital reading, information signage, and IoT terminals. Furthermore, EPD panels possess thin and flexible physical properties, supporting curved and even foldable designs, making them widely used in e-book readers, electronic price tags, and smart office devices, and providing an innovative path for low-carbon and environmentally friendly visualization solutions. Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate includes a display area and a peripheral area surrounding the display area. The array substrate includes a plurality of pixel circuits, a plurality of virtual pixel circuits, and a common signal bus. The plurality of pixel circuits are arranged in an array within the display area. The plurality of virtual pixel circuits are located in the peripheral area. The plurality of virtual pixel circuits include at least one group, each group including a plurality of virtual pixel circuits arranged along an extension direction along the edge of the display area. When there are multiple groups, the multiple groups are arranged sequentially in a direction gradually moving away from the display area. The common signal bus is located in the peripheral area and extends along the edge of the display area. The orthographic projection of the common signal bus on the substrate of the array substrate and the orthographic projection of the at least one group of virtual pixel circuits on the substrate overlap.

[0005] In some embodiments, the common signal bus includes a first portion extending along a first direction, which is the row direction of the plurality of pixel circuit arrays. At least one group includes a first group of virtual pixel circuits located on one side of the display area in a second direction, which is the column direction of the plurality of pixel circuit arrays. The orthographic projection of the first portion of the common signal bus onto the substrate and the orthographic projection of the virtual pixel circuits of the first group onto the substrate overlap.

[0006] In some embodiments, the virtual pixel circuit includes a second capacitor. The second capacitor includes a third plate and a fourth plate disposed on the side of the third plate away from the substrate. A first portion of the common signal bus and the fourth plate of the first group of virtual pixel circuits are electrically connected.

[0007] In some embodiments, the virtual pixel circuit further includes a second transistor. The second transistor of the first group of virtual pixel circuits and the third plate of the first group of virtual pixel circuits are isolated from each other.

[0008] In some embodiments, the first part of the common signal bus and the fourth plate of the virtual pixel circuit of the first group are electrically connected through a first hole structure, which is located above the fourth plate of the virtual pixel circuit of the first group.

[0009] In some embodiments, the display area has at least two first groups on one side in the second direction, and the first hole structure is disposed above the fourth plate of the virtual pixel circuit located in the outermost first group.

[0010] In some embodiments, among at least two first groups, the virtual pixel circuit in the outermost first group is a first type of circuit, and the virtual pixel circuit in the first group between the outermost first group and the display area is a second type of circuit. The size of the second type of circuit along the second direction is equal to the size of the pixel circuit along the second direction, and the size of the first type of circuit along the second direction is less than or equal to the size of the pixel circuit along the second direction.

[0011] In some embodiments, the array substrate further includes a source / drain conductive layer, a first organic layer, and a first passivation layer. The second electrode of the first capacitor and the fourth electrode of the second capacitor are disposed in the source / drain conductive layer. The first organic layer and the first passivation layer are disposed on the side of the source / drain conductive layer away from the substrate, and the first passivation layer is further away from the substrate than the first organic layer. The first via structure includes a first via penetrating the first organic layer and a plurality of second vias penetrating the first passivation layer. The plurality of second vias are located within the area of ​​the first via.

[0012] In some embodiments, the array substrate further includes a source / drain conductive layer. The second plate of the first capacitor and the fourth plate of the second capacitor are disposed in the source / drain conductive layer. The source / drain conductive layer also includes a first transition pattern. The first transition pattern is disposed on the side of the first group of virtual pixel circuits away from the display area and is electrically connected to the fourth plate of the first group of virtual pixel circuits. The orthographic projection of the first transition pattern on the substrate overlaps with the orthographic projection of the first portion of the common signal bus on the substrate, and the first transition pattern and the first portion of the common signal bus are electrically connected through a second via structure.

[0013] In some embodiments, the array substrate further includes a first organic layer and a first passivation layer. The first organic layer and the first passivation layer are disposed on the side of the source / drain conductive layer away from the substrate, and the first passivation layer is farther from the substrate than the first organic layer. The second via structure includes a third via penetrating the first organic layer and a plurality of fourth vias penetrating the first passivation layer. The plurality of fourth vias are located within the range of the third via.

[0014] In some embodiments, the array substrate further includes a first auxiliary signal line. The first auxiliary signal line extends along a first direction and is disposed on the side of the first group of virtual pixel circuits away from the display area. The first auxiliary signal line is located on the side of a first portion of a common signal bus closer to the substrate, and a first adapter pattern is located between the first auxiliary signal line and the first portion of the common signal bus. The first adapter pattern and the first auxiliary signal line are electrically connected through a third hole structure.

[0015] In some embodiments, the array substrate further includes a gate conductive layer and a gate insulating layer. The gate conductive layer and the gate insulating layer are disposed on the side of the source / drain conductive layer near the substrate, and the gate insulating layer is located between the gate conductive layer and the source / drain conductive layer. The first electrode of the first capacitor, the third electrode of the second capacitor, and the first auxiliary signal line are disposed in the gate conductive layer. The third via structure includes a plurality of fifth vias penetrating the gate insulating layer.

[0016] In some embodiments, the array substrate further includes a second auxiliary signal line. The second auxiliary signal line is located in the peripheral region and extends along the extension direction of the edge of the display area. The second auxiliary signal line includes a first portion extending in a first direction, and the first portion of the second auxiliary signal line is disposed on the side of the first portion of the common signal bus away from the substrate. The first portion of the second auxiliary signal line and the first portion of the common signal bus are electrically connected through a fourth hole structure.

[0017] In some embodiments, the array substrate further includes a light-shielding layer, a second passivation layer, and a first electrode layer. The second passivation layer is located between the light-shielding layer and the first electrode layer, with the light-shielding layer closer to the source / drain conductive layer than the first electrode layer. A common signal bus is disposed in the light-shielding layer, and a second auxiliary signal line is disposed in the first electrode layer. The fourth via structure includes a plurality of sixth vias penetrating the second passivation layer.

[0018] In some embodiments, the orthographic projection of the first portion of the second auxiliary signal line onto the substrate overlaps with the orthographic projection of the virtual pixel circuit of the first group onto the substrate.

[0019] In some embodiments, among the plurality of pixel circuits in the same column and the virtual pixel circuits in the first group, the second plates of the plurality of pixel circuits and the fourth plates of the virtual pixel circuits in the first group are sequentially electrically connected along a second direction.

[0020] In some embodiments, the common signal bus includes a second portion extending along a second direction, which is the column direction of the plurality of pixel circuit arrays. At least one group includes a second group of virtual pixel circuits located on one side of the display area in a first direction, which is the row direction of the plurality of pixel circuit arrays. The orthographic projection of the second portion of the common signal bus onto the substrate and the orthographic projection of the virtual pixel circuits of the second group onto the substrate overlap.

[0021] In some embodiments, the virtual pixel circuit includes a second capacitor. The second capacitor includes a third electrode plate and a fourth electrode plate disposed on the side of the third electrode plate away from the substrate. A second portion of the common signal bus is electrically connected to the fourth electrode plate of the second group of virtual pixel circuits.

[0022] In some embodiments, the array substrate further includes a plurality of first connection portions. One first connection portion is located between two adjacent virtual pixel circuits in a second direction, and the fourth plates of a plurality of virtual pixel circuits in a second group are sequentially connected through the plurality of first connection portions. A second portion of the common signal bus and the first connection portions are electrically connected through a fifth hole structure.

[0023] In some embodiments, the array substrate further includes a source / drain conductive layer, a first organic layer, and a first passivation layer. The second electrode of the first capacitor and the fourth electrode of the second capacitor are disposed on the source / drain conductive layer. The first organic layer and the first passivation layer are disposed on the side of the source / drain conductive layer away from the substrate, and the first passivation layer is further away from the substrate than the first organic layer. The fifth via structure includes a seventh via penetrating the first organic layer and an eighth via penetrating the first passivation layer.

[0024] In some embodiments, the virtual pixel circuit further includes a second transistor, which is electrically connected to a third plate of the second group of virtual pixel circuits. The array substrate also includes virtual data signal lines. The virtual data signal lines are located in the peripheral region and extend along a second direction. The virtual data signal lines are electrically connected to the second transistor, and the virtual data signal lines are configured to transmit a common signal.

[0025] In some embodiments, the display area has at least two second groups on one side of the first direction. Of the at least two second groups, the virtual pixel circuit of the outermost second group is a third type of circuit, and the virtual pixel circuit of the second group located between the outermost second group and the display area is a fourth type of circuit. The size of the fourth type of circuit along the first direction is equal to the size of the pixel circuit along the first direction, and the size of the third type of circuit along the second direction is less than or equal to the size of the pixel circuit along the first direction.

[0026] In some embodiments, the array substrate further includes a third auxiliary signal line. The third auxiliary signal line extends along a second direction and is disposed on the side of the second group of virtual pixel circuits away from the display area. The third auxiliary signal line is located on the side of the second portion of the common signal bus closer to the substrate, and the third auxiliary signal line and the second portion of the common signal bus are electrically connected through a sixth hole structure.

[0027] In some embodiments, the array substrate further includes a source / drain conductive layer, a first organic layer, and a first passivation layer. A third auxiliary signal line is disposed in the source / drain conductive layer. The first organic layer and the first passivation layer are disposed on the side of the source / drain conductive layer away from the substrate, and the first passivation layer is further away from the substrate than the first organic layer. The sixth via structure includes a ninth via penetrating the first organic layer and a plurality of tenth vias penetrating the first passivation layer, the plurality of tenth vias being located within the area of ​​the ninth via.

[0028] In some embodiments, the array substrate further includes a second auxiliary signal line. The second auxiliary signal line is located in the peripheral region and extends along the extension direction of the edge of the display area. The second auxiliary signal line includes a second portion extending in a second direction, and the second portion of the second auxiliary signal line is disposed on the side of the second portion of the common signal bus away from the substrate. The second portion of the second auxiliary signal line and the second portion of the common signal bus are electrically connected through a seventh hole structure.

[0029] In some embodiments, the array substrate further includes a light-shielding layer, a second passivation layer, and a first electrode layer. The second passivation layer is located between the light-shielding layer and the first electrode layer, with the light-shielding layer closer to the source / drain conductive layer than the first electrode layer. A common signal bus is disposed in the light-shielding layer, and a second auxiliary signal line is disposed in the first electrode layer. The seventh via structure includes a plurality of eleventh vias penetrating the second passivation layer.

[0030] In some embodiments, the orthographic projection of the second portion of the second auxiliary signal line onto the substrate overlaps with the orthographic projection of the second group of virtual pixel circuits onto the substrate.

[0031] In some embodiments, the array substrate further includes a first common signal line. The first common signal line is located between two adjacent rows of pixel circuits and extends along a first direction. The first common signal line is electrically connected to a second portion of the common signal bus.

[0032] In some embodiments, the array substrate further includes a plurality of second connection portions. One second connection portion is located between two adjacent pixel circuits in a second direction, and the second plates of a column of pixel circuits are sequentially connected through the plurality of second connection portions. A first common signal line is electrically connected to the plurality of second connection portions between two adjacent rows of pixel circuits.

[0033] In some embodiments, the array substrate further includes a source / drain conductive layer, on which the second electrode of the first capacitor is disposed. The source / drain conductive layer also includes a second transition pattern disposed in the corner region of the peripheral area. The common signal bus further includes a third portion for connecting the first portion and the second portion of the common signal bus. The second transition pattern is located on the side of the third portion of the common signal bus closer to the substrate, and the second transition pattern and the third portion of the common signal bus are electrically connected through an eighth-hole structure.

[0034] In some embodiments, the array substrate further includes a first organic layer and a first passivation layer. The first organic layer and the first passivation layer are disposed on the side of the source / drain conductive layer away from the substrate, and the first passivation layer is farther from the substrate than the first organic layer. The eighth via structure includes a twelfth via penetrating the first organic layer and a plurality of thirteenth vias penetrating the first passivation layer. The plurality of thirteenth vias are located within the range of the twelfth via.

[0035] In some embodiments, the array substrate further includes virtual data signal lines. The virtual data signal lines are located in the peripheral region and extend along a second direction. A second adapter pattern is electrically connected to the virtual data signal lines.

[0036] In some embodiments, the array substrate further includes a gate conductive layer located on the side of the source / drain conductive layer near the substrate. The gate conductive layer includes a third transition pattern located on the side of the second transition pattern near the substrate. The third transition pattern and the second transition pattern are electrically connected through a ninth-hole structure.

[0037] In some embodiments, the array substrate further includes a gate insulating layer located between the gate conductive layer and the source / drain conductive layer. The ninth via structure includes a plurality of fourteenth vias penetrating the gate insulating layer.

[0038] In some embodiments, the pixel circuit includes a first capacitor and a first transistor. The first capacitor includes a first electrode plate and a second electrode plate disposed on the side of the first electrode plate away from the substrate. The first transistor and the first electrode plate are electrically connected. The array substrate also includes a light-shielding pattern. The light-shielding pattern is disposed on the side of the first transistor away from the substrate. The common signal bus and the light-shielding pattern are made of the same material and are disposed in the same layer.

[0039] In some embodiments, the pixel circuit further includes a third capacitor, which includes a fifth electrode plate. The virtual pixel circuit further includes a first virtual electrode. The array substrate further includes a first electrode layer. The first electrode layer includes a plurality of first electrodes arranged in an array, each first electrode including a fifth electrode plate and a first virtual electrode. Adjacent rows of first electrodes are staggered in a second direction.

[0040] In some embodiments, the edge of the first electrode layer includes a plurality of protrusions. Alternatively, the edge of the first electrode layer is flush.

[0041] On the other hand, a display panel is provided. The display panel includes an array substrate, an opposing substrate, and a liquid crystal layer as described in any of the above embodiments. The opposing substrate and the array substrate are disposed opposite to each other and spaced apart. The liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0042] In another aspect, a display panel is provided. The display panel includes an array substrate, a counter substrate, and an ink layer as described in any of the above embodiments. The counter substrate and the array substrate are disposed opposite to each other and spaced apart. The ink layer is disposed between the array substrate and the counter substrate.

[0043] In another aspect, a display device is provided. The display device includes a display panel and a driver chip as described in any of the above embodiments. The driver chip and the display panel are electrically connected. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0045] Figure 1 is a plan view of a display device according to some embodiments;

[0046] Figure 2 is a plan view of a display panel according to some embodiments;

[0047] Figure 3 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0048] Figure 4 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0049] Figure 5 is a planar structural diagram of an array substrate according to some embodiments;

[0050] Figure 6 is a partial planar structural diagram of an array substrate according to some embodiments;

[0051] Figure 7 is a partial planar structural diagram of an array substrate according to some embodiments;

[0052] Figure 8 is a planar structural diagram of region A1 of the array substrate in Figure 6 or region A2 of the array substrate in Figure 7.

[0053] Figure 9 is a cross-sectional view of the array substrate in Figure 8 along the section line P1-P1.

[0054] Figure 10 is a planar structural diagram of region A3 of the array substrate in Figure 7;

[0055] Figure 11 is a cross-sectional view of the array substrate in Figure 10 along the section line P2-P2;

[0056] Figure 12 is a planar structural diagram of a partial region of the source / drain conductive layer, common signal bus, gate signal line and first common signal line in an array substrate according to some embodiments;

[0057] Figure 13 is a planar structural diagram of a partial region of the source / drain conductive layer, common signal bus, gate signal line and first common signal line in the array substrate according to some embodiments;

[0058] Figure 14A is a planar structural diagram of region A5 of the array substrate in Figure 6;

[0059] Figure 14B is a planar structural diagram of region A6 of the array substrate in Figure 7;

[0060] Figure 15 is a plan view of the common signal bus in the array substrate according to some embodiments;

[0061] Figure 16 is a planar structural diagram of region A7 of the array substrate in Figure 6;

[0062] Figure 17 is a planar structural diagram of region A8 of the array substrate in Figure 6;

[0063] Figure 18 is a planar structural diagram of region A9 of the array substrate in Figure 7;

[0064] Figure 19 is a planar structural diagram of region A10 of the array substrate in Figure 7;

[0065] Figure 20 is a cross-sectional view of the array substrate in Figure 16 along section line P3-P3 or the array substrate in Figure 17 along section line P4-P4.

[0066] Figure 21 is a cross-sectional view of the array substrate in Figure 18 along section line P5-P5 or the array substrate in Figure 19 along section line P6-P6.

[0067] Figure 22 is a planar structural diagram of region A11 of the array substrate in Figure 6;

[0068] Figure 23 is a planar structural diagram of region A12 of the array substrate in Figure 7;

[0069] Figure 24 is a cross-sectional view of the array substrate in Figure 22 along section line P7-P7;

[0070] Figure 25 is a cross-sectional view of the array substrate in Figure 23 along section line P8-P8;

[0071] Figure 26 is a planar structural diagram of region A4 of the array substrate in Figure 6;

[0072] Figure 27 is a planar structural diagram of region A13 of the array substrate in Figure 6;

[0073] Figure 28 is a planar structural diagram of region A14 of the array substrate in Figure 7;

[0074] Figure 29 is a planar structural diagram of region A15 of the array substrate in Figure 7;

[0075] Figure 30 is a cross-sectional view of the array substrate in Figure 26 along section line P9-P9.

[0076] Figure 31 is a cross-sectional view of the array substrate in Figure 27 along section line P10-P10;

[0077] Figure 32 is a cross-sectional view of the array substrate in Figure 28 along section line P11-P11.

[0078] Figure 33 is a cross-sectional view of the array substrate in Figure 29 along section line P12-P12;

[0079] Figure 34 is a plan view of the second auxiliary signal line in the array substrate according to some embodiments;

[0080] Figure 35 is a cross-sectional view of the array substrate in Figure 22 along section line P13-P13;

[0081] Figure 36 is a partial planar structural diagram of a region of the first electrode layer in an array substrate according to some embodiments;

[0082] Figure 37 is a planar structural diagram of a partial region of the first electrode layer in an array substrate according to some embodiments. Detailed Implementation

[0083] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0084] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0085] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0086] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0087] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0088] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0089] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0090] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0091] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0092] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0093] For ease of description below, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate, the XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0094] It should be noted that, for example, A1 / A2 in the accompanying drawings of this disclosure indicates that a component can be either A1 or A2, and for example, F11 (F1) indicates that component F11 belongs to component F1. Other similar reference numerals in the accompanying drawings also follow the above description.

[0095] As shown in Figure 1, some embodiments of this disclosure provide a display device 1000.

[0096] Exemplarily, the aforementioned display device 1000 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, Global Positioning System (GPS) receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 illustrates a mobile phone as an example of the display device 1000.

[0097] For example, the display device 1000 may be an electronic paper display (EPD) device. Alternatively, the display device 1000 may be a thin film transistor liquid crystal display (TFT-LCD) device.

[0098] In some embodiments, referring to FIG1, the display device 1000 may include a display panel 100 and a driver chip (not shown in the figure). The driver chip is electrically connected to the display panel 100 and can be configured to drive the display panel 100 to display an image.

[0099] For example, the driver chip within the display device 1000 may include a source driver IC.

[0100] For example, the driver chip in the display device 1000 can be encapsulated by means of chip on film (COF), chip on glass (COG) or chip on flexible material (COP) and bonded to the display panel 100.

[0101] In some embodiments, the display device 1000 may further include optical elements (not shown).

[0102] For example, the optical elements within the display device 1000 may include a camera, enabling the display device 1000 to perform various functions such as taking photos, recording videos, or facial recognition.

[0103] The optical elements within the display device 1000 may also include sensors. For example, the optical elements may include an under-display fingerprint sensor, enabling the display device 1000 to perform functions such as fingerprint recognition. Another example is that the optical elements may include an infrared sensor.

[0104] The display panel 100 described above will be described in detail below.

[0105] In some embodiments, as shown in FIG2, FIG2 is a plan view of a display panel 100 according to some embodiments. The display panel 100 may be a rectangular structure.

[0106] It should be noted that the aforementioned "rectangular structure" refers to the fact that the boundary of the display panel 100 is generally rectangular, but it is not limited to a standard rectangle. That is, the "rectangle" here includes not only the shape of a standard rectangle, but also shapes similar to rectangles, taking into account manufacturing conditions. For example, please continue to refer to Figure 2. The long and short sides of the rectangle are curved at each intersection point (i.e., corner G), that is, corner G is smooth, so that the boundary of the display panel 100 is a rounded rectangle in the plan view.

[0107] In other embodiments, the display panel 100 may also be a circular structure or other shapes with corners.

[0108] The following uses a rectangular structure for the display panel 100 as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the shape of the display panel 100 can also be any other shape.

[0109] In some embodiments, referring to FIG2, the display panel 100 may include a display area AA for displaying an image and a peripheral area AN surrounding the display area AA.

[0110] For example, a gate driving circuit (e.g., Gate driver On Array, GOA) and control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.) may be disposed in the peripheral area AN of the display panel 100. However, the function of the peripheral area AN of the display panel 100 includes, but is not limited to, these.

[0111] In some embodiments, referring to FIG2, the display panel 100 includes a plurality of subpixels F1. The plurality of subpixels F1 may be located in the display area AA of the display panel 100 to realize the image display function of the display area AA of the display panel 100. The subpixel F1 may be the smallest light-emitting unit within the display area AA.

[0112] For example, referring to FIG2, the sub-pixel F1 in the display panel 100 may include a pixel circuit F11 (the structure of the pixel circuit F11 will be described in detail below).

[0113] For example, please continue to refer to Figure 2, where multiple sub-pixels F1 within the display panel 100 can be arranged in an array within the display area AA.

[0114] For example, referring to Figure 2, multiple sub-pixels F1 within the display area AA of the display panel 100 can be arranged at intervals along a first direction X and a second direction Y. The first direction X can be the row direction of the array of multiple sub-pixels F1, and the second direction Y can be the column direction of the array of multiple sub-pixels F1.

[0115] Please refer to Figure 2. In the case where multiple sub-pixels F1 within the display panel 100 are arranged in an array within the display area AA, and each sub-pixel F1 includes a pixel circuit F11, the multiple sub-pixels F1 within the display panel 100 include multiple pixel circuits F11, and the multiple pixel circuits F11 are arranged in an array within the display area AA. The first direction X can be the row direction of the array arrangement of the multiple pixel circuits F11, and the second direction Y can be the column direction of the array arrangement of the multiple pixel circuits F11.

[0116] In some embodiments, as shown in FIG3, FIG3 is a cross-sectional structural view of a display panel 100 according to some embodiments. When the display device 1000 is a thin-film transistor liquid crystal display device, the display panel 100 in the display device 1000 is a thin-film transistor liquid crystal display panel, and the display panel 100 may include an array substrate 10, a counter substrate 20, and a liquid crystal layer 30. The counter substrate 20 and the array substrate 10 are disposed opposite to each other and spaced apart, and the liquid crystal layer 30 is disposed between the array substrate 10 and the counter substrate 20.

[0117] An electric field can be generated within the display panel 100, causing the liquid crystal molecules 301 within the liquid crystal layer 30 of the display panel 100 to deflect under the influence of the electric field. By adjusting the intensity of the electric field applied to the liquid crystal layer 30 within the display panel 100, the degree of deflection of the liquid crystal molecules 301 within the liquid crystal layer 30 can be controlled, thereby controlling the amount of light transmitted in the area where the liquid crystal molecules 301 are located within the liquid crystal layer 30, thus enabling the display panel 100 to display images.

[0118] For example, please continue to refer to FIG3, the opposing substrate 20 in the display panel 100 can be a color filter substrate.

[0119] In some embodiments, as shown in FIG4, FIG4 is a cross-sectional structural view of the display panel 100 according to some embodiments. When the display device 1000 is an electronic paper display device, the display panel 100 in the display device 1000 is an electronic paper display panel, and the display panel 100 may include an array substrate 10, an opposing substrate 20, and an ink layer 40. The opposing substrate 20 and the array substrate 10 are disposed opposite to each other and spaced apart, and the ink layer 40 is disposed between the array substrate 10 and the opposing substrate 20.

[0120] An electric field can be generated within the display panel 100, causing the charged particles 401 in the ink layer 40 of the display panel 100 to move under the action of the electric field, thereby enabling the display panel 100 to display images.

[0121] The following uses an electronic paper display panel 100 as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, these embodiments. Any other display panel can also be considered, as long as the same technical concept is applied.

[0122] The array substrate 10 within the aforementioned display panel 100 will be described in detail below.

[0123] In some embodiments, as shown in FIG5 and in conjunction with FIG2, FIG5 is a planar structural diagram of an array substrate 10 according to some embodiments. When the display panel 100 includes a display area AA and a peripheral area AN surrounding the display area AA, the array substrate 10 within the display panel 100 also includes a display area AA and a peripheral area AN surrounding the display area AA.

[0124] For example, referring to FIG5 and in conjunction with FIG2, when the display panel 100 has a rectangular structure, the array substrate 10 within the display panel 100 also has a rectangular structure. The peripheral area AN of the array substrate 10 may include a first border area AN1, a second border area AN2, a third border area AN3, and a fourth border area AN4. The first border area AN1 and the second border area AN2 are disposed on both sides of the display area AA of the array substrate 10 along the first direction X, and the third border area AN3 and the fourth border area AN4 are disposed on both sides of the display area AA of the array substrate 10 along the second direction Y.

[0125] The array substrate 10 may include a multilayer film structure, and the film structure of the array substrate 10 will be described in detail below.

[0126] In some embodiments, as shown in Figures 6, 7, 8, and 9, Figures 6 and 7 are planar structural views of partial regions of the array substrate 10 according to some embodiments, Figure 8 is a planar structural view of region A1 of the array substrate 10 in Figure 6 or region A2 of the array substrate 10 in Figure 7, and Figure 9 is a cross-sectional structural view of the array substrate 10 in Figure 8 along the section line P1-P1. The array substrate 10 may include a substrate 1.

[0127] For example, substrate 1 can be a rigid substrate. For instance, substrate 1 can be a glass substrate or a polymethyl methacrylate (PMMA) substrate, etc.

[0128] Alternatively, substrate 1 can also be a flexible substrate. For example, substrate 1 can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate, etc.

[0129] In some embodiments, please continue to refer to FIG8 and FIG9, the array substrate 10 may further include a gate conductive layer 31.

[0130] For example, referring to FIG9, in the case where the array substrate 10 includes a substrate 1, the gate conductive layer 31 may be located on one side of the substrate 1.

[0131] For example, the material of the gate conductive layer 31 may include one or more (two or more) of the following metallic materials: molybdenum (MO), titanium (Ti), aluminum (Al), and copper (Cu).

[0132] For example, the gate conductive layer 31 can be deposited using a physical vapor deposition (PVD) process.

[0133] In some embodiments, please continue to refer to Figures 8 and 9, the array substrate 10 may also include a source / drain conductive layer 32.

[0134] For example, referring to FIG9, when the array substrate 10 includes a substrate 1 and a gate conductive layer 31, and the gate conductive layer 31 is located on one side of the substrate 1, the source / drain conductive layer 32 may be located on the side of the gate conductive layer 31 away from the substrate 1. That is, the gate conductive layer 31 may be located on the side of the source / drain conductive layer 32 closer to the substrate 1.

[0135] For example, the material of the source and drain conductive layer 32 may include one or more (two or more) of the following metallic materials: molybdenum (MO), titanium (Ti), aluminum (Al), and copper (Cu).

[0136] For example, the source / drain conductive layer 32 can be deposited using a physical vapor deposition process.

[0137] In some embodiments, referring to FIG9, where the array substrate 10 includes a gate conductive layer 31 and a source / drain conductive layer 32, and the gate conductive layer 31 is located on the side of the source / drain conductive layer 32 closer to the substrate 1, the array substrate 10 may further include a gate insulating layer 41. The gate insulating layer 41 may be located between the gate conductive layer 31 and the source / drain conductive layer 32.

[0138] For example, the material of the gate insulating layer 41 may include one or more (two or more) of silicon nitride (Si3N4), silicon oxide (SiO2) and silicon oxynitride (SiON).

[0139] For example, the gate insulating layer 41 can be deposited using a plasma enhanced chemical vapor deposition (PECVD) process.

[0140] In some embodiments, referring to FIG9, where the array substrate 10 includes a substrate 1 and a source / drain conductive layer 32, the array substrate 10 may further include a first passivation layer 42. The first passivation layer 42 is located on the side of the source / drain conductive layer 32 away from the substrate 1.

[0141] For example, the material of the first passivation layer 42 may include one or more (two or more) of silicon nitride (Si3N4), silicon oxide (SiO2) and silicon oxynitride (SiON).

[0142] For example, the first passivation layer 42 can be deposited using a plasma-enhanced chemical vapor deposition process.

[0143] In some embodiments, referring to FIG9, where the array substrate 10 includes a substrate 1, a source / drain conductive layer 32, and a first passivation layer 42, and the first passivation layer 42 is located on the side of the source / drain conductive layer 32 away from the substrate 1, the array substrate 10 may further include a first organic layer 43. The first organic layer 43 is located on the side of the source / drain conductive layer 32 away from the substrate 1, and the first passivation layer 42 is farther from the substrate 1 than the first organic layer 43. That is, the first organic layer 43 is located between the source / drain conductive layer 32 and the first passivation layer 42.

[0144] For example, the material of the first organic layer 43 may include an organic material (ORG).

[0145] For example, the material of the first organic layer 43 may include an organic resin material.

[0146] In some embodiments, please continue to refer to Figures 8 and 9, the array substrate 10 may also include a light-shielding layer 33.

[0147] For example, referring to FIG9, when the array substrate 10 includes a substrate 1 and a source / drain conductive layer 32, the light-shielding layer 33 may be located on the side of the source / drain conductive layer 32 away from the substrate 1.

[0148] For example, please continue to refer to FIG9. When the array substrate 10 includes a source / drain conductive layer 32, a first passivation layer 42 and a first organic layer 43, the first passivation layer 42 and the first organic layer 43 may be located between the source / drain conductive layer 32 and the light-shielding layer 33, and the first passivation layer 42 may be located between the first organic layer 43 and the light-shielding layer 33.

[0149] In the array substrate 10 described above, the first organic layer 43 is located between the source / drain conductive layer 32 and the light-shielding layer 33. The material of the first organic layer 43 includes organic materials. Organic materials have a small dielectric constant, which can effectively suppress the parasitic capacitance effect between the source / drain conductive layer 32 and the light-shielding layer 33.

[0150] In the array substrate 10 described above, the first passivation layer 42 is located between the first organic layer 43 and the light-shielding layer 33, which can increase the adhesion between the first organic layer 43 and the light-shielding layer 33, thereby improving the connection stability between the first organic layer 43 and the light-shielding layer 33.

[0151] For example, the material of the light-shielding layer 33 may include one or more (two or more) of the following metallic materials: molybdenum (MO), titanium (Ti), aluminum (Al), and copper (Cu).

[0152] For example, the light-shielding layer 33 can be deposited using a physical vapor deposition process.

[0153] In some embodiments, please continue to refer to Figures 8 and 9, the array substrate 10 may also include a first electrode layer 34.

[0154] For example, referring to FIG9, when the array substrate 10 includes a source / drain conductive layer 32 and a light-shielding layer 33, the light-shielding layer 33 may be closer to the source / drain conductive layer 32 than the first electrode layer 34. That is, the light-shielding layer 33 may be located between the source / drain conductive layer 32 and the first electrode layer 34.

[0155] For example, the material of the first electrode layer 34 may include indium tin oxide (ITO) or the like.

[0156] In some embodiments, referring to FIG9, when the array substrate 10 includes a light-shielding layer 33 and a first electrode layer 34, the array substrate 10 may further include a second passivation layer 44. The second passivation layer 44 is located between the light-shielding layer 33 and the first electrode layer 34.

[0157] For example, the material of the second passivation layer 44 may include one or more (two or more) of silicon nitride (Si3N4), silicon oxide (SiO2) and silicon oxynitride (SiON).

[0158] For example, the second passivation layer 44 can be deposited using a plasma-enhanced chemical vapor deposition process.

[0159] In some embodiments, please continue to refer to FIG8, the array substrate 10 may further include an active layer 35.

[0160] For example, referring to FIG8, in the case where the array substrate 10 includes a substrate 1 and a gate conductive layer 31, the active layer 35 may be located on the side of the gate conductive layer 31 away from the substrate 1.

[0161] For example, the material of the active layer 35 may include one or more of amorphous silicon (a-Si), low temperature poly-silicon (LTPS), amorphous oxide semiconductor (a-Oxide), and low temperature polycrystalline oxide (LTPO).

[0162] In some embodiments, referring to Figures 6 and 7, the array substrate 10 may include a plurality of pixel circuits F11. That is, the pixel circuit F11 of the sub-pixel F1 in the display panel 100 may be located within the array substrate 10. The pixel circuit F11 described above will be described in detail below.

[0163] In some embodiments, referring to Figures 8 and 9, the pixel circuit F11 may include a first capacitor C1. The first capacitor C1 includes a first electrode C11 and a second electrode C12 disposed on the side of the first electrode C11 away from the substrate 1.

[0164] For example, please continue to refer to Figures 8 and 9. When the array substrate 10 includes a gate conductive layer 31, the first plate C11 of the first capacitor C1 can be disposed on the gate conductive layer 31.

[0165] For example, please continue to refer to Figures 8 and 9. When the array substrate 10 includes a source-drain conductive layer 32, the second electrode C12 of the first capacitor C1 can be disposed on the source-drain conductive layer 32.

[0166] In some embodiments, referring to Figures 8 and 9, the pixel circuit F11 may further include a first transistor T1. When the pixel circuit F11 includes a first capacitor C1, the first transistor T1 may be electrically connected to the first plate C11 of the first capacitor C1.

[0167] For example, referring to FIG8, the first transistor T1 can be a thin film transistor (TFT). The first transistor T1 may include a first active layer pattern T11 and a first gate pattern T12, which are disposed opposite to each other in the third direction Z (i.e., the thickness direction of the substrate 1). The first active layer pattern T11 of the first transistor T1 may include a source region and a drain region, as well as a channel region located between the source region and the drain region.

[0168] The first active layer pattern T11 of the first transistor T1 can be connected to the source contact s and the drain contact d, respectively. Specifically, the source region in the first active layer pattern T11 of the first transistor T1 can be connected to the source contact s, and the drain region in the first active layer pattern T11 of the first transistor T1 can be connected to the drain contact d.

[0169] For example, please continue to refer to FIG8. When the array substrate 10 includes an active layer 35 and the first transistor T1 includes a first active layer pattern T11, the first active layer pattern T11 of the first transistor T1 can be disposed on the active layer 35.

[0170] For example, please continue to refer to FIG8. When the array substrate 10 includes a gate conductive layer 31 and the first transistor T1 includes a first gate pattern T12, the first gate pattern T12 of the first transistor T1 may be disposed on the gate conductive layer 31.

[0171] For example, please continue to refer to FIG8. In the case where the array substrate 10 includes a source-drain conductive layer 32 and the array substrate 10 also includes a source contact s and a drain contact d, both the source contact s and the drain contact d can be disposed on the source-drain conductive layer 32.

[0172] For example, the first transistor T1 can be a low-temperature polysilicon thin-film transistor. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging. When the first transistor T1 is a low-temperature polysilicon thin-film transistor, the material of the first active layer pattern T11 of the first transistor T1 includes low-temperature polysilicon (LTPS).

[0173] Alternatively, the first transistor T1 can be an oxide thin-film transistor. Oxide thin-film transistors have advantages such as low leakage current. When the first transistor T1 is an oxide thin-film transistor, the material of the first active layer pattern T11 of the first transistor T1 includes oxide semiconductor.

[0174] For example, the first transistor T1 can be an N-type transistor. Alternatively, the first transistor T1 can be a P-type transistor.

[0175] For example, the number of first transistors T1 within the pixel circuit F11 can be one.

[0176] Alternatively, please refer to Figure 8. The number of first transistors T1 in the pixel circuit F11 can be multiple (greater than or equal to two).

[0177] For example, referring to Figures 8 and 9, when the pixel circuit F11 includes a first transistor T1, the array substrate 10 may also include a light-shielding pattern 331. The light-shielding pattern 331 is disposed on the side of the first transistor T1 away from the substrate 1.

[0178] In the array substrate 10 described above, the light-shielding pattern 331 is disposed on the side of the first transistor T1 away from the substrate 1, so that the light-shielding pattern 331 can block external light from shining on the first transistor T1 (for example, the channel region in the first active layer pattern T11 of the first transistor T1), thereby making it difficult for light to shine on the first transistor T1, which can prevent the performance of the first transistor T1 from changing due to light exposure, and can prevent the degradation and leakage current of the first transistor T1 caused by light exposure, thus ensuring the normal operation of the first transistor T1 and improving the reliability of the array substrate 10.

[0179] For example, referring to Figures 8 and 9, when the array substrate 10 includes a light-shielding layer 33, the light-shielding pattern 331 can be disposed on the light-shielding layer 33.

[0180] In some embodiments, referring to Figures 8 and 9, the pixel circuit F11 may also include the fifth plate C15 of the third capacitor C3.

[0181] For example, the third capacitor C3 may also include a sixth plate (not shown in the figure), which is disposed on the side of the fifth plate C15 away from the substrate 1.

[0182] Please refer to Figures 8 and 9, and in conjunction with Figure 3, when the display panel 100 includes an array substrate 10, an opposing substrate 20, and a liquid crystal layer 30, with the opposing substrate 20 and the array substrate 10 facing each other and spaced apart, and the liquid crystal layer 30 disposed between the array substrate 10 and the opposing substrate 20, the sixth plate of the third capacitor C3 can be disposed within the opposing substrate 20. An electric field can be generated between the fifth plate C15 and the sixth plate of the third capacitor C3, which can cause the liquid crystal molecules 301 in the liquid crystal layer 30 of the display panel 100 to deflect under the action of the electric field, thereby enabling the display panel 100 to display images.

[0183] Please refer to Figures 8 and 9, and in conjunction with Figure 4, in the case where the display panel 100 includes an array substrate 10, a counter substrate 20, and an ink layer 40, with the counter substrate 20 and the array substrate 10 facing each other and spaced apart, and the ink layer 40 disposed between the array substrate 10 and the counter substrate 20, the sixth plate of the third capacitor C3 can be disposed within the counter substrate 20. An electric field can be generated between the fifth plate C15 and the sixth plate of the third capacitor C3, enabling the charged particles 401 in the ink layer 40 of the display panel 100 to move under the action of the electric field, thereby allowing the display panel 100 to display images.

[0184] For example, please continue to refer to Figures 8 and 9. When the array substrate 10 includes a first electrode layer 34, the fifth electrode plate C15 of the third capacitor C3 may be disposed on the first electrode layer 34.

[0185] In some embodiments, referring to Figures 5, 6, and 7, the array substrate 10 may further include a plurality of virtual pixel circuits F12. The virtual pixel circuits F12 described above will be described in detail below.

[0186] In some embodiments, please continue to refer to Figures 5, 6 and 7, the plurality of virtual pixel circuits F12 in the array substrate 10 may be located in the peripheral area AN of the array substrate 10.

[0187] The plurality of virtual pixel circuits F12 may include at least one group 2, each group 2 including a plurality of virtual pixel circuits F12 arranged along the extending direction of the edge of the display area AA of the array substrate 10. When there are multiple groups 2, the multiple groups 2 may be arranged sequentially along a direction gradually moving away from the display area AA of the array substrate 10.

[0188] In the aforementioned array substrate 10, a plurality of virtual pixel circuits F12 are located in the peripheral region AN of the array substrate 10, and the plurality of virtual pixel circuits F12 include at least one group 2, each group 2 including a plurality of virtual pixel circuits F12 arranged along the extending direction of the edge of the display area AA of the array substrate 10, such that in the fabrication process of the array substrate 10 (e.g., etching process, etc.), the plurality of virtual pixel circuits F12 can balance the pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 and the pixel circuits F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA, etc.). The key process parameters such as etching rate and photoresist development uniformity of 11 can improve the consistency of the morphological features, electrical performance, and optical properties of the pixel circuit F11 located in the edge region of the display area AA of the array substrate 10 with those of the pixel circuit F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA). This can effectively suppress the performance deviation of the pixel circuit F11 located in the edge region of the display area AA of the array substrate 10 caused by the edge effect, which is beneficial to improving the overall brightness uniformity and color reproduction accuracy of the display panel 100 including the array substrate 10.

[0189] For example, referring to Figures 6 and 7, the plurality of virtual pixel circuits F12 within the array substrate 10 may include a first group 21. The virtual pixel circuits F12 of the first group 21 are located on one side of the display area AA of the array substrate 10 in the second direction Y.

[0190] For example, please continue to refer to Figures 6 and 7, and in conjunction with Figure 5, in the case where the peripheral area AN of the array substrate 10 includes a third border area AN3 and a fourth border area AN4, and the third border area AN3 and the fourth border area AN4 are disposed on both sides of the display area AA of the array substrate 10 along the second direction Y, the virtual pixel circuit F12 of the first group 21 can be located in the third border area AN3.

[0191] For example, please continue to refer to Figures 6 and 7, and in conjunction with Figure 5, when the peripheral area AN of the array substrate 10 includes a third border area AN3 and a fourth border area AN4, and the third border area AN3 and the fourth border area AN4 are disposed on both sides of the display area AA of the array substrate 10 along the second direction Y, the virtual pixel circuit F12 of the first group 21 can be located in the fourth border area AN4.

[0192] For example, please continue to refer to Figures 6 and 7, and in conjunction with Figure 5, when the peripheral area AN of the array substrate 10 includes a third border area AN3 and a fourth border area AN4, and the third border area AN3 and the fourth border area AN4 are disposed on both sides of the display area AA of the array substrate 10 along the second direction Y, the virtual pixel circuit F12 of the first group 21 can be located simultaneously in the third border area AN3 and the fourth border area AN4.

[0193] For example, referring to FIG6, in the case where the plurality of virtual pixel circuits F12 in the array substrate 10 include a first group 21, the plurality of virtual pixel circuits F12 may be provided with a first group 21 on one side in the second direction Y.

[0194] Alternatively, referring to Figure 7, in the case where the multiple virtual pixel circuits F12 in the array substrate 10 include a first group 21, at least two first groups 21 may be provided on one side of the multiple virtual pixel circuits F12 in the second direction Y.

[0195] For example, referring to FIG7, in the case where the multiple virtual pixel circuits F12 in the array substrate 10 include a first group 21, two first groups 21 may be provided on one side of the multiple virtual pixel circuits F12 in the second direction Y.

[0196] For example, if the array substrate 10 includes a first group 21 among the multiple virtual pixel circuits F12, then three, four, or five first groups 21 may be provided on one side of the multiple virtual pixel circuits F12 in the second direction Y.

[0197] For example, please continue to refer to FIG7. In the case where the multiple virtual pixel circuits F12 in the array substrate 10 include a first group 21 and at least two first groups 21 are provided on one side of the multiple virtual pixel circuits F12 in the second direction Y, among the at least two first groups 21, the virtual pixel circuit F12 located in the outermost first group 21 is a first type circuit D1, and the virtual pixel circuit F12 located in the first group 21 between the outermost first group 21 and the display area AA of the array substrate 10 is a second type circuit D2.

[0198] Please refer to Figure 7. The dimension LD2 of the second type of circuit D2 along the second direction Y can be equal to the dimension LF11 of the pixel circuit F11 along the second direction Y.

[0199] In the array substrate 10 described above, the dimension LD2 of the second type circuit D2 along the second direction Y is equal to the dimension LF11 of the pixel circuit F11 along the second direction Y. That is, the dimension LD2 of the virtual pixel circuit F12 of the first group 21 located between the outermost first group 21 and the display area AA of the array substrate 10 along the second direction Y is equal to the dimension LF11 of the pixel circuit F11 along the second direction Y. This allows the second type circuit D2 to better balance the pixel circuit F11 located in the edge region of the display area AA of the array substrate 10 and the other regions (e.g., the center of the display area AA) in the fabrication process of the array substrate 10. By adjusting key process parameters such as etching rate and photoresist development uniformity of pixel circuits F11 in the display area AA of the array substrate 10, the consistency of morphological features, electrical performance, and optical properties of pixel circuits F11 in the edge area of ​​the display area AA of the array substrate 10 and pixel circuits F11 in other areas of the display area AA of the array substrate 10 (e.g., the central area of ​​the display area AA) can be further improved. This can more effectively suppress the performance deviation of pixel circuits F11 in the edge area of ​​the display area AA of the array substrate 10 caused by edge effects, and is conducive to further improving the overall brightness uniformity and color reproduction accuracy of the display panel 100 including the array substrate 10.

[0200] Please refer to Figure 7. The dimension LD1 of the first type of circuit D1 along the second direction Y can be less than or equal to the dimension LF11 of the pixel circuit F11 along the second direction Y.

[0201] For example, the dimension LD1 of the first type of circuit D1 along the second direction Y can be equal to the dimension LF11 of the pixel circuit F11 along the second direction Y.

[0202] In the array substrate 10 described above, the dimension LD1 of the first type of circuit D1 along the second direction Y is equal to the dimension LF11 of the pixel circuit F11 along the second direction Y. That is, the dimension LD1 of the virtual pixel circuit F12 located in the outermost first group 21 along the second direction Y is equal to the dimension LF11 of the pixel circuit F11 along the second direction Y. This allows the first type of circuit D1 to better balance the pixel circuit F11 located in the edge region of the display area AA of the array substrate 10 with the pixel circuit F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA). By improving key process parameters such as etching rate and photoresist development uniformity, the consistency of morphological features, electrical performance, and optical properties of pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 and pixel circuits F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA) can be further improved. This can more effectively suppress the performance deviation of pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 caused by edge effects, and further improve the overall brightness uniformity and color reproduction accuracy of the display panel 100 including the array substrate 10.

[0203] For example, please refer to Figure 7. The size LD1 of the first type of circuit D1 along the second direction Y can be smaller than the size LF11 of the pixel circuit F11 along the second direction Y.

[0204] In the array substrate 10 described above, the dimension LD1 of the first type of circuit D1 along the second direction Y is smaller than the dimension LF11 of the pixel circuit F11 along the second direction Y. That is, the dimension LD1 of the virtual pixel circuit F12 located in the outermost first group 21 along the second direction Y is smaller than the dimension LF11 of the pixel circuit F11 along the second direction Y. This makes the dimension LD1 of the virtual pixel circuit F12 located in the outermost first group 21 along the second direction Y smaller, which is beneficial to reducing the size of the peripheral area AN of the array substrate 10. This is beneficial to the array substrate 10 achieving a narrow bezel, and thus beneficial to the display panel 100 including the array substrate 10 achieving a narrow bezel.

[0205] For example, referring to Figures 6 and 7, the plurality of virtual pixel circuits F12 within the array substrate 10 may include a second group 22. The virtual pixel circuits F12 of the second group 22 are located on one side of the display area AA of the array substrate 10 in the first direction X.

[0206] For example, please continue to refer to Figures 6 and 7, and in conjunction with Figure 5, in the case where the peripheral area AN of the array substrate 10 includes a first border area AN1 and a second border area AN2, and the first border area AN1 and the second border area AN2 are disposed on both sides of the display area AA of the array substrate 10 along the first direction X, the virtual pixel circuit F12 of the second group 22 can be located in the first border area AN1.

[0207] For example, if the peripheral area AN of the array substrate 10 includes a first border area AN1 and a second border area AN2, and the first border area AN1 and the second border area AN2 are disposed on both sides of the display area AA of the array substrate 10 along the first direction X, the virtual pixel circuit F12 of the second group 22 can be located in the second border area AN2.

[0208] For example, please continue to refer to Figures 6 and 7, and in conjunction with Figure 5, when the peripheral area AN of the array substrate 10 includes a first border area AN1 and a second border area AN2, and the first border area AN1 and the second border area AN2 are disposed on both sides of the display area AA of the array substrate 10 along the first direction X, the virtual pixel circuit F12 of the second group 22 can be located simultaneously in the first border area AN1 and the second border area AN2.

[0209] For example, please continue to refer to FIG6. In the case where the plurality of virtual pixel circuits F12 in the array substrate 10 include a second group 22, a second group 22 may be provided on one side of the plurality of virtual pixel circuits F12 in the first direction X.

[0210] Alternatively, referring to Figure 7, if the multiple virtual pixel circuits F12 in the array substrate 10 include a second group 22, at least two second groups 22 may be provided on one side of the multiple virtual pixel circuits F12 in the first direction X.

[0211] For example, referring to FIG7, in the case where the multiple virtual pixel circuits F12 in the array substrate 10 include a second group 22, two second groups 22 may be provided on one side of the multiple virtual pixel circuits F12 in the first direction X.

[0212] For example, if the array substrate 10 includes a second group 22 among the multiple virtual pixel circuits F12, then three, four, or five second groups 22 may be provided on one side of the multiple virtual pixel circuits F12 in the first direction X.

[0213] For example, please continue to refer to FIG7. In the case where the multiple virtual pixel circuits F12 in the array substrate 10 include a second group 22, and at least two second groups 22 are provided on one side of the multiple virtual pixel circuits F12 in the first direction X, among the at least two second groups 22, the virtual pixel circuit F12 located in the outermost second group 22 is a third type of circuit D3, and the virtual pixel circuit F12 located in the second group 22 between the outermost second group 22 and the display area AA of the array substrate 10 is a fourth type of circuit D4.

[0214] Please refer to Figure 7. The dimension LD4 of the fourth type of circuit D4 along the first direction X can be equal to the dimension LF12 of the pixel circuit F11 along the first direction X.

[0215] In the aforementioned array substrate 10, the dimension LD4 of the fourth type circuit D4 along the first direction X is equal to the dimension LF12 of the pixel circuit F11 along the first direction X. That is, the dimension LD4 of the virtual pixel circuit F12 of the second group 22 located between the outermost second group 22 and the display area AA of the array substrate 10 along the first direction X is equal to the dimension LF12 of the pixel circuit F11 along the first direction X. This allows the fourth type circuit D4 to better balance the pixel circuit F11 located in the edge region of the display area AA of the array substrate 10 and other regions (e.g., the center of the display area AA) in the fabrication process of the array substrate 10. By adjusting key process parameters such as etching rate and photoresist development uniformity of pixel circuits F11 in the display area AA of the array substrate 10, the consistency of morphological features, electrical performance, and optical properties of pixel circuits F11 in the edge area of ​​the display area AA of the array substrate 10 and pixel circuits F11 in other areas of the display area AA of the array substrate 10 (e.g., the central area of ​​the display area AA) can be further improved. This can more effectively suppress the performance deviation of pixel circuits F11 in the edge area of ​​the display area AA of the array substrate 10 caused by edge effects, and is conducive to further improving the overall brightness uniformity and color reproduction accuracy of the display panel 100 including the array substrate 10.

[0216] Please refer to Figure 7. The dimension LD3 of the third type of circuit D3 along the first direction X can be less than or equal to the dimension LF12 of the pixel circuit F11 along the first direction X.

[0217] For example, please continue to refer to Figure 7. The dimension LD3 of the third type of circuit D3 along the first direction X can be equal to the dimension LF12 of the pixel circuit F11 along the first direction X.

[0218] In the array substrate 10 described above, the dimension LD3 of the third type circuit D3 along the first direction X is equal to the dimension LF12 of the pixel circuit F11 along the first direction X. That is, the dimension LD3 of the virtual pixel circuit F12 located in the outermost second group 22 along the first direction X is equal to the dimension LF12 of the pixel circuit F11 along the first direction X. This allows the third type circuit D3 to better balance the pixel circuit F11 located in the edge region of the display area AA of the array substrate 10 and the pixel circuit F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA). By improving key process parameters such as etching rate and photoresist development uniformity, the consistency of morphological features, electrical performance, and optical properties of pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 and pixel circuits F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA) can be further improved. This can more effectively suppress the performance deviation of pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 caused by edge effects, and further improve the overall brightness uniformity and color reproduction accuracy of the display panel 100 including the array substrate 10.

[0219] For example, the dimension LD3 of the third type circuit D3 along the first direction X can be smaller than the dimension LF12 of the pixel circuit F11 along the first direction X.

[0220] In the array substrate 10 described above, the dimension LD3 of the third type circuit D3 along the first direction X is smaller than the dimension LF12 of the pixel circuit F11 along the first direction X. That is, the dimension LD3 of the virtual pixel circuit F12 of the outermost second group 22 along the first direction X is smaller than the dimension LF12 of the pixel circuit F11 along the first direction X. This makes the dimension LD3 of the virtual pixel circuit F12 of the outermost second group 22 along the first direction X smaller, which is beneficial to reducing the size of the peripheral area AN of the array substrate 10. This is beneficial to the array substrate 10 achieving a narrow bezel, and thus beneficial to the display panel 100 including the array substrate 10 achieving a narrow bezel.

[0221] In some embodiments, as shown in Figures 10 and 11, Figure 10 is a plan view of region A3 of the array substrate 10 in Figure 7, and Figure 11 is a cross-sectional view of the array substrate 10 in Figure 10 along section line P2-P2. The virtual pixel circuit F12 within the array substrate 10 may include a second capacitor C2. The second capacitor C2 includes a third electrode C13 and a fourth electrode C14 disposed on the side of the third electrode C13 away from the substrate 1.

[0222] For example, please continue to refer to FIG10 and FIG11. When the array substrate 10 includes a gate conductive layer 31, the third plate C13 of the second capacitor C2 may be disposed on the gate conductive layer 31.

[0223] For example, please continue to refer to Figures 10 and 11. When the array substrate 10 includes a source-drain conductive layer 32, the fourth plate C14 of the second capacitor C2 may be disposed on the source-drain conductive layer 32.

[0224] For example, as shown in Figures 12 and 13, which are planar structural diagrams of partial regions of the source / drain conductive layer 32, common signal bus M1, gate signal line, and first common signal line Com1 within the array substrate 10 according to some embodiments, the array substrate 10 may further include a plurality of first connection portions 321. A first connection portion 321 may be located between two adjacent virtual pixel circuits F12 in the second direction Y, and the fourth plate C14 of the second capacitor C2 within the plurality of virtual pixel circuits F12 of a second group 22 may be sequentially connected through the plurality of first connection portions 321.

[0225] For example, please continue to refer to FIG12 and FIG13. When the array substrate 10 includes a pixel circuit F11 and the pixel circuit F11 includes a first capacitor C1, in the multiple pixel circuits F11 in the same column and the virtual pixel circuits F12 in the first group 21, the second plate C12 of the first capacitor C1 in the multiple pixel circuits F11 and the fourth plate C14 of the second capacitor C2 in the virtual pixel circuits F12 in the first group 21 are sequentially electrically connected along the second direction Y.

[0226] For example, referring to Figures 12 and 13, the array substrate 10 may also include a plurality of second connection portions 322. A second connection portion 322 may be located between two adjacent pixel circuits F11 in the second direction Y, and the second plates C12 of the first capacitors C1 in a column of pixel circuits F11 may be connected sequentially through a plurality of second connection portions 322.

[0227] In some embodiments, please continue to refer to FIG10, the virtual pixel circuit F12 in the array substrate 10 may further include a second transistor T2.

[0228] For example, referring to FIG10, the second transistor T2 can be a thin film transistor (TFT). The second transistor T2 may include a second active layer pattern T21 and a second gate pattern T22, which are disposed opposite to each other in the third direction Z (i.e., the thickness direction of the substrate 1). The second active layer pattern T21 of the second transistor T2 may include a source region and a drain region, as well as a channel region located between the source region and the drain region.

[0229] For example, please continue to refer to FIG10. When the array substrate 10 includes an active layer 35 and the second transistor T2 includes a second active layer pattern T21, the second active layer pattern T21 of the second transistor T2 can be disposed on the active layer 35.

[0230] For example, please continue to refer to FIG10. When the array substrate 10 includes a gate conductive layer 31 and the second transistor T2 includes a second gate pattern T22, the second gate pattern T22 of the second transistor T2 may be disposed on the gate conductive layer 31.

[0231] For example, the second transistor T2 can be a low-temperature polysilicon thin-film transistor. In the case that the second transistor T2 is a low-temperature polysilicon thin-film transistor, the material of the second active layer pattern T21 of the second transistor T2 includes low-temperature polysilicon (LTPS).

[0232] Alternatively, the second transistor T2 can be an oxide thin-film transistor. In the case where the second transistor T2 is an oxide thin-film transistor, the material of the second active layer pattern T21 of the second transistor T2 includes oxide semiconductor.

[0233] For example, the second transistor T2 can be an N-type transistor. Alternatively, the second transistor T2 can be a P-type transistor.

[0234] For example, the number of second transistors T2 within the virtual pixel circuit F12 can be one.

[0235] Alternatively, please refer to Figure 10. The number of second transistors T2 in the virtual pixel circuit F12 can be multiple (greater than or equal to two).

[0236] In some embodiments, please continue to refer to FIG10 and FIG11, the virtual pixel circuit F12 in the array substrate 10 may further include a first virtual electrode C16.

[0237] For example, please continue to refer to FIG10 and FIG11. When the array substrate 10 includes a first electrode layer 34, the first virtual electrode C16 may be disposed on the first electrode layer 34.

[0238] In some embodiments, referring to Figures 6 and 7, the array substrate 10 may also include various signal lines. These signal lines are described in detail below.

[0239] In some embodiments, referring to Figures 6, 7, and 8, the array substrate 10 may include a data signal line (Data) and a gate signal line (Gate). Both the data signal line (Data) and the gate signal line (Gate) are located in the display area AA of the array substrate 10, and the gate signal line (Gate) may extend along a first direction X, while the data signal line (Data) may extend along a second direction Y.

[0240] Please refer to Figure 8. Since the first direction X is the row direction of the array of multiple pixel circuits F11, and the second direction Y is the column direction of the array of multiple pixel circuits F11, the first direction X and the second direction Y intersect. Therefore, the gate signal line Gate extending along the first direction X and the data signal line Data extending along the second direction Y intersect. The gate signal line Gate and the data signal line Data can jointly define multiple pixel regions Fa. The pixel circuits F11 in the array substrate 10 (e.g., the first capacitor C1 and the first transistor T1 in the pixel circuit F11, etc.) can be located within the pixel regions Fa.

[0241] For example, please continue to refer to FIG8. When the first transistor T1 in the pixel circuit F11 is an N-type transistor, the drain region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the data signal line Data, the source region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the first plate C11 of the first capacitor C1, and the first gate pattern T12 of the first transistor T1 can be electrically connected to the gate signal line Gate.

[0242] Specifically, please continue to refer to Figure 8. When the first transistor T1 in the pixel circuit F11 is an N-type transistor, the drain region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the data signal line Data through the drain contact d, and the source region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the first plate C11 of the first capacitor C1 through the source contact s.

[0243] Alternatively, if the first transistor T1 in the pixel circuit F11 is a P-type transistor, the source region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the data signal line Data, the drain region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the first plate C11 of the first capacitor C1, and the first gate pattern T12 of the first transistor T1 can be electrically connected to the gate signal line Gate.

[0244] Specifically, when the first transistor T1 in the pixel circuit F11 is a P-type transistor, the source region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the data signal line Data through the source contact s, and the drain region in the first active layer pattern T11 of the first transistor T1 can be electrically connected to the first plate C11 of the first capacitor C1 through the drain contact d.

[0245] The following uses an example where the first transistor T1 in the pixel circuit F11 is an N-type transistor to illustrate some embodiments of this disclosure. However, the implementation of this disclosure includes, but is not limited to, this. The first transistor T1 in the pixel circuit F11 can also be a P-type transistor.

[0246] Please refer to Figure 8. The gate signal line Gate can control the first transistor T1 in the pixel circuit F11 to turn on or off. When the first transistor T1 in the pixel circuit F11 is turned on, the data signal line Data can charge the first plate C11 of the first capacitor C1 through the first transistor T1.

[0247] For example, referring to Figures 6, 7, and 8, and in conjunction with Figures 12 and 13, the array substrate 10 can employ a half-gate structure. In the array substrate 10 employing a half-gate structure, each gate signal line (Gate) within the array substrate 10 corresponds to two rows of pixel circuits (F11) (i.e., multiple pixel circuits F11 arranged along the first direction X), and each column of pixel circuits F11 within the array substrate 10 (i.e., multiple pixel circuits F11 arranged along the second direction Y) corresponds to two data signal lines (Data).

[0248] For example, please continue to refer to Figures 12 and 13, and in conjunction with Figures 6 and 7, when the array substrate 10 adopts a Half Gate structure, along the first direction X, the two data signal lines Data corresponding to a column of pixel circuits F11 in the array substrate 10 can be located on opposite sides of the column of pixel circuits F11.

[0249] One of the two data signal lines Data corresponding to a column of pixel circuits F11 in the array substrate 10 can be connected to the first transistor T1 in a part of the pixel circuit F11 in the column of pixel circuits F11, and the other data signal line Data can be connected to the first transistor T1 in another part of the pixel circuit F11 in the column of pixel circuits F11.

[0250] In the array substrate 10 described above, each gate signal line corresponds to two rows of pixel circuits F11. That is, each gate signal line can control the activation of two rows of pixel circuits F11, which can increase the charging time of each row of pixel circuits F11, which helps to ensure that the pixel circuits F11 are fully charged, and thus helps to improve the display effect of the display panel 100 including the array substrate 10 described above.

[0251] For example, please continue to refer to FIG8. In the case where the array substrate 10 includes a gate conductive layer 31, the gate signal line can be disposed on the gate conductive layer 31.

[0252] For example, please continue to refer to FIG8. In the case where the array substrate 10 includes a source-drain conductive layer 32, the data signal line Data can be disposed on the source-drain conductive layer 32.

[0253] In some embodiments, referring to Figures 12 and 13, and in conjunction with Figures 6 and 7, the array substrate 10 may further include a virtual data signal line Data1. The virtual data signal line Data1 is located in the peripheral region AN of the array substrate 10, and the virtual data signal line Data1 may extend along the second direction Y.

[0254] For example, the virtual data signal line Data1 can be configured to transmit a common signal.

[0255] For example, as shown in Figures 14A and 14B, and in conjunction with Figures 6 and 7, Figure 14A is a planar structural diagram of region A5 of the array substrate 10 in Figure 6, and Figure 14B is a planar structural diagram of region A6 of the array substrate 10 in Figure 7. In the array substrate 10, the plurality of virtual pixel circuits F12 include a second group 22. The virtual pixel circuits F12 of the second group 22 are located on one side of the display area AA of the array substrate 10 in the first direction X. Furthermore, if the virtual pixel circuit F12 includes a second capacitor C2 and a second transistor T2, the virtual data signal line Data1 can be electrically connected to the second transistor T2 within the virtual pixel circuit F12.

[0256] Please continue to refer to Figures 14A and 14B. When the virtual data signal line Data1 is configured to transmit a common signal, the second transistor T2 can be electrically connected to the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the second group 22.

[0257] Alternatively, the third plate C13 of the second capacitor C2 within the second transistor T2 and the virtual pixel circuit F12 of the second group 22 can be mutually insulated.

[0258] For example, when the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the second transistor T2 and the second group 22 is mutually insulated, the connecting via between the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the second transistor T2 and the second group 22 can be removed so that the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the second group 22 is mutually insulated.

[0259] For example, please continue to refer to Figures 12 and 13. When the array substrate 10 includes a source-drain conductive layer 32, the virtual data signal line Data1 can be disposed on the source-drain conductive layer 32.

[0260] In some embodiments, referring further to Figures 12 and 13, the array substrate 10 may also include a first common signal line Com1. The first common signal line Com1 may be located between two adjacent rows of pixel circuits F11 and extend along a first direction X.

[0261] For example, please continue to refer to Figures 12 and 13. When the array substrate 10 includes a light-shielding layer 33, the first common signal line Com1 may be disposed on the light-shielding layer 33.

[0262] For example, please continue to refer to Figures 12 and 13. When the array substrate 10 adopts a half-gate structure, that is, each gate signal line Gate in the array substrate 10 corresponds to two rows of pixel circuits F11 and each column of pixel circuits F11 in the array substrate 10 corresponds to two data signal lines Data, the first common signal line Com1 can be located between two adjacent gate signal lines Gate.

[0263] Alternatively, a portion of the first common signal line Com1 may be located between two adjacent gate signal lines Gate, and the orthographic projection of a portion of the first common signal line Com1 on the substrate 1 may overlap with the orthographic projection of the gate signal line Gate on the substrate 1.

[0264] Please refer to Figure 9, and in conjunction with Figures 12 and 13. In the case where the array electrode 10 includes a gate conductive layer 31, a light-shielding layer 33, a first passivation layer 42, and a first organic layer 43, with the first passivation layer 42 and the first organic layer 43 located between the gate conductive layer 31 and the light-shielding layer 33, and the gate signal line Gate is disposed on the gate conductive layer 31 and the first common signal line Com1 is disposed on the light-shielding layer 33, when the orthographic projection of the first common signal line Com1 on the substrate 1 and the orthographic projection of the gate signal line Gate on the substrate 1 overlap, a first organic layer 43 is disposed between the first common signal line Com1 and the gate signal line Gate. The material of the first organic layer 43 includes organic materials. Organic materials have a small dielectric constant, which can effectively suppress the parasitic capacitance effect between the first common signal line Com1 and the gate signal line Gate, and is beneficial to improving the signal transmission rate and signal transmission quality of the first common signal line Com1 and the gate signal line Gate.

[0265] For example, please continue to refer to Figures 12 and 13. In the case where the array substrate 10 includes a plurality of second connection portions 322, one second connection portion 322 is located between two adjacent pixel circuits F11 in the second direction Y, and the second plates C12 of the first capacitors C1 in a column of pixel circuits F11 are connected sequentially through the plurality of second connection portions 322, the first common signal line Com1 can be electrically connected to the plurality of second connection portions 322 between two adjacent rows of pixel circuits F11 to transmit the common signal to the second plates C12 of the first capacitors C1 in the pixel circuits F11.

[0266] In some embodiments, as shown in FIG15, and in conjunction with FIGS. 6 and 7, FIG15 is a plan view of a common signal bus M1 within an array substrate 10 according to some embodiments. The array substrate 10 may further include the common signal bus M1. The common signal bus M1 may be located in the peripheral region AN of the array substrate 10 and extends along the edge of the display area AA of the array substrate 10.

[0267] Please continue to refer to Figures 6 and 7. In the case where the array substrate 10 includes a plurality of virtual pixel circuits F12, the plurality of virtual pixel circuits F12 are located in the peripheral area AN of the array substrate 10, and the plurality of virtual pixel circuits F12 include at least one group 2, each group 2 including a plurality of virtual pixel circuits F12 arranged along the extension direction of the edge of the display area AA of the array substrate 10, the orthographic projection of the common signal bus M1 on the substrate 1 of the array substrate 10 can overlap with the orthographic projection of the virtual pixel circuits F12 of at least one group 2 on the substrate 1.

[0268] In the array substrate 10 described above, the orthographic projection of the common signal bus M1 onto the substrate 1 of the array substrate 10 and the orthographic projection of at least one virtual pixel circuit F12 of group 2 onto the substrate 1 overlap, which can reduce the overall area of ​​the common signal bus M1 and the virtual pixel circuit F12 in the orthographic projection onto the substrate 1. This is beneficial to reducing the size of the peripheral area AN of the array substrate 10, thereby facilitating the narrow bezel of the array substrate 10 and the narrow bezel of the display panel 100 including the array substrate 10.

[0269] Furthermore, while achieving a narrow bezel in the array substrate 10, multiple virtual pixel circuits F12 can be set in the peripheral area AN of the array substrate 10. This allows the multiple virtual pixel circuits F12 to balance key process parameters such as etching rate and photoresist development uniformity of pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 and pixel circuits F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA). This improves the consistency of morphological features, electrical performance, and optical properties of pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 and pixel circuits F11 located in other regions of the display area AA of the array substrate 10 (e.g., the central region of the display area AA). This effectively suppresses the performance deviation of pixel circuits F11 located in the edge region of the display area AA of the array substrate 10 caused by edge effects, which is beneficial to improving the overall brightness uniformity and color reproduction accuracy of the display panel 100 including the array substrate 10.

[0270] Furthermore, while achieving a narrow bezel on the array substrate 10, the width of the common signal bus M1 can still be guaranteed, which is beneficial to improving the signal transmission rate and signal transmission quality of the common signal bus M1.

[0271] For example, referring to FIG15, the common signal bus M1 in the array substrate 10 may include a first portion M11 extending along the first direction X.

[0272] For example, referring to FIG15, the common signal bus M1 in the array substrate 10 may include a second portion M12 extending along the second direction Y.

[0273] For example, please continue to refer to Figures 12 and 13, and in conjunction with Figure 15, when the array substrate 10 includes a first common signal line Com1, which is located between two adjacent rows of pixel circuits F11 and extends along the first direction X, the first common signal line Com1 can be electrically connected to the second part M12 of the common signal bus M1.

[0274] For example, referring to FIG15, in the case where the common signal bus M1 in the array substrate 10 includes a first part M11 and a second part M12, the common signal bus M1 may also include a third part M13. The third part M13 of the common signal bus M1 can be used to connect the first part M11 and the second part M12 of the common signal bus M1.

[0275] For example, please continue to refer to FIG15, and in conjunction with FIG8 and FIG9, when the array substrate 10 includes a light-shielding pattern 331, the common signal bus M1 can be made of the same material as the light-shielding pattern 331 and disposed in the same layer.

[0276] For example, if the array substrate 10 includes a light-shielding layer 33, both the common signal bus M1 and the light-shielding pattern 331 can be disposed on the light-shielding layer 33.

[0277] In some embodiments, as shown in Figures 16, 17, 18, and 19, Figure 16 is a plan view of region A7 of the array substrate 10 in Figure 6, Figure 17 is a plan view of region A8 of the array substrate 10 in Figure 6, Figure 18 is a plan view of region A9 of the array substrate 10 in Figure 7, and Figure 19 is a plan view of region A10 of the array substrate 10 in Figure 7. In the array substrate 10, a common signal bus M1 includes a first portion M11 extending along the first direction X, and a plurality of virtual pixel circuits F12 within the array substrate 10 includes a first group 21. When the virtual pixel circuits F12 of the first group 21 are located on one side of the display area AA of the array substrate 10 in the second direction Y, the orthographic projection of the first portion M11 of the common signal bus M1 onto the substrate 1 can overlap with the orthographic projection of the virtual pixel circuits F12 of the first group 21 within the plurality of virtual pixel circuits F12 onto the substrate 1.

[0278] For example, please continue to refer to Figures 16, 17, 18 and 19. The second transistor T2 in the virtual pixel circuit F12 of the first group 21 can be isolated from the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21.

[0279] For example, if the second transistor T2 in the virtual pixel circuit F12 of the first group 21 and the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21 are mutually insulated, the connecting via between the second transistor T2 in the virtual pixel circuit F12 of the first group 21 and the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21 can be removed, so that the second transistor T2 in the virtual pixel circuit F12 of the first group 21 and the third plate C13 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21 are mutually insulated.

[0280] For example, please continue to refer to Figures 16, 17, 18 and 19. The first part M11 of the common signal bus M1 can be electrically connected to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21.

[0281] In some embodiments, referring to Figures 16 and 17, when the first portion M11 of the common signal bus M1 in the array substrate 10 is electrically connected to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21, and the array substrate 10 includes a substrate 1 and a source / drain conductive layer 32, the source / drain conductive layer 32 may further include a first transition pattern 51. The first transition pattern 51 may be disposed on the side of the virtual pixel circuit F12 of the first group 21 away from the display area AA, and electrically connected to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21.

[0282] The orthographic projection of the first adapter pattern 51 on the substrate 1 can overlap with the orthographic projection of the first part M11 of the common signal bus M1 on the substrate 1, and the first adapter pattern 51 and the first part M11 of the common signal bus M1 can be electrically connected through the second hole structure K2.

[0283] In the array substrate 10 described above, the first transition pattern 51 is electrically connected to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21, and is electrically connected to the first part M11 of the common signal bus M1, so that the common signal bus M1 can transmit the common signal to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21 through the first transition pattern 51.

[0284] Further, please continue to refer to Figures 12 and 13. In the case that the second plate C12 of the first capacitor C1 in the multiple pixel circuits F11 and the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21 are sequentially electrically connected along the second direction Y in the multiple pixel circuits F11, the common signal can also be transmitted to the second plate C12 of the first capacitor C1 in the pixel circuit F11 through the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21.

[0285] For example, as shown in FIG20, and in conjunction with FIG16 and FIG17, FIG20 is a cross-sectional view of the array substrate 10 in FIG16 along section line P3-P3 or the array substrate 10 in FIG17 along section line P4-P4. In the case where the array substrate 10 includes a substrate 1, a source / drain conductive layer 32, a first organic layer 43, and a first passivation layer 42, and the first organic layer 43 and the first passivation layer 42 are disposed on the side of the source / drain conductive layer 32 away from the substrate 1, and the first passivation layer 42 is farther from the substrate 1 than the first organic layer 43, the second via structure K2 may include a third via V3 penetrating the first organic layer 43 and a plurality of fourth vias V4 penetrating the first passivation layer 42. The plurality of fourth vias V4 may be located within the range of the third via V3.

[0286] In the array substrate 10 described above, the second hole structure K2 includes a third via V3 and a fourth via V4, and multiple fourth vias V4 penetrating the first passivation layer 42 are located within the range of the third vias V3 penetrating the first organic layer 43, which makes the size of the third vias V3 penetrating the first organic layer 43 larger, which can reduce the probability of the first organic layer 43 undergoing interface peeling, thereby helping to reduce the probability of the first organic layer 43 falling off.

[0287] In other embodiments, referring to Figures 18 and 19, when the first portion M11 of the common signal bus M1 in the array substrate 10 and the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21 are electrically connected, the first portion M11 of the common signal bus M1 and the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21 can be electrically connected through a first hole structure K1. The first hole structure K1 is disposed above the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the first group 21.

[0288] For example, please continue to refer to Figures 18 and 19. In the case where at least two first groups 21 are provided on one side of the multiple pixel circuits F11 in the second direction Y, the first hole structure K1 can be provided above the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 located in the outermost first group 21.

[0289] In the aforementioned array substrate 10, the first hole structure K1 is disposed above the fourth plate C14 of the second capacitor C2 within the virtual pixel circuit F12 of the outermost first group 21. This allows for a higher consistency between the structure of the virtual pixel circuit F12 of the first group 21 located between the outermost first group 21 and the display area AA of the array substrate 10, and the structure of the pixel circuit F11. Specifically, the structure of the virtual pixel circuit F12 of the inner first group 21 has a higher consistency with the structure of the pixel circuit F11. This further allows the virtual pixel circuit F12 of the inner first group 21 to better balance the pixel circuit F11 located at the edge of the display area AA of the array substrate 10, and the pixel circuit F11 located within the array substrate 10. The etching rate and photoresist development uniformity of key process parameters such as the etching rate and photoresist development uniformity of pixel circuits F11 in other areas of the display area AA (e.g., the central area of ​​the display area AA) can further improve the consistency of the morphological features, electrical performance, and optical properties of pixel circuits F11 located in the edge area of ​​the display area AA of the array substrate 10 with those located in other areas of the display area AA of the array substrate 10. This can more effectively suppress the performance deviation of pixel circuits F11 located in the edge area of ​​the display area AA of the array substrate 10 caused by edge effects, and is conducive to further improving the overall brightness uniformity and color reproduction accuracy of the display panel 100 including the array substrate 10.

[0290] For example, as shown in FIG21, and in conjunction with FIG18 and FIG19, FIG21 is a cross-sectional view of the array substrate 10 in FIG18 along section line P5-P5 or the array substrate 10 in FIG19 along section line P6-P6. In the case where the array substrate 10 includes a substrate 1, a source / drain conductive layer 32, a first organic layer 43, and a first passivation layer 42, and the first organic layer 43 and the first passivation layer 42 are disposed on the side of the source / drain conductive layer 32 away from the substrate 1, and the first passivation layer 42 is farther from the substrate 1 than the first organic layer 43, the first via structure K1 may include a first via V1 penetrating the first organic layer 43 and a plurality of second vias V2 penetrating the first passivation layer 42. The plurality of second vias V2 may be located within the range of the first via V1.

[0291] In the array substrate 10 described above, the first hole structure K1 includes a first via V1 and a second via V2, and a plurality of second via V2 penetrating the first passivation layer 42 are located within the range of the first via V1 penetrating the first organic layer 43, which makes the size of the first via V1 penetrating the first organic layer 43 larger, which can reduce the probability of the first organic layer 43 undergoing interface peeling, thereby helping to reduce the probability of the first organic layer 43 falling off.

[0292] In some embodiments, as shown in Figures 22 and 23, and in conjunction with Figure 15, Figure 22 is a planar structural diagram of region A11 of array substrate 10 in Figure 6, and Figure 23 is a planar structural diagram of region A12 of array substrate 10 in Figure 7. In the array substrate 10, a common signal bus M1 includes a second portion M12 extending along the second direction Y, and a plurality of virtual pixel circuits F12 within the array substrate 10 include a second group 22. When the virtual pixel circuits F12 of the second group 22 are located on one side of the display area AA of the array substrate 10 in the first direction X, the orthographic projection of the second portion M12 of the common signal bus M1 onto the substrate 1 can overlap with the orthographic projection of the virtual pixel circuits F12 of the second group 22 onto the substrate 1.

[0293] For example, referring to Figures 22 and 23, the second part M12 of the common signal bus M1 can be electrically connected to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the second group 22.

[0294] In the array substrate 10 described above, the second part M12 of the common signal bus M1 is electrically connected to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the second group 22. This allows the common signal to be transmitted to the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the second group 22. This also allows the fourth plate C14 of the second capacitor C2 in the virtual pixel circuit F12 of the second group 22 to be used for transmitting the common signal, which is beneficial to improving the transmission rate and transmission quality of the common signal in the array substrate 10.

[0295] For example, please continue to refer to Figures 22 and 23. When the array substrate 10 includes a plurality of first connection portions 321, and one first connection portion 321 is located between two adjacent virtual pixel circuits F12 in the second direction Y, and the fourth plate C14 of the second capacitor C2 in the plurality of virtual pixel circuits F12 of a second group 22 is connected sequentially through the plurality of first connection portions 321, the second part M12 of the common signal bus M1 can be electrically connected to the first connection portion 321 through the fifth hole structure K5.

[0296] For example, as shown in Figures 24 and 25, and in conjunction with Figures 22 and 23, Figure 24 is a cross-sectional view of the array substrate 10 in Figure 22 along section line P7-P7, and Figure 25 is a cross-sectional view of the array substrate 10 in Figure 23 along section line P8-P8. In the case where the array substrate 10 includes a substrate 1, a source / drain conductive layer 32, a first organic layer 43, and a first passivation layer 42, and the first organic layer 43 and the first passivation layer 42 are disposed on the side of the source / drain conductive layer 32 away from the substrate 1, and the first passivation layer 42 is farther from the substrate 1 than the first organic layer 43, the fifth via structure K5 may include a seventh via V7 penetrating the first organic layer 43 and an eighth via V8 penetrating the first passivation layer 42.

[0297] Please refer to Figures 24 and 25. The eighth via V8 can be located within the range of the seventh via V7.

[0298] In some embodiments, as shown in Figures 26, 27, 28, and 29, Figure 26 is a planar structural diagram of region A4 of the array substrate 10 in Figure 6, Figure 27 is a planar structural diagram of region A13 of the array substrate 10 in Figure 6, Figure 28 is a planar structural diagram of region A14 of the array substrate 10 in Figure 7, and Figure 29 is a planar structural diagram of region A15 of the array substrate 10 in Figure 7. When the array substrate 10 includes a substrate 1 and a source / drain conductive layer 32, the source / drain conductive layer 32 may further include a second transition pattern 52. The second transition pattern 52 may be disposed in the corner region R1 of the peripheral region AN of the array substrate 10.

[0299] As shown in Figures 30, 31, 32, and 33, and in conjunction with Figure 15, Figure 30 is a cross-sectional view of the array substrate 10 in Figure 26 along section line P9-P9; Figure 31 is a cross-sectional view of the array substrate 10 in Figure 27 along section line P10-P10; Figure 32 is a cross-sectional view of the array substrate 10 in Figure 28 along section line P11-P11; and Figure 33 is a cross-sectional view of the array substrate 10 in Figure 29 along section line P12-P12. When the common signal bus M1 includes a third part M13, and the third part M13 is used to connect the first part M11 and the second part M12 of the common signal bus M1, the second transition pattern 52 can be located on the side of the third part M13 of the common signal bus M1 closer to the substrate 1, and the second transition pattern 52 can be electrically connected to the third part M13 of the common signal bus M1 through the eighth hole structure K8.

[0300] In the array substrate 10 described above, the second transition pattern 52 and the third part M13 of the common signal bus M1 are electrically connected through the eighth hole structure K8, so that the common signal can be transmitted to the third part M13 of the common signal bus M1 via the second transition pattern 52, and then transmitted into the array substrate 10.

[0301] For example, referring to Figures 30, 31, 32, and 33, in an array substrate 10 comprising a substrate 1, a source / drain conductive layer 32, a first organic layer 43, and a first passivation layer 42, with the first organic layer 43 and the first passivation layer 42 disposed on the side of the source / drain conductive layer 32 away from the substrate 1, and the first passivation layer 42 being farther from the substrate 1 than the first organic layer 43, the eighth via structure K8 may include a twelfth via V12 penetrating the first organic layer 43 and a plurality of thirteenth vias V13 penetrating the first passivation layer 42. The plurality of thirteenth vias V13 may be located within the range of the twelfth via V12.

[0302] For example, please continue to refer to Figures 26, 27, 28 and 29. In the case where the array substrate 10 includes a virtual data signal line Data1, the second adapter pattern 52 can be electrically connected to the virtual data signal line Data1.

[0303] In some embodiments, referring to Figures 26, 28, 30, and 32, when the array substrate 10 includes a second transition pattern 52, the second transition pattern 52 and the third portion M13 of the common signal bus M1 are electrically connected, and the array substrate 10 includes a gate conductive layer 31, the gate conductive layer 31 may include a third transition pattern 53. The third transition pattern 53 is located on the side of the second transition pattern 52 near the substrate 1, and the third transition pattern 53 and the second transition pattern 52 can be electrically connected through the ninth hole structure K9.

[0304] In the array substrate 10 described above, the third transition pattern 53 and the second transition pattern 52 are electrically connected through the ninth hole structure K9. The second transition pattern 52 is electrically connected to the third part M13 of the common signal bus M1, so that the common signal can be transmitted to the third part M13 of the common signal bus M1 via the third transition pattern 53 and the second transition pattern 52, and then transmitted into the array substrate 10.

[0305] For example, referring to Figures 30 and 32, when the array substrate 10 includes a gate insulating layer 41, a gate conductive layer 31 and a source / drain conductive layer 32, and the gate insulating layer 41 is located between the gate conductive layer 31 and the source / drain conductive layer 32, the ninth via structure K9 may include a plurality of fourteenth vias V14 penetrating the gate insulating layer 41.

[0306] In some embodiments, referring to Figures 16, 17, and 20, the array substrate 10 may further include a first auxiliary signal line 61. The first auxiliary signal line 61 extends along a first direction X and is located on the side of the virtual pixel circuit F12 of the first group 21 away from the display area AA of the array substrate 10.

[0307] For example, referring to Figures 16, 17, and 20, in an array substrate 10 including a common signal bus M1, the common signal bus M1 including a first portion M11 extending along a first direction X, and the source / drain conductive layer 32 within the array substrate 10 including a first transition pattern 51, the first transition pattern 51 being disposed on the side of the virtual pixel circuit F12 of the first group 21 away from the display area AA, the first auxiliary signal line 61 can be located on the side of the first portion M11 of the common signal bus M1 closer to the substrate 1, and the first transition pattern 51 can be located between the first auxiliary signal line 61 and the first portion M11 of the common signal bus M1. The first transition pattern 51 and the first auxiliary signal line 61 can be electrically connected through the third hole structure K3.

[0308] In the array substrate 10 described above, the first auxiliary signal line 61 and the first transition pattern 51 are electrically connected, so that the first auxiliary signal line 61 can also be used to transmit common signals, which is beneficial to improving the transmission rate and transmission quality of common signals in the array substrate 10.

[0309] For example, referring to FIG20, in an array substrate 10 including a substrate 1, a gate conductive layer 31, a source / drain conductive layer 32 and a gate insulating layer 41, wherein the gate conductive layer 31 and the gate insulating layer 41 are disposed on the side of the source / drain conductive layer 32 close to the substrate 1, and the gate insulating layer 41 is located between the gate conductive layer 31 and the source / drain conductive layer 32, the first auxiliary signal line 61 may be disposed in the gate conductive layer 31.

[0310] The third via structure K3 may include multiple fifth vias V5 that penetrate the gate insulating layer 41.

[0311] In some embodiments, as shown in FIG34, FIG34 is a planar structural diagram of a second auxiliary signal line 62 within an array substrate 10 according to some embodiments. The array substrate 10 may further include the second auxiliary signal line 62. The second auxiliary signal line 62 is located in the peripheral region AN of the array substrate 10 and may extend along the extension direction of the edge of the display region AA of the array substrate 10.

[0312] For example, referring to Figures 20 and 34, and in conjunction with Figure 15, the second auxiliary signal line 62 may include a first portion 621 extending along the first direction X. The first portion 621 of the second auxiliary signal line 62 may be located on the side of the first portion M11 of the common signal bus M1 away from the substrate 1.

[0313] The first part 621 of the second auxiliary signal line 62 and the first part M11 of the common signal bus M1 can be electrically connected through the fourth hole structure K4.

[0314] In the array substrate 10 described above, the first part 621 of the second auxiliary signal line 62 and the first part M11 of the common signal bus M1 are electrically connected, so that the second auxiliary signal line 62 can also be used to transmit common signals, which is beneficial to improving the transmission rate and transmission quality of common signals in the array substrate 10.

[0315] For example, please continue to refer to FIG20. In the case that the array substrate 10 includes a source / drain conductive layer 32, a light-shielding layer 33, a second passivation layer 44 and a first electrode layer 34, and the second passivation layer 44 is located between the light-shielding layer 33 and the first electrode layer 34, and the light-shielding layer 33 is closer to the source / drain conductive layer 32 than the first electrode layer 34, the common signal bus M1 can be disposed in the light-shielding layer 33, the second auxiliary signal line 62 can be disposed in the first electrode layer 34, and the fourth hole structure K4 can include a plurality of sixth vias V6 penetrating the second passivation layer 44.

[0316] For example, please continue to refer to Figures 16 and 17, and in conjunction with Figure 34, when the second auxiliary signal line 62 includes a first portion 621 extending along the first direction X, the orthographic projection of the first portion 621 of the second auxiliary signal line 62 on the substrate 1 can overlap with the orthographic projection of the virtual pixel circuit F12 of the first group 21 on the substrate 1.

[0317] For example, as shown in FIG35, and in conjunction with FIG34 and FIG15, FIG35 is a cross-sectional view of the array substrate 10 in FIG22 along section line P13-P13. The second auxiliary signal line 62 may include a second portion 622 extending along the second direction Y. The second portion 622 of the second auxiliary signal line 62 may be disposed on the side of the second portion M12 of the common signal bus M1 away from the substrate 1.

[0318] The second part 622 of the second auxiliary signal line 62 and the second part M12 of the common signal bus M1 can be electrically connected through the seventh hole structure K7.

[0319] In the array substrate 10 described above, the second part 622 of the second auxiliary signal line 62 and the second part M12 of the common signal bus M1 are electrically connected, so that the second auxiliary signal line 62 can also be used to transmit common signals, which is beneficial to improving the transmission rate and transmission quality of common signals in the array substrate 10.

[0320] For example, please continue to refer to FIG35. In the case that the array substrate 10 includes a source / drain conductive layer 32, a light-shielding layer 33, a second passivation layer 44 and a first electrode layer 34, and the second passivation layer 44 is located between the light-shielding layer 33 and the first electrode layer 34, and the light-shielding layer 33 is closer to the source / drain conductive layer 32 than the first electrode layer 34, the common signal bus M1 can be disposed in the light-shielding layer 33, the second auxiliary signal line 62 can be disposed in the first electrode layer 34, and the seventh hole structure K7 can include a plurality of eleventh vias V11 penetrating the second passivation layer 44.

[0321] For example, please continue to refer to FIG22 and in conjunction with FIG34, when the second auxiliary signal line 62 includes a second portion 622 extending along the second direction Y, the orthographic projection of the second portion 622 of the second auxiliary signal line 62 on the substrate 1 can overlap with the orthographic projection of the virtual pixel circuit F12 of the second group 22 on the substrate 1.

[0322] In some embodiments, referring to Figures 22 and 35, the array substrate 10 may further include a third auxiliary signal line 63. The third auxiliary signal line 63 extends along the second direction Y and is located on the side of the virtual pixel circuit F12 of the second group 22 away from the display area AA of the array substrate 10.

[0323] For example, referring to Figures 22 and 35, and in conjunction with Figure 15, when the array substrate 10 includes a common signal bus M1, and the common signal bus M1 includes a second portion M12 extending along the second direction Y, the third auxiliary signal line 63 can be located on the side of the second portion M12 of the common signal bus M1 closer to the substrate 1. The third auxiliary signal line 63 and the second portion M12 of the common signal bus M1 can be electrically connected through the sixth hole structure K6.

[0324] In the array substrate 10 described above, the third auxiliary signal line 63 is electrically connected to the second part M12 of the common signal bus M1, so that the third auxiliary signal line 63 can also be used to transmit the common signal, which is beneficial to improving the transmission rate and transmission quality of the common signal in the array substrate 10.

[0325] For example, referring to Figure 35, in an array substrate 10 comprising a source / drain conductive layer 32, a first organic layer 43, and a first passivation layer 42, with the first organic layer 43 and the first passivation layer 42 disposed on the side of the source / drain conductive layer 32 away from the substrate 1, and the first passivation layer 42 being farther from the substrate 1 than the first organic layer 43, the third auxiliary signal line 63 can be disposed in the source / drain conductive layer 32. The sixth via structure K6 can include a ninth via V9 penetrating the first organic layer 43 and multiple tenth vias V10 penetrating the first passivation layer 42. The multiple tenth vias V10 can be located within the range of the ninth via V9.

[0326] In some embodiments, as shown in Figures 36 and 37, and in conjunction with Figures 8, 9, 10, and 11, Figures 36 and 37 are planar structural diagrams of a partial region of the first electrode layer 34 within the array substrate 10 according to some embodiments. When the array substrate 10 includes the first electrode layer 34, the first electrode layer 34 may include a plurality of first electrodes 341 arranged in an array.

[0327] In the case that the pixel circuit F11 in the array substrate 10 includes the fifth plate C15 of the third capacitor C3, and the virtual pixel circuit F12 in the array substrate 10 includes the first virtual electrode C16, the plurality of first electrodes 341 may include the fifth plate C15 of the third capacitor C3 and the first virtual electrode C16.

[0328] Among them, two adjacent rows of first electrodes 341 can be staggered in the second direction Y.

[0329] In the aforementioned array substrate 10, the adjacent rows of first electrodes 341 are staggered in the second direction Y (i.e., mosaic design), which can prevent splicing defects caused by poor splicing exposure accuracy during the splicing of the array substrate 10, thus improving the display effect.

[0330] For example, please continue to refer to Figure 36, the edge of the first electrode layer 34 can be flush.

[0331] For example, the edge of the first electrode layer 34 can be flush with the edge of the light-shielding layer 33 in the array substrate 10.

[0332] Alternatively, referring to Figure 37, the edge of the first electrode layer 34 may include a plurality of protrusions 342.

[0333] For example, referring to Figure 37, the edges of the first electrode layer 34 can be serrated. For example, referring to Figure 37, the protrusion 342 within the first electrode layer 34 can be an integral part of the first virtual electrode C16. That is, the protrusion 342 can be a part of the first virtual electrode C16.

[0334] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising a display area and a peripheral area surrounding the display area; The array substrate includes: Multiple pixel circuits are arranged in an array within the display area; Multiple virtual pixel circuits are located in the peripheral area; the multiple virtual pixel circuits include at least one group, each group including multiple virtual pixel circuits arranged along the extension direction of the edge of the display area; when there are multiple groups, the multiple groups are arranged sequentially in a direction gradually away from the display area; A common signal bus is located in the peripheral area and extends along the edge of the display area; the orthographic projection of the common signal bus on the substrate of the array substrate and the orthographic projection of at least one of the virtual pixel circuits of the group on the substrate overlap.

2. The array substrate according to claim 1, wherein, The common signal bus includes a first portion extending along a first direction, the first direction being the row direction in which the plurality of pixel circuit arrays are arranged; The at least one group includes a first group, wherein the virtual pixel circuits of the first group are located on one side of the display area in a second direction, the second direction being the column direction in which the plurality of pixel circuit arrays are arranged; The orthographic projection of the first part of the common signal bus on the substrate and the orthographic projection of the first group of virtual pixel circuits on the substrate overlap.

3. The array substrate according to claim 2, wherein, The virtual pixel circuit includes a second capacitor, the second capacitor includes a third electrode plate, and a fourth electrode plate disposed on the side of the third electrode plate away from the substrate; The first part of the common signal bus is electrically connected to the fourth plate of the virtual pixel circuit of the first group.

4. The array substrate according to claim 3, wherein, The virtual pixel circuit also includes a second transistor; The second transistor of the virtual pixel circuit of the first group and the third plate of the virtual pixel circuit of the first group are insulated from each other.

5. The array substrate according to claim 3 or 4, wherein, The first part of the common signal bus and the fourth plate of the virtual pixel circuit of the first group are electrically connected through a first hole structure, which is located above the fourth plate of the virtual pixel circuit of the first group.

6. The array substrate according to claim 5, wherein, The display area has at least two of the first groups on one side in the second direction, and the first hole structure is located above the fourth plate of the virtual pixel circuit of the outermost first group.

7. The array substrate according to claim 6, wherein, In at least two of the first groups, the virtual pixel circuit of the outermost first group is a first type of circuit, and the virtual pixel circuit of the first group located between the outermost first group and the display area is a second type of circuit. The size of the second type of circuit along the second direction is equal to the size of the pixel circuit along the second direction, and the size of the first type of circuit along the second direction is less than or equal to the size of the pixel circuit along the second direction.

8. The array substrate according to any one of claims 5 to 7, wherein, The array substrate further includes a source / drain conductive layer, a first organic layer, and a first passivation layer; The fourth electrode of the second capacitor is disposed in the source-drain conductive layer, the first organic layer and the first passivation layer are disposed on the side of the source-drain conductive layer away from the substrate, and the first passivation layer is farther away from the substrate than the first organic layer; The first via structure includes a first via penetrating the first organic layer and a plurality of second vias penetrating the first passivation layer, wherein the plurality of second vias are located within the range of the first via.

9. The array substrate according to claim 3 or 4, wherein, The array substrate further includes a source-drain conductive layer, and the fourth electrode of the second capacitor is disposed in the source-drain conductive layer; The source and drain conductive layer further includes a first transition pattern, which is disposed on the side of the first group of virtual pixel circuits away from the display area and is electrically connected to the fourth electrode plate of the first group of virtual pixel circuits. The orthographic projection of the first adapter pattern on the substrate and the orthographic projection of the first portion of the common signal bus on the substrate overlap, and the first adapter pattern and the first portion of the common signal bus are electrically connected through a second hole structure.

10. The array substrate according to claim 9, wherein, The array substrate further includes a first organic layer and a first passivation layer, disposed on the side of the source / drain conductive layer away from the substrate, and the first passivation layer is farther from the substrate than the first organic layer; The second hole structure includes a third via penetrating the first organic layer and a plurality of fourth vias penetrating the first passivation layer, wherein the plurality of fourth vias are located within the range of the third via.

11. The array substrate according to claim 9 or 10, wherein, The array substrate further includes a first auxiliary signal line, which extends along the first direction and is located on the side of the virtual pixel circuit of the first group away from the display area; The first auxiliary signal line is located on the side of the first portion of the common signal bus closer to the substrate, and the first adapter pattern is located between the first auxiliary signal line and the first portion of the common signal bus; The first adapter pattern and the first auxiliary signal line are electrically connected through a third hole structure.

12. The array substrate according to claim 11, wherein, The array substrate further includes a gate conductive layer and a gate insulating layer, which are disposed on the side of the source / drain conductive layer close to the substrate, and the gate insulating layer is located between the gate conductive layer and the source / drain conductive layer; The third plate of the second capacitor and the first auxiliary signal line are disposed in the gate conductive layer; The third hole structure includes multiple fifth vias penetrating the gate insulating layer.

13. The array substrate according to any one of claims 9-12, wherein, The array substrate also includes a second auxiliary signal line, located in the peripheral area and extending along the edge of the display area; The second auxiliary signal line includes a first portion extending along the first direction, disposed on the side of the first portion of the common signal bus away from the substrate; The first part of the second auxiliary signal line and the first part of the common signal bus are electrically connected through a fourth hole structure.

14. The array substrate according to claim 13, wherein, The array substrate further includes a light-shielding layer, a second passivation layer, and a first electrode layer. The second passivation layer is located between the light-shielding layer and the first electrode layer, and the light-shielding layer is closer to the source / drain conductive layer than the first electrode layer. The common signal bus is located in the light-shielding layer, and the second auxiliary signal line is located in the first electrode layer; The fourth hole structure includes a plurality of sixth vias penetrating the second passivation layer.

15. The array substrate according to claim 13 or 14, wherein, The orthographic projection of the first portion of the second auxiliary signal line onto the substrate overlaps with the orthographic projection of the virtual pixel circuit of the first group onto the substrate.

16. The array substrate according to any one of claims 3 to 15, wherein, The pixel circuit includes a first capacitor; the first capacitor includes a first electrode plate and a second electrode plate disposed on the side of the first electrode plate away from the substrate; In the plurality of pixel circuits in the same column and the virtual pixel circuit of the first group, the second electrode plates of the plurality of pixel circuits and the fourth electrode plate of the virtual pixel circuit of the first group are electrically connected sequentially along the second direction.

17. The array substrate according to any one of claims 1-16, wherein, The common signal bus includes a second portion extending along a second direction, which is the column direction in which the plurality of pixel circuit arrays are arranged; The at least one group includes a second group, wherein the virtual pixel circuits of the second group are located on one side of the display area in a first direction, the first direction being the row direction in which the plurality of pixel circuit arrays are arranged; The orthographic projection of the second part of the common signal bus on the substrate and the orthographic projection of the second group of virtual pixel circuits on the substrate overlap.

18. The array substrate according to claim 17, wherein, The virtual pixel circuit includes a second capacitor, the second capacitor includes a third electrode plate, and a fourth electrode plate disposed on the side of the third electrode plate away from the substrate; The second part of the common signal bus and the fourth plate of the virtual pixel circuit of the second group are electrically connected.

19. The array substrate according to claim 18, wherein, The array substrate further includes a plurality of first connection portions, one of which is located between two adjacent virtual pixel circuits in the second direction; the fourth electrode plates of the plurality of virtual pixel circuits in the second group are sequentially connected through the plurality of first connection portions. The second part of the common signal bus and the first connection part are electrically connected through a fifth hole structure.

20. The array substrate according to claim 19, wherein, The array substrate further includes a source / drain conductive layer, a first organic layer, and a first passivation layer; The fourth plate of the second capacitor is disposed on the source-drain conductive layer, the first organic layer and the first passivation layer are disposed on the side of the source-drain conductive layer away from the substrate, and the first passivation layer is farther away from the substrate than the first organic layer; The fifth pore structure includes a seventh via penetrating the first organic layer and an eighth via penetrating the first passivation layer.

21. The array substrate according to any one of claims 18-20, wherein, The virtual pixel circuit further includes a second transistor, and the second transistor and the third plate of the second group of virtual pixel circuits are electrically connected. The array substrate also includes a virtual data signal line located in the peripheral area and extending along a second direction; the virtual data signal line is electrically connected to the second transistor, and the virtual data signal line is configured to transmit a common signal.

22. The array substrate according to any one of claims 17-21, wherein, The display area has at least two of the second groups on one side in the first direction; Of the at least two second groups, the virtual pixel circuit of the outermost second group is a third type of circuit, and the virtual pixel circuit of the second group located between the outermost second group and the display area is a fourth type of circuit. The size of the fourth type of circuit along the first direction is equal to the size of the pixel circuit along the first direction, and the size of the third type of circuit along the second direction is less than or equal to the size of the pixel circuit along the first direction.

23. The array substrate according to any one of claims 17-21, wherein, The array substrate further includes a third auxiliary signal line, which extends along the second direction and is located on the side of the virtual pixel circuit of the second group away from the display area; The third auxiliary signal line is located on the side of the second part of the common signal bus closer to the substrate, and the third auxiliary signal line and the second part of the common signal bus are electrically connected through a sixth hole structure.

24. The array substrate according to claim 23, wherein, The array substrate further includes a source / drain conductive layer, a first organic layer, and a first passivation layer; The third auxiliary signal line is disposed in the source-drain conductive layer, the first organic layer and the first passivation layer are disposed on the side of the source-drain conductive layer away from the substrate, and the first passivation layer is farther away from the substrate than the first organic layer; The sixth hole structure includes a ninth via penetrating the first organic layer and a plurality of tenth via penetrating the first passivation layer, wherein the plurality of tenth vias are located within the range of the ninth via.

25. The array substrate according to any one of claims 17-21 and 23-24, wherein, The array substrate also includes a second auxiliary signal line, located in the peripheral area and extending along the edge of the display area; The second auxiliary signal line includes a second portion extending along the second direction, disposed on the side of the second portion of the common signal bus away from the substrate; The second part of the second auxiliary signal line and the second part of the common signal bus are electrically connected through a seventh hole structure.

26. The array substrate according to claim 25, wherein, The array substrate further includes a light-shielding layer, a second passivation layer, and a first electrode layer. The second passivation layer is located between the light-shielding layer and the first electrode layer, and the light-shielding layer is closer to the source / drain conductive layer than the first electrode layer. The common signal bus is located in the light-shielding layer, and the second auxiliary signal line is located in the first electrode layer; The seventh hole structure includes multiple eleventh vias penetrating the second passivation layer.

27. The array substrate according to claim 25 or 26, wherein, The second portion of the second auxiliary signal line is projected onto the substrate in an orthographic projection, and the second group of virtual pixel circuits is projected onto the substrate in an orthographic projection.

28. The array substrate according to any one of claims 17 to 27, wherein, The array substrate further includes a first common signal line located between two adjacent rows of pixel circuits and extending along the first direction; The first common signal line and the second part of the common signal bus are electrically connected.

29. The array substrate according to claim 28, wherein, The pixel circuit includes a first capacitor; the first capacitor includes a first electrode plate and a second electrode plate disposed on the side of the first electrode plate away from the substrate; The array substrate further includes a plurality of second connection portions, one of which is located between two adjacent pixel circuits in the second direction; the second plates of a column of pixel circuits are connected sequentially through the plurality of second connection portions. The first common signal line and the plurality of second connection portions between the two adjacent rows of pixel circuits are electrically connected.

30. The array substrate according to any one of claims 17 to 29, wherein, The pixel circuit includes a first capacitor; the first capacitor includes a first electrode plate and a second electrode plate disposed on the side of the first electrode plate away from the substrate; The array substrate further includes a source-drain conductive layer, and the second electrode of the first capacitor is disposed on the source-drain conductive layer. The source and drain conductive layer also includes a second transition pattern, which is disposed in the corner area of ​​the peripheral area; The common signal bus also includes a third part for connecting the first part of the common signal bus and the second part of the common signal bus; the second adapter pattern is located on the side of the third part of the common signal bus closer to the substrate, and the second adapter pattern and the third part of the common signal bus are electrically connected through an eighth hole structure.

31. The array substrate according to claim 30, wherein, The array substrate further includes a first organic layer and a first passivation layer; the first organic layer and the first passivation layer are disposed on the side of the source and drain conductive layer away from the substrate, and the first passivation layer is farther from the substrate than the first organic layer; The eighth hole structure includes a twelfth via penetrating the first organic layer and a plurality of thirteenth via penetrating the first passivation layer, wherein the plurality of thirteenth vias are located within the range of the twelfth via.

32. The array substrate according to claim 30 or 31, wherein, The array substrate also includes virtual data signal lines located in the peripheral area and extending along the second direction; The second adapter pattern and the virtual data signal line are electrically connected.

33. The array substrate according to any one of claims 30-32, wherein, The array substrate further includes a gate conductive layer located on the side of the source / drain conductive layer close to the substrate; The gate conductive layer includes a third transition pattern located on the side of the second transition pattern close to the substrate; the third transition pattern and the second transition pattern are electrically connected through a ninth hole structure.

34. The array substrate according to claim 33, wherein, The array substrate further includes a gate insulating layer located between the gate conductive layer and the source / drain conductive layer; The ninth hole structure includes multiple fourteenth vias penetrating the gate insulating layer.

35. The array substrate according to any one of claims 1-34, wherein, The pixel circuit includes a first capacitor and a first transistor; the first capacitor includes a first electrode plate and a second electrode plate disposed on the side of the first electrode plate away from the substrate, and the first transistor and the first electrode plate are electrically connected. The array substrate also includes a light-shielding pattern disposed on the side of the first transistor away from the substrate; The common signal bus and the light-shielding pattern are made of the same material and are arranged on the same layer.

36. The array substrate according to any one of claims 2-35, wherein, The pixel circuit also includes a third capacitor, which includes a fifth electrode plate; the virtual pixel circuit also includes a first virtual electrode. The array substrate further includes a first electrode layer; the first electrode layer includes a plurality of first electrodes arranged in an array, the plurality of first electrodes including the fifth electrode plate and the first virtual electrode; In this arrangement, two adjacent rows of the first electrodes are staggered in the second direction.

37. The array substrate according to claim 36, wherein, The edge of the first electrode layer includes multiple protrusions; Alternatively, the edges of the first electrode layer may be flush.

38. A display panel, comprising: The array substrate as described in any one of claims 1 to 37; The opposing substrate is positioned opposite to and spaced apart from the array substrate; A liquid crystal layer is disposed between the array substrate and the opposing substrate.

39. A display panel, comprising: The array substrate as described in any one of claims 1 to 37; The opposing substrate is positioned opposite to and spaced apart from the array substrate; An ink layer is disposed between the array substrate and the opposing substrate.

40. A display device, comprising: The display panel as described in claim 38 or 39; The driver chip is electrically connected to the display panel.

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