Semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

The present application discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a silicon carbide semiconductor body (100); the silicon carbide semiconductor body (100) comprises a first device region (200) and a second device region (300); a first semiconductor graphene layer (400) is located on an electrode arrangement surface (101) in the first device region (200); a second semiconductor graphene layer (500) is located on the electrode arrangement surface (101) in the second device region (300); and at a same preset temperature, the mobility of the first semiconductor graphene layer (400) and the mobility of the second semiconductor graphene layer (500) are both greater than the mobility of silicon carbide. The first semiconductor graphene layer (400) and the second semiconductor graphene layer (500) are provided to improve the mobility of the semiconductor device.

Description

Semiconductor devices and manufacturing methods, power modules, power conversion circuits and vehicles

[0001] This application claims priority to Chinese Patent Application No. 202510205097.8, filed with the Chinese Patent Office on February 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, such as semiconductor devices and manufacturing methods, power modules, power conversion circuits, and vehicles. Background Technology

[0003] Wide-bandgap semiconductor materials such as silicon carbide (SiC) are widely used in power electronics, automotive, and aerospace fields due to their excellent high-temperature performance, chemical stability, and electronic properties. They exhibit superior performance in applications with wide temperature ranges, high power, and high switching frequencies. The development of SiC integrated circuits (ICs) that integrate control systems and semiconductor devices onto a single chip is crucial to fully realizing the potential of SiC.

[0004] Silicon carbide complementary metal-oxide-semiconductor (CMOS) technology ensures low power consumption and maintains certain logic levels at different temperatures. SiC CMOS consists of n-channel metal-oxide-semiconductor (MOS) and p-channel MOS.

[0005] However, the main challenge in CMOS fabrication is the low channel mobility of NMOS and PMOS, and the difference in mobility between NMOS and PMOS carriers, which severely hinders the potential of SiC in improving system power density and switching performance. Summary of the Invention

[0006] This application provides semiconductor devices and manufacturing methods, power modules, power conversion circuits, and vehicles to improve the channel mobility of NMOS and PMOS and solve the problem of the difference in mobility between NMOS and PMOS carriers.

[0007] This application provides a semiconductor device, including:

[0008] The silicon carbide semiconductor body includes an electrode mounting surface and is configured with a first conductivity type; the silicon carbide semiconductor body also includes a first device region and a second device region.

[0009] A first semiconductor graphene layer is located on the electrode surface of the first device region, and is configured to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the first semiconductor graphene layer is greater than that of silicon carbide.

[0010] The second semiconductor graphene layer is located on the electrode surface of the second device region and is configured to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the second semiconductor graphene layer is greater than that of silicon carbide.

[0011] In a semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide-semiconductor field-effect transistor of the first conductivity type with the current conduction direction in the first direction, and the portion located in the second device region is a silicon carbide metal-oxide-semiconductor field-effect transistor of the second conductivity type with the current conduction direction in the first direction. The first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor and the second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor together constitute a silicon carbide complementary metal-oxide-semiconductor; the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body.

[0012] In one embodiment, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.4 eV.

[0013] In one embodiment, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.6 eV.

[0014] In one embodiment, the first device region includes two first regions and a well region; the two first regions are configured with a first conductivity type and are located on the electrode mounting surface, and the well region is configured with a second conductivity type and is located between the two first regions; the second device region includes two second regions, which are configured with a second conductivity type and are located on the electrode mounting surface; a first semiconductor graphene layer is connected to the two first regions; and a second semiconductor graphene layer is connected to the two second regions.

[0015] In one embodiment, the first semiconductor graphene layer and the silicon carbide semiconductor body are covalently connected in an orderly manner; and / or, the second semiconductor graphene layer and the silicon carbide semiconductor body are covalently connected in an orderly manner.

[0016] In one embodiment, the semiconductor device further includes:

[0017] The first insulating layer is located on the electrode mounting surface;

[0018] The first electrode is located in the first device region and on the side of the first insulating layer away from the first semiconductor graphene layer;

[0019] The second electrode is located in the second device region and on the side of the first insulating layer away from the second semiconductor graphene layer;

[0020] The third and fourth electrodes are located in the first device region and on the electrode mounting surface, and are respectively connected to the two first regions;

[0021] The fifth and sixth electrodes are located in the second device region and on the electrode mounting surface, and are connected to the two second regions respectively.

[0022] In one embodiment, the first semiconductor graphene layer is configured with a first conductivity type; and / or, the second semiconductor graphene layer is configured with a second conductivity type.

[0023] In one embodiment, the semiconductor device further includes a first protective layer located on the side of the first semiconductor graphene layer away from the silicon carbide semiconductor body; and / or, it further includes a second protective layer located on the side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

[0024] In one embodiment, the first protective layer includes a gold protective layer or an aluminum oxide protective layer; the second protective layer includes a gold protective layer or an aluminum oxide protective layer.

[0025] In one embodiment, there are multiple first device regions and multiple second device regions.

[0026] This application also provides a method for manufacturing a semiconductor device, comprising:

[0027] A silicon carbide semiconductor body is provided, the silicon carbide semiconductor body includes an electrode placement surface, the silicon carbide semiconductor body is configured with a first conductivity type; the silicon carbide semiconductor body also includes a first device region and a second device region.

[0028] A first semiconductor graphene layer is formed on the electrode surface. The first semiconductor graphene layer is located in the first device region and is configured to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the first semiconductor graphene layer is greater than that of silicon carbide.

[0029] A second semiconductor graphene layer is formed on the electrode surface. The second semiconductor graphene layer is located in the second device region and is configured to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the second semiconductor graphene layer is greater than that of silicon carbide. The portion located in the first device region is a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction. The portion located in the second device region is a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction. The first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor and the second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor together constitute a silicon carbide complementary metal-oxide-semiconductor. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body.

[0030] In one embodiment, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.4 eV.

[0031] In one embodiment, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.6 eV.

[0032] In one embodiment, a first semiconductor graphene layer is formed on the electrode surface, comprising:

[0033] The electrode surface is heated to a preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming a first semiconductor graphene layer on the electrode surface.

[0034] A second semiconductor graphene layer is formed on the electrode surface, including:

[0035] The electrode surface is heated to a preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming a second semiconductor graphene layer on the electrode surface.

[0036] In one embodiment, heating the electrode surface to a preset temperature causes the silicon on the electrode surface to evaporate, thereby forming a first semiconductor graphene layer on the electrode surface, including:

[0037] The electrode surfaces of the first silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite to each other;

[0038] The electrode surface is heated to a preset temperature so that the carbon surface of the first silicon carbide semiconductor layer and the electrode surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode surface is the silicon surface.

[0039] Silicon evaporates from the electrode surface, thereby forming a first semiconductor graphene layer on the electrode surface;

[0040] Heating the electrode surface to a preset temperature causes the silicon on the electrode surface to evaporate, thereby forming a second semiconductor graphene layer on the electrode surface, including:

[0041] The electrode surfaces of the second silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite to each other;

[0042] The electrode surface is heated to a preset temperature so that the carbon surface of the second silicon carbide semiconductor layer and the electrode surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein, the electrode surface is the silicon surface;

[0043] Silicon evaporates from the electrode surface, thereby forming a second semiconductor graphene layer on the electrode surface.

[0044] In one embodiment, after forming a first semiconductor graphene layer on the electrode surface, the method further includes: forming a first protective layer on the side of the first semiconductor graphene layer away from the silicon carbide semiconductor body; and / or,

[0045] After forming the second semiconductor graphene layer on the electrode surface, the method further includes forming a second protective layer on the side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

[0046] This application also provides a power module, including a substrate and at least one of the above-described semiconductor devices, wherein the substrate is configured to carry the semiconductor devices.

[0047] This application also provides a power conversion circuit, which is configured to perform one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0048] This application also provides a vehicle, including a load and the aforementioned power conversion circuit, the power conversion circuit being configured to convert AC and / or DC power into AC and / or DC power before inputting it to the load. Attached Figure Description

[0049] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of this application;

[0050] Figure 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application;

[0051] Figure 3 is a cross-sectional view corresponding to the steps of a semiconductor device manufacturing method according to an embodiment of this application;

[0052] Figure 4 is a cross-sectional view corresponding to the steps of another semiconductor device manufacturing method provided according to an embodiment of this application;

[0053] Figure 5 is a cross-sectional view corresponding to the steps of another semiconductor device manufacturing method provided according to an embodiment of this application;

[0054] Figure 6 is a schematic diagram of the process included in S120 and S130 in Figure 2;

[0055] Figure 7 is a schematic diagram of the process included in S1201 of Figure 6;

[0056] Figure 8 is a schematic diagram of the process included in S1301 of Figure 6;

[0057] Figure 9 is a structural schematic diagram of the relevant steps in Figures 7 and 8. Detailed Implementation

[0058] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, for example, including, in addition to processes, methods, systems, products, or devices that include the series of steps or units shown in the embodiments of this application, other processes, methods, systems, products, and devices that are not explicitly listed in this series of steps or units, or other steps or units inherent to these processes, methods, systems, products, or devices.

[0059] To address the issues of low channel mobility in NMOS and PMOS, and the difference in carrier mobility between NMOS and PMOS, this application provides the following technical solutions:

[0060] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of this application. As shown in Figure 1, the semiconductor device includes: a silicon carbide semiconductor body 100, which includes an electrode surface 101 and is configured with a first conductivity type; the silicon carbide semiconductor body 100 also includes a first device region 200 and a second device region 300; a first semiconductor graphene layer 400 located on the electrode surface 101 of the first device region 200, configured to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer 400 is greater than that of silicon carbide; and a second semiconductor graphene layer 500 located on the electrode surface 101 of the second device region 300, configured to improve the mobility of the semiconductor device. The mobility of the second semiconductor graphene layer 500 is greater than that of silicon carbide at the same preset temperature. In the semiconductor device, the portion located in the first device region 200 is a first conductivity type silicon carbide metal-oxide semiconductor field-effect transistor with the current conduction direction in the first direction, and the portion located in the second device region 300 is a second conductivity type silicon carbide metal-oxide semiconductor field-effect transistor with the current conduction direction in the first direction. The first conductivity type silicon carbide metal-oxide semiconductor field-effect transistor and the second conductivity type silicon carbide metal-oxide semiconductor field-effect transistor together constitute a silicon carbide complementary metal-oxide semiconductor. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body 100.

[0061] In the embodiments of this application, the silicon carbide semiconductor body 100 may include a substrate and an epitaxial layer, or it may only include an epitaxial layer. The epitaxial layer is a semiconductor layer formed by a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0062] In this embodiment, if the first conductivity type is N-type, then the second conductivity type is P-type; if the first conductivity type is P-type, then the second conductivity type is N-type. This embodiment uses N-type as an example for illustration. The conductivity type of the silicon carbide semiconductor body 100 is set to N-type. The first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor is an N-type silicon carbide metal-oxide-semiconductor field-effect transistor, and the second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor is a P-type silicon carbide metal-oxide-semiconductor field-effect transistor.

[0063] The mobility of the same semiconductor material varies with temperature. In this embodiment, under the same preset temperature, the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than that of silicon carbide. That is, under the same preset temperature, the electron mobility resistance in the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is less than the carrier mobility resistance in silicon carbide. Specifically, in the first device region 200, within a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current direction in the first direction, under the control of the gate, the current flows from the source to the drain through the first semiconductor graphene layer 400. In the second device region 300, within a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current direction in the first direction, under the control of the gate, the current flows from the source to the drain through the second semiconductor graphene layer 500. The arrangement of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 increases the channel carrier mobility within the semiconductor device, thereby reducing the on-resistance of the semiconductor device, while ensuring the same hole and electron mobility within the conduction channel.

[0064] The mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 depends on the growth quality of the material and can range from tens of centimeters. 2 / Vs to 5000cm 2 Approximately / Vs. The mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 at room temperature is greater than or equal to 1000 cm⁻¹. 2 / Vs, and can even reach 5500cm 2 / Vs. Room temperature, also known as ambient temperature or general temperature, is generally defined as 25 degrees Celsius, and sometimes as 300K (about 27 degrees Celsius). However, the mobility required for semiconductor devices is only a few tens of centimeters. 2 Approximately / Vs. Therefore, the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 can improve the mobility of semiconductor devices.

[0065] The technical solution provided in this application embodiment, in a SiC complementary metal-oxide-semiconductor (CMOS) device composed of a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) and a second conductivity type SiC MOSFET, has a first semiconductor graphene layer 400 located in a conduction channel below the first electrode 602 in the first conductivity type SiC MOSFET, which helps to improve the mobility of the semiconductor device. Similarly, a second semiconductor graphene layer 500 located in a conduction channel below the second electrode 702 in the second conductivity type SiC MOSFET also helps to improve the mobility of the semiconductor device. Because the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, and a mobility greater than that of silicon carbide, and possess semiconductor properties, they ensure the same hole and electron mobility within the conduction channel. This effectively solves the problem of uniformity in channel mobility between the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET, improves the uniformity of switching speed between the first conductivity type channel and the second conductivity type channel, as well as overall efficiency and thermal management efficiency, resulting in faster response speeds for semiconductor devices.

[0066] The band gap of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than or equal to 0.4 eV. In one embodiment, the band gap of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than or equal to 0.6 eV.

[0067] Because the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, and mobility greater than that of silicon carbide, and possess semiconductor properties, their band gap is greater than or equal to 0.4 eV, for example, greater than or equal to 0.6 eV, and their mobility is greater than or equal to 1000 cm⁻¹. 2 / Vs, and can even reach 5500cm 2The system maintains a uniform hole and electron mobility within the conduction channel, effectively solving the uniformity problem of channel mobility between the first and second conductivity types of SiC MOSFETs. This improves the uniformity of switching speeds between the first and second conductivity types, as well as overall efficiency and thermal management efficiency, resulting in faster response speeds for the semiconductor device. As shown in Figure 1, the first device region 200 includes two first regions 201 and a well region 202. The first regions 201 are configured as the first conductivity type and are located on the electrode surface 101, while the well region 202 is configured as the second conductivity type and is located between the two first regions 201. The second device region 300 includes two second regions 301, which are configured as the second conductivity type and are located on the electrode surface 101. The first semiconductor graphene layer 400 is connected to the two first regions 201, and the second semiconductor graphene layer 500 is connected to the two second regions 301.

[0068] In this embodiment, the first device region 201 in the first device region 200 is an N+ active region, and the well region 202 is a P-type well region. The first device region 200 also includes a third region 203, wherein the third region 203 is a P+ active region. The first device region 200 also includes a first semiconductor graphene layer 400. The first semiconductor graphene layer 400 is connected to the two first regions 201. The second device region 300 in the second device region 300 is a P+ active region. The second device region 300 also includes a fourth region 302. The fourth region 302 is an N+ active region. The second device region 300 also includes a second semiconductor graphene layer 500. The second semiconductor graphene layer 500 is connected to the two second regions 301. The above technical solution clearly defines the positions of the semiconductor graphene layers in the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET with the conduction current direction in the first direction in a CMOS planar device.

[0069] In a first conductivity type silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) with the current conduction direction in the first direction, under the control of the gate, the current flows from the source to the drain through a first region 201, a first semiconductor graphene layer 400, and another first region 201. In a second conductivity type silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) with the current conduction direction in the first direction, under the control of the gate, the current flows from the source to the drain through a second region 301, a second semiconductor graphene layer 500, and another second region 301.

[0070] The first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 are connected in an orderly manner by covalent bonds; and / or, the second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100 are connected in an orderly manner by covalent bonds.

[0071] In this embodiment, the first semiconductor graphene layer 400 is covalently bonded to the silicon carbide semiconductor body 100 during growth, eliminating the need for an adhesive layer, thus simplifying the fabrication process and reducing costs. The first semiconductor graphene layer 400 is a two-dimensional semiconductor material. The first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 are connected by ordered covalent bonds. The first semiconductor graphene layer 400 exhibits high mobility. Therefore, the technical solution for forming the first semiconductor graphene layer 400 significantly increases the channel carrier mobility within the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0072] During the growth process, the second semiconductor graphene layer 500 is covalently bonded to the silicon carbide semiconductor body 100, eliminating the need for an adhesive layer, thus simplifying the fabrication process and reducing costs. The second semiconductor graphene layer 500 is a two-dimensional semiconductor material. The orderly covalent bonding between the second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100, coupled with its high mobility, significantly increases the channel carrier mobility within the semiconductor device, thereby reducing its on-resistance.

[0073] Because the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, and mobility greater than that of silicon carbide, and possess semiconductor properties, their band gap is greater than or equal to 0.4 eV, for example, greater than or equal to 0.6 eV, and their mobility is greater than or equal to 1000 cm⁻¹. 2 / Vs, and can even reach 5500cm 2 With a value of approximately / Vs, the same hole and electron mobility is ensured within the conduction channel, effectively solving the problem of uniformity in channel mobility between the first and second conductivity type SiC MOSFETs. This improves the uniformity of switching speed between the first and second conductivity type channels, as well as overall efficiency and thermal management efficiency, resulting in faster response speeds for semiconductor devices.

[0074] As shown in Figure 1, the semiconductor device further includes: a first insulating layer 601 located on the electrode mounting surface 101; a first electrode 602 located in the first device region 200 and on the side of the first insulating layer 601 away from the first semiconductor graphene layer 400; a second electrode 702 located in the second device region 300 and on the side of the first insulating layer 601 away from the second semiconductor graphene layer 500; a third electrode 603 and a fourth electrode 604 located in the first device region 200 and on the electrode mounting surface 101, respectively connected to the two first regions 201; and a fifth electrode 703 and a sixth electrode 704 located in the second device region 300 and on the electrode mounting surface 101, respectively connected to the two second regions 301.

[0075] In the first device region 200, within a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction, under the control of the first electrode 602, the current flows through the first semiconductor graphene layer 400 from the third electrode 603 to the fourth electrode 604. For example, the third electrode 603 is the source and the fourth electrode 604 is the drain. In the second device region 300, within a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current conduction direction in the first direction, under the control of the second electrode 702, the current flows through the second semiconductor graphene layer 500 from the fifth electrode 703 to the sixth electrode 704. For example, the fifth electrode 703 is the source and the sixth electrode 704 is the drain. The arrangement of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 increases the channel carrier mobility within the semiconductor device, thereby reducing the on-resistance of the semiconductor device. At the same time, it ensures the same hole and electron mobility within the conduction channel, effectively solving the problem of uniformity of channel mobility between the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET. This improves the uniformity of switching speed between the first conductivity type channel and the second conductivity type channel, as well as the overall efficiency and thermal management efficiency, resulting in a faster response speed for the semiconductor device.

[0076] In this embodiment, the first insulating layer 601 may be a gate oxide layer. The first electrode 602 may be a polysilicon gate. The second electrode 702 may be a polysilicon gate. The third electrode 603 and the fourth electrode 604 are the source and drain of the first device region 200, respectively; the fifth electrode 703 and the sixth electrode 704 are the source and drain of the second device region 300, respectively.

[0077] As shown in Figure 1, the semiconductor device also includes a second insulating layer 800, which is configured to insulate the gate and source, as well as the gate and drain.

[0078] In Figure 1, the silicon carbide semiconductor body 100 includes multiple drift layers stacked sequentially. Figure 1 exemplarily shows three drift layers. Since the silicon carbide semiconductor body 100 is of the first conductivity type, which is the same conductivity type as the inversion layer of the second conductivity type SiC MOS, the second conductivity type SiC MOS located in the second device region 300 does not need to have a well region.

[0079] For example, under the same selected room temperature conditions, the maximum room temperature mobility of the first semiconductor graphene layer 400 can reach 5500 cm⁻¹. 2 V -1 s -1 This significantly increases the channel carrier mobility within the semiconductor device, thereby reducing the on-resistance of the semiconductor device. The room-temperature mobility of the second semiconductor graphene layer 500 is the same as that of the first semiconductor graphene layer 400.

[0080] Based on the above technical solution, referring to Figure 1, the first semiconductor graphene layer 400 is configured as a first conductivity type; and / or, the second semiconductor graphene layer 500 is configured as a second conductivity type.

[0081] In the first conductivity type SiC MOS device, the first semiconductor graphene layer 400 is configured with the first conductivity type, which is the same as the conductivity type of the carriers in the channel, further increasing the carrier concentration of the device. In the second conductivity type SiC MOS device, the second semiconductor graphene layer 500 is configured with the second conductivity type, which is the same as the conductivity type of the carriers in the channel, further increasing the carrier concentration of the device.

[0082] Based on the above technical solution, referring to Figure 1, the semiconductor device further includes a first protective layer 401, which is located on the side of the first semiconductor graphene layer 400 away from the silicon carbide semiconductor body 100; and / or, it further includes a second protective layer 501, which is located on the side of the second semiconductor graphene layer 500 away from the silicon carbide semiconductor body 100.

[0083] The first protective layer 401 is a thin film formed by atomic layer deposition. It is configured to protect the first semiconductor graphene layer 400 from the surface of the silicon carbide semiconductor body 100, so as to avoid damage to the first semiconductor graphene layer 400 during epitaxy and the formation of subsequent film layers, thereby ensuring that the first semiconductor graphene layer 400 has a high mobility, thereby increasing the structural stability of the semiconductor device.

[0084] The first protective layer 401 is relatively thin, with a minimum thickness of 5 nm. While achieving the function of protecting the first semiconductor graphene layer 400 from the surface of the silicon carbide semiconductor body 100, it has little impact on the on-resistance of the semiconductor device.

[0085] The second protective layer 501 is a thin film formed by atomic layer deposition. It is configured to protect the second semiconductor graphene layer 500 from the surface of the silicon carbide semiconductor body 100, so as to avoid damage to the second semiconductor graphene layer 500 during epitaxy and the formation of subsequent film layers, thereby ensuring that the second semiconductor graphene layer 500 has a high mobility, thus increasing the structural stability of the semiconductor device.

[0086] The second protective layer 501 is relatively thin, with a minimum thickness of 5nm. While achieving the function of protecting the second semiconductor graphene layer 500 from the surface of the silicon carbide semiconductor body 100, it has little impact on the on-resistance of the semiconductor device.

[0087] Referring to Figure 1, the first protective layer 401 includes a gold protective layer or an aluminum oxide protective layer; the second protective layer 501 includes a gold protective layer or an aluminum oxide protective layer.

[0088] The gold or aluminum oxide protective layer has stable physicochemical properties and can protect the first semiconductor graphene layer 400 from the surface of the silicon carbide semiconductor body 100, as well as the second semiconductor graphene layer 500 from the surface of the silicon carbide semiconductor body 100, thus preventing damage to the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 during epitaxy and the formation of subsequent film layers.

[0089] There are multiple first device regions 200 and multiple second device regions 300.

[0090] This application also provides a method for manufacturing a semiconductor device. Figure 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application. As shown in Figure 2, the method for manufacturing the semiconductor device includes:

[0091] S110. A silicon carbide semiconductor body is provided, the silicon carbide semiconductor body includes an electrode placement surface, the silicon carbide semiconductor body is configured with a first conductivity type; the silicon carbide semiconductor body also includes a first device region and a second device region.

[0092] Referring to Figure 3, a silicon carbide semiconductor body 100 is provided. The silicon carbide semiconductor body 100 includes an electrode placement surface 101 and is configured with a first conductivity type. The silicon carbide semiconductor body 100 also includes a first device region 200 and a second device region 300.

[0093] S120. A first semiconductor graphene layer is formed on the electrode surface. The first semiconductor graphene layer is located in the first device region and is configured to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the first semiconductor graphene layer is greater than that of silicon carbide.

[0094] Referring to Figure 4, a first semiconductor graphene layer 400 is formed on the electrode surface 101. The first semiconductor graphene layer 400 is located in the first device region 200, and at the same preset temperature, the mobility of the first semiconductor graphene layer 400 is greater than that of silicon carbide.

[0095] S130. A second semiconductor graphene layer is formed on the electrode surface. The second semiconductor graphene layer is located in the second device region and is configured to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the second semiconductor graphene layer is greater than that of silicon carbide.

[0096] Referring to Figure 4, a second semiconductor graphene layer 500 is formed on the electrode surface 101. The second semiconductor graphene layer 500 is located in the second device region 300, and at the same preset temperature, the mobility of the second semiconductor graphene layer 500 is greater than that of silicon carbide.

[0097] The mobility of the same semiconductor material varies with temperature. In this embodiment, under the same preset temperature, the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than that of silicon carbide. That is, under the same preset temperature, the electron mobility resistance in the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is less than the carrier mobility resistance in silicon carbide. Specifically, in the first device region 200, within a first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current direction in the first direction, under the control of the gate, the current flows from the source to the drain through the first semiconductor graphene layer 400. In the second device region 300, within a second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor with the current direction in the first direction, under the control of the gate, the current flows from the source to the drain through the second semiconductor graphene layer 500. The arrangement of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 increases the channel carrier mobility within the semiconductor device, thereby reducing the on-resistance of the semiconductor device, while ensuring the same hole and electron mobility within the conduction channel.

[0098] The mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 depends on the growth quality of the material and can range from tens of centimeters. 2 / Vs to 5000cm 2Approximately / Vs. The mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 at room temperature is greater than or equal to 1000 cm⁻¹. 2 / Vs, and can even reach 5500cm 2 / Vs. Room temperature, also known as ambient temperature or general temperature, is generally defined as 25 degrees Celsius, and sometimes as 300K (about 27 degrees Celsius). However, the mobility required for semiconductor devices is only a few tens of centimeters. 2 Approximately / Vs. Therefore, the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 can improve the mobility of semiconductor devices.

[0099] The technical solution provided in this application, in a SiC complementary metal-oxide-semiconductor (CMOS) device composed of a first conductivity type SiC MOSFET and a second conductivity type SiC MOSFET, has a first semiconductor graphene layer 400 located in a conduction channel below the first electrode 602 in the first conductivity type SiC MOSFET, which helps to improve the mobility of the semiconductor device. Similarly, a second semiconductor graphene layer 500 located in a conduction channel below the second electrode 702 in the second conductivity type SiC MOSFET also helps to improve the mobility of the semiconductor device. Because the first and second semiconductor graphene layers 400 and 500 have high strength, high thermal conductivity, and mobility greater than that of silicon carbide, and possess semiconductor properties, they ensure the same hole and electron mobility within the conduction channel. This effectively solves the problem of uniformity in the channel mobility of the first and second conductivity type SiC MOSFETs, improves the uniformity of switching speed between the first and second conductivity type channels, enhances overall efficiency and thermal management efficiency, and results in a faster response speed for the semiconductor device. The band gap of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than or equal to 0.4 eV. In one embodiment, the band gap of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than or equal to 0.6 eV.

[0100] Because the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, and mobility greater than that of silicon carbide, and possess semiconductor properties, their band gap is greater than or equal to 0.4 eV, for example, greater than or equal to 0.6 eV, and their mobility is greater than or equal to 1000 cm⁻¹. 2 / Vs ensures the same hole and electron mobility within the conduction channel, effectively solving the uniformity problem of channel mobility between the first and second conductivity type SiC MOSFETs. This improves the uniformity of switching speed between the first and second conductivity type channels, as well as overall efficiency and thermal management efficiency, resulting in faster response speeds for semiconductor devices.

[0101] In this embodiment of the application, FIG6 is a schematic diagram of the process included in S120 and S130 of FIG2. As shown in FIG6, S120 forms a first semiconductor graphene layer on the electrode setting surface, including:

[0102] S1201. The electrode surface is heated to a preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming a first semiconductor graphene layer on the electrode surface.

[0103] Referring to Figure 4, the electrode surface 101 is heated to a preset temperature, causing the silicon on the electrode surface 101 to evaporate, thereby forming a first semiconductor graphene layer 400 on the electrode surface 101. The first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 are connected by covalent bonding.

[0104] The first semiconductor graphene layer 400 is fabricated using a heated electrode surface 101. During heating, silicon evaporates before carbon, resulting in spontaneous crystallization of the first semiconductor graphene layer 400 on the electrode surface 101. The first semiconductor graphene layer 400 is covalently bonded to the silicon carbide semiconductor body 100 during growth, eliminating the need for an adhesive layer, thus simplifying the fabrication process and reducing costs. The first semiconductor graphene layer 400 is a two-dimensional semiconductor material. The ordered covalent bonding between the first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 gives it a high mobility, significantly increasing the channel carrier mobility within the semiconductor device and reducing its on-resistance. Furthermore, the first semiconductor graphene layer 400 also possesses advantages such as high strength and high thermal conductivity.

[0105] In this embodiment of the application, as shown in FIG6, S130 forms a second semiconductor graphene layer on the electrode setting surface, including:

[0106] S1301. The electrode surface is heated to a preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming a second semiconductor graphene layer on the electrode surface.

[0107] Referring to Figure 4, the electrode surface 101 is heated to a preset temperature, causing the silicon on the electrode surface 101 to evaporate, thereby forming a second semiconductor graphene layer 500 on the electrode surface 101. The second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100 are connected by covalent bonding.

[0108] The fabrication of the second semiconductor graphene layer 500 involves using a heated electrode surface 101. During heating, silicon evaporates before carbon, resulting in spontaneous crystallization of the second semiconductor graphene layer 500 on the electrode surface 101. The second semiconductor graphene layer 500 is covalently bonded to the silicon carbide semiconductor body 100 during growth, eliminating the need for an adhesive layer, thus simplifying the fabrication process and reducing costs. The second semiconductor graphene layer 500 is a two-dimensional semiconductor material. The ordered covalent bonding between the second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100 gives it a high mobility, significantly increasing the channel carrier mobility within the semiconductor device and reducing its on-resistance. Furthermore, the second semiconductor graphene layer 500 also possesses advantages such as high strength and high thermal conductivity.

[0109] Based on the above technical solution, Figure 7 is a schematic diagram of the process included in S1201 of Figure 6. As shown in Figure 7, S1201 heats the electrode surface to a preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming a first semiconductor graphene layer on the electrode surface, including:

[0110] S12011, The electrode surfaces of the first silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite to each other.

[0111] Referring to Figure 9, a first silicon carbide semiconductor layer 111 is provided, and the first silicon carbide semiconductor layer 111 and the electrode setting surface 101 of the silicon carbide semiconductor body 100 are arranged opposite to each other.

[0112] S12012. The electrode setting surface is heated to a preset temperature so that the carbon surface of the first silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is the silicon surface.

[0113] Referring to Figure 9, the electrode setting surface 101 of the silicon carbide semiconductor body 100 is heated to a preset temperature so that the carbon surface of the first silicon carbide semiconductor layer 111 and the electrode setting surface 101 provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein, the electrode setting surface 101 is the silicon surface.

[0114] S12013, Silicon is evaporated from the electrode surface, thereby forming a first semiconductor graphene layer on the electrode surface.

[0115] Referring to Figure 9, during the heating process, the silicon on the electrode surface 101 evaporates before the carbon, thereby spontaneously crystallizing on the electrode surface 101 to form a first semiconductor graphene layer 400.

[0116] Based on the above technical solution, Figure 8 is a schematic diagram of the process included in S1301 of Figure 6. As shown in Figure 8, S1301 heats the electrode surface to a preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming a second semiconductor graphene layer on the electrode surface, including:

[0117] S13011, The electrode surfaces of the second silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite to each other.

[0118] Referring to Figure 9, a second silicon carbide semiconductor layer 112 is provided, and the second silicon carbide semiconductor layer 112 and the electrode setting surface 101 of the silicon carbide semiconductor body 100 are arranged opposite to each other.

[0119] S13012. The electrode setting surface is heated to a preset temperature so that the carbon surface of the second silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is the silicon surface.

[0120] Referring to Figure 9, the electrode setting surface 101 of the silicon carbide semiconductor body 100 is heated to a preset temperature so that the carbon surface of the second silicon carbide semiconductor layer 112 and the electrode setting surface 101 provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein, the electrode setting surface 101 is the silicon surface.

[0121] S13013, Silicon evaporation on the electrode surface, thereby forming a second semiconductor graphene layer on the electrode surface.

[0122] Referring to Figure 9, during the heating process, the silicon on the electrode surface 101 evaporates before the carbon, thereby spontaneously crystallizing on the electrode surface 101 to form a second semiconductor graphene layer 500.

[0123] The first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 are covalently bonded to the silicon carbide semiconductor body 100 during growth, eliminating the need for an adhesive layer, thus simplifying the fabrication process and reducing costs. Because the carbon facet of the silicon carbide semiconductor layer and one side of the silicon carbide semiconductor body 100 provide quasi-equilibrium conditions between the carbon and silicon faces at a predetermined temperature, a semiconductor graphene layer with a thickness equal to that of a single carbon atom can be formed on one side of the silicon carbide semiconductor body 100. In summary, the semiconductor graphene layer is essentially a single layer of carbon atoms in the silicon carbide semiconductor body 100, with a thickness equivalent to that of a single layer of carbon atoms in the silicon carbide epitaxial layer. The thickness of the semiconductor graphene layer is greater than or equal to 0.2 nm and less than or equal to 0.3 nm, with an average thickness of approximately 0.25 nm. The bonds between the semiconductor graphene layer and the silicon carbide semiconductor body 100 are ordered and periodically arranged, ensuring that the semiconductor graphene layer is a two-dimensional semiconductor material. The band gap of this semiconductor graphene layer is smaller than that of silicon, with a band gap greater than or equal to 0.4 eV, for example, greater than or equal to 0.6 eV, and a mobility greater than or equal to 1000 cm⁻¹. 2 / Vs, and can even reach 5500cm 2 / Vs around.

[0124] Based on the above technical solution, after forming the first semiconductor graphene layer on the electrode surface in S120, a first protective layer is formed on the side of the first semiconductor graphene layer away from the silicon carbide semiconductor body; and / or, after forming the second semiconductor graphene layer on the electrode surface in S130, a second protective layer is formed on the side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

[0125] Referring to FIG5, after the first semiconductor graphene layer 400 is formed on the electrode setting surface 101, a first protective layer 401 is formed on the side of the first semiconductor graphene layer 400 away from the silicon carbide semiconductor body 100; and / or, after the second semiconductor graphene layer 500 is formed on the electrode setting surface 101, a second protective layer 501 is formed on the side of the second semiconductor graphene layer 500 away from the silicon carbide semiconductor body 100.

[0126] This application provides a power module including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of this application will not be elaborated further here.

[0127] This application provides a power conversion circuit, which is configured to perform one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.

[0128] Therefore, the power conversion circuit incorporates the beneficial effects of any semiconductor device described in any embodiment of this application, which will not be elaborated further here.

[0129] This application embodiment also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is configured to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0130] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of this application will not be repeated here.

[0131] The various processes shown above can be used to rearrange, add, or delete steps. For example, the multiple steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

Claims

1. A semiconductor device, wherein, include: A silicon carbide semiconductor body (100) includes an electrode placement surface (101) and is configured with a first conductivity type; the silicon carbide semiconductor body (100) also includes a first device region (200) and a second device region (300). A first semiconductor graphene layer (400) is located on the electrode placement surface (101) of the first device region (200), and is configured to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer (400) is greater than that of silicon carbide. A second semiconductor graphene layer (500) is located on the electrode placement surface (101) of the second device region (300), and is configured to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the second semiconductor graphene layer (500) is greater than that of silicon carbide. In the semiconductor device, the portion located in the first device region (200) is a silicon carbide metal-oxide semiconductor field-effect transistor of the first conductivity type with the current conduction direction in the first direction, and the portion located in the second device region (300) is a silicon carbide metal-oxide semiconductor field-effect transistor of the second conductivity type with the current conduction direction in the first direction. The first conductivity type silicon carbide metal-oxide semiconductor field-effect transistor and the second conductivity type silicon carbide metal-oxide semiconductor field-effect transistor together constitute a silicon carbide complementary metal-oxide semiconductor; the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body (100).

2. The semiconductor device according to claim 1, wherein, The band gap of the first semiconductor graphene layer (400) and the second semiconductor graphene layer (500) is greater than or equal to 0.4 eV.

3. The semiconductor device according to claim 2, wherein, The band gap of the first semiconductor graphene layer (400) and the second semiconductor graphene layer (500) is greater than or equal to 0.6 eV.

4. The semiconductor device according to claim 1, wherein, The first device region (200) includes two first regions (201) and a well region (202); the two first regions (201) are configured with a first conductivity type and are located on the electrode mounting surface (101), and the well region (202) is configured with a second conductivity type and is located between the two first regions (201); the second device region includes two second regions (301), the two second regions (301) are configured with a second conductivity type and are located on the electrode mounting surface (101); The first semiconductor graphene layer (400) and the two first regions (201) are connected; The second semiconductor graphene layer (500) and the two second regions (301) are connected.

5. The semiconductor device according to claim 1, wherein, Meet at least one of the following: The first semiconductor graphene layer (400) and the silicon carbide semiconductor body (100) are connected in an orderly manner by covalent bonds; The second semiconductor graphene layer (500) and the silicon carbide semiconductor body (100) are connected in an orderly manner by covalent bonds.

6. The semiconductor device according to claim 4, wherein, The semiconductor device further includes: A first insulating layer (601) is located on the electrode mounting surface (101); The first electrode (602) is located in the first device region (200) and on the side of the first insulating layer (601) away from the first semiconductor graphene layer (400); The second electrode (702) is located in the second device region (300) and on the side of the first insulating layer (601) away from the second semiconductor graphene layer (500); The third electrode (603) and the fourth electrode (603) are located in the first device region (200) and on the electrode placement surface (101), respectively connected to the two first regions (201); The fifth electrode (703) and the sixth electrode (704) are located in the second device region (300) and on the electrode placement surface (101), respectively connected to the two second regions (301).

7. The semiconductor device according to claim 1, wherein, Meet at least one of the following: The first semiconductor graphene layer (400) is configured with a first conductivity type; The second semiconductor graphene layer (500) is configured as a second conductivity type.

8. The semiconductor device according to claim 1, further comprising at least one of the following: A first protective layer (401) is located on the side of the first semiconductor graphene layer (400) away from the silicon carbide semiconductor body (100); A second protective layer (501) is located on the side of the second semiconductor graphene layer (500) away from the silicon carbide semiconductor body (100).

9. The semiconductor device according to claim 8, wherein, The first protective layer (401) includes a gold protective layer or an aluminum oxide protective layer; the second protective layer includes a gold protective layer or an aluminum oxide protective layer.

10. The semiconductor device according to claim 1, wherein, There are multiple first device regions (200) and multiple second device regions (300).

11. A method for manufacturing a semiconductor device, comprising: A silicon carbide semiconductor body is provided, wherein the silicon carbide semiconductor body includes an electrode placement surface, and the silicon carbide semiconductor body is configured with a first conductivity type; the silicon carbide semiconductor body further includes a first device region and a second device region. A first semiconductor graphene layer is formed on the electrode surface, wherein the first semiconductor graphene layer is located in the first device region, and is configured to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer is greater than the mobility of silicon carbide. A second semiconductor graphene layer is formed on the electrode surface, wherein the second semiconductor graphene layer is located in the second device region, and is configured to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the second semiconductor graphene layer is greater than that of silicon carbide. The portion located in the first device region is a silicon carbide metal-oxide-semiconductor field-effect transistor of the first conductivity type, with the current conduction direction in the first direction. The portion located in the second device region is a silicon carbide metal-oxide-semiconductor field-effect transistor of the second conductivity type, with the current conduction direction in the first direction. The first conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor and the second conductivity type silicon carbide metal-oxide-semiconductor field-effect transistor together constitute a silicon carbide complementary metal-oxide-semiconductor. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body.

12. The method for manufacturing a semiconductor device according to claim 11, wherein, The band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.4 eV.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, The band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.6 eV.

14. The method for manufacturing a semiconductor device according to claim 11, wherein, The first semiconductor graphene layer is formed on the electrode surface, including: The electrode surface is heated to a preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming the first semiconductor graphene layer on the electrode surface. Forming the second semiconductor graphene layer on the electrode surface includes: The electrode surface is heated to the preset temperature, causing the silicon on the electrode surface to evaporate, thereby forming the second semiconductor graphene layer on the electrode surface.

15. The method for manufacturing a semiconductor device according to claim 14, wherein, Heating the electrode surface to the preset temperature causes the silicon on the electrode surface to evaporate, thereby forming the first semiconductor graphene layer on the electrode surface, including: The electrode surfaces of the first silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite to each other; The electrode surface is heated to the preset temperature so that the carbon surface of the first silicon carbide semiconductor layer and the electrode surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode surface is the silicon surface; Silicon evaporates from the electrode surface, thereby forming the first semiconductor graphene layer on the electrode surface. Heating the electrode surface to the preset temperature causes the silicon on the electrode surface to evaporate, thereby forming the second semiconductor graphene layer on the electrode surface, including: The electrode surfaces of the second silicon carbide semiconductor layer and the silicon carbide semiconductor body are arranged opposite to each other; The electrode surface is heated to the preset temperature so that the carbon surface of the second silicon carbide semiconductor layer and the electrode surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode surface is the silicon surface; Silicon evaporates from the electrode surface, thereby forming the second semiconductor graphene layer on the electrode surface.

16. The method for manufacturing a semiconductor device according to claim 11, further comprising at least one of the following: After the first semiconductor graphene layer is formed on the electrode surface, a first protective layer is formed on the side of the first semiconductor graphene layer away from the silicon carbide semiconductor body. After the second semiconductor graphene layer is formed on the electrode surface, a second protective layer is formed on the side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

17. A power module comprising a substrate and a semiconductor device according to any one of claims 1-10, wherein the substrate is configured to support the semiconductor device.

18. A power conversion circuit, the power conversion circuit being configured to perform at least one of the following: current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-10, wherein the semiconductor device is electrically connected to the circuit board.

19. A vehicle, comprising a load and a power conversion circuit as claimed in claim 18, the power conversion circuit being configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the power to the load.

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