Discontinuous-current-type resonant gate drive circuit having variable duty cycle output

Abstract

The present invention belongs to the field of power electronics. Disclosed is a discontinuous-current-type resonant gate drive circuit having a variable duty cycle output. The resonant gate drive circuit comprises: one PMOS transistor, two NMOS transistors, one inductor L and one voltage-stabilizing capacitor, wherein by means of controlling the timing of gate drive signals of the PMOS transistor and the NMOS transistors, on-off states of the PMOS transistor and the NMOS transistors are controlled, and the inductor current flowing through the inductor is controlled to be in a discontinuous state, thereby controlling resonant states of the inductor and a gate capacitor of a driven circuit, and the duty cycle of a drive output voltage. The inductor current of the circuit in the present invention is discontinuous, which greatly reduces the turn-on loss of the circuit and improves the recycling ratio of gate drive energy. Duty cycle variation of a drive signal can be realized by means of controlling the duty cycle of the drive signal. Therefore, the technical problems of low energy recovery rate, excessive number of control signals, difficult signal matching, large occupied area, being adverse to miniaturization, non-adjustable duty cycle, etc., in drive technology are solved.

Description

Resonant gate drive circuit with discontinuous current type variable duty cycle output Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a resonant gate drive circuit with discontinuous current type variable duty cycle output. Background Technology

[0002] Resonant converter circuits (LLCs), due to their excellent soft-switching characteristics, can achieve ZVS of the primary-side MOSFET and ZVS and ZCS of the secondary-side synchronous rectifier across the entire load range. This makes them suitable for high-frequency operation and provides very high power density, making them widely used in high-power-density applications. The drive losses of MOSFETs are proportional to the switching frequency. At MHz operating frequencies, MOSFET drive losses gradually become a key factor limiting further improvements in efficiency and power density, especially in low-voltage, high-current output applications. Due to the large output current, multiple MOSFETs often need to be connected in parallel on the secondary side of the LLC to reduce the conduction losses of the synchronous rectifier, which leads to increased system drive losses. To reduce the drive losses of converters at high frequencies and improve system conversion efficiency and power density, many resonant gate drivers have been proposed in recent years. However, for low-voltage, high-current LLC applications, they suffer from problems such as large footprint, low gate drive energy recovery ratio, small drive current, and unadjustable drive signal duty cycle. Summary of the Invention

[0003] This invention provides a resonant gate drive circuit with discontinuous current type variable duty cycle output, which solves the technical problems of the above-mentioned drive technology, such as low energy recovery rate, large number of control signals, difficult signal matching, large area occupation, unfavorable for miniaturization, and non-adjustable duty cycle.

[0004] This invention provides a resonant gate drive circuit with discontinuous current-type variable duty cycle output, comprising: a PMOS transistor Q1, NMOS transistors Q2 and Q3, an inductor L, and a voltage regulator capacitor C. R ;

[0005] The gate of the PMOS transistor Q1 is connected to the first drive signal, the source is connected to an external power supply, and the drain is connected to one end of the inductor L, the drain of the NMOS transistor Q2, and the drive signal output terminal of the resonant gate drive circuit. The drive signal output terminal is connected to the signal input terminal of the driven circuit.

[0006] The gate of the NMOS transistor Q2 is connected to the second drive signal, and the source is grounded;

[0007] The gate of NMOS transistor Q3 is connected to the third drive signal, its drain is connected to the other end of the inductor L, and its source is connected to the voltage regulator capacitor C.R One end of the voltage regulator capacitor C R The other end is grounded;

[0008] By controlling the timing of the first drive signal, the second drive signal, and the third drive signal, the switching states of the PMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q3 are controlled, and the inductor current flowing through the inductor L is made discontinuous. This, in turn, controls the resonant state of the inductor L and the gate capacitance of the driven circuit, as well as the duty cycle of the drive output voltage.

[0009] Optionally, in one embodiment of the present invention, controlling the switching states of the PMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q3 by controlling the timing of the first driving signal, the second driving signal, and the third driving signal includes:

[0010] The first drive signal v that controls the PMOS transistor Q1 g1 When the signal is high, the PMOS transistor Q1 is turned off, and when the first drive signal v g1 When the voltage level is low, the PMOS transistor Q1 is turned on;

[0011] The second drive signal v controls the NMOS transistor Q2 g2 When the signal is high, the NMOS transistor Q2 is turned on, and when the second drive signal v g2 When the signal is low, the NMOS transistor Q2 is turned off;

[0012] The third drive signal v controls the NMOS transistor Q3 g3 When the signal is high, the NMOS transistor Q3 is turned on, and when the third drive signal v g3 When the signal is low, the NMOS transistor Q3 is turned off.

[0013] Optionally, in one embodiment of the present invention, the driven circuit includes a driven transistor Q and an equivalent gate capacitance C. geq Among them, the equivalent gate capacitance C geq One end of the circuit is connected to the gate of the driven transistor and the drive signal output terminal of the resonant gate drive circuit, and the other end is connected to the source of the driven transistor and ground. The drain of the driven transistor is connected to the main power circuit. By controlling the timing of the first drive signal, the second drive signal, and the third drive signal, the switching states of the PMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q3 are controlled, and the inductor current flowing through the inductor L is made discontinuous. This controls the resonant state of the inductor L and the gate capacitance of the driven circuit, as well as the duty cycle of the drive output voltage, to operate in the following mode:

[0014] During t0-t1: the first drive signal, the second drive signal, and the third drive signal are all at a high level, and the equivalent gate capacitance C geq The initial voltage across the terminals is 0, and NMOS transistors Q2 and Q3 are turned on. The voltage regulator capacitor C... R The inductor L is resonantly charged, and the inductor current i L The voltage regulator capacitor C increases approximately linearly from 0. R The voltage across the terminals drops;

[0015] During t1-t2: the first drive signal and the third drive signal are at high level, the second drive signal is at low level, the NMOS transistor Q2 is turned off, and the voltage regulator capacitor C... R The inductor L and the equivalent gate capacitance C geq Resonance, inductor current i L The voltage rises first and then falls, driving the output voltage v gsr It keeps rising until it equals the external power supply voltage Vcc.

[0016] During t2-t3: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the PMOS transistor Q1 is turned on, and the external power supply Vcc, the inductor L, and the voltage regulator capacitor C are connected. R Resonant charging and discharging, inductor current i L The voltage drops until it reaches 0, at which point the voltage regulator capacitor C... R The voltage across the terminals increases;

[0017] During t3-t4: the first drive signal, the second drive signal, and the third drive signal are all at a low level, NMOS transistor Q3 is turned off, and the drive output voltage v gsr Clamped to a high level by the external power supply Vcc;

[0018] During t4-t5: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the NMOS transistor Q3 is turned on, the external power supply Vcc is supplied to the inductor L, and the voltage regulator capacitor C... R Charging, inductor current i L The voltage regulator capacitor C rises approximately linearly from 0. R The voltage across the terminals increases;

[0019] During t5-t6: the first drive signal and the third drive signal are at high level, the second drive signal is at low level, the PMOS transistor Q1 is turned off, and the equivalent gate capacitance C... geq The inductor L and the voltage regulator C R Resonance, inductor current i L The voltage rises first and then falls, driving the output voltage vgsr It keeps decreasing until it reaches zero;

[0020] During t6-t7: the first drive signal, the second drive signal, and the third drive signal are all at a high level, the NMOS transistor Q2 is turned on, and the inductor L and the voltage regulator capacitor C... R Resonance, inductor current i L The voltage regulator capacitor C drops. R The voltage across the terminals rises until the inductor current i L Reduced to 0;

[0021] During t7-t8: the first drive signal and the second drive signal are at high level, the third drive signal is at low level, NMOS transistor Q3 is turned off, and the inductor current i L When the value is 0, the drive output voltage v gsr The NMOS transistor Q2 is clamped to 0.

[0022] The resonant gate drive circuit with discontinuous current-type variable duty cycle output according to embodiments of the present invention has the following beneficial effects:

[0023] 1) The circuit of this invention has a small inductance value, which saves cost and space and is conducive to miniaturization and integration;

[0024] 2) The inductor current of the circuit of the present invention is discontinuous, which greatly reduces the conduction loss of the circuit and increases the gate drive energy recovery ratio.

[0025] 3) The circuit of the present invention implements soft switching, reduces the switching loss of the circuit, and can work efficiently at high frequencies.

[0026] 4) The circuit of the present invention can realize the duty cycle transformation of the drive signal by controlling the duty cycle of the drive signal.

[0027] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0029] Figure 1 is a diagram of a resonant gate drive circuit for discontinuous current type variable duty cycle output according to an embodiment of the present invention;

[0030] Figure 2 is a timing diagram of key waveforms in an embodiment of the present invention;

[0031] Figure 3 is a schematic diagram of the current loop of different modes of the circuit in an embodiment of the present invention;

[0032] Figure 4 is a timing diagram of the key waveforms of the circuit drive output duty cycle change in an embodiment of the present invention. Detailed Implementation

[0033] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0034] Figure 1 is a resonant gate drive circuit diagram of a discontinuous current type variable duty cycle output according to an embodiment of the present invention.

[0035] As shown in Figure 1, the resonant gate drive circuit for discontinuous current type variable duty cycle output includes: PMOS transistor Q1, NMOS transistors Q2 and Q3, inductor L, and voltage regulator capacitor C. R .

[0036] The gate of PMOS transistor Q1 is connected to the first drive signal, the source is connected to the external power supply, and the drain is connected to one end of inductor L, the drain of NMOS transistor Q2, and the drive signal output terminal of the resonant gate drive circuit. The drive signal output terminal is connected to the signal input terminal of the driven circuit.

[0037] The gate of NMOS transistor Q2 is connected to the second drive signal, and the source is grounded;

[0038] The gate of NMOS transistor Q3 is connected to the third drive signal, the drain is connected to the other end of inductor L, and the source is connected to the Zener capacitor C. R One end, the voltage regulator capacitor C R The other end is grounded;

[0039] By controlling the timing of the first, second, and third driving signals, the switching states of PMOS transistors Q1, Q2, and Q3, as well as the discontinuous state of the inductor current flowing through inductor L, are controlled. This, in turn, controls the resonant state of inductor L and the gate capacitance of the driven circuit, and the duty cycle of the driving output voltage.

[0040] As shown in Figure 1, the driving circuit is powered by an external power supply Vcc. The driving circuit includes a PMOS transistor Q1, two NMOS transistors Q2 and Q3, an inductor L, and a voltage regulator capacitor C. R Utilizing the principle of lossless LC resonant charging and discharging, an externally input driving signal v g1 -v g3The timing of the circuit controls the switching states of the three MOS transistors, enabling resonant charging and discharging of the inductor and gate capacitor, thus achieving near-lossless gate drive. By controlling the current flowing through the inductor to be discontinuous, low cycle conduction loss and smaller inductor design are achieved, resulting in a resonant gate drive circuit with high energy recovery ratio and small footprint.

[0041] Figure 1 also includes a driven circuit, which includes a driven transistor Q and an equivalent gate capacitance C. geq Among them, the equivalent gate capacitance C geq One end of the circuit is connected to the gate of the driven transistor and the drive signal output terminal of the resonant gate drive circuit, and the other end is connected to the source of the driven transistor and ground. The drain of the driven transistor is connected to the main power circuit.

[0042] As shown in Figure 2, the switching states of PMOS transistors Q1, Q2, and Q3 are controlled by controlling the timing of the first, second, and third drive signals, including:

[0043] The first drive signal v controlling PMOS transistor Q1 g1 When the signal is high, PMOS transistor Q1 is turned off, and when the first drive signal v g1 When the signal is low, PMOS transistor Q1 is turned on;

[0044] The second drive signal v controls the NMOS transistor Q2 g2 When the signal is high, NMOS transistor Q2 is turned on, and when the second drive signal v g2 When the signal is low, NMOS transistor Q2 is turned off;

[0045] The third drive signal v controls NMOS transistor Q3 g3 When the signal is high, NMOS transistor Q3 is turned on, and when the third drive signal v g3 When the signal is low, NMOS transistor Q3 is turned off.

[0046] By controlling the three drive signals v g1 -v g3 The timing is configured to drive the output signal v. gsr control.

[0047] In one embodiment of the present invention, as shown in FIG3, the proposed resonant gate drive circuit with discontinuous current type variable duty cycle output can be in eight states according to different operating modes during one working cycle. The dashed part is the main current path under the operating mode, and the current direction is indicated by arrows.

[0048] As shown in Figure 4, the proposed resonant gate drive circuit with discontinuous current-type variable duty cycle output can be adjusted according to system requirements by controlling three drive signals v. g1-v g3 The timing can be adjusted to drive the output signal v gsr Changes in duty cycle.

[0049] Combining Figures 2 and 3, the specific circuit operating modes under steady state are analyzed as follows:

[0050] During t0-t1: the first drive signal, the second drive signal, and the third drive signal are all at a high level, and the equivalent gate capacitance C geq The initial voltage across the terminals is 0, NMOS transistors Q2 and Q3 are turned on, and the voltage regulator capacitor C... R When inductor L is resonantly charged, the inductor current i L Starting from 0, the voltage rises approximately linearly, and the voltage regulator capacitor C... R The voltage across the terminals drops;

[0051] During t1-t2: the first and third drive signals are high, the second drive signal is low, NMOS transistor Q2 is off, and the voltage regulator capacitor C... R Inductor L and equivalent gate capacitance C geq Resonance, inductor current i L The voltage rises first and then falls, driving the output voltage v gsr It keeps rising until it equals the external power supply voltage Vcc.

[0052] During t2-t3: the first and second drive signals are low, the third drive signal is high, PMOS transistor Q1 is turned on, and the external power supply Vcc, inductor L, and voltage regulator capacitor C are activated. R Resonant charging and discharging, inductor current i L The voltage drops until it reaches 0, and the voltage regulator capacitor C... R The voltage across the terminals increases;

[0053] During t3-t4: the first drive signal, the second drive signal, and the third drive signal are all at a low level, NMOS transistor Q3 is turned off, and the drive output voltage v gsr Clamped to a high level by the external power supply Vcc;

[0054] During t4-t5: the first and second drive signals are low, the third drive signal is high, NMOS transistor Q3 is turned on, and external power supply Vcc supplies power to inductor L and voltage regulator capacitor C. R Charging, inductor current i L The voltage regulator capacitor C rises approximately linearly from 0. R The voltage across the terminals increases;

[0055] During t5-t6: the first and third drive signals are high, the second drive signal is low, PMOS transistor Q1 is turned off, and the equivalent gate capacitance C... geq Inductor L and voltage regulator capacitor CR Resonance, inductor current i L The voltage rises first and then falls, driving the output voltage v gsr It keeps decreasing until it reaches zero;

[0056] During t6-t7: The first drive signal, the second drive signal, and the third drive signal are all at a high level, NMOS transistor Q2 is turned on, and inductor L and voltage regulator capacitor C are... R Resonance, inductor current i L The voltage drops, and the voltage regulator capacitor C... R The voltage across the terminals rises until the inductor current i L Reduced to 0;

[0057] During t7-t8: the first and second drive signals are high, the third drive signal is low, NMOS transistor Q3 is turned off, and the inductor current i L When the value is 0, the drive output voltage v gsr The NMOS transistor Q2 clamps the signal to 0.

[0058] Comparing Figures 2 and 4, it is proposed that the resonant gate drive circuit with discontinuous current-type variable duty cycle output can achieve the driving voltage v by changing the duration of one operating cycle t3-t4. gsr Changes in duty cycle.

[0059] The resonant gate drive circuit with discontinuous current type variable duty cycle output proposed in the embodiment of the present invention controls the switching of the switching transistor by controlling three drive signals. The inductor and the gate capacitance of the driven transistor form a resonance, realizing energy recovery and greatly reducing drive loss. By controlling the current flowing through the inductor to be discontinuous, low cycle conduction loss and smaller inductor design are achieved, thereby realizing a high energy recovery ratio, small footprint and variable duty cycle output.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A resonant gate drive circuit with discontinuous current-type variable duty cycle output, characterized in that, include: PMOS transistor Q1, NMOS transistors Q2 and Q3, inductor L, and voltage regulator capacitor C R ; The gate of the PMOS transistor Q1 is connected to the first drive signal, the source is connected to an external power supply, and the drain is connected to one end of the inductor L, the drain of the NMOS transistor Q2, and the drive signal output terminal of the resonant gate drive circuit. The drive signal output terminal is connected to the signal input terminal of the driven circuit. The gate of the NMOS transistor Q2 is connected to the second drive signal, and the source is grounded; The gate of NMOS transistor Q3 is connected to the third drive signal, its drain is connected to the other end of the inductor L, and its source is connected to the voltage regulator capacitor C. R One end of the voltage regulator capacitor C R The other end is grounded; By controlling the timing of the first drive signal, the second drive signal, and the third drive signal, the switching states of the PMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q3 are controlled, and the inductor current flowing through the inductor L is made discontinuous. This, in turn, controls the resonant state of the inductor L and the gate capacitance of the driven circuit, as well as the duty cycle of the drive output voltage.

2. The resonant gate drive circuit with discontinuous current type variable duty cycle output according to claim 1, characterized in that, The switching states of the PMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q3 are controlled by controlling the timing of the first drive signal, the second drive signal, and the third drive signal, including: The first drive signal v that controls the PMOS transistor Q1 g1 When the signal is high, the PMOS transistor Q1 is turned off, and when the first drive signal v g1 When the voltage level is low, the PMOS transistor Q1 is turned on; The second drive signal v controls the NMOS transistor Q2 g2 When the signal is high, the NMOS transistor Q2 is turned on, and when the second drive signal v g2 When the signal is low, the NMOS transistor Q2 is turned off; The third drive signal v controls the NMOS transistor Q3 g3 When the signal is high, the NMOS transistor Q3 is turned on, and when the third drive signal v g3 When the signal is low, the NMOS transistor Q3 is turned off.

3. The resonant gate drive circuit with discontinuous current type variable duty cycle output according to claim 2, characterized in that, The driven circuit includes a driven transistor Q and an equivalent gate capacitance C. geq Among them, the equivalent gate capacitance C geq One end of the circuit is connected to the gate of the driven transistor and the drive signal output terminal of the resonant gate drive circuit, and the other end is connected to the source of the driven transistor and ground. The drain of the driven transistor is connected to the main power circuit. By controlling the timing of the first drive signal, the second drive signal, and the third drive signal, the switching states of the PMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q3 are controlled, and the inductor current flowing through the inductor L is made discontinuous. This controls the resonant state of the inductor L and the gate capacitance of the driven circuit, as well as the duty cycle of the drive output voltage, to operate in the following mode: During t0-t1: the first drive signal, the second drive signal, and the third drive signal are all at a high level, and the equivalent gate capacitance C geq The initial voltage across the terminals is 0, and NMOS transistors Q2 and Q3 are turned on. The voltage regulator capacitor C... R The inductor L is resonantly charged, and the inductor current i L The voltage regulator capacitor C rises approximately linearly from 0. R The voltage across the terminals drops; During t1-t2: the first drive signal and the third drive signal are at high level, the second drive signal is at low level, the NMOS transistor Q2 is turned off, and the voltage regulator capacitor C... R The inductor L and the equivalent gate capacitance C geq Resonance, inductor current i L The voltage rises first and then falls, driving the output voltage v gsr It keeps rising until it equals the external power supply voltage Vcc. During t2-t3: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the PMOS transistor Q1 is turned on, and the external power supply Vcc, the inductor L, and the voltage regulator capacitor C are connected. R Resonant charging and discharging, inductor current i L The voltage drops until it reaches 0, at which point the voltage regulator capacitor C... R The voltage across the terminals increases; During t3-t4: the first drive signal, the second drive signal, and the third drive signal are all at a low level, NMOS transistor Q3 is turned off, and the drive output voltage v gsr Clamped to a high level by the external power supply Vcc; During t4-t5: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the NMOS transistor Q3 is turned on, the external power supply Vcc is supplied to the inductor L, and the voltage regulator capacitor C... R Charging, inductor current i L The voltage regulator capacitor C rises approximately linearly from 0. R The voltage across the terminals increases; During t5-t6: the first drive signal and the third drive signal are at high level, the second drive signal is at low level, the PMOS transistor Q1 is turned off, and the equivalent gate capacitance C... geq The inductor L and the voltage regulator C R Resonance, inductor current i L The voltage rises first and then falls, driving the output voltage v gsr It keeps decreasing until it reaches zero; During t6-t7: the first drive signal, the second drive signal, and the third drive signal are all at a high level, the NMOS transistor Q2 is turned on, and the inductor L and the voltage regulator capacitor C... R Resonance, inductor current i L The voltage regulator capacitor C drops. R The voltage across the terminals rises until the inductor current i L Reduced to 0; During t7-t8: the first drive signal and the second drive signal are at high level, the third drive signal is at low level, NMOS transistor Q3 is turned off, and the inductor current i L When the value is 0, the drive output voltage v gsr The NMOS transistor Q2 is clamped to 0.

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