Transistor, semiconductor device and manufacturing method therefor, and electronic device
Patent Information
- Application Number
- PCT/CN2025/137557
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-21
- Filing Date
- 2025-11-25
- Publication Date
- 2026-08-27
Smart Images
Figure CN2025137557_27082026_PF_FP_ABST
Abstract
Description
Transistors, semiconductor devices and their manufacturing methods, electronic devices
[0001] This application claims priority to Chinese Patent Application No. 2025101998954, filed on February 21, 2025, entitled "Transistor, Semiconductor Device and Method of Manufacturing Thereof, Electronic Device", the contents of which are to be construed as incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and more particularly to a transistor, a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology
[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.
[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.
[0006] This application provides a transistor, which includes: a first electrode, a second electrode, a first semiconductor layer, a first gate electrode, a second gate electrode, and a gate insulating layer located on a substrate;
[0007] The first gate electrode, the first electrode, and the second electrode are spaced apart along a direction perpendicular to the substrate; the first semiconductor layer and the second gate electrode both extend along a direction perpendicular to the substrate; the first electrode and the second electrode are located on the sidewall of the first semiconductor layer;
[0008] One end of the second gate electrode is at least partially surrounded by the first gate electrode;
[0009] The first semiconductor layer is insulated from the second gate electrode, and the first gate electrode is insulated from the second gate electrode by the gate insulating layer.
[0010] In some embodiments of this application, at least a portion of one end face of the second gate electrode and the sidewall connected to that end face are surrounded by the first gate electrode.
[0011] In some embodiments of this application, the second gate electrode has a first end close to the substrate and a second end away from the substrate; the end face of the first end is completely surrounded by the first gate electrode, and the four sidewalls of the first end connected to the end face are completely surrounded by the first gate electrode.
[0012] In some embodiments of this application, the first gate electrode has a through hole that is closed at one end and open at the other end, and the first end of the second gate electrode extends into the through hole through the opening.
[0013] In some embodiments of this application, the first electrode at least partially surrounds the first semiconductor layer and the second gate electrode; and / or,
[0014] The second electrode at least partially surrounds the first semiconductor layer and the second gate electrode.
[0015] In some embodiments of this application, the first semiconductor layer at least partially surrounds the second gate electrode.
[0016] This application embodiment also provides a semiconductor device, the semiconductor device comprising: a plurality of memory cells located on a substrate; the plurality of memory cells are arranged in an array and spaced apart on the substrate along row and column directions parallel to the substrate;
[0017] The storage cell includes read transistors and write transistors stacked along a direction perpendicular to the substrate; the read transistors are transistors as described above.
[0018] In some embodiments of this application, the write transistor includes a third electrode, a fourth electrode, a second semiconductor layer, and a third gate electrode, wherein the second semiconductor layer and the third gate electrode are insulated from each other by the gate insulating layer;
[0019] Both the second semiconductor layer and the third gate electrode extend in a direction perpendicular to the substrate; the second semiconductor layer at least partially surrounds the third gate electrode.
[0020] The third electrode and the fourth electrode are spaced apart along a direction perpendicular to the substrate, and both the third electrode and the fourth electrode are located on at least one side of the second semiconductor layer; the third electrode is connected to the second gate electrode located in the same memory cell.
[0021] In some embodiments of this application, the storage unit further includes a storage node, and the storage node, the second gate electrode, and the third electrode located in the same storage unit are an integral structure.
[0022] In some embodiments of this application, the semiconductor device further includes read word lines, read bit lines, source lines, write word lines, and write bit lines;
[0023] The read line extends along the column direction and is connected to the first gate electrode of a column of memory cells spaced apart along the column direction; and / or,
[0024] The read bit line extends along the row direction and is connected to the first electrode of a row of memory cells spaced apart along the row direction; and / or,
[0025] The source line extends along the row direction and is connected to the second electrode of a row of memory cells spaced apart along the row direction; and / or,
[0026] The write line extends along the column direction and is connected to the third gate electrode of a column of memory cells spaced apart along the column direction; and / or,
[0027] The write bit line extends along the row direction and is connected to the fourth electrode of a row of memory cells spaced apart along the row direction.
[0028] This application also provides a method for manufacturing a semiconductor device, the method comprising:
[0029] A first gate electrode, a first electrode, and a second electrode are sequentially formed on one side of the substrate and are stacked and spaced apart.
[0030] The second electrode and the first electrode are etched along the direction toward the substrate to form a first through hole through the second electrode and the first electrode, wherein the first through hole does not expose the first gate electrode;
[0031] A first semiconductor layer and a sacrificial layer are sequentially formed on the sidewall of the first via;
[0032] The bottom of the first through hole is etched to extend the first through hole into the interior of the first gate electrode;
[0033] Remove the sacrificial layer from the sidewall of the first through hole;
[0034] A gate insulating layer and a second gate electrode are sequentially formed on the inner wall of the first through hole.
[0035] In some embodiments of this application, the step of sequentially forming a first gate electrode, a first electrode, and a second electrode stacked and spaced apart on one side of the substrate includes:
[0036] An insulating layer and a gate electrode layer are sequentially formed on one side of the substrate;
[0037] The gate electrode layer is patterned and etched, and the patterned gate electrode layer includes multiple read lines spaced apart along a row direction parallel to the substrate and extending along a column direction parallel to the substrate; each read line includes multiple first gate electrodes distributed along the column direction;
[0038] An insulating layer and a first electrode layer covering the patterned gate electrode layer are sequentially formed on the substrate surface;
[0039] The first electrode layer is patterned and etched, and the patterned first electrode layer includes multiple read lines extending along the row direction and spaced apart along the column direction; each read line includes multiple first electrodes distributed along the row direction.
[0040] An insulating layer and a second electrode layer covering the patterned first electrode layer are sequentially formed on the substrate surface;
[0041] The second electrode layer is patterned by etching, and the patterned second electrode layer includes multiple source lines extending along the row direction and spaced apart along the column direction; each source line includes multiple second electrodes distributed along the row direction.
[0042] In some embodiments of this application, etching the second electrode and the first electrode along a direction toward the substrate to form a first via through the second electrode and the first electrode, wherein the first via does not expose the first gate electrode, includes:
[0043] The second electrode and the first electrode, as well as the insulating layer between them, are etched along the direction toward the substrate to form a first via through the second electrode and the first electrode, as well as the insulating layer between them. The first via exposes the insulating layer between the first gate electrode and the first electrode. The width of the first via in the row direction is smaller than the width of the first gate electrode in the row direction.
[0044] In some embodiments of this application, the manufacturing method further includes: after forming the second gate electrode,
[0045] A fourth electrode is formed on the side of the second gate electrode away from the substrate, stacked with and spaced apart from the second gate electrode;
[0046] The fourth electrode is etched along the direction toward the substrate to form a second through-hole through the fourth electrode, the second through-hole exposing the second gate electrode;
[0047] A second semiconductor layer, a gate insulating layer, and a third gate electrode are sequentially formed within the second via.
[0048] A writing line connected to the third gate electrode is formed on the side of the third gate electrode away from the substrate.
[0049] In some embodiments of this application, forming a fourth electrode stacked and spaced apart from the second gate electrode on the side of the second gate electrode away from the substrate; and etching the fourth electrode along a direction toward the substrate to form a second through-hole through the fourth electrode, includes:
[0050] An insulating layer and a third electrode layer covering the second gate electrode are sequentially formed on the substrate surface;
[0051] The third electrode layer is patterned and etched, and the patterned third electrode layer includes multiple write bit lines extending along a row direction parallel to the substrate and spaced apart along a column direction parallel to the substrate; each write bit line includes multiple fourth electrodes distributed along the row direction.
[0052] An insulating layer covering the patterned third electrode layer is formed on the substrate surface;
[0053] The fourth electrode and the insulating layers on both sides are etched along the direction toward the substrate to form a second via through the fourth electrode and the insulating layers on both sides, the second via exposing the second gate electrode.
[0054] This application also provides an electronic device, which includes the transistor or semiconductor device described above, or a semiconductor device obtained by the manufacturing method described above.
[0055] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.
[0056] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.
[0057] Overview of the attached figures
[0058] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0059] Figure 1A is a longitudinal cross-sectional schematic diagram of a transistor according to an exemplary embodiment of this application;
[0060] Figure 1B is a schematic cross-sectional view of the transistor shown in Figure 1A on a section parallel to the substrate;
[0061] Figure 2A is a top view of a semiconductor device according to an exemplary embodiment of this application;
[0062] Figure 2B is a schematic diagram of the longitudinal section structure of the semiconductor device shown in Figure 2A on the section perpendicular to the substrate aa'.
[0063] Figure 2C is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in Figure 2A on a section perpendicular to the substrate bb'.
[0064] Figure 3 is a logic circuit diagram of a semiconductor device according to an embodiment of this application;
[0065] Figure 4 is a process flow diagram of a semiconductor device manufacturing method according to an exemplary embodiment of this application;
[0066] Figure 5A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming readout lines;
[0067] Figure 5B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 5A on the section perpendicular to the substrate aa'.
[0068] Figure 5C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 5A on the section perpendicular to the substrate bb'.
[0069] Figure 6A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after the source line has been formed;
[0070] Figure 6B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 6A on the section aa' perpendicular to the substrate;
[0071] Figure 6C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 6A on the section perpendicular to the substrate bb'.
[0072] Figure 7A is a schematic cross-section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a first through-hole, on a section parallel to the substrate.
[0073] Figure 7B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 7A on the section aa' perpendicular to the substrate;
[0074] Figure 7C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 7A on the section perpendicular to the substrate bb'.
[0075] Figure 8A is a schematic cross-section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a sacrificial layer, on a section parallel to the substrate.
[0076] Figure 8B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 8A on the section aa' perpendicular to the substrate;
[0077] Figure 8C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 8A on the section perpendicular to the substrate bb'.
[0078] Figure 9A is a schematic cross-section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the first through-hole is extended into the first gate electrode, on a section parallel to the substrate.
[0079] Figure 9B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 9A on the section aa' perpendicular to the substrate;
[0080] Figure 9C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 9A on the section perpendicular to the substrate bb'.
[0081] Figure 10A is a schematic cross-section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the second gate electrode, on a section parallel to the substrate.
[0082] Figure 10B is a schematic diagram of the longitudinal section structure of the semiconductor structure shown in Figure 10A on the section perpendicular to the substrate aa'.
[0083] Figure 10C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 10A on the section perpendicular to the substrate bb'.
[0084] Figure 11A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after the write bit line has been formed;
[0085] Figure 11B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 11A on the section aa' perpendicular to the substrate;
[0086] Figure 11C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 11A on the section perpendicular to the substrate bb'.
[0087] Figure 12A is a schematic cross-section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the third gate electrode, on a section parallel to the substrate.
[0088] Figure 12B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 12A on the section aa' perpendicular to the substrate;
[0089] Figure 12C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 12A on the section perpendicular to the substrate bb'.
[0090] Detailed Explanation
[0091] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.
[0092] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.
[0093] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.
[0094] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.
[0095] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0096] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.
[0097] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
[0098] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0099] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0100] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0101] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values shown in the drawings.
[0102] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.
[0103] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.
[0104] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.
[0105] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0106] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0107] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".
[0108] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.
[0109] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functional circuits are already distributed. The devices involved in the inventive construction of the embodiments of this application are disposed on the main surface of the support structure.
[0110] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.
[0111] This application provides a transistor. FIG1A is a longitudinal cross-sectional view of a transistor according to an exemplary embodiment of this application; FIG1B is a cross-sectional view of the transistor shown in FIG1A on a section parallel to the substrate. In FIG1B, the cross-section passes through the first gate electrode G1.
[0112] As shown in Figures 1A and 1B, the transistor includes: a first electrode P1, a second electrode P2, a first semiconductor layer C1, a first gate electrode G1, a second gate electrode G2, and a gate insulating layer 20 located on a substrate 10.
[0113] The first gate electrode G1, the first electrode P1, and the second electrode P2 are distributed at intervals along a direction perpendicular to the substrate 10;
[0114] The first semiconductor layer C1 and the second gate electrode G2 both extend in a direction perpendicular to the substrate 10, and the first semiconductor layer C1 at least partially surrounds the second gate electrode G2; the first electrode P1 and the second electrode P2 are both located on the sidewall of the first semiconductor layer C1.
[0115] One end of the second gate electrode G2 is at least partially surrounded by the first gate electrode G1;
[0116] The first semiconductor layer C1 and the second gate electrode G2, as well as the first gate electrode G1 and the second gate electrode G2, are insulated from each other by the gate insulating layer 20.
[0117] In this embodiment, the second gate electrode G2 of the read transistor is surrounded by the first gate electrode G1, which increases the contact area between the second gate electrode G2 and the first gate electrode G1. This allows the first gate electrode G1, the second gate electrode G2, and the gate insulating layer 20 between them to form a capacitor structure, achieving capacitive coupling. This enables the switching of the transistor to be controlled through the first gate electrode G1.
[0118] In some embodiments of this application, at least a portion of one end face of the second gate electrode G2 and the sidewall connected to that end face are surrounded by the first gate electrode G1.
[0119] In some embodiments of this application, the second gate electrode G2 has a first end close to the substrate 10 and a second end away from the substrate 10; the end face of the first end is completely surrounded by the first gate electrode G1, and the four sidewalls of the first end connected to the end face are completely surrounded by the first gate electrode G1.
[0120] In some embodiments of this application, the first gate electrode G1 has a through hole that is closed at one end and open at the other end, and the first end of the second gate electrode G2 extends into the through hole through the opening.
[0121] In some embodiments of this application, as shown in FIG1A, the orthographic projection of the first end of the second gate electrode G2 on the substrate 10 falls within the range of the orthographic projection of the second end on the substrate 10. In other embodiments, the orthographic projection of the second end of the second gate electrode G2 on the substrate 10 may also fall within the range of the orthographic projection of the first end on the substrate 10.
[0122] In some embodiments of this application, as shown in FIG1A, the first electrode P1 at least partially surrounds the first semiconductor layer C1 and the second gate electrode G2.
[0123] In some embodiments of this application, as shown in FIG1A, the second electrode P2 at least partially surrounds the first semiconductor layer C1 and the second gate electrode G2.
[0124] In some embodiments of this application, as shown in FIG1A, the first semiconductor layer C1 at least partially surrounds the second gate electrode G2.
[0125] This application also provides a semiconductor device. FIG2A is a top view of a semiconductor device according to an exemplary embodiment of this application; FIG2B is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in FIG2A on the cross-section aa' perpendicular to the substrate; FIG2C is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in FIG2A on the cross-section bb' perpendicular to the substrate.
[0126] As shown in Figures 2A to 2C, the semiconductor device includes: a plurality of memory cells located on a substrate 10; the plurality of memory cells are arranged in an array and spaced apart on the substrate 10 along row and column directions parallel to the substrate 10;
[0127] The storage cell includes read transistors and write transistors stacked along a direction perpendicular to the substrate 10; the read transistors are transistors as described above.
[0128] The semiconductor device in this application embodiment controls the switching of the read transistor through capacitive coupling: when writing data, the write transistor is used as a switch to write 0 and 1 bits; when reading data, the first gate electrode is used as the selector of the read transistor. The first gate electrode of the read transistor corresponding to the bit to be read does not interfere, while the read transistor corresponding to other bits that do not need to be read is turned off by controlling it through the first gate electrode, thereby enabling the selection of a specific read transistor and avoiding current sharing.
[0129] Furthermore, the semiconductor device in this application embodiment stacks the read transistors and write transistors in a vertical direction, which can reduce the area occupied by the memory cell and increase the integration density of the device.
[0130] Figure 3 is a logic circuit diagram of the semiconductor device according to an embodiment of this application. As shown in Figure 3, the semiconductor device of this embodiment controls the switching of the read transistor through capacitive coupling: when writing data, the write transistor is used as a switch to write 0 and 1 bits; when reading data, the first gate electrode G1 is used as the selector of the read transistor. The first gate electrode G1 of the read transistor corresponding to the bit that needs to be read does not interfere, while the first gate electrode G1 controls the read transistor corresponding to other bits that do not need to be read to be turned off, thereby enabling the selection of a specific read transistor and avoiding current sharing.
[0131] In some embodiments of this application, the write transistor includes a third electrode P3, a fourth electrode P4, a second semiconductor layer C2 and a third gate electrode G3, wherein the second semiconductor layer C2 and the third gate electrode G3 are insulated from each other by a gate insulating layer 20.
[0132] The second semiconductor layer C2 and the third gate electrode G3 both extend in a direction perpendicular to the substrate 10; the second semiconductor layer C2 at least partially surrounds the third gate electrode G3;
[0133] The third electrode P3 and the fourth electrode P4 are distributed at intervals along a direction perpendicular to the substrate 10, and both the third electrode P3 and the fourth electrode P4 are located on at least one side of the second semiconductor layer C2.
[0134] The third electrode P3 is connected to the second gate electrode G2 located in the same memory cell.
[0135] In some embodiments of this application, as shown in Figures 2B and 2C, the second semiconductor layer C2 can be a cylindrical shape closed at one end. The third electrode P3 is located on the side of the closed end of the second semiconductor layer C2 near the substrate 10, and the fourth electrode P4 is located on the sidewall of the second semiconductor layer C2, possibly surrounding the sidewall of the second semiconductor layer C2. In other embodiments, the third electrode P3 may surround the end face of the closed end of the second semiconductor layer C2 and at least part of the sidewall, and the fourth electrode P4 may be located only on one sidewall of the second semiconductor layer C2.
[0136] In some embodiments of this application, the storage unit further includes a storage node SN, and the storage node SN, the second gate electrode G2 and the third electrode P3 located in the same storage unit are an integral structure.
[0137] In some embodiments of this application, the semiconductor device further includes a read word line RWL, a read bit line RBL, a source line SL, a write word line WWL, and a write bit line WBL;
[0138] The read word line RWL extends along the column direction and is connected to the first gate electrode G1 of a column of memory cells spaced apart along the column direction; and / or,
[0139] The read bit line RBL extends along the row direction and is connected to the first electrode P1 of a row of memory cells spaced apart along the row direction; and / or,
[0140] The source line SL extends along the row direction and is connected to the second electrode P2 of a row of memory cells spaced apart along the row direction; and / or,
[0141] The write line WWL extends along the column direction and is connected to the third gate electrode G3 of a column of memory cells spaced apart along the column direction; and / or,
[0142] The write bit line WBL extends along the row direction and is connected to the fourth electrode P4 of a row of memory cells spaced apart along the row direction.
[0143] In this application, the first semiconductor layer and the second semiconductor layer can be understood as semiconductor materials, and their shape and structure are not emphasized, but only their function.
[0144] For example, the materials of the first semiconductor layer and the second semiconductor layer can each be independently silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or wide band gap materials, such as metal oxide materials with a band gap of greater than 1.65 eV.
[0145] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.
[0146] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.
[0147] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.
[0148] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.
[0149] In some embodiments of this application, the materials of the read bit line and the write bit line can be independently selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).
[0150] In some embodiments of this application, the materials of the reading lines and writing lines can each be independently selected from any one or more of the following different types of materials:
[0151] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.
[0152] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.
[0153] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.
[0154] In some embodiments of this application, the gate insulating layer may independently comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.
[0155] Low-K materials, such as silicon oxide.
[0156] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.
[0157] This application also provides a method for manufacturing a semiconductor device. The semiconductor device described above can be obtained by this method.
[0158] Figure 4 is a process flow diagram of a semiconductor device manufacturing method according to an exemplary embodiment of this application. As shown in Figure 4, the manufacturing method includes:
[0159] A first gate electrode, a first electrode, and a second electrode are sequentially formed on one side of the substrate and are stacked and spaced apart.
[0160] The second electrode and the first electrode are etched along the direction toward the substrate to form a first through hole through the second electrode and the first electrode, wherein the first through hole does not expose the first gate electrode;
[0161] A first semiconductor layer and a sacrificial layer are sequentially formed on the sidewall of the first via;
[0162] The bottom of the first through hole is etched to extend the first through hole into the interior of the first gate electrode;
[0163] Remove the sacrificial layer from the sidewall of the first through hole;
[0164] A gate insulating layer and a second gate electrode are sequentially formed on the inner wall of the first through hole.
[0165] In some embodiments of this application, the step of sequentially forming a first gate electrode, a first electrode, and a second electrode stacked and spaced apart on one side of the substrate includes:
[0166] An insulating layer and a gate electrode layer are sequentially formed on one side of the substrate;
[0167] The gate electrode layer is patterned and etched, and the patterned gate electrode layer includes multiple read lines spaced apart along a row direction parallel to the substrate and extending along a column direction parallel to the substrate; each read line includes multiple first gate electrodes distributed along the column direction;
[0168] An insulating layer and a first electrode layer covering the patterned gate electrode layer are sequentially formed on the substrate surface;
[0169] The first electrode layer is patterned and etched, and the patterned first electrode layer includes multiple read lines extending along the row direction and spaced apart along the column direction; each read line includes multiple first electrodes distributed along the row direction.
[0170] An insulating layer and a second electrode layer covering the patterned first electrode layer are sequentially formed on the substrate surface;
[0171] The second electrode layer is patterned by etching, and the patterned second electrode layer includes multiple source lines extending along the row direction and spaced apart along the column direction; each source line includes multiple second electrodes distributed along the row direction.
[0172] In some embodiments of this application, etching the second electrode and the first electrode along a direction toward the substrate to form a first via through the second electrode and the first electrode, wherein the first via does not expose the first gate electrode, includes:
[0173] The second electrode and the first electrode, as well as the insulating layer between them, are etched along the direction toward the substrate to form a first via through the second electrode and the first electrode, as well as the insulating layer between them. The first via exposes the insulating layer between the first gate electrode and the first electrode. The width of the first via in the row direction is smaller than the width of the first gate electrode in the row direction.
[0174] In some embodiments of this application, the manufacturing method further includes: after forming the second gate electrode,
[0175] A fourth electrode is formed on the side of the second gate electrode away from the substrate, stacked with and spaced apart from the second gate electrode;
[0176] The fourth electrode is etched along the direction toward the substrate to form a second through-hole through the fourth electrode, the second through-hole exposing the second gate electrode;
[0177] A second semiconductor layer, a gate insulating layer, and a third gate electrode are sequentially formed within the second via.
[0178] A writing line connected to the third gate electrode is formed on the side of the third gate electrode away from the substrate.
[0179] In some embodiments of this application, forming a fourth electrode stacked and spaced apart from the second gate electrode on the side of the second gate electrode away from the substrate; and etching the fourth electrode along a direction toward the substrate to form a second through-hole through the fourth electrode, includes:
[0180] An insulating layer and a third electrode layer covering the second gate electrode are sequentially formed on the substrate surface;
[0181] The third electrode layer is patterned and etched, and the patterned third electrode layer includes multiple write bit lines extending along a row direction parallel to the substrate and spaced apart along a column direction parallel to the substrate; each write bit line includes multiple fourth electrodes distributed along the row direction.
[0182] An insulating layer covering the patterned third electrode layer is formed on the substrate surface;
[0183] The fourth electrode and the insulating layers on both sides are etched along the direction toward the substrate to form a second via through the fourth electrode and the insulating layers on both sides, the second via exposing the second gate electrode.
[0184] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes film coating, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.
[0185] As shown in Figures 5A to 12C, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.
[0186] S10: A first gate electrode G1 is formed on one side of the substrate 10.
[0187] For example, step S10 may include:
[0188] S11: An insulating layer 11 and a gate electrode layer are sequentially formed on one side of the substrate 10;
[0189] S12: The gate electrode layer is patterned and etched. The patterned gate electrode layer includes multiple read word lines RWL that are spaced apart along the row direction parallel to the substrate 10 and extend along the column direction parallel to the substrate 10. Each read word line RWL includes multiple first gate electrodes G1 that are distributed along the column direction.
[0190] S13: An insulating layer 11 covering the patterned gate electrode layer is deposited on the surface of the substrate 10, and the insulating layer 11 is planarized as shown in Figures 5A to 5C.
[0191] In this application, the row direction intersects the column direction; for example, the row direction and the column direction can be perpendicular to each other. For example, the row direction can be the aa' direction as shown in Figure 5A; the column direction can be the bb' direction as shown in Figure 5A.
[0192] S20: A first electrode P1 and a second electrode P2 are sequentially stacked and spaced apart on the surface of the substrate 10.
[0193] For example, step S20 may include:
[0194] S21: A first electrode layer is deposited on the surface of substrate 10;
[0195] S22: The first electrode layer is patterned and etched. The patterned first electrode layer includes multiple read lines RBL that extend along the row direction and are spaced apart along the column direction. Each read line RBL includes multiple first electrodes P1 that are distributed along the row direction.
[0196] S23: An insulating layer 11 and a second electrode layer covering the patterned first electrode layer are sequentially formed on the surface of the substrate 10;
[0197] S24: The second electrode layer is patterned and etched, the patterned second electrode layer including multiple source lines SL extending along the row direction and spaced apart along the column direction; each source line SL includes multiple second electrodes P2 distributed along the row direction;
[0198] S25: Deposit an insulating layer 11 on the surface of the substrate 10 and planarize the insulating layer 11 on the surface until the source line SL is exposed, as shown in Figures 6A to 6C.
[0199] As shown in Figures 6B and 6C, the read bit line RBL and the source line SL can be aligned vertically in a one-to-one correspondence.
[0200] S30: Etch the second electrode P2 and the first electrode P1 along the direction toward the substrate 10 to form a first through hole K1 that passes through the second electrode P2 and the first electrode P1. The first through hole K1 does not expose the first gate electrode G1.
[0201] For example, step S30 may include:
[0202] S31: A hard mask HM is formed on the surface of the substrate 10;
[0203] S32: Etch the hard mask HM, the second electrode P2, the first electrode P1, and the insulating layer 11 between them along the direction toward the substrate 10 to form a first via K1 that penetrates the hard mask HM, the second electrode P2, the first electrode P1, and the insulating layer 11 between them. The first via K1 exposes the insulating layer 11 between the first gate electrode G1 and the first electrode P1, that is, the first via K1 does not expose the first gate electrode G1, as shown in Figures 7A to 7C. Among them, the cross-section in Figure 7A passes through the second electrode P2.
[0204] As shown in Figures 7A to 7C, a first through hole K1 passes through a second electrode P2 and a first electrode P1, and the first through hole K1 is located above a first gate electrode G1.
[0205] As shown in Figures 7A and 7B, the width of the first through hole K1 in the row direction is smaller than the width of the first gate electrode G1 in the row direction.
[0206] S40: A first semiconductor layer C1 and a sacrificial layer 12 are sequentially formed on the sidewall of the first via K1.
[0207] For example, step S40 may include:
[0208] S41: Sequentially deposit a first semiconductor layer C1 and a sacrificial layer 12 on the surface of substrate 10, covering the inner wall (including the sidewall and bottom wall) of the first via K1 and the hard mask HM on the surface of substrate 10.
[0209] S42: Remove the bottom wall of the first via K1 and the first semiconductor layer C1 and sacrificial layer 12 on the hard mask HM by etching, such as dry etching, as shown in Figures 8A to 8C. The cross-section in Figure 8A passes through the second electrode P2.
[0210] For example, the material of the sacrificial layer 12 can be polysilicon, aluminum oxide, etc. The sacrificial layer 12 can protect the first semiconductor layer C1 from damage when the bottom of the first via K1 is subsequently etched.
[0211] S50: Etch the bottom of the first through hole K1, for example, by dry etching, so that the first through hole K1 extends into the interior of the first gate electrode G1.
[0212] S60: Remove the sacrificial layer 12 from the sidewall of the first through-hole K1, as shown in Figures 9A to 9C. The cross-section in Figure 9A passes through the first gate electrode G1.
[0213] As shown in Figures 9B and 9C, the diameter of the first through hole K1 located in the first gate electrode G1 is smaller than the diameter of the first through hole K1 located above the first gate electrode G1.
[0214] S70: A gate insulating layer 20 and a second gate electrode G2 are sequentially formed on the inner wall of the first through hole K1, as shown in Figures 10A to 10C. The cross-section in Figure 10A passes through the first gate electrode G1.
[0215] For example, step S70 may include:
[0216] S71: Deposit a gate insulating layer 20 and a gate electrode layer on the surface of substrate 10 that cover the inner wall of the first via K1 and the hard mask HM on the surface of substrate 10.
[0217] S72: By etching away the gate insulating layer 20 and the gate electrode layer on the hard mask HM, the gate insulating layer 20 and the gate electrode layer in each first via K1 are disconnected, resulting in a spaced gate insulating layer 20 and a second gate electrode G2.
[0218] S73: An insulating layer 11 is deposited on the surface of the substrate 10 to cover each of the second gate electrodes G2, as shown in Figures 10A to 10C. In Figure 10A, the cross-section passes through the first gate electrode G1.
[0219] S80: A fourth electrode P4 is formed on the side of the second gate electrode G2 away from the substrate, stacked with and spaced apart from the second gate electrode.
[0220] For example, step S80 may include:
[0221] S81: An insulating layer 11 and a third electrode layer covering the second gate electrode G2 are sequentially formed on the surface of the substrate 10;
[0222] S82: The third electrode layer is patterned and etched. The patterned third electrode layer includes multiple write bit lines WBL that extend along the row direction and are spaced apart along the column direction. Each write bit line WBL includes multiple fourth electrodes P4 that are distributed along the row direction.
[0223] S83: An insulating layer 11 is deposited on the surface of the substrate 10 and the insulating layer 11 on the surface is planarized to expose the fourth electrode P4, as shown in Figures 11A to 11C.
[0224] S90: The fourth electrode P4 is etched along the direction toward the substrate 10 to form a second through hole K2 through the fourth electrode P4, and the second through hole K2 exposes the second gate electrode G2; the second semiconductor layer C2, the gate insulating layer 20 and the third gate electrode G3 are formed sequentially in the second through hole K2.
[0225] For example, step S90 may include:
[0226] S91: An insulating layer 11 covering the patterned third electrode layer is formed on the surface of the substrate 10;
[0227] S92: The fourth electrode P4 and the insulating layer 11 on both sides are etched along the direction toward the substrate 10 to form a second through hole K2 that penetrates the fourth electrode P4 and the insulating layer 11 on both sides, and the second through hole K2 exposes the second gate electrode G2.
[0228] S93: A second semiconductor layer C2, a gate insulating layer 20, and a third gate electrode G3 are sequentially formed within the second via K2, as shown in Figures 12A to 12C. The cross-section in Figure 12A passes through the fourth electrode P4.
[0229] S100: A write line WWL connected to the third gate electrode G3 is formed on the side of the third gate electrode G3 away from the substrate 10. An insulating layer 11 is deposited on the surface of the substrate 10 and planarized, as shown in Figures 2A to 2C.
[0230] This application also provides an electronic device, which includes the transistor or semiconductor device described above, or a semiconductor device obtained by the manufacturing method described above.
[0231] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0232] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A transistor, comprising: The first electrode, the second electrode, the first semiconductor layer, the first gate electrode, the second gate electrode, and the gate insulating layer are located on the substrate; The first gate electrode, the first electrode, and the second electrode are spaced apart along a direction perpendicular to the substrate; the first semiconductor layer and the second gate electrode both extend along a direction perpendicular to the substrate; the first electrode and the second electrode are located on the sidewall of the first semiconductor layer; One end of the second gate electrode is at least partially surrounded by the first gate electrode; The first semiconductor layer is insulated from the second gate electrode, and the first gate electrode is insulated from the second gate electrode by the gate insulating layer.
2. The transistor according to claim 1, wherein, At least a portion of the end face of the second gate electrode and the sidewall connected to the end face are surrounded by the first gate electrode.
3. The transistor according to claim 1 or 2, wherein, The second gate electrode has a first end close to the substrate and a second end away from the substrate; the end face of the first end is completely surrounded by the first gate electrode, and the four sidewalls of the first end connected to the end face are completely surrounded by the first gate electrode.
4. The transistor according to any one of claims 1 to 3, wherein, The first gate electrode has a through hole that is closed at one end and open at the other end, and the first end of the second gate electrode extends into the through hole through the opening.
5. The transistor according to any one of claims 1 to 4, wherein, The first electrode at least partially surrounds the first semiconductor layer and the second gate electrode; and / or, The second electrode at least partially surrounds the first semiconductor layer and the second gate electrode.
6. The transistor according to any one of claims 1 to 5, wherein, The first semiconductor layer at least partially surrounds the second gate electrode.
7. A semiconductor device, comprising: Multiple memory cells located on the substrate; The plurality of storage cells are arranged in an array and spaced apart on the substrate along row and column directions parallel to the substrate; The storage cell includes read transistors and write transistors stacked along a direction perpendicular to the substrate; the read transistors are transistors according to any one of claims 1 to 6.
8. The semiconductor device according to claim 7, wherein, The write transistor includes a third electrode, a fourth electrode, a second semiconductor layer, and a third gate electrode, wherein the second semiconductor layer and the third gate electrode are insulated from each other by the gate insulating layer; Both the second semiconductor layer and the third gate electrode extend in a direction perpendicular to the substrate; the second semiconductor layer at least partially surrounds the third gate electrode. The third electrode and the fourth electrode are spaced apart along a direction perpendicular to the substrate, and both the third electrode and the fourth electrode are located on at least one side of the second semiconductor layer; the third electrode is connected to the second gate electrode located in the same memory cell.
9. The semiconductor device according to claim 8, wherein, The storage unit also includes a storage node, and the storage node, the second gate electrode and the third electrode located in the same storage unit are an integral structure.
10. The semiconductor device according to claim 8 or 9, further comprising read word lines, read bit lines, source lines, write word lines, and write bit lines; The read line extends along the column direction and is connected to the first gate electrode of a column of memory cells spaced apart along the column direction; and / or, The read bit line extends along the row direction and is connected to the first electrode of a row of memory cells spaced apart along the row direction; and / or, The source line extends along the row direction and is connected to the second electrode of a row of memory cells spaced apart along the row direction; and / or, The write line extends along the column direction and is connected to the third gate electrode of a column of memory cells spaced apart along the column direction; and / or, The write bit line extends along the row direction and is connected to the fourth electrode of a row of memory cells spaced apart along the row direction.
11. A method for manufacturing a semiconductor device, comprising: A first gate electrode, a first electrode, and a second electrode are sequentially formed on one side of the substrate and are stacked and spaced apart. The second electrode and the first electrode are etched along the direction toward the substrate to form a first through hole through the second electrode and the first electrode, wherein the first through hole does not expose the first gate electrode; A first semiconductor layer and a sacrificial layer are sequentially formed on the sidewall of the first via; The bottom of the first through hole is etched to extend the first through hole into the interior of the first gate electrode; Remove the sacrificial layer from the sidewall of the first through hole; A gate insulating layer and a second gate electrode are sequentially formed on the inner wall of the first through hole.
12. The manufacturing method according to claim 11, wherein, The first gate electrode, the first electrode, and the second electrode, which are sequentially stacked and spaced apart on one side of the substrate, include: An insulating layer and a gate electrode layer are sequentially formed on one side of the substrate; The gate electrode layer is patterned and etched, and the patterned gate electrode layer includes multiple read lines spaced apart along a row direction parallel to the substrate and extending along a column direction parallel to the substrate; each read line includes multiple first gate electrodes distributed along the column direction; An insulating layer and a first electrode layer covering the patterned gate electrode layer are sequentially formed on the substrate surface; The first electrode layer is patterned and etched, and the patterned first electrode layer includes multiple read lines extending along the row direction and spaced apart along the column direction; each read line includes multiple first electrodes distributed along the row direction. An insulating layer and a second electrode layer covering the patterned first electrode layer are sequentially formed on the substrate surface; The second electrode layer is patterned by etching, and the patterned second electrode layer includes multiple source lines extending along the row direction and spaced apart along the column direction; each source line includes multiple second electrodes distributed along the row direction.
13. The manufacturing method according to claim 12, wherein, The etching of the second electrode and the first electrode along a direction toward the substrate to form a first through-hole penetrating the second electrode and the first electrode, wherein the first through-hole does not expose the first gate electrode, includes: The second electrode and the first electrode, as well as the insulating layer between them, are etched along the direction toward the substrate to form a first via through the second electrode and the first electrode, as well as the insulating layer between them. The first via exposes the insulating layer between the first gate electrode and the first electrode. The width of the first via in the row direction is smaller than the width of the first gate electrode in the row direction.
14. The manufacturing method according to any one of claims 11 to 13, further comprising: After the second gate electrode is formed A fourth electrode is formed on the side of the second gate electrode away from the substrate, stacked with and spaced apart from the second gate electrode; The fourth electrode is etched along the direction toward the substrate to form a second through-hole through the fourth electrode, the second through-hole exposing the second gate electrode; A second semiconductor layer, a gate insulating layer, and a third gate electrode are sequentially formed within the second via. A writing line connected to the third gate electrode is formed on the side of the third gate electrode away from the substrate.
15. The manufacturing method according to claim 14, wherein, A fourth electrode is formed on the side of the second gate electrode away from the substrate, stacked with and spaced apart from the second gate electrode; Etching the fourth electrode along a direction toward the substrate to form a second through-hole penetrating the fourth electrode includes: An insulating layer and a third electrode layer covering the second gate electrode are sequentially formed on the substrate surface; The third electrode layer is patterned and etched, and the patterned third electrode layer includes multiple write bit lines extending along a row direction parallel to the substrate and spaced apart along a column direction parallel to the substrate; each write bit line includes multiple fourth electrodes distributed along the row direction. An insulating layer covering the patterned third electrode layer is formed on the substrate surface; The fourth electrode and the insulating layers on both sides are etched along the direction toward the substrate to form a second via through the fourth electrode and the insulating layers on both sides, the second via exposing the second gate electrode.
16. An electronic device comprising a transistor according to any one of claims 1 to 6, or comprising a semiconductor device according to any one of claims 7 to 10, or comprising a semiconductor device obtained by the manufacturing method according to any one of claims 11 to 15.