Semiconductor device, manufacturing method therefor, and electronic device

Abstract

The embodiments of the present disclosure provide a semiconductor device, a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one stacked unit, each stacked unit comprising: interlayer dielectric layers and memory layers alternately stacked in a vertical direction, each memory layer comprising: a semiconductor layer and a gate of a transistor, and a first electrode of a capacitor, the semiconductor layer and the gate being arranged side by side in a first direction, and the first electrode being coupled to one end of the semiconductor layer in a second direction; the first direction and the second direction intersect one another and are both perpendicular to the vertical direction; the second electrode extends in the vertical direction and passes through the plurality of interlayer dielectric layers and the first electrode in each memory layer, and a capacitor dielectric layer is provided between the second electrode and each first electrode; and a bit line extends in the vertical direction and is coupled to the other end of the semiconductor layer in each memory layer in the second direction.

Description

Semiconductor devices, their manufacturing methods and electronic devices

[0001] Cross-reference to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202510199204.0, filed on February 21, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices, methods of manufacturing the same, and electronic devices. Background Technology

[0004] The development of application markets such as the Internet of Things (IoT), artificial intelligence (AI), and smart cities has significantly increased the application demand for massive computing architectures. Massive computing architectures process massive amounts of data, placing higher demands on memory performance. Among mainstream memory technologies, Random Access Memory (RAM) is characterized by its high speed and ability to be read and written at any time, making it suitable for storing frequently accessed data or data currently being processed. The development of big data has placed even higher demands on RAM. Three-dimensional architectures can increase RAM's storage capacity and represent a major direction for future RAM development. Summary of the Invention

[0005] According to a first aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: at least one stacking unit, each of the stacking units comprising:

[0006] Alternating interlayer dielectric layers and memory layers stacked vertically, each memory layer comprising: a semiconductor layer and a gate of a transistor, and a first electrode of a capacitor, the semiconductor layer and the gate being arranged side by side along a first direction, the first electrode being coupled to one end of the semiconductor layer along a second direction; the first direction and the second direction intersect and are both perpendicular to the vertical direction;

[0007] The second electrode extends along the vertical direction and passes through the interlayer dielectric layers and the first electrode in each of the memory layers, with a capacitor dielectric layer provided between the second electrode and each of the first electrodes;

[0008] Bit lines extend along the vertical direction and are coupled to the other end of the semiconductor layer in each memory layer along the second direction.

[0009] According to a second aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising:

[0010] An initial stacking cell and an isolation layer surrounding the initial stacking cell are formed on a substrate. The initial stacking cell includes a support layer and an initial semiconductor layer that are alternately stacked in a vertical direction.

[0011] On the first side of the initial stacked cell, a first hole is formed extending along the vertical direction to expose each of the initial semiconductor layers, and a bit line is formed within the first hole;

[0012] On the second side opposite to the first side, a second hole is formed extending in the vertical direction to expose each of the initial semiconductor layers. Each of the initial semiconductor layers is laterally etched within the second hole to form a first groove within each of the initial semiconductor layers.

[0013] A first electrode is formed in each of the first grooves, a capacitor dielectric layer is formed on the sidewall of the first electrode, and a second electrode is formed in the second hole that contacts the capacitor dielectric layer.

[0014] On the third and / or fourth side of the initial stacked cell, trenches are formed extending along the vertical direction to expose each of the initial semiconductor layers; the third and fourth sides are disposed opposite each other along a first direction, the first and second sides are disposed opposite each other along a second direction, the first and second directions intersect and are both perpendicular to the vertical direction;

[0015] Each initial semiconductor layer is laterally etched within the trench to form a second groove within each initial semiconductor layer, and a gate dielectric layer and a gate are sequentially formed within each second groove.

[0016] According to a third aspect of this disclosure, an electronic device is provided, including the semiconductor device described above, and / or a semiconductor device formed by the manufacturing method of the semiconductor device described above. Attached Figure Description

[0017] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0018] Figures 2a to 2d are multiple cross-sectional schematic diagrams of the semiconductor device shown in Figure 1.

[0019] Figure 3 is a schematic diagram of the structure of the semiconductor device provided in the embodiment of this disclosure.

[0020] Figure 4 is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure.

[0021] Figure 5 is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure.

[0022] Figure 6 is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure.

[0023] Figure 7 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0024] Figure 8 is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure.

[0025] Figure 9 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0026] Figure 10 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0027] Figure 11 is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this disclosure.

[0028] Figures 12 to 26d are schematic diagrams of the structure of a semiconductor device during the manufacturing process according to an embodiment of this disclosure. Detailed Implementation

[0029] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0030] Where possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. It is obvious that the aspects described are only some, and not all, of the aspects of this disclosure. Features in the various aspects may be interchanged and / or combined.

[0031] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0032] As the manufacturing process of 2D DRAM (Dynamic Random Access Memory) approaches its limits, 3D DRAM architecture represents the main direction for future DRAM development. Currently, 3D DRAM primarily employs a vertical gate structure. Since bit lines and word lines are typically perpendicular, in semiconductor devices using a vertical gate structure, bit lines extend horizontally, and the bit lines coupled to multiple vertically stacked memory cells also stack vertically. This results in small spacing between adjacent bit lines and significant coupling. Currently, the severe bit line coupling in vertical gate 3D DRAM poses a significant challenge to the future development of 3D DRAM, leading to circuit load problems.

[0033] In view of this, the present disclosure provides a semiconductor device. FIG1 is a schematic diagram of the semiconductor device provided in the present disclosure, and FIG2a to FIG2d are cross-sectional schematic diagrams of the semiconductor device shown in FIG1 along lines aa′, bb′, cc′ and dd′, respectively. As shown in FIG1 and FIG2a to FIG2d, the semiconductor device includes: at least one stacking unit 110, each stacking unit 110 including: interlayer dielectric layers 111 and memory layers alternately stacked in a vertical direction, each memory layer including: semiconductor layer 210 and gate 230 of a transistor, and a first electrode 310 of a capacitor. The semiconductor layer 210 and the gate 230 are arranged side by side in a first direction, and the first electrode 310 is coupled to one end of the semiconductor layer 210 in a second direction; the first direction and the second direction intersect and are both perpendicular to the vertical direction. A second electrode 320 extends in a vertical direction and passes through the multiple interlayer dielectric layers 111 and the first electrode 310 in each memory layer. A capacitor dielectric layer 330 is provided between the second electrode 320 and each first electrode 310. Bit line 410 extends vertically and is coupled to the other end of semiconductor layer 210 in each memory layer along the second direction.

[0034] This embodiment is illustrated by taking the example where the first direction and the second direction are perpendicular to each other. For example, the vertical direction is the Z direction, the first direction is the X direction, and the second direction is the Y direction. In other embodiments, the first direction and the second direction may intersect but not be perpendicular.

[0035] As shown in Figures 2a to 2d, the stacked unit 110 includes interlayer dielectric layers 111 and memory layers alternately stacked along the vertical direction (Z direction). Each memory layer is used to form a memory cell, and the interlayer dielectric layers 111 are used to isolate adjacent memory cells along the vertical direction (Z direction). Each memory cell includes a transistor and a capacitor. As shown in Figures 1 and 2b, the transistor includes a semiconductor layer 210 and a gate 230 disposed side-by-side along a first direction (X direction) in the memory layer, with a gate dielectric layer 220 disposed between the semiconductor layer 210 and the gate 230. The semiconductor layer 210 includes a channel region disposed opposite to the gate 230 through the gate dielectric layer 220, and the channel region extends along a second direction (Y direction).

[0036] For example, the semiconductor layer can be made of semiconductor materials such as silicon, germanium, and gallium arsenide (GaAs), or metal oxide materials such as IGZO (indium gallium zinc oxide), ITO (indium tin oxide), and ITZO (indium tin zinc oxide). In this embodiment, the semiconductor layer is made of a single-crystal semiconductor, such as single-crystal silicon.

[0037] The first electrode 310 of the capacitor is located in the memory layer and is coupled to one end of the semiconductor layer 210 along the second direction (Y direction). This coupling includes both contact connection and non-contact connection. In other words, the first electrode 310 can be directly contacted to one end of the semiconductor layer 210 along the second direction, or the first electrode 310 can be non-contactly connected to the semiconductor layer 210 through other conductive structures or semiconductor structures.

[0038] All memory cells in the stacked cell share a second electrode 320, which is located in the stacked cell in the form of a second electrode post. As shown in FIG2c, the second electrode post extends vertically (Z direction) and passes through the first electrode 310 in each memory layer, wherein the portion of the second electrode post in each memory layer serves as the second electrode layer of the capacitor in the corresponding memory cell of that memory layer. In other words, the second electrode layers of all memory cells in the stacked cell are interconnected. A capacitor dielectric layer 330 is provided between the second electrode 320 and the first electrode 310 of each memory layer to isolate the first electrode 310 and the second electrode 320.

[0039] As shown in Figures 1 and 2a, the bit line 410 extends vertically and is coupled to the other end of the semiconductor layer 210 in each memory layer along the second direction (Y direction). For example, the bit line 410 can be directly connected to the semiconductor layer 210, or it can be non-contactly connected to the semiconductor layer 210 through other conductive or semiconductor structures.

[0040] As shown in Figure 1, bit line 410 and capacitor are located on opposite sides of the channel region along the second direction (Y direction). The voltage signal on the transistor gate 230 controls the transistor to turn on or off. During data writing, when the transistor is on, bit line 410 can share charge with the first electrode 310 of the capacitor through the channel region, thereby writing data into the capacitor. When the transistor is off, the capacitor stores data. During data reading, when the transistor is on, the first electrode 310 of the capacitor can share charge with bit line 410 through the channel region, thereby reading the data from the capacitor.

[0041] This embodiment provides a semiconductor device including at least one stacked cell. Each stacked cell includes multiple memory cells stacked vertically and coupled to the same bit line. The gate of each memory cell extends horizontally. On one hand, the semiconductor device provided by this embodiment increases the number of memory cells per unit area, thereby increasing the storage density of the semiconductor device and leveraging its miniaturization. On the other hand, the vertical bit line structure within each stacked cell ensures that only one memory cell is opened during a read operation, rather than multiple memory cells being opened simultaneously. Therefore, there is no bit line coupling within the stacked cell. Furthermore, the layout of the multiple stacked cells is more flexible, making it easier to increase the distance between bit lines in adjacent stacked cells, reducing the coupling between bit lines in adjacent stacked cells, thereby significantly reducing the coupling between bit lines within the semiconductor device and thus reducing the circuit load.

[0042] In some embodiments, as shown in FIG1, the semiconductor layer 210 includes a first region A, a second region B, and a third region C sequentially disposed along a second direction (Y direction). The second region B is disposed opposite to the gate 230 through the gate dielectric layer 220, and the second region B is used to form a channel region. The first region A is used to form the source, and the third region C is used to form the drain.

[0043] For example, the width W2 of the second region B along the first direction is less than the width W1 of the first region A along the first direction, and less than the width W3 of the third region C along the first direction.

[0044] In some embodiments, as shown in FIG1, the width W2 of the second region B along the first direction is smaller than the width W1 of the first region A along the first direction, and smaller than the width W3 of the third region C along the first direction. Furthermore, the sides of the first region A, the second region B, and the third region C near the gate 230 are flush with each other, making the semiconductor layer 210 approximately "U"-shaped. In this structure, the relative areas of the gate 230 with the first region A and the third region C are small, thereby reducing the relative areas of the gate with the source and drain, and lowering the gate-induced drain leakage (GIDL) current.

[0045] Furthermore, the second region B can also be located at any other position between the first region A and the third region C. Figure 3 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. In some embodiments, as shown in Figure 3, the center lines of the second region B and the first region A and the third region C are substantially aligned, making the semiconductor layer 210 approximately "I"-shaped. In this way, the gate 230 extends into the semiconductor layer 210, which can reduce the size of the memory cell along the first direction, thus facilitating the provision of storage density per unit area.

[0046] Figure 4 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. In some other embodiments, as shown in Figure 4, the width W2 of the second region B along the first direction may also be equal to the width W1 of the first region A along the first direction and the width W3 of the third region C along the first direction. In practical applications, the width W1 of the first region A, the width W2 of the second region B, and the width W3 of the third region C can be adjusted according to different requirements for transistor performance.

[0047] In some embodiments, the bit line may pass through a first region A of the semiconductor layer in each memory layer. That is, the first aperture used to form the bit line during manufacturing passes through the semiconductor layer.

[0048] Figure 5 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. As shown in Figure 5, the bit line 410 passes through the first region A of the semiconductor layer 210 and is surrounded by the semiconductor layer 210. For example, the bit line 410 can directly contact the first region A of the semiconductor layer 210, which serves as the source of a transistor. The composition of the first region is the same as that of the second region, used to form a junctionless transistor. For example, the composition of both the first region A and the second region B is intrinsic semiconductor or both are metal oxides such as ITO, ITZO, or IGZO.

[0049] Figure 6 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. As shown in Figure 6, the first region A may further include a source doped region 260, which contacts the bit line 410 and the second region B. The source doped region 260 is used to form the source of the transistor. Compared to the junctionless transistor in Figure 5, in this embodiment, the use of a doped region to form the source reduces the contact resistance between the bit line and the source, reduces the resistance to current transmission, and thus improves the conductivity and response speed of the transistor. Furthermore, the source doped region can make the electric field between the drain and the source more uniform, avoiding or reducing the probability of breakdown and device damage caused by excessively high local electric fields.

[0050] As shown in Figure 6, the source doped region 260 can be arranged around the bit line 410 to increase the contact area between the bit line 410 and the source doped region 260, thereby further reducing the contact resistance. For example, the first region A can be completely doped to form the source doped region 260.

[0051] The type of dopant ions in the source doping region 260 can be either P-type or N-type, and this disclosure does not limit this. In this embodiment, the dopant ions in the source doping region 260 are N-type dopant ions to form an NMOS transistor. The N-type dopant ion can be a phosphorus ion (P).

[0052] In some embodiments, referring back to FIG1 and FIG2a, the semiconductor device may further include: a source layer 240 disposed around the sidewall of the bit line 410, the source layer 240 extending in a vertical direction and penetrating a first region A of a plurality of interlayer dielectric layers 111 and a semiconductor layer 210 in each memory layer, the source layer 240 being in contact with the first region A.

[0053] In this embodiment, the source layer 240 surrounds the entire sidewall of the bit line 410, wherein the portion of the source layer 240 located in each memory layer is used to form the source of a transistor. The material of the source layer can be a doped semiconductor, such as doped silicon, doped germanium, or doped silicon-germanium. The source layer can be formed by a deposition process. Compared to the source doped region formed by doping shown in Figure 6, in this embodiment, the concentration of doped ions in the source layer formed by the deposition process is more uniform, resulting in better consistency of the source of each transistor, and thus better transistor consistency, which is beneficial to improving the accuracy of data read and write. In addition, as shown in Figure 6, the source layer 240 can also surround the bottom of the bit line 410.

[0054] In some embodiments, in each memory layer, the first electrode passes through a third region of the semiconductor layer. That is, the first groove used to form the first electrode during the manufacturing process passes through the semiconductor layer.

[0055] Referring back to Figure 5, the first electrode 310 passes through the third region C of the semiconductor layer 210, and the first electrode 310 is surrounded by the semiconductor layer 210. The first electrode 310 can directly contact the third region C of the semiconductor layer 210, which serves as the drain of the transistor. The composition of the third region C is the same as that of the second region B, used to form a junctionless transistor. For example, the composition of both the third region C and the second region B is intrinsic semiconductor or both are metal oxides such as ITO, ITZO, and IGZO.

[0056] Referring back to Figure 6, for example, the third region C may include a drain-doped region 270, which contacts the first electrode 310 and the second region B. The drain-doped region 270 is used to form the drain of the transistor. Compared to the junctionless transistor in Figure 5, in this embodiment, using a doped region to form the drain reduces the contact resistance between the bit line and the drain, and makes the electric field between the drain and the source more uniform, which is beneficial to improving the performance of the transistor.

[0057] As shown in Figure 6, in each memory layer, the drain doped region 270 can be disposed around the first electrode 310 to increase the contact area between the first electrode 310 and the drain doped region 270, thereby further reducing the contact resistance. For example, the third region C can be entirely doped to form the drain doped region 270.

[0058] The type of doped ions in the drain doped region 270 is the same as that in the source doped region 260; both are either N-type or P-type doped ions. In this embodiment, the doped ions in the drain doped region 270 are also N-type doped ions, such as phosphorus ions (P).

[0059] In some embodiments, referring back to Figures 1 and 2c, each memory layer further includes a drain layer 250 disposed around the sidewall of the first electrode 310, the drain layer 250 passing through a third region C of the semiconductor layer in the same memory layer and in contact with the third region C.

[0060] In each memory layer, the drain layer 250 surrounds the entire sidewall of the first electrode 310 to increase the contact area between the drain layer 250 and the first electrode 310 and reduce the contact resistance. The material of the drain layer 250 can be a doped semiconductor, such as doped silicon, doped germanium, or doped silicon-germanium. The drain layer 250 can be formed by a deposition process, as detailed in the manufacturing method described later in this document. Compared to the drain doped region formed by doping shown in Figure 6, in this embodiment, the concentration of doped ions in the deposited drain layer is more uniform, resulting in better consistency of the drain of each transistor, which in turn improves the consistency of the transistor and enhances the accuracy of data read and write operations.

[0061] In some embodiments, as shown in Figures 1-2d, the semiconductor device further includes an isolation layer 500, which surrounds the stacked unit 110 and is used to isolate adjacent stacked units. The isolation layer is made of silicon oxide, doped silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (HfOx), or other low-k dielectric materials. Doped silicon oxide includes, but is not limited to, fluorine-doped silicon oxide and carbon-doped silicon oxide. In this embodiment, the isolation layer is made of spin-on insulating dielectric (SOD), and the spin-on insulating dielectric is composed of silicon oxide.

[0062] Figure 7 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. In some embodiments, as shown in Figure 7, the bit line 410 may also be configured to pass through the isolation layer 500 in a vertical direction instead of passing through the semiconductor layer 210. The sidewalls of the bit line 410 are surrounded by the source layer 240, which penetrates the isolation layer 500 and contacts the other end of the semiconductor layer 210 in each memory layer along a second direction.

[0063] It should be understood that in other embodiments, the source layer 240 may also be partially located within the isolation layer 500 and partially located within the interlayer dielectric layer 111 and the semiconductor layer 210.

[0064] In some embodiments, the capacitor dielectric layer includes a ferroelectric layer. The capacitor dielectric layer may consist only of a ferroelectric layer, or it may be a composite structure consisting of a ferroelectric layer and a dielectric layer stacked along a first direction. The ferroelectric layer may be a single layer formed of a single ferroelectric material, or it may be a multilayer composite ferroelectric layer formed by stacking multiple ferroelectric materials along the first direction. It should be understood that in other embodiments, the capacitor dielectric layer may also consist only of a dielectric layer, the material of which may include a high-k dielectric material. The capacitor dielectric layer may also include an antiferroelectric material.

[0065] The ferroelectric layer is made of ferroelectric materials, including but not limited to hafnium oxide-based ferroelectric materials and titanium-based ferroelectric materials with perovskite structures. Hafnium oxide-based ferroelectric materials include, but are not limited to, zirconium-doped hafnium oxide (HfZrO2) and lanthanum-doped hafnium oxide. Titanium-based ferroelectric materials include, but are not limited to, barium titanate (PZT) and strontium titanate.

[0066] When using a ferroelectric layer as the capacitor dielectric layer, during the data write operation, a turn-on voltage Vwl greater than the threshold voltage is applied to the gate of the transistor to turn it on. If data "1" is written to the memory cell, a power supply voltage Vcc (e.g., 1V) is applied to the bit line. The charge on the bit line is shared to the first electrode of the capacitor, causing the voltage at the first electrode to rise to the power supply voltage. Simultaneously, a reference voltage is applied to the second electrode, which is less than the power supply voltage but greater than the ground voltage. For example, the reference voltage is equal to half the power supply voltage. The power supply voltage at the first electrode is greater than the reference voltage at the second electrode, causing the ferroelectric material to form a first polarization state, thus writing the data "1".

[0067] If data "0" is written into a memory cell, a ground voltage (e.g., 0V) is applied to the bit line. The charge on the bit line is shared to the first electrode of the capacitor, adjusting the voltage of the first electrode to the ground voltage. At the same time, a reference voltage is applied to the second electrode. The ground voltage of the first electrode is less than the reference voltage of the second electrode, causing the ferroelectric material to form a second polarization state, and the data "0" is written.

[0068] During the data read operation, a reference voltage is applied to the bit line, a power supply voltage is applied to the second electrode of the capacitor, and then a turn-on voltage Vwl is applied to the gate of the transistor to turn it on. At this time, the voltage at the first electrode of the capacitor is the reference voltage, and the capacitor's two plates are energized. The capacitor will decide whether to switch its state or not based on its current polarization state. If the state switches, the voltage on the bit line will change significantly; if the state does not switch, the voltage change on the bit line will be small. By sensing the voltage change on the bit line using a sensing amplifier, the data in the memory cell can be read.

[0069] The semiconductor device that includes the ferroelectric layer is called ferroelectric RAM. Ferroelectric RAM is relatively simple to operate, and the polarization state of the ferroelectric layer remains unchanged after power is turned off, so the data will not be lost and it has the characteristics of non-volatility.

[0070] In some embodiments, the capacitor dielectric layer 330 may consist only of a ferroelectric layer. As shown in FIG2c, the ferroelectric layer (i.e., the capacitor dielectric layer 330) surrounds the entire sidewall of the second electrode 320, extending vertically and passing through multiple interlayer dielectric layers 111 and the first electrode 310 in each memory layer. That is, the ferroelectric layer is continuous in the vertical direction. The portion of the ferroelectric layer located in each memory layer constitutes the dielectric layer of the capacitor in a memory cell. This continuous ferroelectric layer configuration simplifies the manufacturing process.

[0071] In other embodiments, as shown in FIG8, the ferroelectric layer may include a plurality of sub-ferroelectric layers 331 spaced apart in a vertical direction. Each sub-ferroelectric layer 331 is located in a memory layer and passes through the first electrode 310 in the same memory layer and surrounds the sidewall of the second electrode 320. Adjacent sub-ferroelectric layers 331 in the vertical direction are isolated by an interlayer dielectric layer 111. That is, the ferroelectric layer is discontinuous in the vertical direction, and the sub-ferroelectric layers in the capacitors of different memory cells are isolated from each other. This arrangement reduces the coupling effect between the capacitors of adjacent memory cells, improving the reliability and accuracy of data read / write.

[0072] In some embodiments, each memory layer includes two gates belonging to the same transistor, the two gates being located on opposite sides of the semiconductor layer along a first direction, and a gate dielectric layer being provided between each gate and the semiconductor layer.

[0073] Figure 9 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. As shown in Figure 9, each transistor has two gates 230, and the two gates 230 are respectively located on both sides of the second region B of the semiconductor layer 210 along the first direction (X direction). The two gates 230 are arranged opposite to each other and jointly control the channel region, forming a dual-gate transistor. The dual-gate transistor has a higher current density in the channel region, a faster switching speed, and is beneficial for reducing leakage current, improving transistor performance, and thus improving storage performance. The dimensions of the two gates 230 along the second direction (Y direction) can be equal or unequal, and this disclosure does not limit this. In this embodiment, the dimensions of the two gates 230 along the second direction are equal to obtain substantially the same control capability over the channel region, achieve better electric field distribution, and improve transistor performance.

[0074] In some embodiments, as shown in FIG1, the semiconductor device includes a plurality of stacked cells 110 arranged side by side along a second direction (Y direction). The plurality of stacked cells 110 have the same orientation, that is, the semiconductor layer 210 and the gate 230 of each stacked cell are arranged side by side along a first direction (X direction), and the gate 230 of each stacked cell is located on the same side of the semiconductor layer 210. The memory layers of the plurality of stacked cells 110 are aligned with each other along the vertical direction (Z direction), and the interlayer dielectric layers 111 are aligned with each other along the vertical direction.

[0075] As shown in Figures 1 and 2d, the semiconductor device further includes: a plurality of word lines 420 stacked in a vertical direction, each word line 420 being located in the same memory layer of the plurality of stacked cells 110, and adjacent word lines 420 in the vertical direction being isolated by an interlayer dielectric layer 111. Each word line 420 extends in a second direction and is in contact with a gate 230 in the same memory layer of the plurality of stacked cells.

[0076] For example, word line 420 and gate 230 are integrated, that is, they are a single unit with no interface between word line 420 and gate 230, and are formed in one piece.

[0077] As shown in Figure 1, stacked cells can be selected via word lines, and then a specific memory cell can be selected from the stacked cells via bit lines, thus enabling read and write operations on any memory cell in the memory array. In this embodiment, word lines are set horizontally and bit lines are set vertically, forming a memory with a vertical bit line structure. This significantly reduces the parasitic capacitance between bit lines, thereby greatly improving the load in the circuit.

[0078] For example, multiple stacked cells arranged side-by-side along the second direction (Y direction) are called a column of stacked cells, and multiple word lines stacked vertically are called a group of word lines. When the transistor in the memory cell is a dual-gate transistor, as shown in Figure 9, a column of stacked cells 110 corresponds to two groups of word lines 420. The two groups of word lines 420 are located on both sides of the column of stacked cells 110 along the first direction (X direction). The two word lines 420 located in the same memory layer of the two groups of word lines 420 are respectively connected to the two gates 230 of the same transistor.

[0079] In some embodiments, the semiconductor device may include a stacked cell array comprising multiple columns of stacked cells spaced apart along a first direction. For example, each column of stacked cells has a third side and a fourth side opposite each other along the first direction. In the embodiment shown in FIG1, the word lines of odd-numbered columns of stacked cells are located on the third side of the stacked cells (e.g., the right side in FIG1), and the word lines of even-numbered columns of stacked cells are located on the fourth side of the stacked cells (e.g., the left side in FIG1), such that the word lines of two adjacent columns of stacked cells are located between or outside the two columns of stacked cells. This arrangement allows for the simultaneous formation of two adjacent sets of word lines, simplifying the manufacturing process.

[0080] As an example, as shown in FIG10, the word lines 420 of each column of stacking units 110 may also be located on the same side of the stacking units 110. For example, in FIG10, the word lines 420 are located on the left side of the stacking units, such that the stacking units 110 and the word lines 420 are alternately arranged along the first direction.

[0081] This disclosure uses an example of a stacked cell comprising five memory layers for illustration. However, the number of memory layers is not limited to five. A stacked cell may include more memory layers, such as 8, 10, or 12 layers, and this disclosure does not impose any limitations on this. The more memory layers a stacked cell includes, the higher the storage density of the semiconductor device, which is more conducive to device miniaturization.

[0082] The semiconductor device provided in this disclosure employs a vertical bit line structure, which can reduce parasitic capacitance between bit lines, thereby improving load issues in the circuit. Furthermore, the source and drain are arranged in a ring, while the gate is only opposite a small portion of the source and drain, effectively reducing gate-drain leakage current, improving transistor performance, and thus enhancing the device's storage performance.

[0083] It should be noted that the bit line and source structures, capacitor and drain structures, gate and word line structures, and ferroelectric layer structures provided in the above embodiments of this disclosure can be arbitrarily combined to obtain new implementation methods, and are not limited to the implementation methods provided in this disclosure.

[0084] This disclosure also provides a method for manufacturing a semiconductor device. Figure 11 is a schematic flowchart of the method for manufacturing a semiconductor device according to an embodiment of this disclosure. As shown in Figure 11, the manufacturing method includes:

[0085] S100: At least one initial stacking unit and an isolation layer surrounding the initial stacking unit are formed on a substrate; the initial stacking unit includes a support layer and an initial semiconductor layer that are alternately stacked in a vertical direction;

[0086] S200: On the first side of the initial stacked cell, a first hole is formed extending vertically to expose each initial semiconductor layer, and a bit line is formed in the first hole;

[0087] S300: On the second side opposite to the first side, a second hole is formed extending vertically to expose each initial semiconductor layer. Each initial semiconductor layer is laterally etched within the second hole to form a first groove within each initial semiconductor layer.

[0088] S400: A first electrode is formed in each first groove, a capacitor dielectric layer is formed on the sidewall of the first electrode, and a second electrode in contact with the capacitor dielectric layer is formed in the second hole.

[0089] S500: A groove extending in the vertical direction is formed on the third and / or fourth side of the initial stacking unit; the third and fourth sides are arranged opposite each other in the first direction, and the first and second sides are arranged opposite each other in the second direction, the first and second directions intersect and are both perpendicular to the vertical direction;

[0090] S600: Each initial semiconductor layer is laterally etched in the trench to form a second groove in each initial semiconductor layer, and a gate dielectric layer and a gate are sequentially formed in each second groove.

[0091] Figures 12 to 26d are schematic cross-sectional views of a semiconductor device manufactured according to an embodiment of the present disclosure. The manufacturing method of the semiconductor device provided in the embodiment of the present disclosure will be further described in detail below with reference to Figures 12 to 26d.

[0092] Figures 12 to 17 illustrate a process for forming initial stacked cells. As shown in Figure 17, a plurality of initial stacked cells and an isolation layer 500 surrounding the initial stacked cells are formed on the substrate 100. Each initial stacked cell includes a support layer and an initial semiconductor layer 621 alternately stacked along the vertical direction (Z direction). The initial stacked cells are located in the same position as the stacked cells 110.

[0093] The substrate 100 may be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), III-V compounds (e.g., GaN, GaAs, InAs, etc.), or any other suitable semiconductor material. The substrate may also be made of other materials. In this embodiment, the substrate 100 is a silicon substrate.

[0094] In some embodiments, the support layer is an interlayer dielectric layer 111, that is, the initial stacking unit includes an interlayer dielectric layer 111 and an initial semiconductor layer 621 alternately stacked in the vertical direction. Such an initial stacking unit can be obtained by the following manufacturing method:

[0095] A stacked layer is formed on a substrate, the stacked layer comprising sacrificial material layers and semiconductor material layers alternately stacked in a vertical direction; the stacked layer is patterned and etched to form a patterned stacked layer, the patterned stacked layer comprising sacrificial layers and initial semiconductor layers alternately stacked in a vertical direction; initial trenches are formed at locations for forming trenches, extending vertically to expose each sacrificial layer; sacrificial layers are removed based on the initial trenches, and interlayer dielectric material is filled at the locations where sacrificial layers have been removed to obtain initial stacked cells, the initial stacked cells comprising alternating interlayer dielectric layers and initial semiconductor layers.

[0096] The following is a detailed description with reference to Figures 12 to 17. As shown in Figure 12, a sacrificial material layer 610 and a semiconductor material layer 620 are alternately formed on the substrate 100. That is, the sacrificial material layer 610 is formed first, and then the semiconductor material layer 620 is formed on the sacrificial material layer 610, so that a sacrificial material layer 610 is provided below each semiconductor material layer 620.

[0097] In some embodiments, the step of forming the semiconductor material layer 620 specifically includes: forming the semiconductor material layer on the sacrificial material layer using an epitaxial growth process.

[0098] Epitaxial growth refers to the formation of a single-crystal layer on a substrate with the same crystal orientation as the substrate. In this embodiment, the substrate used for epitaxial growth is a sacrificial material layer. For example, the semiconductor material layer has a single-crystal structure, and the composition of the semiconductor material layer can be single-crystal semiconductors such as single-crystal silicon, single-crystal germanium, or gallium arsenide. In this embodiment, the semiconductor material layer is a single-crystal silicon layer. The sacrificial material layer enables the semiconductor material layer to form a single-crystal structure and has a suitable etching selectivity with the semiconductor material layer so that the semiconductor material layer is essentially not etched when the sacrificial material layer is removed. For example, the composition of the sacrificial material layer can be a silicon-germanium alloy.

[0099] In this embodiment, a silicon-germanium alloy is used as the sacrificial material layer, and an epitaxial growth process is employed to prepare a semiconductor material layer with a single-crystal structure. This allows the channel region of the final transistor to have a single-crystal structure, which can improve the carrier transport rate, reduce the on-resistance of the transistor, and increase the switching speed of the transistor, thereby comprehensively improving the performance of the transistor and thus enhancing the storage performance of the semiconductor device. Furthermore, epitaxial growth of single-crystal semiconductors on silicon-germanium alloy offers high manufacturability.

[0100] Referring again to Figure 12, a first protective dielectric layer 630 is formed on the uppermost semiconductor material layer 620 to protect the semiconductor material layer 620. For example, the material of the first protective dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the first protective dielectric layer is silicon oxide prepared using the TEOS (Tetraethoxysilane) process.

[0101] Referring to Figure 13, an isolation groove is formed within the stacked layer, extending vertically (Z-direction) through the entire stacked layer. The isolation groove divides the stacked layer into multiple stacked blocks. A first isolation material is filled within the isolation groove to form a first sub-isolation layer 510, which isolates adjacent stacked blocks.

[0102] Figure 13 illustrates the formation of multiple isolation slots extending along the second direction (Y direction) within the stacked layer. It should be understood that in other embodiments, multiple isolation slots extending along the first direction may also be formed within the stacked layer, or isolation slots extending along both the second and first directions may be formed to obtain multiple stacked blocks arranged in an array. This embodiment uses only one stacked block as an example for illustration, and the manufacturing process for other stacked blocks can be referred to the manufacturing process for this stacked block.

[0103] For example, the material of the first sub-isolation layer includes silicon oxide, doped silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (HfOx), or other low-k dielectric materials. In this embodiment, the material of the first sub-isolation layer is a spin-on insulating medium (SOD), and the composition of the spin-on insulating medium is, for example, silicon oxide.

[0104] Referring to Figures 14a and 14b, the stacked layers are patterned by etching to form a patterned stacked layer. The patterned stacked layer includes a sacrificial layer 611 and an initial semiconductor layer 621 that are alternately stacked in the vertical direction; Figure 14b is a top view of the initial semiconductor layer in Figure 14a.

[0105] As shown in Figure 14b, the patterned stack layer includes multiple body regions 11 for forming initial stacking units, word line regions 12 for forming word lines, and trench regions 13 for forming trenches. The word line regions 12 and trench regions 13 extend along a second direction (Y direction). The word line regions 12 and trench regions 13 pass through the stack block along the second direction.

[0106] Within each main body region, the initial semiconductor layer 621 includes a first initial region A′ corresponding to region A of the semiconductor layer in FIG1, a second initial region B′ corresponding to the second region B, a third initial region C′ corresponding to the third region C, and a fourth initial region D′ corresponding to the gate. The length of the fourth initial region D′ along the second direction is less than the sum of the lengths of the first initial region A′, the second initial region B′, and the third initial region C′ along the second direction.

[0107] In this embodiment, the first, second, and third regions of the semiconductor layer in the final stacked unit, as well as the region containing the gate, are formed during the patterning process of the stacked layers. It is understood that if it is desired to form the semiconductor devices shown in Figures 3 to 7 and Figure 9, it is necessary to form the corresponding patterned stacked layers in this step.

[0108] For example, a dry etching process can be used to etch the stacked layers. In some specific embodiments, a patterned mask layer can be formed on the stacked layers, covering the main region 11, the word line region 12, and the trench region 13. Based on the patterned mask layer, a first protective dielectric layer, alternately stacked semiconductor material layers, and sacrificial material layers are sequentially etched using a dry etching process to obtain the patterned stacked layers. In the patterned stacked layers, each sacrificial layer and each initial semiconductor layer have the same pattern.

[0109] Referring to Figure 15, a second insulating material is filled at the locations within the stack where the sacrificial material layer and semiconductor material layer are removed, resulting in a second sub-isolation layer 520. For example, the second insulating material includes silicon oxide or other low-dielectric-constant materials. In this embodiment, the second sub-isolation layer 520 is made of the same material as the first sub-isolation layer 510, which is a spin-coated insulating medium.

[0110] Referring again to Figure 15, an initial trench 710 extending along a second direction (Y direction) is formed within the trench region. The initial trench 710 penetrates each initial semiconductor layer and each sacrificial layer along a vertical direction (Z direction). For example, the initial trench 710 may traverse the entire stack along the second direction (Y direction).

[0111] In some embodiments, as shown in FIG15, the manufacturing method further includes: forming a first initial hole 720 and a second initial hole 730 extending vertically to expose each sacrificial layer; wherein the first initial hole 720 is located at the same position as the first hole, and the second initial hole 730 is located at the same position as the second hole.

[0112] For example, as shown in FIG15, both the first initial via 720 and the second initial via 730 penetrate the entire stacked layer vertically to expose each sacrificial layer 611. It should be noted that in some other embodiments, an insulating dielectric layer may be formed on the surface of the substrate 100, and then alternating layers of sacrificial material and semiconductor material layers may be formed on the insulating dielectric layer. The insulating dielectric layer can also serve as an etch stop layer, so that the first initial via stops at the insulating dielectric layer after penetrating all the initial semiconductor layers and sacrificial layers. This facilitates control of the depth of the first initial via and isolates the subsequently formed bit lines from the substrate.

[0113] For example, the first initial hole 720, the second initial hole 730, and the initial trench 710 are formed simultaneously. In some embodiments, the first initial hole 720, the second initial hole 730, and the initial trench 710 can be formed simultaneously by performing photolithography, development, and etching processes sequentially. The etching process includes, but is not limited to, dry etching.

[0114] Referring to Figure 16, the entire sacrificial layer 611 is removed based on the initial trench 710, the first initial hole 720, and the second initial hole 730. For example, a wet etching process can be used to remove the sacrificial layer.

[0115] It should be noted that in this embodiment, the sacrificial layer is removed through the initial trench 710, the first initial hole 720, and the second initial hole 730. This increases the contact area between the etching solution and the sacrificial layer, thereby increasing the speed of sacrificial layer removal. Furthermore, compared to removing the sacrificial layer solely through the initial trench, this embodiment uses the first initial hole 720 and the second initial hole 730 to more thoroughly remove the sacrificial layer above and below the first and third initial regions, preventing residual sacrificial layer from causing capacitor connections between vertically adjacent memory cells.

[0116] In another embodiment, in this step, only the initial groove 710 may be set, or only the initial groove 710 and the second initial hole 730 may be set, or only the initial groove 710 and the first initial hole 720 may be set.

[0117] Referring to Figures 16 and 17, interlayer dielectric material is filled at the locations where the sacrificial layer has been removed to obtain an initial stacked cell. The initial stacked cell includes an interlayer dielectric layer 111 and an initial semiconductor layer 621 alternately stacked along the vertical direction (Z direction). In this step, interlayer dielectric material is also simultaneously filled into the initial trench 710, the first initial via 720, and the second initial via 730. The interlayer dielectric material includes silicon oxide, doped silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (HfOx), or other low-k dielectric materials. In this embodiment, the interlayer dielectric material is silicon oxide, the same material as the first protective dielectric layer 630. For example, in this step, a silicon thermal oxidation process can be used to form the silicon oxide.

[0118] Next, step S200 is executed to form the first hole and form a bit line within the first hole.

[0119] In some embodiments, if a first initial hole is formed during the removal of the sacrificial layer, and the first initial hole and the first aperture are located at the same position, then step S200 forming the first aperture can be achieved by removing at least a portion of the interlayer dielectric material within the first initial hole to expose each initial semiconductor layer, and the space within the first initial hole where the interlayer dielectric material has been removed forms the first aperture.

[0120] Figure 18b is a cross-sectional view of Figure 18a along line aa′. For example, as shown in Figures 18a and 18b, a portion of the interlayer dielectric material within the first initial hole is removed to expose each initial semiconductor layer 621, resulting in a first hole 721. A certain thickness of interlayer dielectric material 111′ is retained at the bottom of the first initial hole. This isolates the bit line 410 from the substrate, preventing bit line current leakage into the substrate and affecting data read / write operations in other stacked cells when the substrate is retained. In this embodiment, the thickness of the retained interlayer dielectric material 111′ is substantially the same as the thickness of the bottommost interlayer dielectric layer 111.

[0121] As another example, if an insulating dielectric layer is provided on the substrate surface and the first initial hole remains on the insulating dielectric layer, then all interlayer dielectric material in the first initial hole can be removed to form the first hole.

[0122] In some embodiments, the manufacturing method further includes forming a source layer on the sidewall of the first aperture before forming the bit line; wherein the bit line is surrounded by the source layer.

[0123] Referring again to Figures 18a and 18b, a source layer 240 is formed on the sidewall and bottom of the first hole 721.

[0124] The source layer 240 is made of a doped semiconductor. Doped semiconductors include, but are not limited to, doped silicon, doped germanium, and silicon-germanium doping. Doping elements include, but are not limited to, phosphorus and boron. In this embodiment, the source layer is made of phosphorus-doped silicon.

[0125] For example, the source layer 240 can be formed using a deposition process. Deposition processes include, but are not limited to: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and combinations thereof.

[0126] In some embodiments, only the source layer 240 on the sidewall of the first hole 721 can be retained, and then the source layer 240 at the bottom of the first hole 721 can be removed by dry etching.

[0127] Referring again to Figures 18a and 18b, a bit line 410 is formed on the surface of the source layer 240, and the sidewalls of the bit line 410 are covered by the source layer 240. For example, the bottom of the bit line 410 may also be covered by the source layer 240.

[0128] The material of bit line 410 includes, but is not limited to, metals such as W, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, and Au; alloys such as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, and stainless steel; as well as conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive doped semiconductors, and conductive metal oxide semiconductors. Metal nitrides can be titanium nitride, tungsten nitride, tantalum nitride, etc., and doped semiconductors can be doped polycrystalline silicon, etc. Conductive metal oxide semiconductors can be indium tin oxide, etc. In this embodiment, the bit line includes a metal layer, such as a tungsten layer. For example, the bit line can be formed using a deposition process.

[0129] In this embodiment, bit lines 410 and source layers 240 are formed as shown in FIG1. ​​In other embodiments, if it is desired to form the structure shown in FIG5, then the source layer 240 may not be grown in the first via 721, but the bit lines 410 may be formed directly, with the bit lines 410 in direct contact with each initial semiconductor layer 621.

[0130] In some other embodiments, if it is desired to form the source shown in FIG5, the manufacturing method further includes: implanting first doped ions into at least a portion of the first initial region A′ of the initial semiconductor layer 621 to form a source doped region; the source doped region is disposed around the bit line 410.

[0131] This disclosure does not limit the order of doping steps in the entire manufacturing process. For example, doping can be performed after the patterned stacked layers are formed, after the first via is formed, or after the bit lines are formed, etc. In practical applications, the timing of doping can be selected as needed.

[0132] Referring to Figure 19a, a second protective dielectric layer 640 is formed on the bit line. The second protective dielectric layer 640 also covers the first protective dielectric layer 630, the first sub-isolation layer 510, and the second sub-isolation layer 520. The second protective dielectric layer 640 is used to protect the bit line and the source layer.

[0133] Next, steps S300 and S400 are performed to form a second hole and a capacitor is formed within the second hole.

[0134] In some embodiments, if a second initial hole is formed during the removal of the sacrificial layer, and the second initial hole and the second hole are located at the same position, then step S300, forming the second hole, can be achieved by removing at least a portion of the interlayer dielectric material within the second initial hole to expose each initial semiconductor layer, and the space within the second initial hole where the interlayer dielectric material has been removed forms the second hole.

[0135] Referring to Figures 19a and 19b, a portion of the interlayer dielectric material within the second initial hole can be removed to form the second hole 731, while a certain thickness of interlayer dielectric material 111' is retained at the bottom of the second initial hole. This isolates the first electrode of the capacitor subsequently formed within the second hole from the substrate, preventing current leakage from the first electrode into the substrate and affecting data read / write operations in other stacked cells when the substrate is retained. In this embodiment, the thickness of the retained interlayer dielectric material 111' is substantially the same as the thickness of the bottommost interlayer dielectric layer 111.

[0136] As another example, if an insulating dielectric layer is provided on the substrate surface and the second initial hole remains on the insulating dielectric layer, then all interlayer dielectric material in the second initial hole can be removed to form the second hole.

[0137] Referring to Figure 20, each initial semiconductor layer 621 is etched laterally within the second hole 731 to form a first groove 810 within each initial semiconductor layer 621. Here, "lateral" refers to any direction perpendicular to the vertical direction (Z direction).

[0138] For example, a wet etching process can be used to etch the initial semiconductor layer laterally from inside the second hole. The wet etching process is isotropic, allowing simultaneous etching of the initial semiconductor layer along various directions in the horizontal plane, centered on the second hole, to form an annular first groove on the sidewall of the second hole. Referring to Figure 1, the top view of the first groove 810 is essentially similar to the top view of the second hole 731. That is, if the top view of the second hole 731 is circular, then the top view of the first groove 810 can be a concentric circle with a larger radius. If the top view of the second hole 731 is elliptical, then the top view of the first groove 810 can be a concentric ellipse with a larger radius.

[0139] In some embodiments, the manufacturing method further includes forming a drain layer on the sidewall of the first groove before forming the first electrode; wherein the first electrode is surrounded by the drain layer.

[0140] Referring to Figures 21 and 22, a drain layer 250 is formed on the sidewall of the first groove 810, and a first electrode 310 is formed on the sidewall of the drain layer 250.

[0141] In some embodiments, the step of forming a drain layer 250 on the sidewall of the first groove 810 includes: depositing a drain material layer in the second hole 731 and the first groove 810, and etching the drain material layer to at least remove the drain material layer on the sidewall of the second hole 731, leaving only the drain material layer in a portion of the space inside the first groove 810 to form the drain layer 250.

[0142] The drain layer 250 is made of a doped semiconductor. Doped semiconductors include, but are not limited to, doped silicon, doped germanium, and doped silicon-germanium. The material of the drain layer can be the same as or different from the material of the source layer, but they should both be P-type semiconductors or both N-type semiconductors. For example, a deposition process can be used to form the drain material layer. For example, a dry etching process or a wet etching process can be used to etch the drain material layer.

[0143] The steps for forming the first electrode are similar to those for forming the drain layer. A first electrode material layer can be deposited in the second hole 731 and the first groove 810, and the first electrode material layer can be etched to at least remove the first electrode material layer on the sidewall of the second hole 731, leaving only the first electrode material layer in a portion of the space inside the first groove 810 to form the first electrode 310.

[0144] Referring to Figures 23a and 23b, a capacitor dielectric layer 330 is formed on the sidewall of the first electrode 310, and a second electrode 320 is formed on the sidewall of the capacitor dielectric layer 330.

[0145] For example, the capacitor dielectric layer 330 is a ferroelectric layer. In this embodiment, the ferroelectric layer not only covers the sidewall of the first electrode 310, but also the sidewall of the interlayer dielectric layer 111, that is, a continuous ferroelectric layer in the vertical direction is formed in the second hole.

[0146] In other embodiments, the drain layer 250 and the first electrode 310 may not completely occupy the first groove, causing the sidewall of the first electrode to recede relative to the sidewall of the interlayer dielectric layer by a certain distance. In this case, ferroelectric material can be formed in the remaining space of the first groove. For example, a ferroelectric material layer can be deposited in the second hole and the first groove, and the ferroelectric material layer can be etched to remove at least the ferroelectric material layer on the sidewall of the second hole, leaving only the ferroelectric material layer in a portion of the space inside the first groove to form a sub-ferroelectric layer, resulting in the capacitor shown in FIG8.

[0147] Referring again to Figures 23a and 23b, a second electrode 320 in contact with the ferroelectric layer is formed within the second hole. For example, the steps of forming the second electrode include: filling the remaining space of the second hole with a second electrode material layer until it covers the second protective dielectric layer 640; etching back the second electrode material layer until the second protective dielectric layer 640 is exposed; and forming the second electrode 320 with the remaining second electrode material layer within the second hole.

[0148] For example, the materials of the first electrode and the second electrode can be selected from the materials of the bit line described above. In this embodiment, the materials of both the first electrode and the second electrode are metal nitrides, such as titanium nitride.

[0149] In this embodiment, a capacitor and drain layer as shown in FIG1 are formed. In other embodiments, if it is desired to form the structure shown in FIG5, the drain layer 250 may not be grown in the second hole 731, but the first electrode 310 may be formed directly, and the first electrode 310 may be in direct contact with each initial semiconductor layer 621.

[0150] In some other embodiments, if it is desired to form the drain shown in FIG6, the manufacturing method further includes: implanting second doped ions into at least a portion of a region within the third region C′ of the initial semiconductor layer to form a drain doped region; the drain doped region is disposed around the bit line.

[0151] This disclosure does not limit the order of doping steps in the entire manufacturing process. For example, doping can be performed after the patterned stacked layers are formed, after the second pore is formed, or after the capacitor is formed, etc. In practical applications, the timing of doping can be selected as needed.

[0152] Referring to Figure 24, a third protective dielectric layer 650 is formed on the second protective dielectric layer 640. The third protective dielectric layer 650 is used to protect the capacitor.

[0153] Next, steps S500 and S600 are performed to form a trench and a gate.

[0154] In some embodiments, step S500 forming a trench can be achieved by removing at least a portion of the interlayer dielectric material in the initial trench to expose each initial semiconductor layer, and the space in the initial trench where the interlayer dielectric material has been removed forms a trench.

[0155] Referring to Figure 24, a portion of the interlayer dielectric material within the initial trench can be removed to expose each initial semiconductor layer 621, forming a trench 711, with a certain thickness of interlayer dielectric material remaining at the bottom of the initial trench. In this embodiment, the thickness of the retained interlayer dielectric material is substantially the same as the thickness of the bottommost interlayer dielectric layer. In another embodiment, all the interlayer dielectric material within the initial trench can also be removed to form the trench 711.

[0156] Referring to Figures 25a, 25b, 25c, 25d and 25e, each of the initial semiconductor layers is laterally etched within trench 711 to form a second groove 820 within each initial semiconductor layer. The process for forming the second groove can be the same as the process for forming the first groove, i.e., a wet etching process is used to etch the initial semiconductor layer laterally from the inside of the trench to form the second groove.

[0157] It should be noted that when forming the second groove 820, the initial semiconductor layer was not completely etched away. Instead, only a portion of the initial semiconductor layer was etched away from the third and / or fourth sides. The remaining initial semiconductor layer constitutes the semiconductor layer 210 of the transistor. Along the second direction, the semiconductor layer 210 between the first hole and the second hole is continuous to form a channel region.

[0158] In this embodiment, as shown in FIG25b, by controlling the concentration of the etching solution, etching time, etc., only the initial semiconductor layer in the fourth region D′ of the word line region and the main body region is etched, while the initial semiconductor layer in the second region B′ is retained to form semiconductor layer 210.

[0159] Referring to Figures 26a, 26b, 26c and 26d, a gate dielectric layer 220 is formed on the sidewall of the second recess 820, a gate 230 is formed on the sidewall of the gate dielectric layer 220, and a word line 420 is formed on the sidewall of the gate 230.

[0160] In this embodiment, a gate dielectric layer 220 is formed on all sidewalls, top walls, and bottom walls of the second groove. The gate 230 and word line 420 are integral and made of the same material. The steps of forming the gate and word line may include: depositing gate material on the surface of the gate dielectric layer 220 to fill the second groove and trench, forming a gate material layer; then etching back the gate material layer to remove the gate material layer in the trench, retaining the gate material layer in the second groove to form the gate 230 and word line 420.

[0161] For example, the materials of the gate and word line can be selected from the materials of the bit line described above. In this embodiment, both the gate and word line include a metal layer, such as a tungsten layer.

[0162] Referring to Figures 26a to 26d, a third insulating material is filled into the trench to form a third sub-insulating layer 530. The first sub-insulating layer 510, the second sub-insulating layer 520, and the third sub-insulating layer 530 constitute the insulating layer 500 surrounding the stacked unit. For example, the material of the third sub-insulating layer includes silicon oxide or other low-dielectric-constant materials. The material of the third sub-insulating layer can be silicon oxide formed using a plasma-enhanced chemical vapor deposition process. In this embodiment, the materials of the first sub-insulating layer 510, the second sub-insulating layer 520, and the third sub-insulating layer 530 are all silicon oxide.

[0163] In this embodiment, by first forming a first initial via, a second initial via, and an initial trench, the sacrificial layer is replaced with an interlayer dielectric layer. This method can remove the sacrificial layer more cleanly, avoiding short circuits between adjacent memory cells caused by residual sacrificial layers. Furthermore, removing the sacrificial layer before forming the source and drain layers can avoid damage to the source and drain layers during the sacrificial layer removal process, thereby improving the quality of the source and drain layers and ultimately enhancing the performance of the semiconductor device.

[0164] In the above embodiments, the sacrificial layer in the initial stacked cell has been replaced with an interlayer dielectric layer during the etching of the first via, the second via, and the trench. In other embodiments, the operation of replacing the sacrificial layer with the interlayer dielectric layer may be performed after the formation of the first via, and / or the second via, and / or the trench.

[0165] In some embodiments, the support layer is a sacrificial layer, that is, the initial stacking unit in step S100 includes alternately stacked sacrificial layers and initial semiconductor layers.

[0166] For example, forming the first hole in step S200 specifically includes: etching the sacrificial layer and the initial semiconductor layer on the first side of the initial stacked cell to form a first hole extending vertically to expose each initial semiconductor layer.

[0167] Step S300 forms the second hole, specifically including: on the second side opposite to the first side, etching the sacrificial layer and the initial semiconductor layer to form a second hole extending vertically to expose each initial semiconductor layer.

[0168] Step S500 forms a trench, specifically including: etching a sacrificial layer and an initial semiconductor layer on the third and / or fourth side of the initial stacked cell to form a trench extending vertically to expose each initial semiconductor layer.

[0169] The manufacturing method further includes: after forming a first hole, removing a sacrificial layer in a local area surrounding the first hole based on the first hole, and filling the location where the sacrificial layer was removed with an interlayer dielectric material; after forming a second hole, removing a sacrificial layer in a local area surrounding the second hole based on the second hole, and filling the location where the sacrificial layer was removed with an interlayer dielectric material; after forming a trench, removing the remaining sacrificial layer based on the trench, and filling the location where the sacrificial layer was removed with an interlayer dielectric material to form an interlayer dielectric layer.

[0170] For example, if the initial semiconductor layer has the same first initial region, second initial region, third initial region, fourth initial region, and word line region as the patterned stacked layer shown in FIG14b, then the sacrificial layer above and below the first initial region can be removed through the first via, and the location where the sacrificial layer was removed can be filled with interlayer dielectric material, after which the source layer and bit line are formed. The sacrificial layer above and below the third initial region can be removed through the second via, and the location where the sacrificial layer was removed can be filled with interlayer dielectric material, after which a first trench is formed, and a drain layer and a first electrode are formed within the first trench. Alternatively, all remaining sacrificial layers can be removed through a trench, and the location where the sacrificial layer was removed can be filled with interlayer dielectric material to obtain an interlayer dielectric layer, after which a second trench is formed, and a gate dielectric layer, gate, and word line are formed within the second trench.

[0171] In another embodiment, when forming the first and second holes, the step of replacing the sacrificial layer with an interlayer dielectric layer may be omitted. Instead, after forming the trench, all sacrificial layers are removed based on the trench, and an interlayer dielectric layer is formed at the location where the sacrificial layer was removed.

[0172] Furthermore, the embodiments shown in Figures 12 to 26d of this disclosure illustrate the manufacturing process of a stacked cell including a single-gate transistor. In other embodiments, if a dual-gate transistor is used, the manufacturing process described above is also applicable to dual-gate transistors, except that the patterned stacked layer needs to be adjusted to include two word line regions and two trench regions according to the gate and word line structure shown in Figure 9, and a trench is formed in each trench region during the trench forming step.

[0173] In summary, the semiconductor device manufacturing method provided in this disclosure forms a fourth initial region corresponding to the gate in advance during the patterning etching of the stacked layer. The gate can then be formed horizontally by self-alignment. The formation process is relatively simple, but reliable and highly manufacturable. The gate can correspond well to the channel region to control the channel region. Furthermore, the relative area between the gate and the source and drain is small, which can effectively reduce the gate-drain leakage current.

[0174] This disclosure also provides an electronic device, including the semiconductor device described above, and / or a semiconductor device formed by the manufacturing method of the semiconductor device described above.

[0175] For example, the semiconductor device provided in this disclosure embodiment is a memory. The memory can be DRAM, ferroelectric memory, etc.

[0176] It should be noted that since the electronic devices in the embodiments of this application include semiconductor devices manufactured using the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, which will not be repeated here.

[0177] For example, electronic devices include storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks, etc. Storage devices may include, for example, memory in a computer; this application does not limit the scope of the application to such devices.

[0178] In the technical solution provided by the embodiments of this disclosure, the semiconductor device includes at least one stacked unit, each stacked unit including multiple memory cells stacked vertically, and the multiple memory cells are coupled to the same bit line, while the gate of each memory cell extends horizontally. On the one hand, the semiconductor device provided by the embodiments of this disclosure can increase the number of memory cells per unit area, thereby increasing the storage density of the semiconductor device and utilizing the miniaturization of the semiconductor device. On the other hand, the vertical bit line structure adopted in each stacked unit determines that only one memory cell in the stacked unit will be opened during the read operation, and multiple memory cells will not be opened simultaneously, so there is no bit line coupling within the stacked unit. In addition, the layout adjustment of multiple stacked units is more flexible, and it is easier to increase the distance between bit lines in adjacent stacked units, reduce the coupling effect between bit lines of adjacent stacked units, thereby greatly reducing the coupling effect between bit lines within the semiconductor device, thereby reducing the circuit load.

[0179] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, comprising: At least one stacking unit, each of the stacking units comprising: Alternating interlayer dielectric layers and memory layers stacked vertically, each memory layer comprising: a semiconductor layer and a gate of a transistor, and a first electrode of a capacitor, the semiconductor layer and the gate being arranged side by side along a first direction, the first electrode being coupled to one end of the semiconductor layer along a second direction; the first direction and the second direction intersect and are both perpendicular to the vertical direction; The second electrode extends along the vertical direction and passes through the interlayer dielectric layers and the first electrode in each of the memory layers, with a capacitor dielectric layer provided between the second electrode and each of the first electrodes; Bit lines extend along the vertical direction and are coupled to the other end of the semiconductor layer in each memory layer along the second direction.

2. The semiconductor device according to claim 1, wherein, The capacitor dielectric layer includes a ferroelectric layer.

3. The semiconductor device according to claim 2, wherein, The ferroelectric layer surrounds the sidewall of the second electrode and extends along the vertical direction through the first electrode in each of the plurality of interlayer dielectric layers and each of the memory layers.

4. The semiconductor device according to claim 2, wherein, The ferroelectric layer includes a plurality of sub-ferroelectric layers spaced apart along the vertical direction. Each sub-ferroelectric layer is located in a memory layer. Each sub-ferroelectric layer passes through the first electrode in the same memory layer and is disposed around the sidewall of the second electrode. Adjacent sub-ferroelectric layers along the vertical direction are isolated by the interlayer dielectric layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The semiconductor layer is made of a single-crystal semiconductor.

6. The semiconductor device according to any one of claims 1 to 4, wherein, The semiconductor layer includes a first region, a second region, and a third region sequentially disposed along the second direction, wherein the width of the second region along the first direction is smaller than the widths of the first region and the third region along the first direction. The bit line passes through a first region of the semiconductor layer in each of the memory layers; In each of the memory layers, the first electrode passes through a third region of the semiconductor layer.

7. The semiconductor device according to claim 6, wherein, The first region includes a source doped region, which is in contact with the bit line.

8. The semiconductor device according to claim 6, wherein, The semiconductor device further includes: a source layer disposed around the bit line sidewall, the source layer extending along the vertical direction to a first region passing through the semiconductor layer in the plurality of interlayer dielectric layers and each of the memory layers, the source layer being in contact with the first region.

9. The semiconductor device according to claim 6 or 7, wherein, The third region includes a drain-doped region that is in contact with the first electrode.

10. The semiconductor device according to claim 6 or 7, wherein, Each of the memory layers further includes a drain layer disposed around the first electrode, the drain layer penetrating a third region of the semiconductor layer in the same memory layer and contacting the third region.

11. The semiconductor device according to claim 1, wherein, Each memory layer includes two gates belonging to the same transistor, the two gates being located on opposite sides of the semiconductor layer along the first direction, and a gate dielectric layer being provided between each gate and the semiconductor layer.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The semiconductor device includes a plurality of stacked cells arranged side by side along the second direction, and the memory layers of the plurality of stacked cells are aligned with each other along the vertical direction; The semiconductor device further includes: a plurality of word lines stacked along the vertical direction, each word line being located in the memory layer, and each word line extending along the second direction and contacting a gate in one of the plurality of stacked cells.

13. A method for manufacturing a semiconductor device, the method comprising: At least one initial stacking unit and an isolation layer surrounding the initial stacking unit are formed on a substrate, the initial stacking unit comprising a support layer and an initial semiconductor layer alternately stacked in a vertical direction; On the first side of the initial stacked cell, a first hole is formed extending along the vertical direction to expose each of the initial semiconductor layers, and a bit line is formed within the first hole; On the second side opposite to the first side, a second hole is formed extending in the vertical direction to expose each of the initial semiconductor layers. Each of the initial semiconductor layers is laterally etched within the second hole to form a first groove within each of the initial semiconductor layers. A first electrode is formed in each of the first grooves, a capacitor dielectric layer is formed on the sidewall of the first electrode, and a second electrode is formed in the second hole that contacts the capacitor dielectric layer. On the third and / or fourth side of the initial stacking unit, a groove extending along the vertical direction is formed; the third and fourth sides are arranged opposite each other along a first direction, and the first and second sides are arranged opposite each other along a second direction, the first and second directions intersect and are both perpendicular to the vertical direction; Each initial semiconductor layer is laterally etched within the trench to form a second groove within each initial semiconductor layer, and a gate dielectric layer and a gate are sequentially formed within each second groove.

14. The manufacturing method according to claim 13, wherein, The support layer includes an interlayer dielectric layer; The process of forming at least one initial stacking unit on the substrate includes: A stacked layer is formed on a substrate, the stacked layer comprising sacrificial material layers and semiconductor material layers alternately stacked along the vertical direction; The stacked layers are patterned by etching to form a patterned stacked layer; the patterned stacked layer includes sacrificial layers and initial semiconductor layers that are alternately stacked along the vertical direction; At the locations where the trenches are formed, initial trenches are formed that extend along the vertical direction to expose each of the sacrificial layers; The sacrificial layer is removed based on the initial trench, and the location where the sacrificial layer was removed is filled with interlayer dielectric material to obtain the initial stacking unit, which includes alternately stacked interlayer dielectric layers and initial semiconductor layers.

15. The manufacturing method according to claim 14, wherein, The method further includes: A first initial hole and a second initial hole are formed extending along the vertical direction to expose each of the sacrificial layers; wherein the first initial hole is in the same position as the first hole, and the second initial hole is in the same position as the second hole; In the steps of removing the sacrificial layer and filling the interlayer dielectric material, the sacrificial layer is also removed based on the first initial hole and the second initial hole, and the interlayer dielectric material is filled in the first initial hole, the second initial hole and the initial trench.

16. The manufacturing method according to claim 15, wherein, Forming the first hole includes: removing at least a portion of the interlayer dielectric material within the first initial hole to expose each of the initial semiconductor layers, thereby forming the first hole; Forming the second hole includes: removing at least a portion of the interlayer dielectric material within the second initial hole to expose each of the initial semiconductor layers, thereby forming the second hole; Forming the trench includes: removing at least a portion of the interlayer dielectric material within the initial trench to expose each of the initial semiconductor layers, thereby forming the trench.

17. The manufacturing method according to claim 14, wherein, The formation of the stacked layers on the substrate includes: A sacrificial material layer and a semiconductor material layer are alternately formed on the substrate; wherein, in the step of forming the semiconductor material layer, an epitaxial growth process is used to form the semiconductor material layer.

18. The manufacturing method according to claim 17, wherein, The sacrificial material layer comprises a silicon-germanium alloy, and the semiconductor material layer comprises a single-crystal semiconductor.

19. The manufacturing method according to claim 13, wherein, The manufacturing method further includes: Before the bit line is formed, a source layer is formed on the sidewall of the first hole; wherein the bit line is surrounded by the source layer.

20. The manufacturing method according to claim 13, wherein, The manufacturing method further includes: Before forming the first electrode, a drain layer is formed on the sidewall of the first groove; wherein the first electrode is surrounded by the drain layer.

21. An electronic device comprising a semiconductor device as claimed in any one of claims 1 to 12, and / or comprising a semiconductor device formed using a manufacturing method of a semiconductor device as claimed in any one of claims 13 to 20.

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