Display panel and display apparatus

Abstract

Provided in the present disclosure are a display panel and a display apparatus. The display panel comprises a second initialization signal transmission layer, which comprises a plurality of second initialization signal lines and a plurality of second initialization compensation lines. Each second initialization signal line comprises a second body portion and a second extension portion, wherein the second body portion extends in a first direction, the second extension portion extends in a second direction, and the second initialization compensation lines extend in the second direction; the second body portion is coupled to a first electrode of a corresponding second reset transistor; and the second extension portion comprises an extension connection part and an extension compensation part, a first end of the extension connection part is coupled to the second body portion, and a second end of the extension connection part is respectively coupled to the extension compensation part and the corresponding second initialization compensation line.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510186030.4, filed in China on February 19, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0004] With the continuous development of display technology, display products with fingerprint recognition functionality are widely used in various fields. These products utilize the light emitted from pixels, reflected by the finger, and imaged onto a sensor through a small hole to achieve under-display fingerprint recognition. However, due to space limitations in the driver backplane, light leakage slits form between metal layers in these displays. This results in periodic interference stripes being collected during fingerprint recognition. The width of these interference stripes is close to the width of normal fingerprint stripes, and their period is similar to that of the fingerprint stripes, making them impossible to filter out using algorithms. Therefore, display products with fingerprint recognition functionality in related technologies cannot guarantee the accuracy of fingerprint recognition, resulting in poor fingerprint recognition performance. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display panel and a display device.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] A first aspect of this disclosure provides a display panel including a second initialization signal transmission layer and a plurality of sub-pixels; wherein...

[0008] The sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a second reset transistor, and the second electrode of the second reset transistor is coupled to the anode of the light-emitting element.

[0009] The second initialization signal transmission layer includes multiple second initialization signal lines and multiple second initialization compensation lines; the second initialization signal line includes a second main body and a second extension, the second main body extends along a first direction, the second extension extends along a second direction, the second initialization compensation line extends along the second direction, and the first direction intersects the second direction;

[0010] The second main body is coupled to the first terminal of the corresponding second reset transistor; the second extension includes an extension connection portion and an extension compensation portion, the first end of the extension connection portion is coupled to the second main body, and the second end of the extension connection portion is coupled to the extension compensation portion and the corresponding second initialization compensation line, respectively.

[0011] Optionally, the extended connection portion includes an intermediate portion located between its first end and second end, the intermediate portion having a first width along a first direction, and the width of the extended compensation portion along the first direction being greater than the first width.

[0012] Optionally, along the second direction, the width of the extended compensation portion is smaller than the width of the second end of the extended connection portion.

[0013] Optionally, the minimum width d1 of the extended compensation portion along the first direction satisfies: 2.8μm≤d1≤3.2μm;

[0014] The maximum width d2 of the extended compensation portion along the first direction satisfies: 5.3μm≤d2≤5.7μm;

[0015] The minimum width d3 of the extended compensation portion along the second direction satisfies: 2.1μm≤d3≤2.5μm;

[0016] The maximum width d4 of the extended compensation portion along the second direction satisfies: 3.4μm≤d3≤3.8μm.

[0017] Optionally, the display panel further includes a first source / drain metal layer, and the extension compensation portion is disposed in the same layer and with the same material as the first source / drain metal layer.

[0018] Optionally, the orthographic projection of the second initialization compensation line on the substrate of the display panel at least partially overlaps with the orthographic projection of the extended compensation portion on the substrate.

[0019] Optionally, the second initialization compensation line includes a plurality of first parts, a plurality of second parts, and a plurality of third parts, wherein the first parts and the second parts are alternately arranged, and a third part is provided between the first parts and the second parts;

[0020] The first part includes a connecting pattern and a compensation pattern; the connecting pattern is coupled to the second end of the extended connecting part, and the orthographic projection of the compensation pattern on the substrate at least partially overlaps with the orthographic projection of the extended compensation part on the substrate; the width of the compensation pattern along the first direction is greater than the width of the third part along the first direction.

[0021] Optionally, the maximum width of the compensation pattern along the first direction is the same as the maximum width of the extended compensation portion along the first direction, and the orthographic projection of the extended compensation portion on the substrate of the display panel is located inside the orthographic projection of the compensation pattern on the substrate.

[0022] Optionally, the minimum width d5 ​​of the compensation pattern along the first direction satisfies: 1.9μm≤d5≤2.3μm;

[0023] The maximum width d6 of the compensation pattern along the first direction satisfies: 5.2μm≤d6≤5.6μm;

[0024] The minimum width d7 of the compensation pattern along the second direction satisfies: 3.4μm≤d7≤3.8μm;

[0025] The maximum width d8 of the compensation pattern along the second direction satisfies: 6μm≤d8≤6.4μm.

[0026] Optionally, the display panel further includes a second source / drain metal layer, wherein the compensation pattern is disposed in the same layer and with the same material as the second source / drain metal layer.

[0027] Optionally, the display panel further includes:

[0028] A first initialization signal transmission layer, the first initialization signal transmission layer including a plurality of first initialization signal lines, the first initialization signal lines including at least a portion extending along the first direction;

[0029] The sub-pixel driving circuit further includes a driving transistor, a first reset transistor, and a first conductive connection portion, wherein the second terminal of the first reset transistor is coupled to the gate of the driving transistor;

[0030] The first conductive connection portion includes a first main body portion, which is coupled to the first electrode of the corresponding first reset transistor and the corresponding first initialization signal line, respectively.

[0031] The first conductive connection portion further includes a first compensation portion coupled to the first main body portion. In the layout area of ​​the same row of sub-pixel driving circuits arranged along the first direction, the first compensation portion and the extended compensation portion are alternately arranged along the first direction.

[0032] Optionally, the first initialization signal transmission layer further includes: a plurality of first initialization compensation lines, the first initialization compensation lines extending along the second direction, and the first initialization compensation lines being coupled to the corresponding first compensation portions.

[0033] Optionally, the width of the first compensation portion along the first direction is approximately the same as the width of the extended compensation portion along the first direction.

[0034] Optionally, the display panel further includes a first source / drain metal layer, wherein the first compensation portion is disposed in the same layer and with the same material as the first source / drain metal layer.

[0035] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel. Attached Figure Description

[0036] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0037] Figure 1 is a schematic diagram of the circuit structure of the sub-pixel driving circuit in the display panel provided in an embodiment of this disclosure;

[0038] Figure 2 is a cross-sectional schematic diagram of the display panel provided in an embodiment of this disclosure;

[0039] Figure 3 is a schematic diagram of the layout of the active layer and the first gate metal layer in the display panel provided in an embodiment of this disclosure;

[0040] Figure 4 is a schematic diagram of the layout of the second gate metal layer in the display panel provided in an embodiment of this disclosure;

[0041] Figure 5 is a schematic diagram of the layout of adding the second gate metal layer shown in Figure 4 to the basis of Figure 3;

[0042] Figure 6 is a schematic diagram of the layout of the first source / drain metal layer in the display panel provided in an embodiment of this disclosure;

[0043] Figure 7 is a schematic diagram of the vias included in the interlayer insulating layer of the display panel provided in the embodiment of this disclosure;

[0044] Figure 8 is a schematic diagram of the layout of adding the first source / drain metal layer shown in Figure 6 and the via shown in Figure 7 to the layout of Figure 5;

[0045] Figure 9 is a schematic diagram of the layout of the second source / drain metal layer in the display panel provided in an embodiment of this disclosure;

[0046] Figure 10 is a schematic diagram of the vias included in the first planarization layer of the display panel provided in an embodiment of this disclosure;

[0047] Figure 11 is a schematic diagram of the layout of the vias in the interlayer insulating layer, the first source / drain metal layer, the vias in the first planarization layer, and the second source / drain metal layer in the display panel provided in the embodiment of this disclosure.

[0048] Figure 12 is a schematic diagram of the layout of adding the second source / drain metal layer shown in Figure 9 and the via shown in Figure 10 to the basis of Figure 8;

[0049] Figure 13 is a schematic diagram of the distribution of light-transmitting holes formed by stacking an active layer, a first source / drain metal layer, and a second source / drain metal layer in a display panel provided in an embodiment of this disclosure.

[0050] Figure 14 is a schematic diagram of the distribution of light-transmitting holes formed by stacking the active layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer in the display panel provided in the embodiment of this disclosure.

[0051] Figure 15 is a schematic diagram of the layout of the anode layer in the display panel provided in an embodiment of this disclosure;

[0052] Figure 16 is a schematic diagram of the layout of vias including the anode layer and the second planarization layer shown in Figure 15, based on Figure 12.

[0053] Figure 17 is a schematic diagram of the distribution of light-transmitting holes formed by stacking an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and an anode layer in a display panel provided in an embodiment of this disclosure.

[0054] Figure 18 is a schematic diagram of the dimensions of the extended compensation portion provided in an embodiment of this disclosure;

[0055] Figure 19 is a schematic diagram of the dimensions of the compensation graphic provided in an embodiment of this disclosure;

[0056] Figure 20 is a schematic diagram of periodic interference stripes collected in related technologies;

[0057] Figure 21 is a schematic diagram of fingerprint stripes collected in the display panel provided in the embodiment of this disclosure; Detailed Implementation

[0058] To further illustrate the display panel and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0059] Please refer to Figures 1, 3 to 12, 15, and 16. This disclosure provides a display panel including a second initialization signal transmission layer and a plurality of sub-pixels; wherein,

[0060] The sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a second reset transistor T7, and the second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element.

[0061] The second initialization signal transmission layer includes multiple second initialization signal lines Vinit2 and multiple second initialization compensation lines Vinit2'; the second initialization signal line Vinit2 includes a second main body portion 31 and a second extension portion 32, the second main body portion 31 extends along a first direction, the second extension portion 32 extends along a second direction, the second initialization compensation line Vinit2' extends along the second direction, and the first direction intersects with the second direction;

[0062] The second main body 31 is coupled to the first terminal of the corresponding second reset transistor T7; the second extension 32 includes an extension connection portion 320 and an extension compensation portion 321. The first end 320a of the extension connection portion 320 is coupled to the second main body 31, and the second end 320b of the extension connection portion 320 is coupled to the extension compensation portion 321 and the corresponding second initialization compensation line Vinit2', respectively.

[0063] For example, the display panel includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0064] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive it to emit light. The structure of the sub-pixel driving circuit is diverse, for example, it includes a 7T1C (i.e., 7 transistors and 1 capacitor) circuit structure, an 8T1C (i.e., 8 transistors and 1 capacitor) circuit structure, a 9T1C (i.e., 9 transistors and 1 capacitor) circuit structure, etc., but is not limited to these.

[0065] The following section uses the 8T1C circuit structure of the sub-pixel driving circuit as an example to explain the specific structure of the sub-pixel driving circuit in detail.

[0066] As shown in Figure 1, the sub-pixel driving circuit includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a power control transistor T5, a light emission control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst.

[0067] The gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst1, the first terminal of the first reset transistor T1 is coupled to the first initialization signal line Vinit1, and the second terminal of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3.

[0068] The gate of the compensation transistor T2 is coupled to the corresponding first scan line G1. The first terminal of the compensation transistor T2 is coupled to the second terminal of the driving transistor T3, and the second terminal of the compensation transistor T2 is coupled to the gate of the driving transistor T3. For example, the second terminal of the first reset transistor T1 and the second terminal of the compensation transistor T2 are formed into a single structure and coupled to the fourth conductive connection portion 24 through the sixth via Via6. The fourth conductive connection portion 24 is also coupled to the gate of the driving transistor T3 through the seventh via Via7.

[0069] The gate of the data writing transistor T4 is coupled to the corresponding first scan line G1, the first terminal of the data writing transistor T4 is coupled to the corresponding data line DA, and the second terminal of the data writing transistor T4 is coupled to the first terminal of the driving transistor T3.

[0070] The gate of the power control transistor T5 is coupled to the corresponding light emission control signal line EM, the first terminal of the power control transistor T5 is coupled to the power signal line VDD, and the second terminal of the power control transistor T5 is coupled to the first terminal of the driving transistor.

[0071] The gate of the light-emitting control transistor T6 is coupled to the corresponding light-emitting control signal line EM. The first terminal of the light-emitting control transistor T6 is coupled to the second terminal of the driving transistor T3. The second terminal of the light-emitting control transistor T6 is coupled to the anode Ano of the light-emitting element. The cathode of the light-emitting element receives the negative power supply signal VSS.

[0072] The gate of the second reset transistor T7 is coupled to the corresponding second reset signal line Rst2, the first terminal of the second reset transistor T7 is coupled to the second initialization signal line Vinit2, and the second terminal of the second reset transistor T7 is coupled to the anode of the light-emitting element. For example, the second terminal of the light-emitting control transistor T6 and the second terminal of the second reset transistor T7 are formed into a single structure and coupled to the sixth conductive connection portion 26 through the tenth via Via10. The sixth conductive connection portion 26 is also coupled to the eighth conductive connection portion 28 through the eleventh via Via11, and the eighth conductive connection portion 28 is coupled to the anode Ano of the corresponding light-emitting element through the nineteenth via Via19.

[0073] The gate of the third reset transistor T8 is coupled to the corresponding second reset signal line Rst2, the first terminal of the third reset transistor T8 is coupled to the third initialization signal line Vinit3, and the second terminal of the third reset transistor T8 is coupled to the first terminal of the driving transistor T3. For example, the second terminal of the third reset transistor T8 is coupled to the fifth conductive connection portion 25 through the eighth via Via8, and the fifth conductive connection portion 25 is also coupled to the first terminal of the driving transistor T3 through the ninth via Via9.

[0074] The first plate Cst1 of the storage capacitor Cst is reused as the gate T3-g of the driving transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line VDD.

[0075] It should be noted that the display panel includes multiple first reset signal lines Rst1, each of which corresponds to a multi-row sub-pixel driving circuit. The first reset signal line Rst1 is coupled to the gate of each first reset transistor T1 in the corresponding row sub-pixel driving circuit.

[0076] The display panel includes multiple second reset signal lines Rst2, each of which corresponds to a multi-row sub-pixel driving circuit. The second reset signal line Rst2 is coupled to the gate of each second reset transistor T7 and the gate of each third reset transistor T8 in the corresponding row sub-pixel driving circuit.

[0077] The display panel includes multiple first scan lines G1, each of which corresponds to a multi-row sub-pixel driving circuit. Each first scan line G1 is coupled to the gate of each compensation transistor T2 and the gate of each data writing transistor T4 in the corresponding row sub-pixel driving circuit.

[0078] The display panel includes multiple light-emitting control signal lines EM, each of which corresponds to a multi-row sub-pixel driving circuit. Each light-emitting control signal line EM is coupled to the gate of each power control transistor T5 and the gate of each light-emitting control transistor T6 in the corresponding row of sub-pixel driving circuit.

[0079] The display panel includes multiple data lines DA, each corresponding to one of the multiple columns of sub-pixel driving circuits. Each data line DA is coupled to the first terminal of each data writing transistor T4 in its corresponding column of sub-pixel driving circuit. For example, the data line DA is coupled to the corresponding second conductive connection portion 22 via a first via Via1, and the second conductive connection portion 22 is coupled to the first terminal of the corresponding data writing transistor T4 via a second via Via2.

[0080] The display panel includes multiple power lines VDD, each corresponding to one of the multiple columns of sub-pixel driving circuits. Each power line VDD is coupled to the first terminal of each power control transistor T5 and the second plate Cst2 of each storage capacitor Cst in the corresponding column of sub-pixel driving circuits. For example, the power line VDD is coupled to the corresponding third conductive connection 23 via a third via Via3. The third conductive connection 23 is coupled to the first terminal of the corresponding power control transistor T5 via a fourth via Via4, and also to the second plate Cst2 of the corresponding storage capacitor Cst via a fifth via Via5. The sub-pixel driving circuits in the same row are divided into multiple circuit groups, each group containing two adjacent sub-pixel driving circuits. The two third conductive connections in the same circuit group form an integral structure.

[0081] As shown in Figure 2, exemplarily, the display panel includes, sequentially stacked along a direction away from the substrate 70, a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, etc. The display substrate may also include a passivation layer PVX, but is not limited to this.

[0082] For example, the second initialization signal transmission layer includes multiple second initialization signal lines Vinit2 and multiple second initialization compensation lines Vinit2'; the multiple second initialization signal lines Vinit2 are arranged sequentially along the second direction, each second initialization signal line Vinit2 includes at least a portion extending along the first direction, and the second initialization signal lines Vinit2 are disposed in the same layer and with the same material as the first source / drain metal layer; the multiple second initialization compensation lines Vinit2' are arranged sequentially along the first direction, each second initialization compensation line Vinit2' includes at least a portion extending along the second direction, and the second initialization compensation lines Vinit2' are disposed in the same layer and with the same material as the second source / drain metal layer.

[0083] For example, the second initialization signal line Vinit2 includes a second main body 31 and a second extension 32 of an integral structure. The second main body 31 is coupled to the first terminal of the corresponding second reset transistor T7 through a twelfth via Via12. The second extension 32 includes an extension connection portion 320 and an extension compensation portion 321. The first end 320a of the extension connection portion 320 is formed as an integral structure with the second main body 31, and the second end 320b of the extension connection portion 320 is formed as an integral structure with the extension compensation portion 321. The extension connection portion is coupled to the corresponding second initialization compensation line Vinit2' through a thirteenth via Via13.

[0084] For example, the second initialization signal transmission layer includes multiple second initialization signal lines Vinit2 and multiple second initialization compensation lines Vinit2' which are formed together into a mesh structure for transmitting the second initialization signal. The second reset transistor T7 uses the second initialization signal to reset the anode of the light-emitting element.

[0085] As can be seen from the specific structure of the display panel described above, the display panel provided in this embodiment includes a second initialization signal transmission layer comprising multiple second initialization signal lines Vinit2 and multiple second initialization compensation lines Vinit2'. Each second initialization signal line Vinit2 includes a second main body portion 31 and a second extension portion 32. The second main body portion 31 is coupled to the first electrode of the corresponding second reset transistor T7. The second extension portion 32 includes an extension connection portion 320 and an extension compensation portion 321. The first end 320a of the extension connection portion 320 is coupled to the second main body portion 31, and the second end 320b of the extension connection portion 320 is coupled to the extension compensation portion 321 and the corresponding second initialization compensation line Vinit2', respectively. This configuration allows the second initialization signal transmission layer to form a mesh structure, which helps to better reduce the loading when the second initialization signal transmission layer transmits the second initialization signal; simultaneously, it ensures good connection performance between the second initialization signal transmission layer and the first electrode of the second reset transistor T7.

[0086] Furthermore, in the display panel provided in this embodiment, the second extension portion 32 includes an extension connection portion 320 and an extension compensation portion 321. This allows the extension compensation portion 321 to further block the light-transmitting area of ​​the display panel, optimizing the arrangement of light-transmitting holes within the pixel layout period. This effectively reduces the periodic interference stripes collected during fingerprint recognition, and subsequent algorithm optimization can maintain fingerprint recognition accuracy. Therefore, the display panel provided in this embodiment achieves a uniform arrangement of light-transmitting holes formed by various functional patterns with light-blocking properties within a period. This ensures that the consistency difference in the shape of the light-transmitting holes in the horizontal and vertical directions is less than 5%, thereby eliminating the periodic interference stripes collected during fingerprint recognition, improving fingerprint recognition accuracy, and effectively enhancing fingerprint recognition performance.

[0087] As shown in FIG6, in some embodiments, the extended connection portion 320 includes an intermediate portion 320c located between its first end and second end, the intermediate portion 320c having a first width along a first direction, and the width of the extended compensation portion 321 along the first direction being greater than the first width.

[0088] The aforementioned setting ensures that the width of the extended compensation portion 321 along the first direction is greater than the first width, enabling the extended compensation portion 321 to achieve a larger occlusion area relative to the middle portion 320c along the first direction. This further optimizes the arrangement of light-transmitting holes within the pixel layout period, effectively reduces the periodic interference stripes collected during fingerprint recognition, improves the accuracy of fingerprint recognition, and effectively enhances the performance of fingerprint recognition.

[0089] As shown in FIG6, in some embodiments, the width of the extended compensation portion 321 is set to be smaller than the width of the second end 320b of the extended connection portion 320 along the second direction.

[0090] The above configuration allows the extended compensation portion 321 to effectively avoid other functional graphics adjacent to it in the second direction, ensuring a larger occlusion area while avoiding short circuits with other functional graphics, thus guaranteeing the manufacturing yield of the display panel.

[0091] As shown in Figure 18, in some embodiments, the minimum width d1 of the extended compensation portion 321 along the first direction satisfies: 2.8μm≤d1≤3.2μm;

[0092] The maximum width d2 of the extended compensation portion 321 along the first direction satisfies: 5.3μm≤d2≤5.7μm;

[0093] The minimum width d3 of the extended compensation portion 321 along the second direction satisfies: 2.1μm≤d3≤2.5μm;

[0094] The maximum width d4 of the extended compensation portion 321 along the second direction satisfies: 3.4μm≤d3≤3.8μm.

[0095] By setting the dimensions of the extended compensation portion 321 along the first and second directions within the aforementioned range, not only is the light-shielding area of ​​the extended compensation portion 321 increased and the arrangement of light-transmitting holes within the pixel layout cycle further optimized, the extended compensation portion 321 can also effectively avoid other adjacent functional graphics. While ensuring a larger shading area, it avoids short circuits with other functional graphics, thus ensuring the manufacturing yield of the display panel.

[0096] As shown in Figures 6, 9 and 11, in some embodiments, the orthographic projection of the second initialization compensation line Vinit2' onto the substrate of the display panel at least partially overlaps with the orthographic projection of the extended compensation portion 321 onto the substrate.

[0097] As shown in Figures 6, 9, and 11, in some embodiments, the second initialization compensation line Vinit2' includes a plurality of first portions 41, a plurality of second portions 42, and a plurality of third portions 43, wherein the first portions 41 and the second portions 42 are alternately arranged, and a third portion 43 is provided between the first portions 41 and the second portions 42; the first portion 41 includes a connecting pattern 41a and a compensation pattern 41b; the connecting pattern 41a is coupled to the second end 320b of the extended connecting portion 320, and the orthographic projection of the compensation pattern 41b on the substrate at least partially overlaps with the orthographic projection of the extended compensation portion 321 on the substrate; the width of the compensation pattern 41b along the first direction is greater than the width of the third portion 43 along the first direction.

[0098] For example, the first part 41, the second part 42 and the third part 43 are formed as a single structure.

[0099] For example, the width of the connecting pattern 41a along the first direction is greater than the width of the third portion 43 along the first direction. The width of the second portion 42 along the first direction is greater than the width of the third portion 43 along the first direction.

[0100] For example, the connection pattern 41a is coupled to the second end 320b of the extended connection portion 320 via the thirteenth via Via 13.

[0101] For example, the maximum width of the compensation pattern 41b along the first direction is the same as the maximum width of the extended compensation portion 321 along the first direction, and the orthographic projection of the extended compensation portion 321 on the substrate of the display panel is located inside the orthographic projection of the compensation pattern 41b on the substrate.

[0102] The above configuration allows the extended compensation portion 321 and the compensation pattern 41b, which are configured in different layers, to jointly block the light-transmitting area of ​​the display panel, thus better ensuring the light-blocking effect and optimizing the arrangement of light-transmitting holes within the pixel layout cycle, thereby effectively reducing the periodic interference stripes collected during fingerprint recognition.

[0103] As shown in Figure 19, in some embodiments, the minimum width d5 ​​of the compensation pattern 41b along the first direction satisfies: 1.9μm≤d5≤2.3μm;

[0104] The maximum width d6 of the compensation pattern 41b along the first direction satisfies: 5.2μm≤d6≤5.6μm;

[0105] The minimum width d7 of the compensation pattern 41b along the second direction satisfies: 3.4μm≤d7≤3.8μm;

[0106] The maximum width d8 of the compensation pattern 41b along the second direction satisfies: 6μm≤d8≤6.4μm.

[0107] Setting the dimensions of the compensation pattern 41b along the first and second directions within the aforementioned range not only increases the light-blocking area of ​​the compensation pattern 41b and further optimizes the arrangement of light-transmitting holes within the pixel layout cycle, but also enables the compensation pattern 41b to effectively avoid other adjacent functional patterns. While ensuring a larger blocking area, it avoids short circuits with other functional patterns, thus ensuring the manufacturing yield of the display panel.

[0108] As shown in Figures 1, 3 to 12, in some embodiments, the display panel further includes: a first initialization signal transmission layer, the first initialization signal transmission layer including a plurality of first initialization signal lines Vinit1, the first initialization signal lines Vinit1 including at least a portion extending along the first direction;

[0109] The sub-pixel driving circuit further includes a driving transistor T3, a first reset transistor T1, and a first conductive connection portion 21, wherein the second terminal of the first reset transistor T1 is coupled to the gate of the driving transistor T3.

[0110] The first conductive connection portion 21 includes a first main body portion 51, which is coupled to the first electrode of the corresponding first reset transistor T1 and the corresponding first initialization signal line Vinit1.

[0111] As shown in FIG6, part of the first conductive connection portion 21 also includes a first compensation portion 52 coupled to the first main body portion 51. In the layout area of ​​the same row of sub-pixel driving circuits arranged along the first direction, the first compensation portion 52 and the extended compensation portion 321 are alternately arranged along the first direction.

[0112] For example, the first initialization signal transmission layer includes a plurality of first initialization signal lines Vinit1 and a plurality of first initialization compensation lines Vinit1'; the plurality of first initialization signal lines Vinit1 are arranged sequentially along the second direction, each first initialization signal line Vinit1 includes at least a portion extending along the first direction, and the first initialization signal lines Vinit1 are disposed in the same layer and with the same material as the second gate metal layer; the plurality of first initialization compensation lines Vinit1' are arranged sequentially along the first direction, each first initialization compensation line Vinit1' includes at least a portion extending along the second direction, and the first initialization compensation lines Vinit1' are disposed in the same layer and with the same material as the second source / drain metal layer.

[0113] For example, the first main body portion 51 is coupled to the first pole of the corresponding first reset transistor T1 through the fourteenth via Via14, and the first main body portion 51 is coupled to the corresponding first initialization signal line Vinit1 through the fifteenth via Via15.

[0114] For example, a portion of the first conductive connection portion 21 further includes a first compensation portion 52 integrally formed with the first main body portion 51. A portion of the first compensation portion 52 is coupled to the corresponding first initialization compensation line Vinit1' through the sixteenth via Via16, while another portion of the first compensation portion 52 is not coupled to the corresponding first initialization compensation line Vinit1' through the sixteenth via Via16.

[0115] For example, the first initialization signal transmission layer includes multiple first initialization signal lines Vinit1 and multiple first initialization compensation lines Vinit1' which are formed together into a mesh structure for transmitting the first initialization signal. The first reset transistor T1 uses the first initialization signal to reset the gate of the driving transistor T3.

[0116] It should be noted that the layout area of ​​the sub-pixel driving circuits arranged in the same row along the first direction refers to the layout area occupied by all the sub-pixel driving circuits in the same row arranged along the first direction. The layout area occupied by each sub-pixel driving circuit can be a region capable of accommodating that sub-pixel driving circuit. For example, this region can be a rectangular region, but it is not limited to this.

[0117] In the display panel provided in the above embodiments, the first initialization signal transmission layer is configured to include multiple first initialization signal lines Vinit1 and multiple first initialization compensation lines Vinit1', so that the first initialization signal transmission layer forms a grid structure, which is beneficial to better reduce the loading when the first initialization signal transmission layer transmits the first initialization signal.

[0118] Furthermore, in the display panel provided in the above embodiments, the first compensation portion 52 and the extended compensation portion 321 are alternately arranged along the first direction in the layout area of ​​the sub-pixel driving circuits arranged in the same row along the first direction, so that the first compensation portion 52 and the extended compensation portion 321 can alternately block the light-transmitting area of ​​the display panel along the first direction, thereby optimizing the arrangement of light-transmitting holes within the pixel layout cycle. This achieves uniform arrangement of light-transmitting holes formed by various functional graphics with light-blocking properties in the display panel within the cycle, and enables the distribution consistency difference of the light-transmitting hole shape in the horizontal and vertical directions to be less than 5%. This eliminates the periodic interference stripes collected by the display product during fingerprint recognition, improves the accuracy of fingerprint recognition, and effectively enhances the performance of fingerprint recognition.

[0119] More specifically, Figure 13 is a schematic diagram showing the distribution of light-transmitting holes formed by stacking the active layer, the first source / drain metal layer, and the second source / drain metal layer in the display panel provided in the embodiment of this disclosure; Figure 14 is a schematic diagram showing the distribution of light-transmitting holes formed by stacking the active layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer in the display panel provided in the embodiment of this disclosure; Figure 17 is a schematic diagram showing the distribution of light-transmitting holes formed by stacking the active layer, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the anode layer in the display panel provided in the embodiment of this disclosure; it can be seen from the above figures that the light-transmitting holes formed by various functional patterns with light-shielding properties in the display panel are uniformly arranged within a period, and the consistency difference of the shape of the light-transmitting holes in the horizontal and vertical directions within a period is less than 5%.

[0120] Figure 20 is a schematic diagram of periodic interference stripes collected in related technologies; Figure 21 is a schematic diagram of fingerprint stripes collected in a display panel provided in the present disclosure embodiment; by comparing Figure 20 and Figure 21, it can be seen that the periodic interference stripes in the fingerprint stripes collected by the display panel provided in the present disclosure embodiment are eliminated.

[0121] As shown in Figure 6, in some embodiments, the width of the first compensation portion 52 along the first direction is set to be approximately the same as the width of the extended compensation portion 321 along the first direction.

[0122] The above-mentioned configuration improves the consistency of the occlusion width of the first compensation portion 52 and the extended compensation portion 321 in the first direction, further optimizes the arrangement of light-transmitting holes within the pixel layout period, and realizes that the light-transmitting holes formed by various functional graphics with light-blocking properties in the display panel are evenly arranged within the period. It can achieve a consistency difference of less than 5% in the distribution of light-transmitting hole shapes in the horizontal and vertical directions, thereby eliminating the periodic interference stripes collected by the display product during fingerprint recognition, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition.

[0123] As shown in Figures 3 to 16, in some embodiments, the display panel further includes a third initialization signal layer. The third initialization signal transmission layer includes multiple third initialization signal lines Vinit3 and multiple third initialization compensation lines. The multiple third initialization signal lines Vinit3 are arranged sequentially along the second direction, and each third initialization signal line Vinit3 includes at least a portion extending along the first direction. The third initialization signal lines Vinit3 are disposed in the same layer and with the same material as the second gate metal layer. The multiple third initialization compensation lines are arranged sequentially along the first direction, and each third initialization compensation line includes at least a portion extending along the second direction. The third initialization compensation lines are disposed in the same layer and with the same material as the second source / drain metal layer.

[0124] For example, the sub-pixel driving circuit further includes a seventh conductive connection portion 27, which is coupled to the first terminal of the third reset transistor T8 through a seventeenth via Via 17, and coupled to the third initialization signal line Vinit3 through an eighteenth via Via 18. Partially, the seventh conductive connection portion 27 is coupled to the third initialization compensation line through a nineteenth via.

[0125] For example, the multiple first initialization compensation lines Vinit1', multiple second initialization compensation lines Vinit2', and multiple third initialization compensation lines in the display panel form multiple groups of signal lines arranged sequentially along the first direction. Each group of signal lines includes a first initialization compensation line Vinit1', a first second initialization compensation line Vinit2', a third initialization compensation line, and a second second initialization compensation line Vinit2' arranged sequentially along the first direction.

[0126] For example, the third initialization signal transmission layer includes multiple third initialization signal lines Vinit3 and multiple third initialization compensation lines forming a mesh structure for transmitting the third initialization signal. The third reset transistor T8 uses the third initialization signal to reset the first terminal of the driving transistor T3.

[0127] For example, the third initialization compensation line has the same structure as the first initialization compensation line Vinit1', except that it is connected to the corresponding initialization signal line through different vias.

[0128] In the display panel provided in the above embodiments, the third initialization signal transmission layer is configured to include multiple third initialization signal lines Vinit3 and multiple third initialization compensation lines, so that the third initialization signal transmission layer forms a grid structure, which is beneficial to better reduce the loading when the third initialization signal transmission layer transmits the third initialization signal.

[0129] Furthermore, by arranging the first initialization compensation line Vinit1', the second initialization compensation line Vinit2', and the third initialization compensation line in the aforementioned manner, the first initialization compensation line Vinit1', the second initialization compensation line Vinit2', and the third initialization compensation line can periodically block the light-transmitting area of ​​the display panel along the first direction. This optimizes the arrangement of light-transmitting holes within the pixel layout period, enabling the consistency difference of the light-transmitting hole shape distribution in the horizontal and vertical directions to be less than 5%. This eliminates the periodic interference stripes collected by the display product during fingerprint recognition, improves the accuracy of fingerprint recognition, and effectively enhances the performance of fingerprint recognition.

[0130] In some embodiments, the display panel further includes a first source / drain metal layer and a second source / drain metal layer, wherein the first compensation portion 52 is disposed in the same layer and with the same material as the first source / drain metal layer; the extended compensation portion 321 is disposed in the same layer and with the same material as the first source / drain metal layer; and the compensation pattern 41b is disposed in the same layer and with the same material as the second source / drain metal layer.

[0131] The above configuration allows the fabrication of the first compensation portion 52, the extended compensation portion 321, and the compensation pattern 41b to be carried out without introducing additional processes, thus ensuring compatibility with existing processes in the display panel. This configuration also allows the display panel to increase the light-shielding area and optimize the arrangement of light-transmitting holes within the pixel layout cycle simply by designing the first and second source / drain metal layers.

[0132] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0133] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0134] For example, the display panel includes an OLED flexible display panel, and the display device includes an OLED flexible display device, but is not limited thereto.

[0135] In the display panel provided in the above embodiment, the second initialization signal transmission layer includes multiple second initialization signal lines Vinit2 and multiple second initialization compensation lines Vinit2'. Each second initialization signal line Vinit2 includes a second main body portion 31 and a second extension portion 32. The second main body portion 31 is coupled to the first electrode of the corresponding second reset transistor T7. The second extension portion 32 includes an extension connection portion 320 and an extension compensation portion 321. The first end 320a of the extension connection portion 320 is coupled to the second main body portion 31, and the second end 320b of the extension connection portion 320 is coupled to the extension compensation portion 321 and the corresponding second initialization compensation line Vinit2', respectively. This configuration allows the second initialization signal transmission layer to form a mesh structure, which helps to better reduce the loading when the second initialization signal transmission layer transmits the second initialization signal; at the same time, it ensures good connection performance between the second initialization signal transmission layer and the first electrode of the second reset transistor T7.

[0136] Furthermore, in the display panel provided in the above embodiments, the second extension portion 32 includes an extension connection portion 320 and an extension compensation portion 321. This allows the extension compensation portion 321 to further block the light-transmitting area of ​​the display panel, optimizing the arrangement of light-transmitting holes within the pixel layout period. This effectively reduces the periodic interference stripes collected during fingerprint recognition. Subsequent algorithm optimization ensures that the accuracy of fingerprint recognition is not affected. Therefore, the display panel provided in this disclosure embodiment achieves a uniform arrangement of light-transmitting holes formed by various functional patterns with light-blocking properties within a period. This results in a consistency difference of less than 5% in the shape distribution of the light-transmitting holes in both the horizontal and vertical directions, thereby eliminating the periodic interference stripes collected by the display product during fingerprint recognition, improving the accuracy of fingerprint recognition, and effectively enhancing the performance of fingerprint recognition.

[0137] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0138] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0139] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0140] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0141] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0142] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0143] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0144] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0145] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising a second initialization signal transmission layer and a plurality of sub-pixels; The sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a second reset transistor, and the second electrode of the second reset transistor is coupled to the anode of the light-emitting element. The second initialization signal transmission layer includes multiple second initialization signal lines and multiple second initialization compensation lines; The second initialization signal line includes a second main body and a second extension. The second main body extends along a first direction, the second extension extends along a second direction, and the second initialization compensation line extends along the second direction. The first direction intersects the second direction. The second main body is coupled to the first terminal of the corresponding second reset transistor; the second extension includes an extension connection portion and an extension compensation portion, the first end of the extension connection portion is coupled to the second main body, and the second end of the extension connection portion is coupled to the extension compensation portion and the corresponding second initialization compensation line, respectively.

2. The display panel according to claim 1, wherein, The extended connection portion includes an intermediate portion located between its first end and second end, the intermediate portion having a first width along a first direction, and the width of the extended compensation portion along the first direction being greater than the first width.

3. The display panel according to claim 2, wherein, Along the second direction, the width of the extended compensation portion is smaller than the width of the second end of the extended connection portion.

4. The display panel according to any one of claims 1 to 3, wherein, The minimum width d1 of the extended compensation portion along the first direction satisfies: 2.8μm≤d1≤3.2μm; The maximum width d2 of the extended compensation portion along the first direction satisfies: 5.3μm≤d2≤5.7μm; The minimum width d3 of the extended compensation portion along the second direction satisfies: 2.1μm≤d3≤2.5μm; The maximum width d4 of the extended compensation portion along the second direction satisfies: 3.4μm≤d3≤3.8μm.

5. The display panel according to any one of claims 1 to 3, wherein, The display panel also includes a first source / drain metal layer, and the extended compensation portion is made of the same material as the first source / drain metal layer.

6. The display panel according to claim 1, wherein, The orthographic projection of the second initialization compensation line on the substrate of the display panel at least partially overlaps with the orthographic projection of the extended compensation portion on the substrate.

7. The display panel according to claim 6, wherein, The second initialization compensation line includes multiple first parts, multiple second parts, and multiple third parts, with the first parts and second parts alternately arranged, and a third part between the first parts and the second parts; The first part includes a connection pattern and a compensation pattern; the connection pattern is coupled to the second end of the extended connection portion, and the orthographic projection of the compensation pattern on the substrate at least partially overlaps with the orthographic projection of the extended compensation portion on the substrate. The width of the compensation pattern along the first direction is greater than the width of the third part along the first direction.

8. The display panel according to claim 7, wherein, The maximum width of the compensation pattern along the first direction is the same as the maximum width of the extended compensation portion along the first direction, and the orthographic projection of the extended compensation portion on the substrate of the display panel is located inside the orthographic projection of the compensation pattern on the substrate.

9. The display panel according to any one of claims 7 or 8, wherein, The minimum width d5 ​​of the compensation pattern along the first direction satisfies: 1.9μm≤d5≤2.3μm; The maximum width d6 of the compensation pattern along the first direction satisfies: 5.2μm≤d6≤5.6μm; The minimum width d7 of the compensation pattern along the second direction satisfies: 3.4μm≤d7≤3.8μm; The maximum width d8 of the compensation pattern along the second direction satisfies: 6μm≤d8≤6.4μm.

10. The display panel according to claim 7 or 8, wherein, The display panel also includes a second source / drain metal layer, and the compensation pattern is set in the same layer and material as the second source / drain metal layer.

11. The display panel according to claim 1, wherein, The display panel also includes: A first initialization signal transmission layer, the first initialization signal transmission layer including a plurality of first initialization signal lines, the first initialization signal lines including at least a portion extending along the first direction; The sub-pixel driving circuit further includes a driving transistor, a first reset transistor, and a first conductive connection portion, wherein the second terminal of the first reset transistor is coupled to the gate of the driving transistor; The first conductive connection portion includes a first main body portion, which is coupled to the first electrode of the corresponding first reset transistor and the corresponding first initialization signal line, respectively. The first conductive connection portion further includes a first compensation portion coupled to the first main body portion. In the layout area of ​​the same row of sub-pixel driving circuits arranged along the first direction, the first compensation portion and the extended compensation portion are alternately arranged along the first direction.

12. The display panel according to claim 11, wherein, The first initialization signal transmission layer further includes: multiple first initialization compensation lines, which extend along the second direction and are coupled to the corresponding first compensation portion.

13. The display panel according to claim 12, wherein, The width of the first compensation portion along the first direction is approximately the same as the width of the extended compensation portion along the first direction.

14. The display panel according to any one of claims 11 to 13, wherein, The display panel further includes a first source / drain metal layer, and the first compensation portion is disposed in the same layer and with the same material as the first source / drain metal layer.

15. A display device comprising a display panel as claimed in any one of claims 1 to 14.

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