Display panel and display apparatus

Abstract

A display panel, comprising: a substrate; and a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing control lines and a plurality of multiplexing data lines, which are disposed on the substrate. At least one multiplexing circuit is connected to the plurality of multiplexing control lines, at least two of the plurality of data lines and at least one of the plurality of multiplexing data lines. The at least one multiplexing circuit comprises a plurality of multiplexing control transistors, at least one multiplexing control transistor comprising a first gate electrode, a second gate electrode and an active layer, wherein the first gate electrode is located on the side of the active layer that is away from the substrate, and the second gate electrode is located on the side of the active layer that is close to the substrate; and the second gate electrode is configured to receive a regulated voltage signal or is connected to the first gate electrode.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202510207168.8, filed on February 24, 2025, entitled “Display Panel and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display panel and display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a display panel and a display device.

[0006] On one hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing control lines, and a plurality of multiplexing data lines. The plurality of data lines are connected to the plurality of sub-pixels. The plurality of multiplexing circuits, the plurality of multiplexing control lines, and the plurality of multiplexing data lines are located on one side of the plurality of sub-pixels. At least one of the plurality of multiplexing circuits is connected to at least two of the plurality of multiplexing control lines, at least one of the plurality of multiplexing data lines, and at least one of the plurality of multiplexing data lines. The at least one multiplexing circuit includes: a plurality of multiplexing control transistors. The at least one of the plurality of multiplexing control transistors includes: a first gate, a second gate, and an active layer. The first gate is located on the side of the active layer away from the substrate, and the second gate is located on the side of the active layer closer to the substrate. The second gate is configured to receive a regulated signal or is connected to the first gate.

[0007] In some exemplary embodiments, the at least one multiplexing circuit is configured to, under the control of the plurality of multiplexing control lines, time-division multiplex the signal transmitted by the at least one multiplexed data line to the at least two data lines.

[0008] In some exemplary embodiments, the second gates of the plurality of multiplexing control transistors of the at least one multiplexing circuit are integral structures and configured to receive regulated signals; the orthographic projection of the integral structure onto the substrate includes the orthographic projection of the active layer of the plurality of multiplexing control transistors onto the substrate.

[0009] In some exemplary embodiments, the display panel further includes: a first shielding structure, the orthographic projection of the first shielding structure onto the substrate at least partially overlapping the orthographic projections of the plurality of sub-pixels onto the substrate, the first shielding structure being connected to a second gate of the plurality of multiplexed control transistors.

[0010] In some exemplary embodiments, at least one of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit, the pixel circuit including a driving transistor, and the orthographic projection of the first occlusion structure onto the substrate includes the orthographic projection of the channel region of the active layer of the driving transistor of the pixel circuit onto the substrate.

[0011] In some exemplary embodiments, the pixel circuit is connected to a first power line, the light-emitting element is connected to a second power line, and the first power signal provided by the first power line is greater than the second power signal provided by the second power line; the regulated signal includes the first power signal.

[0012] In some exemplary embodiments, the at least one multiplexing circuit includes: multiple sets of multiplexing units, each set of multiplexing units including multiple multiplexing control transistors; the first gate and the second gate of the multiple multiplexing control transistors of a set of multiplexing units are connected to the same multiplexing control line, and the second gate of the multiple multiple multiplexing control transistors of the set of multiplexing units is an integral structure.

[0013] In some exemplary embodiments, the display panel further includes at least one of the following: a first shielding structure and a second shielding structure. The first shielding structure includes: a plurality of shielding strips; the at least one multiplexing circuit includes: a plurality of multiplexing units, at least one of the multiple multiplexing units including at least one multiplexing control transistor; the orthographic projection of at least one of the plurality of shielding strips onto the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of two adjacent multiplexing units onto the substrate. The second shielding structure is located on the side of the plurality of multiplexing circuits away from the substrate, and the orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projections of the plurality of multiplexing circuits onto the substrate.

[0014] In some exemplary embodiments, the second shielding structure is located on the side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of perforations.

[0015] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate, wherein the first shielding structure is located on the second source / drain metal layer.

[0016] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a light-emitting element, the light-emitting element including a first electrode, a light-emitting functional layer and a second electrode arranged sequentially along a direction away from the substrate, and the second shielding structure is arranged in the same layer as the first electrode of the light-emitting element.

[0017] In some exemplary embodiments, the substrate includes a display area and a first border area located on one side of the display area, and the plurality of sub-pixels are located in the display area; the first border area includes: a first sub-region, a bending region and a second sub-region arranged sequentially along a direction away from the display area, and the plurality of multiplexing circuits are located in the first sub-region or the second sub-region.

[0018] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0019] On the other hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, and a plurality of multiplexing circuits. The substrate includes a display area and a first border area located on one side of the display area; the plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels. The plurality of multiplexing circuits are located in the first border area and are connected to the plurality of data lines. The display panel further includes at least one of the following: a first shielding structure and a second shielding structure. The first shielding structure is located in the first border area and includes a plurality of shielding strips; at least one multiplexing circuit includes a plurality of multiplexing units, and at least one multiplexing unit includes at least one multiplexing control transistor; the orthographic projection of the shielding strips on the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of two adjacent multiplexing units on the substrate. The second shielding structure is located in the first border area and on the side of the plurality of multiplexing circuits away from the substrate; the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projections of the plurality of multiplexing circuits on the substrate.

[0020] In some exemplary embodiments, the second shielding structure is located on the side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of perforations.

[0021] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate, wherein the first shielding structure is located on the second source / drain metal layer.

[0022] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a light-emitting element, the light-emitting element including a first electrode, a light-emitting functional layer and a second electrode arranged sequentially along a direction away from the substrate, and the second shielding structure is arranged in the same layer as the first electrode of the light-emitting element.

[0023] In some exemplary embodiments, the first border area includes: a first sub-region, a bending region, and a second sub-region arranged sequentially along a direction away from the display area, wherein the plurality of multiplexing circuits are located in the second sub-region.

[0024] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0025] Overview of the attached figures

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0027] Figure 1A is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0028] Figure 1B is another schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0029] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0030] Figure 3 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0031] Figure 4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0032] Figure 5 is a partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0033] Figure 6A is a schematic diagram of the bottom shielding metal layer in Figure 5;

[0034] Figure 6B is a schematic diagram of the semiconductor layer, the first conductive layer and the second conductive layer in Figure 5;

[0035] Figure 6C is a schematic diagram of the bottom shielding metal layer, semiconductor layer, first conductive layer and second conductive layer in Figure 5.

[0036] Figure 7 is another equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0037] Figure 8 is another partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0038] Figure 9A is a schematic diagram of the bottom shielding metal layer in Figure 8;

[0039] Figure 9B is a schematic diagram of the bottom shielding metal layer and semiconductor layer in Figure 8;

[0040] Figure 9C is a schematic diagram of the semiconductor layer and the first conductive layer in Figure 8;

[0041] Figure 10 is another equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0042] Figure 11 is another partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0043] Figure 12A is a schematic diagram of the bottom shielding metal layer in Figure 11;

[0044] Figure 12B is a schematic diagram of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer in Figure 11;

[0045] Figure 13 is another partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0046] Figure 14 is another partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0047] Figure 15 is a schematic diagram of the second shielding structure in Figure 14;

[0048] Figure 16 is another partial plan view of a display panel according to at least one embodiment of the present disclosure;

[0049] Figure 17 is another schematic diagram of the first border area of ​​a display panel according to at least one embodiment of the present disclosure;

[0050] Figure 18 is a schematic diagram of the bending of a display panel according to at least one embodiment of the present disclosure;

[0051] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0052] Detailed Explanation

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0054] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0055] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0056] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0057] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or link; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Linkage" can include "electrical connection." "Electrical connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0058] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0059] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0060] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0061] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0062] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0063] In this disclosure, "about" and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "same" can include cases where index values ​​differ by no more than 10%.

[0064] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0065] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The phrase "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The phrase "the shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0066] As display technology evolves towards higher integration and lower cost, the trend of OLED display products expanding from small-sized mobile phones and watches to medium-sized applications is becoming increasingly apparent. Demand for medium-sized displays, such as tablets and automotive products, is growing rapidly, and the need for lower costs is attracting increasing market attention. Demultiplexers can effectively reduce the number of data channels, thereby reducing the number of integrated circuits (ICs) or supporting low-cost, low-channel-count ICs. However, process variations or extreme temperature conditions during actual use can cause threshold voltage shifts in transistors, easily affecting the output stability of the demultiplexer and consequently impacting the display quality of the display panel. For example, demultiplexers often use low-temperature polysilicon thin-film transistors (LTPS), whose threshold voltages are unstable and have poor uniformity. After prolonged reliability testing, the threshold voltage can easily deviate beyond the operating range of the demultiplexer, leading to abnormal display.

[0067] This embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing control lines, and a plurality of multiplexing data lines. The plurality of data lines are connected to the plurality of sub-pixels. The plurality of multiplexing circuits, the plurality of multiplexing control lines, and the plurality of multiplexing data lines are located on one side of the plurality of sub-pixels. At least one of the plurality of multiplexing circuits is connected to at least two of the plurality of multiplexing control lines, at least one of the plurality of multiplexing data lines, and at least one of the plurality of multiplexing data lines. At least one multiplexing circuit includes a plurality of multiplexing control transistors, and at least one of the plurality of multiplexing control transistors includes: a first gate, a second gate, and an active layer. The first gate is located on the side of the active layer away from the substrate, and the second gate is located on the side of the active layer closer to the substrate. The second gate is configured to receive a regulated signal or is connected to the first gate.

[0068] In the display panel provided in this embodiment, the multiplexing control transistor of the multiplexing circuit includes a first gate and a second gate. The second gate can receive a regulated signal or be connected to the first gate, which can effectively improve the characteristic stability of the multiplexing control transistor, ensure the output stability of the multiplexing circuit, and thus guarantee the display quality of the display panel. Moreover, by improving the characteristic stability of the multiplexing circuit itself, it is beneficial to improve the anti-interference capability of the multiplexing circuit against external signals.

[0069] In some exemplary embodiments, at least one multiplexing circuit can be configured to, under the control of multiple multiplexing control lines, time-division multiplex the signal transmitted by at least one multiplexed data line to at least two data lines. For example, the multiplexing circuit can be connected to two multiplexing control lines, and under the control of the two multiplexing control lines, time-division multiplex the signal transmitted by one multiplexed data line to two data lines.

[0070] In some exemplary embodiments, the second gates of multiple multiplexing control transistors in at least one multiplexing circuit are a single, integral structure configured to receive a regulated signal; the orthographic projection of the integral structure onto the substrate may include the orthographic projection of the active layer of the multiple multiplexing control transistors onto the substrate. This example improves the characteristic stability of the multiplexing control transistors by configuring the second gates of the multiple multiplexing control transistors to receive a regulated signal.

[0071] In some exemplary embodiments, at least one multiplexing circuit may include: multiple sets of multiplexing units, each set of multiplexing units including multiple multiplexing control transistors; the first gate and second gate of the multiple multiplexing control transistors in one set of multiplexing units are connected to the same multiplexing control line, and the second gates of the multiple multiplexing control transistors in one set of multiplexing units are of a single integrated structure. This example improves the characteristic stability of the multiplexing control transistors by connecting the second gates of the multiple multiplexing control transistors to their first gates.

[0072] In some exemplary embodiments, the display panel may further include at least one of the following: a first shielding structure and a second shielding structure. The first shielding structure may include: a plurality of shielding strips; the at least one multiplexing circuit includes: a plurality of multiplexing units, at least one multiplexing unit including at least one multiplexing control transistor; the orthographic projection of the shielding strips onto the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of two adjacent multiplexing units onto the substrate. The second shielding structure may be located on the side of the plurality of multiplexing circuits away from the substrate, and the orthographic projection of the second shielding structure onto the substrate at least partially overlaps with the orthographic projections of the plurality of multiplexing circuits onto the substrate. This example demonstrates that by setting the first shielding structure, signal shielding can be performed between adjacent multiplexing units to prevent crosstalk; by setting the second shielding structure, interference from other signals (such as touch signals, antenna signals, etc.) to the multiplexing circuit can be prevented.

[0073] The following examples illustrate the solution of this embodiment.

[0074] Figure 1A is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 1B is another schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 1A shows a schematic diagram of a small-sized display panel; Figure 1B shows a schematic diagram of a medium-sized display panel.

[0075] In some examples, as shown in Figures 1A and 1B, the display panel can be a closed polygon including linear edges. The display panel can include a display area AA and a border area BB surrounding the display area AA. The border area BB can include a first border area B1 and a second border area B2 located on both sides of the display area AA along a first direction D1, and a third border area B3 and a fourth border area B4 located on both sides of the display area AA along a second direction D2. The first border area B1 can be connected to the third border area B3 and the fourth border area B4, and the second border area B2 can be connected to the third border area B3 and the fourth border area B4. The first border area B1, the second border area B2, the third border area B3, and the fourth border area B4, when connected, can surround the display area AA. For example, the first border area B1 can also be called the lower border area of ​​the display panel, the second border area B2 can also be called the upper border area of ​​the display panel, the third border area B3 can also be called the left border area of ​​the display panel, and the fourth border area B4 can also be called the right border area of ​​the display panel. However, this embodiment is not limited in this respect.

[0076] In some examples, the display area AA may include: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and illumination control signals, or may include scan signals, reset control signals, and illumination control signals.

[0077] In some examples, the second direction D2 can be the extension direction of the grid line GL within the display area AA (e.g., the row direction); the first direction D1 can be the extension direction of the data line DL within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0078] In some examples, a pixel unit of the display area AA may include multiple sub-pixels. For instance, a pixel unit may include four sub-pixels, which may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and two third sub-pixels emitting a third color light (e.g., green light). In other examples, a pixel unit may include three sub-pixels, which may be a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light.

[0079] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves the product yield.

[0080] In some examples, the shape of the light-emitting element of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited to this. In other examples, when a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement.

[0081] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0082] In some examples, as shown in Figure 1A, the first border region B1 may include: a first sub-region B11, a bent region B12, and a second sub-region B13 sequentially disposed along the side away from the display region AA in a first direction D1. The first sub-region B11 may be connected to the display region AA, the third border region B3, and the fourth border region B4. The bent region B12 may be connected between the first sub-region B11 and the second sub-region B13. The bent region B12 may be configured to bend the second sub-region B13 to the back side of the display region AA.

[0083] In some examples, as shown in Figure 1A, the first sub-region B11 may include a first routing area FA1, and multiple multiplexing circuits 30 may be located on the side of the first routing area FA1 near the display area AA. The first routing area FA1 may include multiple multiplexed data lines connected to the multiple multiplexing circuits 30. The multiple multiplexing circuits 30 may be located at the boundary of the first sub-region B11 near the display area AA. In other examples, a portion of the multiple multiplexing circuits may be located in the display area AA, and another portion may be located in the first sub-region B11. In still other examples, the multiple multiplexing circuits may be arranged in the display area AA to reduce the size of the first sub-region B11 along the first direction D1, achieving a narrow bezel design.

[0084] In some examples, as shown in Figure 1A, the second sub-region B13 may include: a second trace area FA2, a first signal access area B131, and a second signal access area B132, sequentially arranged in the first direction D1 away from the bending area B12. The second trace area FA2 may include multiple data lead-out traces for transmitting data signals. These data lead-out traces in the second trace area FA2 may extend to the first signal access area B131. The first signal access area B131 may be provided with multiple first contact pads, which may be configured to connect to an integrated circuit (IC). Some of the multiple first contact pads may be configured to provide data signals through the multiple data lead-out traces. The second signal access area B132 may be provided with multiple second contact pads, which may be configured to bond to an external flexible printed circuit board (FPC). At least one first contact pad in the first signal access area B131 and at least one second contact pad in the second signal access area B132 may be connected via an inner lead bonding (ILB).

[0085] In some examples, as shown in Figure 1B, the first border region B1 may include two first signal access regions B131a and B131b, and two second signal access regions B132a and B132b. The two second signal access regions B132a and B132b may be located on the side of the two first signal access regions B131a and B131b away from the display region AA. Multiple multiplexing circuits 30 may be located in a first sub-region B11 of the first border region B1, and two routing areas FAa and FAb may be located in a second sub-region B13. The two routing areas FAa and FAb may include multiple multiplexed data lines connected to the multiple multiplexing circuits 30. The two first signal access regions B131a and B131b may be arranged along a second direction D2, and the two second signal access regions B132a and B132b may also be arranged along a second direction D2.

[0086] In some examples, as shown in Figure 1B, the third border area B3 can be provided with a first gate driving circuit 191, and the fourth border area B4 can be provided with a second gate driving circuit 192. The first gate driving circuit 191 and the second gate driving circuit 192 can be connected to multiple gate lines GL of the display area AA and configured to provide pixel control signals to the pixel circuits of multiple sub-pixels PX of the display area AA.

[0087] In some examples, as shown in Figure 1B, the bezel area BB may be provided with a first bezel power line VLD and a second bezel power line VLS. The first bezel power line VLD may be located on the side of the second bezel power line VLS closer to the display area AA. The second bezel power line VLS may be located on the side of the first gate drive circuit 191 and the second gate drive circuit 192 away from the display area AA, and the first bezel power line VLD may be located on the side of the first gate drive circuit 191 and the second gate drive circuit 192 closer to the display area AA. One end of the first bezel power line VLD may be connected to a second contact pad in the second signal access area B132a, and the other end may be connected to a second contact pad in the second signal access area B132b. One end of the second bezel power line VLS may be connected to a second contact pad in the second signal access area B132a, and the other end may be connected to a second contact pad in the second signal access area B132b. The first border power line VLD can be configured to provide a first power signal to the pixel circuit of multiple sub-pixels PX, and the second border power line VLS can be configured to provide a second power signal to the light-emitting elements of multiple sub-pixels PX. The first power signal can be greater than the second power signal.

[0088] In some examples, as shown in Figure 1B, the first sub-region B11 of the first border region B1 may further include: a first power connection line 81, a second power connection line 82, and a plurality of third power connection lines 83. The first power connection line 81 and the second power connection line 82 may extend along a second direction D2. The first power connection line 81 may be located on the side of the plurality of multiplexing circuits 30 closer to the display area AA, and the second power connection line 82 may be located on the side of the plurality of multiplexing circuits 30 farther from the display area AA. The plurality of third power connection lines 83 may extend along a first direction D1 and connect the first power connection line 81 and the second power connection line 82. The orthographic projection of the third power connection line 83 onto the substrate may overlap with the orthographic projection of the plurality of multiplexing circuits 30 onto the substrate.

[0089] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is illustrated using a 7T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include a first transistor (also referred to as a first reset transistor) T1, a second transistor (also referred to as a threshold compensation transistor) T2, a third transistor (also referred to as a driving transistor) T3, a fourth transistor (also referred to as a data writing transistor) T4, a fifth transistor (also referred to as a first light-emitting control transistor) T5, a sixth transistor (also referred to as a second light-emitting control transistor) T6, a seventh transistor (also referred to as a second reset transistor) T7, and a storage capacitor Cst. The light-emitting element EL may include a first electrode, a second electrode, and a light-emitting functional layer disposed between the first electrode and the second electrode. The first electrode of the light-emitting element EL may be an anode, and the second electrode of the light-emitting element EL may be a cathode.

[0090] In some examples, as shown in Figure 2, the display panel may include: a scan line GAL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first power signal to the pixel circuit, and the second power line PL2 can be configured to provide a constant second power signal to the cathode of the light-emitting element EL, wherein the first power signal is greater than the second power signal. The first power line PL1 can be connected to a first frame power line VLD, and the second power line PL2 can be connected to a second frame power line VLS. The scan line GAL can be configured to provide a scan signal to the pixel circuit, the data line DL can be configured to provide a data signal to the pixel circuit, the light emission control line EML can be configured to provide a light emission control signal to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit. In some examples, the second reset control line RST2, electrically connected to the pixel circuit in row j, and the first reset control line RST1, electrically connected to the pixel circuit in row j+1, can be a single integrated structure. Here, j is an integer greater than 0. This reduces the number of signal lines on the display panel, enabling a narrow bezel design.

[0091] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals may be constant voltage signals, the magnitude of which may be, for example, between a first power supply signal and a second power supply signal, but is not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0092] In some examples, as shown in Figure 2, the third transistor T3 is electrically connected to the light-emitting element EL and outputs a drive current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal, data signal, first power signal, and second power signal. The gate of the fourth transistor T4 is electrically connected to the scan line GAL, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GAL, the second terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the first terminal of the second transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the fifth transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power line PL1, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The gates of the first transistor T1 and the third transistor T3 are electrically connected, and the third transistor T3 is configured to reset its gate. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL, and the seventh transistor T7 is configured to reset its anode. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0093] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0094] Figure 3 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 3 illustrates the structure of a sub-pixel of the display area as an example. Figure 3 also illustrates the pixel circuit of each sub-pixel, including a transistor 16 and a capacitor 17 as an example. The transistor 16 can be a low-temperature polycrystalline silicon thin-film transistor. For example, the transistor 16 can be the sixth transistor T6 or the seventh transistor T7 of the pixel circuit shown in Figure 2, and the capacitor 17 can be the storage capacitor Cst of the pixel circuit shown in Figure 2.

[0095] In some examples, as shown in Figure 3, the display panel may include a substrate 100, and a circuit structure layer 120, a light-emitting structure layer 130, and an encapsulation structure layer 140 sequentially disposed on the substrate 100. The circuit structure layer 120 of the display area may include pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 130 of the display area may include light-emitting elements for multiple sub-pixels. In other examples, a touch structure layer may be disposed on the side of the encapsulation structure layer 140 away from the substrate 100 to integrate touch functionality.

[0096] In some examples, the circuit structure layer 120 of the display panel may include: a bottom shielding metal (BSM) layer 200 disposed on the substrate 100, a semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source / drain metal layer) and a fourth conductive layer (also referred to as a second source / drain metal layer). A first insulating layer (also called a buffer layer) 101 may be disposed between the bottom shielding metal layer 200 and the semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be disposed between the semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be disposed between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be disposed between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first planarization layer) 106 may be disposed between the third conductive layer and the fourth conductive layer, wherein the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 100; and a seventh insulating layer (also called a second planarization layer) 107 may be disposed on the side of the fourth conductive layer away from the substrate 100. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be inorganic insulating layers, while the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers. However, this embodiment is not limited to these limitations. In other examples, the fifth insulating layer may be omitted between the third and fourth conductive layers, and only the sixth insulating layer may be provided between the third and fourth conductive layers.

[0097] In some examples, the substrate 100 can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0098] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0099] In some examples, as shown in FIG3, the semiconductor layer of the display area may include an active layer 160 of the transistor 16 of the pixel circuit. The active layer 160 of the transistor 16 may include a first region 1601, a second region 1602, and a channel region 1600 located between the first region 1601 and the second region 1602. The first conductive layer may include a gate 163 of the transistor 16 and a first electrode 171 of the capacitor 17. The orthographic projection of the gate 163 of the transistor 16 onto the substrate 100 may cover the orthographic projection of the channel region 1600 of the active layer 160 onto the substrate 100. The second conductive layer may include a second electrode 172 of the capacitor 17. The orthographic projections of the second electrode 172 and the first electrode 171 of the capacitor 17 onto the substrate 100 may at least partially overlap, for example, they may coincide.

[0100] In some examples, as shown in Figure 3, the third conductive layer of the display area may include a source 161 and a drain 162 of transistor 16. The source 161 of transistor 16 may be electrically connected to the first region 1601 of the active layer 160, and the drain 162 may be electrically connected to the second region 1602 of the first active layer 160. The fourth conductive layer may include an anode transition electrode 181. The anode transition electrode 181 may be electrically connected to the drain 162 of transistor 16 of the pixel circuit through vias formed in the fifth insulating layer 105 and the sixth insulating layer 106. In this example, the anode transition electrode 181 enables the electrical connection between the pixel circuit and the light-emitting element.

[0101] In some examples, as shown in Figure 3, the light-emitting structure layer 130 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, a light-emitting functional layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on a seventh insulating layer 107 and electrically connected to an anode transfer electrode 181 through a via formed in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the light-emitting functional layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the light-emitting functional layer 132 and connected to the light-emitting functional layer 132. The light-emitting functional layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0102] In some examples, the light-emitting functional layer 132 of the light-emitting element may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0103] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the light-emitting functional layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0104] In some examples, as shown in Figure 3, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, which can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, such as polymer materials containing desiccants or polymer materials that can block moisture, or polymer resins to planarize the surface of the display panel and relieve stress on the first and third encapsulation layers 141 and 143. It may also include water-absorbing materials such as desiccants to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0105] Figure 4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 4 illustrates a multiplexing circuit employing a 1:2 design. This example multiplexing circuit can provide data signals from three multiplexed data lines to six data lines. In some examples, as shown in Figure 4, a multiplexing circuit can be electrically connected to two multiplexed control lines (e.g., including a first multiplexed control line ML1 and a second multiplexed control line ML2), three multiplexed data lines (e.g., including a first multiplexed data line SL1, a second multiplexed data line SL2, and a third multiplexed data line SL3), and multiple data lines (e.g., including first data lines DL1 to sixth data lines DL6).

[0106] In some examples, the multiplexing circuit may include six multiplexing control transistors (i.e., first multiplexing control transistor M1 to sixth multiplexing control transistor M6). The first gate of the first reset control transistor M1, the first gate of the second multiplexing control transistor M2, and the first gate of the third multiplexing control transistor M3 may be connected to the first multiplexing control line ML1, and the first gate of the fourth multiplexing control transistor M4, the first gate of the fifth multiplexing control transistor M5, and the first gate of the sixth multiplexing control transistor M6 may be connected to the second multiplexing control line ML2.

[0107] In some examples, the second gates of the first multiplexing control transistor M1, the second multiplexing control transistor M2, the third multiplexing control transistor M3, the fourth multiplexing control transistor M4, the fifth multiplexing control transistor M5, and the sixth multiplexing control transistor M6 can be electrically connected to the voltage regulator line VL and configured to receive a regulated signal. For example, the regulated signal may include a first power supply signal. The fact that the second gates of the six multiplexing control transistors in this example multiplexing circuit receive the regulated signal can improve the characteristic stability of the multiplexing control transistors. For example, the threshold voltage of the multiplexing control transistors can be reduced by 0.5V to 1.5V; for instance, the threshold voltage of the multiplexing control transistors can be reduced from 2.7V to approximately 1.2V.

[0108] In some examples, the first terminals of the first multiplexed control transistor M1 and the fourth multiplexed control transistor M4 can be connected to the first multiplexed data line SL1; the first terminals of the second multiplexed control transistor M2 and the fifth multiplexed control transistor M5 can be connected to the second multiplexed data line SL2; and the first terminals of the third multiplexed control transistor M3 and the sixth multiplexed control transistor M6 can be connected to the third multiplexed data line SL3. The second terminal of the first multiplexed control transistor M1 is connected to the first data line DL1; the second terminal of the second multiplexed control transistor M2 is connected to the second data line DL2; the second terminal of the third multiplexed control transistor M3 is connected to the third data line DL3; the second terminal of the fourth multiplexed control transistor M4 is connected to the fourth data line DL4; the second terminal of the fifth multiplexed control transistor M5 is connected to the fifth data line DL5; and the second terminal of the sixth multiplexed control transistor M6 is connected to the sixth data line DL6.

[0109] In some examples, each data line may be connected to at least one column of pixel circuits within the display area AA. A column of pixel circuits may include multiple pixel circuits arranged along a first direction D1. For example, a first data line DL1 may be connected to the pixel circuit of a first sub-pixel emitting a first color light (e.g., red light R), a second data line DL2 may be connected to the pixel circuit of a third sub-pixel emitting a third color light (e.g., green light G), a third data line DL3 may be connected to the pixel circuit of a second sub-pixel emitting a second color light (e.g., blue light B), a fourth data line DL4 may be connected to the pixel circuit of a first sub-pixel emitting the first color light (e.g., red light R), a fifth data line DL5 may be connected to the pixel circuit of a third sub-pixel emitting the third color light (e.g., green light G), and a sixth data line DL6 may be connected to the pixel circuit of a second sub-pixel emitting the second color light (e.g., blue light B).

[0110] In some examples, under the control of the first multiplexing control line ML1, the multiplexing circuit can provide data signals to the first data line DL1, the second data line DL2, and the third data line DL3. Under the control of the second multiplexing control line ML2, the multiplexing circuit can provide data signals to the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6.

[0111] Figure 5 is a partial planar schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 6A is a schematic diagram of the bottom shielding metal layer in Figure 5; Figure 6B is a schematic diagram of the semiconductor layer, the first conductive layer, and the second conductive layer in Figure 5; Figure 6C is a schematic diagram of the bottom shielding metal layer, the semiconductor layer, the first conductive layer, and the second conductive layer in Figure 5. Figure 5 illustrates two multiplexed circuits 30 in the first frame region as an example. The film layer structure of the display panel in this example can be as shown in Figure 3.

[0112] In some examples, as shown in Figures 5 to 6C, the bottom shielding metal layer may include: a first shielding structure 201 located in the display area AA, a first connecting structure 211 and a second connecting structure 212 located in the first sub-area B11 of the first border area, and a plurality of first shielding blocks 220. The first shielding structure 201, the first connecting structure 211, the second connecting structure 212, and the plurality of first shielding blocks may be an integral structure. The first shielding structure 201 and the first connecting structure 211 may be directly connected. The first connecting structure 211 may extend along the second direction D2 and connect with the plurality of second connecting structures 212. The plurality of second connecting structures 212 may extend along the first direction D1 and be arranged sequentially along the second direction D2. The plurality of first shielding blocks 220 may extend along the first direction D1 and be arranged sequentially along the second direction D2. A single first shielding block 220 may be connected to three second connecting structures 212. The orthographic projection of a single first shielding block 220 onto the substrate may be rectangular.

[0113] In some examples, as shown in Figures 5 to 6C, the semiconductor layer of the first sub-region B11 may include: active layers of multiple multiplexed control transistors (e.g., active layers M10a, M10b, M10c, and M10d of the first multiplexed control transistor M1, active layers M20a, M20b, M20c, and M20d of the second multiplexed control transistor M2, and active layers M30a, M30b, M30c, and M30d of the third multiplexed control transistor M3). The active layers M10a, M10b, M10c, and M10d of the first multiplexed control transistor M1 may be aligned along a first direction D1, and the active layers M10a of the first multiplexed control transistor M1, M20a of the second multiplexed control transistor M2, and M30a of the third multiplexed control transistor M3 may be aligned along a second direction D2. The orthographic projection of a single active layer of a single multiplexed control transistor onto the substrate may be approximately rectangular. The orthographic projection of a single first blocking block 220 onto the substrate can include the orthographic projection of the active layers of three multiplexed control transistors onto the substrate. A single first blocking block 220 can be multiplexed as the second gate of three multiplexed control transistors. For example, the second gates of the first multiplexed control transistor M1, the second multiplexed control transistor M2, and the third multiplexed control transistor M3 can be a single structure, which can be a single first blocking block 220. In this example, the second gates of three multiplexed control transistors connected to the same multiplexing control line in a multiplexing circuit can be a single structure.

[0114] In some examples, the first conductive layer of the first sub-region B11 may include: first gates of multiple multiplexed control transistors (e.g., first gate M13 of first multiplexed control transistor M1, first gate M23 of second multiplexed control transistor M2, first gate M33 of third multiplexed control transistor M3, first gate M43 of fourth multiplexed control transistor M4, first gate M53 of fifth multiplexed control transistor M5, and first gate M63 of sixth multiplexed control transistor M6), multiple first connection blocks (e.g., first connection blocks 411, 412, 413, 414, 415, and 416), multiple second connection blocks (e.g., second connection blocks 421, 422, 423, 424, 425, and 426), and multiple multiplexed data lines (e.g., second multiplexed data line SL2). The second conductive layer of the first sub-region B11 may include multiple multiplexed data lines (e.g., first multiplexed data line SL1 and second multiplexed data line SL2).

[0115] In some examples, multiple first connection blocks may be located on the side of the first gate of multiple multiplexed control transistors closer to the display area AA, and multiple second connection blocks and multiple multiplexed data lines may be located on the side of the first gate of multiple multiplexed control transistors away from the display area AA.

[0116] In some examples, as shown in Figure 5, the third conductive layer of the first sub-region B11 may include: a first peripheral trace 41, a first multiplexed control line ML1, a second multiplexed control line ML2, multiple third connection blocks (e.g., third connection blocks 431, 432, and 433), and the first and second terminals of multiple multiplexed control transistors (e.g., including the first terminal M11 and the second terminal M12 of the first multiplexed control transistor M1, the first terminal M21 and the second terminal M22 of the second multiplexed control transistor M2, the first terminal M31 and the second terminal M32 of the third multiplexed control transistor M3, the first terminal M41 and the second terminal M42 of the fourth multiplexed control transistor M4, the first terminal M51 and the second terminal M52 of the fifth multiplexed control transistor M5, and the first terminal M61 and the second terminal M62 of the sixth multiplexed control transistor M6). The first multiplexed control line ML1 and the second multiplexed control line ML2 may extend at least along the second direction D2 and be located along the first direction D1 on the side of the multiple multiplexed control transistors away from the display area AA.

[0117] In some examples, the orthographic projection of the first peripheral trace 41 onto the substrate and the orthographic projection of the first connection structure 211 onto the substrate may at least partially overlap. The first peripheral trace 41 may be connected to the first connection structure 211. For example, the first peripheral trace 41 is the first power connection line 81 shown in FIG. 1B. The first peripheral trace 41 may be configured to transmit a first power signal, such that the entire bottom shielding metal layer can transmit the first power signal, and the second gates of multiple multiplexed control transistors receive the first power signal. In other examples, the first peripheral trace 41 may be configured to transmit other regulated signals.

[0118] In some examples, the first terminal M11 of the first multiplexed control transistor M1 can be connected to the first region of the active layers M10a, M10b, M10c, and M10d of the first multiplexed control transistor M1, and can also be connected to the second connection block 421. The first terminal M41 of the fourth multiplexed control transistor M4 can be connected to the first region of the active layer of the fourth multiplexed control transistor M4, and can also be connected to the second connection block 424. The second connection blocks 421 and 424 can be connected to the third connection block 431 located on the third conductive layer, and the third connection block 431 can be connected to a first multiplexed data line SL1 located on the second conductive layer.

[0119] In some examples, the first terminal M21 of the second multiplexed control transistor M2 can be connected to the first region of the active layers M20a, M20b, M20c, and M20d of the second multiplexed control transistor M2, and can also be connected to the second connection block 422. The first terminal M51 of the fifth multiplexed control transistor M5 can be connected to the first region of the active layer of the fifth multiplexed control transistor M5, and can also be connected to the second connection block 425. The second connection blocks 422 and 425 can be connected to the third connection block 432 located on the third conductive layer, and the third connection block 432 can be connected to a second multiplexed data line SL2 located on the first conductive layer.

[0120] In some examples, the first terminal M31 of the third multiplexed control transistor M3 can be connected to the first region of the active layers M30a, M30b, M30c, and M30d of the third multiplexed control transistor M3, and can also be connected to the second connection block 423. The first terminal M61 of the sixth multiplexed control transistor M6 can be connected to the first region of the active layer of the sixth multiplexed control transistor M6, and can also be connected to the second connection block 426. The second connection blocks 423 and 426 can be connected to the third connection block 433 located on the third conductive layer, and the third connection block 433 can be connected to a third multiplexed data line SL3 located on the second conductive layer. In this example, multiple multiplexed data lines can be alternately arranged on the first and second conductive layers.

[0121] In some examples, the second terminal M12 of the first multiplexed control transistor M1 can be connected to the second region of the active layers M10a, M10b, M10c, and M10d of the first multiplexed control transistor M1, and can also be connected to the first connection block 411. The first connection block 411 or the second terminal M12 of the first multiplexed control transistor M1 can be connected to a data line. The second terminal M22 of the second multiplexed control transistor M2 can be connected to the second region of the active layers M20a, M20b, M20c, and M20d of the second multiplexed control transistor M2, and can also be connected to the first connection block 412. The first connection block 412 or the second terminal M22 of the second multiplexed control transistor M2 can be connected to a data line. The second terminal M32 of the third multiplexed control transistor M3 can be connected to the second region of the active layers M30a, M30b, M30c, and M30d of the third multiplexed control transistor M3, and can also be connected to the first connection block 413. The second terminal M32 of the first connection block 413 or the third multiplexed control transistor M3 can be connected to a data line.

[0122] In some examples, the second terminal M42 of the fourth multiplexed control transistor M4 can be connected to the second region of the active layer of the fourth multiplexed control transistor M4, and can also be connected to the first connection block 414. The second terminal M52 of the fifth multiplexed control transistor M5 can be connected to the second region of the active layer of the fifth multiplexed control transistor M5, and can also be connected to the first connection block 415. The second terminal M62 of the sixth multiplexed control transistor M6 can be connected to the second region of the active layer of the sixth multiplexed control transistor M6, and can also be connected to the first connection block 416.

[0123] In some examples, the first gate M13 of the first multiplexed control transistor M1, the first gate M23 of the second multiplexed control transistor M2, and the first gate M33 of the third multiplexed control transistor M3 can be connected to the first multiplexed control line ML1. The first gate M43 of the fourth multiplexed control transistor M4, the first gate M53 of the fifth multiplexed control transistor M5, and the first gate M63 of the sixth multiplexed control transistor M6 can be connected to the second multiplexed control line ML2.

[0124] The display panel in this example integrates the second gates of multiple multiplexing control transistors connected to the same multiplexing control line in the multiplexing circuit into a single structure, and this integrated structure can be configured to receive a first power signal, which can improve the characteristic stability of the multiplexing control transistors and thus improve the reliability of the multiplexing circuit.

[0125] Figure 7 is another equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 7 illustrates a multiplexing circuit employing a 1:2 design. Figure 7 illustrates two multiplexing circuits. The multiplexing circuit of this example can provide a data signal from one multiplexed data line to two data lines in a time-division multiplexing manner. As shown in Figure 7, a multiplexing circuit 30 can be connected to two multiplexed control lines (e.g., including a first multiplexed control line ML1 and a second multiplexed control line ML2), one multiplexed data line SL, and multiple data lines (e.g., a first data line DL1 and a second data line DL2).

[0126] In some examples, the multiplexing circuit 30 may include two multiplexing control transistors (e.g., a seventh multiplexing control transistor M7 and an eighth multiplexing control transistor M8). The first gate of the seventh multiplexing control transistor M7 may be connected to a first multiplexing control line ML1, and the first gate of the eighth multiplexing control transistor M8 may be connected to a second multiplexing control line ML2. The second gates of the seventh multiplexing control transistor M7 and the eighth multiplexing control transistor M8 may be electrically connected to a voltage regulator line VL, configured to receive a regulated signal, such as a first power supply signal.

[0127] In some examples, the first terminals of the seventh multiplexing control transistor M7 and the eighth multiplexing control transistor M8 can be connected to the same multiplexed data line SL. The second terminal of the seventh multiplexing control transistor M7 can be connected to the first data line DL1, and the second terminal of the eighth multiplexing control transistor M8 can be connected to the second data line DL2. A column of sub-pixels connected to the first data line DL1 may include a first sub-pixel emitting red light R and a third sub-pixel emitting green light G, and a column of sub-pixels connected to the second data line DL2 may include a second sub-pixel emitting blue light.

[0128] In some examples, under the control of the first multiplexing control line ML1, the multiplexing circuit can provide a data signal to the first data line DL1, and under the control of the second multiplexing control line ML2, the multiplexing circuit can provide a data signal to the second data line DL2.

[0129] Figure 8 is another partial planar schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 9A is a schematic diagram of the bottom shielding metal layer in Figure 8; Figure 9B is a schematic diagram of the bottom shielding metal layer and the semiconductor layer in Figure 8; Figure 9C is a schematic diagram of the semiconductor layer and the first conductive layer in Figure 8. Figure 8 illustrates four multiplexed circuits 30 in the first frame region as an example. The film layer structure of the display panel in this example can be as shown in Figure 3. Figure 8 mainly illustrates the bottom shielding metal layer, the semiconductor layer, the first conductive layer, and the third conductive layer, omitting the other film layers.

[0130] In some examples, as shown in Figures 8 to 9C, the bottom shielding metal layer may include: a first shielding structure 201 located in the display area AA, and a second shielding block 221 located in the first sub-area B11 of the first border area. The first shielding structure 201 and the second shielding block 221 are directly connected and can be an integral structure. The first shielding structure 201 in the display area AA can be approximately a mesh structure.

[0131] In some examples, the semiconductor layer of the display panel may include: active layers of transistors for multiple pixel circuits located in display area AA (e.g., active layer T20 of the second transistor T2, active layer T30 of the third transistor T3, active layer T40 of the fourth transistor T4, active layer T50 of the fifth transistor T5, active layer T60 of the sixth transistor T6, and active layer T70 of the seventh transistor T7); and active layers of multiple multiplexed control transistors located in the first sub-region B11 (e.g., active layers M70a and M70b of the seventh multiplexed control transistor M7, and active layers M80a and M80b of the eighth multiplexed control transistor M8). The active layers of the seven transistors of a single pixel circuit may be a single, integral structure. The active layer M70a of the seventh multiplexing control transistor M7 and the active layer M80a of the eighth multiplexing control transistor M8 in the multiplexing circuit can be an integral structure, and the active layer M70b of the seventh multiplexing control transistor M7 and the active layer M80b of the eighth multiplexing control transistor M8 can be an integral structure.

[0132] In some examples, the orthographic projection of the second shielding block 221 onto the substrate can cover the orthographic projection of the active layers of multiple multiplexed control transistors onto the substrate. The second shielding block 221 can be reused as an integral structure of the second gates of multiple multiplexed control transistors, and the orthographic projection of this integral structure onto the substrate can include the orthographic projection of the active layers of multiple multiplexed control transistors onto the substrate. The orthographic projection of the first shielding structure 201 onto the substrate can include the orthographic projection of the channel region of the active layer T30 of the third transistor T3 onto the substrate, ensuring the performance of the third transistor T3.

[0133] In some examples, the first conductive layer may include: the scan line GAL, the light emission control line EML, the second reset control line RST2, and the gate of the third transistor T3 of the multiple pixel circuits located in the display area AA; and the first gates of the multiple multiplexed control transistors located in the first sub-region B11 (e.g., including the first gate M73 of the seventh multiplexed control transistor M7 and the first gate M83 of the eighth multiplexed control transistor M8). The gate of the third transistor T3 may be multiplexed as the first electrode of the storage capacitor Cst. The overlapping portion of the scan line GAL with the active layer T40 of the fourth transistor T4 may be multiplexed as the gate of the fourth transistor T4, and the overlapping portion of the scan line GAL with the active layer T20 of the second transistor T2 may be multiplexed as the gate of the second transistor T2. The overlapping portion of the light emission control line EML with the active layer T50 of the fifth transistor T5 may be multiplexed as the gate of the fifth transistor T5, and the overlapping portion of the light emission control line EML with the active layer T60 of the sixth transistor T6 may be multiplexed as the gate of the sixth transistor T6. The overlapping portion of the second reset control line RST2 with the active layer T70 of the seventh transistor T7 can be reused as the gate of the seventh transistor T7. The orthogonal projection of the first gate M73 of the seventh multiplexed control transistor M7 and the first gate M83 of the eighth multiplexed control transistor M8 onto the substrate can be a strip extending along the first direction D1.

[0134] In some examples, the third conductive layer may include: multiple connection electrodes located in the display area AA, first and second electrodes of multiple multiplexed control transistors located in the first sub-region B11 (e.g., first electrode M71 and second electrode M72 of the seventh multiplexed control transistor M7, and first electrode M81 and second electrode M82 of the eighth multiplexed control transistor M8), and a first multiplexed control line ML1 and a second multiplexed control line ML2. The first multiplexed control line ML1 and the second multiplexed control line ML2 may be located on the side of the multiple multiplexed control transistors away from the display area AA. The first electrode M71 of the seventh multiplexed control transistor M7 and the first electrode M81 of the eighth multiplexed control transistor M8 may be a single structure. For example, the first electrodes of the seventh multiplexed control transistor M7 and the first electrodes of the eighth multiplexed control transistor M8 in two adjacent multiplexing circuits 30 may be a single structure and connected to the same multiplexed data line. The second electrode M72 of the seventh multiplexed control transistor M7 may be connected to one data line, and the second electrode M82 of the eighth multiplexed control transistor M8 may be connected to another data line. The first gate M73 of the seventh multiplexing control transistor M7 can be connected to the first multiplexing control line ML1, and the first gate M83 of the eighth multiplexing control transistor M8 can be connected to the second multiplexing control line ML2.

[0135] In some examples, the second blocking block 221 and the first blocking structure 201 of the display area AA can be an integral structure. The first blocking structure 201 can extend to the second border area, the third border area, and the fourth border area, and be connected to the first border power line VLD, thereby receiving the first power signal. In other examples, the second blocking block 221 can be connected to a trace located in the first border area that transmits the first power signal, thereby receiving the first power signal. Further descriptions of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0136] Figure 10 is another equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 10, a multiplexing circuit may include six multiplexing control transistors (i.e., first multiplexing control transistor M1 to sixth multiplexing control transistor M6). The first and second gates of the first multiplexing control transistor M1, the first and second gates of the second multiplexing control transistor M2, and the first and second gates of the third multiplexing control transistor M3 may be connected to the first multiplexing control line ML1, and the first and second gates of the fourth multiplexing control transistor M4, the first and second gates of the fifth multiplexing control transistor M5, and the first and second gates of the sixth multiplexing control transistor M6 may be connected to the second multiplexing control line ML2. Further description of the circuit structure of the multiplexing circuit of this example can be found in the description of the embodiment shown in Figure 4, and will not be repeated here.

[0137] Figure 11 is another partial planar schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 12A is a schematic diagram of the bottom shielding metal layer in Figure 11; Figure 12B is a schematic diagram of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 11. In some examples, as shown in Figures 11 to 12B, the bottom shielding metal layer may include a plurality of first shielding blocks 220a and 220b located in the first frame region. The first shielding blocks 220a and 220b may be arranged at intervals along the second direction D2. The first shielding block 220a may be an integral structure of the second gate of the first multiplexed control transistor M1, the second gate of the second multiplexed control transistor M2, and the second gate of the third multiplexed control transistor M3. The orthographic projection of the first shielding block 220a onto the substrate may include the orthographic projection of the active layers of the first multiplexed control transistor M1, the second multiplexed control transistor M2, and the third multiplexed control transistor M3 onto the substrate. The first shielding block 220a may be connected to the first multiplexed control line ML1.

[0138] In some examples, the first blocking block 220b can be an integral structure of the second gates of the fourth multiplexed control transistor M4, the fifth multiplexed control transistor M5, and the sixth multiplexed control transistor M6. The orthographic projection of the first blocking block 220b onto the substrate can include the orthographic projections of the active layers of the fourth multiplexed control transistor M4, the fifth multiplexed control transistor M5, and the sixth multiplexed control transistor M6 onto the substrate. The first blocking block 220b can be connected to the second multiplexed control line ML2.

[0139] This example improves the stability of the multiplexed control transistor's characteristics by connecting the second gate of the multiplexed control transistor to the first gate. Further descriptions of the display panel in this example can be found in the foregoing embodiments and will not be repeated here.

[0140] Figure 13 is another partial plan view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 13, the multiplexing circuit 30 may include two multiplexing units (e.g., multiplexing units 30-1 and 30-2). A single multiplexing unit may include multiple multiplexing control transistors connected to the same multiplexing control line. For example, multiplexing unit 30-1 may include a first multiplexing control transistor, a second multiplexing control transistor, and a third multiplexing control transistor connected to the first multiplexing control line ML1; multiplexing unit 30-2 may include a fourth multiplexing control transistor, a fifth multiplexing control transistor, and a sixth multiplexing control transistor connected to the second multiplexing control line ML2.

[0141] In some examples, as shown in Figure 13, the display panel may further include a first shielding structure 51. The first shielding structure 51 may be located on the side of the multiplexing circuit 30 away from the substrate. The first shielding structure 51 may, for example, be located on a fourth conductive layer. The first shielding structure 51 may include a plurality of shielding strips 511 and at least one connecting strip 512. The plurality of shielding strips 511 and the connecting strip 512 may be directly connected. The connecting strip 512 may be located on the same side of the plurality of shielding strips 511, for example, on the side of the plurality of shielding strips 511 closer to the display area. The shielding strips 511 may extend along a first direction D1, and the connecting strip 512 may extend at least along a second direction D2. The first shielding structure 51 may be configured to receive a regulated signal, such as a first power signal or a second power signal.

[0142] In some examples, as shown in Figure 13, the orthographic projection of the shielding strip 511 onto the substrate may lie between the orthographic projections of two adjacent multiplexing units (e.g., multiplexing unit 30-1 and multiplexing unit 30-2) onto the substrate. The orthographic projection of the shielding strip 511 onto the substrate may not overlap with the orthographic projection of the active layer of the multiple multiplexed control transistors onto the substrate.

[0143] This example demonstrates how setting a first shielding structure can shield signals between adjacent multiplexing units, preventing crosstalk between them. The remaining structure of the display panel in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0144] Figure 14 is another partial plan view of a display panel according to at least one embodiment of the present disclosure; Figure 15 is a schematic diagram of the second shielding structure in Figure 14. In some examples, as shown in Figures 14 and 15, the display panel may include a first shielding structure 51 and a second shielding structure 52. The second shielding structure 52 may be located on the side of the first shielding structure 51 away from the substrate. For example, the first shielding structure 51 may be located in the fourth conductive layer, and the second shielding structure 52 may be disposed in the same layer as the first electrode of the light-emitting element.

[0145] In some examples, the second shielding structure 52 may include multiple cutouts 520. These cutouts 520 may be arranged in an array along a first direction D1 and a second direction D2, with multiple rows of cutouts staggered along the first direction D1. Since the second shielding structure 52 is disposed on the same layer as the first electrode of the light-emitting element, and a planarization layer (e.g., the seventh insulating layer shown in FIG. 3) is disposed on the side of the second shielding structure 52 near the substrate, the multiple cutouts 520 in the second shielding structure 52 can provide venting channels for the planarization layer, which helps to ensure the uniformity and stability of the film layer.

[0146] This example demonstrates how a first shielding structure can shield signals between adjacent multiplexing units, preventing crosstalk between them. A second shielding structure can shield the multiplexing circuit from the influence of other signals (such as touch signals or antenna signals). By designing a perforated second shielding structure, the capacitance of the multiplexing circuit can be reduced, thus lowering its power consumption. Further details regarding this example can be found in the descriptions of the foregoing embodiments and will not be repeated here.

[0147] Figure 16 is another partial plan view of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 15, the display panel may include a second shielding structure 52. The second shielding structure 52 may be disposed in the same layer as the first electrode of the light-emitting element, or the second shielding structure 52 may be located in the fourth conductive layer. The second shielding structure 52 may include a plurality of cutouts 520. In other examples, the second shielding structure 52 may be a full-surface structure.

[0148] This example demonstrates how a second shielding structure can shield the multiplexing circuit from the influence of other signals (such as touch signals or antenna signals). By designing a perforated second shielding structure, the capacitance of the multiplexing circuit can be reduced, thereby lowering its power consumption. Further details regarding this example can be found in the descriptions of the foregoing embodiments and will not be repeated here.

[0149] Figure 17 is another schematic diagram of the first border region of a display panel according to at least one embodiment of the present disclosure. Figure 18 is a bending schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the first border region B1 may include: a first sub-region B11, a bending region B12, and a second sub-region B13 arranged sequentially along a direction away from the display region AA. The first sub-region B11 may include a first wiring area FA1; the second sub-region B13 may include a second wiring area FA2, a third wiring area FA3, a first signal access area B131, and a second signal access area B132 arranged sequentially along a direction away from the bending region B12. A plurality of multiplexing circuits 30 may be located in the second sub-region B13, and between the second wiring area FA2 and the third wiring area FA3.

[0150] In some examples, Figure 18 shows a cross-sectional view of the display panel 70 after bending. The third direction D3 can be perpendicular to the plane of the display panel 70. The integrated circuit 61 can be bonded to the first contact pad of the first signal access area, and the flexible circuit board 62 can be bonded to the second contact pad of the second signal access area. The cover plate 71 can cover the display surface of the display panel 70, and the heat dissipation structure 72 and the antenna structure 73 can be disposed on the non-display surface of the display panel 70. The non-display surface of the display panel 70 can be the back of the display panel. When the multiplexing circuit 30 is disposed in the second sub-region B13, after the display panel 70 is bent, the multiplexing circuit 30 will be close to the lower edge of the antenna structure 73, and there will be interference between the antenna structure 73 and the multiplexing circuit 30. There is no interference in region 701 in Figure 18, but there is interference in region 700. The electromagnetic interference between the multiplexing circuit 30 and the antenna structure 73 is the fundamental frequency harmonic generated, which interferes with the radio frequency antenna, thereby affecting the display of the display panel. This example improves the stability of the multiplexing control transistor and enhances its anti-interference capability by introducing a second gate into the multiplexing control transistor of the multiplexing circuit 30. This second gate is connected to a regulated signal or to the first gate. In other examples, providing a second shielding structure on the side of the multiplexing circuit 30 away from the substrate can help shield against antenna signal interference. The structural description of the multiplexing circuit in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0151] This embodiment also provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, and a plurality of multiplexing circuits. The substrate includes a display area and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels; the plurality of multiplexing circuits are located in the first border area and are connected to the plurality of data lines. The display panel further includes at least one of the following: a first shielding structure and a second shielding structure. The first shielding structure is located in the first border area and includes a plurality of shielding strips, at least one multiplexing circuit includes a plurality of multiplexing units, at least one multiplexing unit includes at least one multiplexing control transistor, and the orthographic projection of the shielding strips on the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of two adjacent multiplexing units on the substrate. The second shielding structure is located in the first border area and on the side of the plurality of multiplexing circuits away from the substrate, and the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projections of the plurality of multiplexing circuits on the substrate.

[0152] The display panel provided in this embodiment can shield signals between adjacent multiplexing units by setting a first shielding structure, which can prevent crosstalk between adjacent multiplexing units; by setting a second shielding structure, it can shield the influence of other signals (such as touch signals or antenna signals) on the multiplexing circuit.

[0153] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0154] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 19, this embodiment provides a display device 91, which may include a display panel 910. The display panel 910 may be a flexible OLED display panel, a QLED display panel, a Micro-LED display panel, or a Mini-LED display panel. The display device 91 may be a product with image (including static images or dynamic images, wherein the dynamic image may be video) display function. For example, the display device may be any of the following products: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment of e-government, bank, hospital, power and other departments), monitor, etc. As another example, the display device may also be any of the following products: microdisplay, VR device or AR device including microdisplay, etc.

[0155] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0156] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, comprising: Base; Multiple sub-pixels and multiple data lines are disposed on the substrate, and the multiple data lines are connected to the multiple sub-pixels; Multiple multiplexing circuits, multiple multiplexing control lines, and multiple multiplexing data lines are disposed on the substrate and located on one side of the multiple sub-pixels. At least one of the multiple multiplexing circuits is connected to at least two of the multiple multiplexing control lines, at least two of the multiple multiple data lines, and at least one of the multiple multiple multiplexing data lines. The at least one multiplexing circuit includes: a plurality of multiplexing control transistors, at least one of the plurality of multiplexing control transistors including: a first gate, a second gate and an active layer, the first gate being located on the side of the active layer away from the substrate, and the second gate being located on the side of the active layer close to the substrate; the second gate is configured to receive a regulated signal or be connected to the first gate.

2. The display panel according to claim 1, wherein, The at least one multiplexing circuit is configured to, under the control of the plurality of multiplexing control lines, time-division multiplex the signal transmitted by the at least one multiplexed data line to the at least two data lines.

3. The display panel according to claim 1 or 2, wherein, The second gates of the plurality of multiplexing control transistors in the at least one multiplexing circuit are integral structures and configured to receive regulated signals; the orthographic projection of the integral structure onto the substrate includes the orthographic projection of the active layer of the plurality of multiplexing control transistors onto the substrate.

4. The display panel according to claim 3, further comprising: A first occlusion structure, wherein the orthographic projection of the first occlusion structure on the substrate at least partially overlaps with the orthographic projection of the plurality of sub-pixels on the substrate, and the first occlusion structure is connected to the second gate of the plurality of multiplexing control transistors.

5. The display panel according to claim 4, wherein, At least one of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit, the pixel circuit including a driving transistor, and the orthographic projection of the first occlusion structure onto the substrate includes the orthographic projection of the channel region of the active layer of the driving transistor of the pixel circuit onto the substrate.

6. The display panel according to claim 5, wherein, The pixel circuit is connected to the first power line, and the light-emitting element is connected to the second power line. The first power signal provided by the first power line is greater than the second power signal provided by the second power line. The regulated signal includes: the first power supply signal.

7. The display panel according to any one of claims 1 to 6, wherein, The at least one multiplexing circuit includes: multiple sets of multiplexing units, each set of multiplexing units including multiple multiplexing control transistors; the first gate and the second gate of the multiple multiplexing control transistors of a set of multiplexing units are connected to the same multiplexing control line, and the second gate of the multiple multiple multiplexing control transistors of the set of multiplexing units is an integral structure.

8. The display panel according to any one of claims 1 to 7, further comprising at least one of the following: A first shielding structure, comprising: Multiple shielding strips; The at least one multiplexing circuit includes: multiple sets of multiplexing units, at least one set of multiplexing units including at least one multiplexing control transistor; at least one of the multiple shielding strips has its orthographic projection on the substrate located between the orthographic projections of the active layers of the multiplexing control transistors of two adjacent sets of multiplexing units on the substrate. A second shielding structure is located on the side of the plurality of multiplexed circuits away from the substrate, and the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the plurality of multiplexed circuits on the substrate.

9. The display panel according to claim 8, wherein, The second shielding structure is located on the side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of hollowed-out portions.

10. The display panel according to claim 8 or 9, wherein, In a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source / drain metal layer and a second source / drain metal layer disposed on the substrate, wherein the first shielding structure is located on the second source / drain metal layer.

11. The display panel according to claim 8, wherein, At least one of the plurality of sub-pixels includes a light-emitting element, the light-emitting element including a first electrode, a light-emitting functional layer and a second electrode arranged sequentially along a direction away from the substrate, and the second shielding structure is arranged in the same layer as the first electrode of the light-emitting element.

12. The display panel according to any one of claims 1 to 11, wherein, The substrate includes a display area and a first border area located on one side of the display area, and the plurality of sub-pixels are located in the display area; the first border area includes: a first sub-region, a bending region and a second sub-region arranged sequentially along a direction away from the display area, and the plurality of multiplexing circuits are located in the first sub-region or the second sub-region.

13. A display device comprising a display panel as claimed in any one of claims 1 to 12.

14. A display panel, comprising: The substrate includes a display area and a first border area located on one side of the display area; Multiple sub-pixels and multiple data lines are disposed on the substrate and located in the display area, and the multiple data lines and the multiple sub-pixels are connected. Multiple multiplexing circuits are located in the first frame area and connected to the multiple data lines; The display panel further includes at least one of the following: A first shielding structure is located in the first frame region and includes multiple shielding strips. At least one of the multiple multiplexing circuits includes multiple sets of multiplexing units. At least one set of multiplexing units includes at least one multiplexing control transistor. The orthographic projection of at least one of the multiple shielding strips on the substrate is located between the orthographic projections of the active layers of the multiplexing control transistors of two adjacent sets of multiplexing units on the substrate. The second shielding structure is located in the first frame region and on the side of the plurality of multiplexed circuits away from the substrate, and the orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the plurality of multiplexed circuits on the substrate.

15. The display panel according to claim 14, wherein, The second shielding structure is located on the side of the first shielding structure away from the substrate, and the second shielding structure includes a plurality of hollowed-out portions.

16. The display panel according to claim 14 or 15, wherein, In a direction perpendicular to the display panel, the display panel includes: a gate metal layer, a first source / drain metal layer and a second source / drain metal layer disposed on the substrate, wherein the first shielding structure is located on the second source / drain metal layer.

17. The display panel according to any one of claims 14 to 16, wherein, At least one of the plurality of sub-pixels includes a light-emitting element, the light-emitting element including a first electrode, a light-emitting functional layer and a second electrode arranged sequentially along a direction away from the substrate, and the second shielding structure is arranged in the same layer as the first electrode of the light-emitting element.

18. The display panel according to any one of claims 14 to 17, wherein, The first border area includes: a first sub-region, a bending region, and a second sub-region arranged sequentially along a direction away from the display area, and the plurality of multiplexing circuits are located in the second sub-region.

Images