Quantum chip with ferromegnetic insulator for operation of quantum dots

Abstract

The disclosure regards a quantum chip for operation and manipulation of semiconductor spin qubits, the quantum chip comprising a semiconducting substrate (200) comprising a plurality of quantum dots (204), each quantum dot configured to host a two-level system, wherein said two-level system is associated with an energy difference. The quantum dots are coupled to a gate (202) and a ferromagnetic insulator (205) is arranged between the gate (202) and the gate dielectric (201) in a predefined pattern to selectively cover specific quantum dots (204). The ferromagnetic insulator results in local variations of the Larmor frequency (fL). The disclosure further relates to a system for manipulating quantum dots, a method for probing individual qubits in a spin qubit system, and a method for manufacturing a quantum chip.

Description

[0001] P7539PC00

[0002] Quantum chip for operation of quantum dots

[0003] The present disclosure relates to a novel quantum chip and system for manipulating quantum dots, a method for doing the same, and a method for manufacturing a quantum chip for operation and manipulation of quantum dots.

[0004] Background

[0005] In the field of quantum technology, one of the bottlenecks for the realization of a functional quantum computer is the scalability of quantum chips. A quantum chip may comprise a one-dimensional or two-dimensional pattern of quantum dots, where each quantum dot can host a two-level system that can be occupied by an electron or a hole. Such a configuration is also known as an array of spin qubits. A common way of interacting with the spin qubits and performing quantum operations is to use a waveform source, which can coherently drive transitions in the two-level systems and transport electrons or holes between quantum dots. However, to achieve precise control over quantum operations, it is essential that the waveform source interacts with only one quantum dot at a time. This selective interaction is challenging because quantum dots can have similar properties, such as identical Larmor frequencies, leading to a simultaneous response to the waveform source. Such unintended interactions can compromise the individual addressability of an array of quantum dots, which is a critical requirement for scalable quantum computing platforms. Addressing this issue is an active area of research in the field, as overcoming it would enable precise control and manipulation of individual spin qubits.

[0006] To address the above challenge, scientists have utilized permanent magnets positioned on substrates in the vicinity of arrays of quantum dots, in order to affect the Larmor frequency of individual quantum dots, thereby enabling the excitation of the two-level system in a single quantum dot without unintentionally interfering with its neighbouring quantum dots. However, that technique has various limitations, as it requires additional lithography steps, thereby complicating the device. Specifically, the use of permanent magnets introduces further disadvantages, as the deposition of such materials would require an additional fabrication step to complete a quantum chip device. Having further fabrication steps not only raises manufacturing complexity and costs but also increases the risk of introducing impurities into the quantum chip. Such impurities may interfere with the quantum dots, and be a source of decoherence thatP7539PC00

[0007] can significantly decrease the quality of the qubits. Moreover, the accurate deposition of permanent magnets is a challenging task, leading to misaligned patterns and reduced yield of the devices. Additionally, permanent magnets are associated with low accuracy in tuning the Larmor frequency, as their magnetic fields cannot be precisely controlled or adjusted after fabrication. This limitation further hinders their ability to ensure precise individual addressability of quantum dots. A further challenge with using micromagnets is that they are not compatible with 3D integration of the CMOS gate stack.

[0008] Hence, there is a need for a novel solution that can provide individual addressability of arrays of quantum dots on a substrate, while minimizing or eliminating unnecessary fabrication steps.

[0009] Summary

[0010] One purpose of the present disclosure is to provide a technique for having individual addressability of quantum dots on a substrate. As most of the quantum dots are defined in semiconducting materials, a standard component of a quantum chip is electrostatic gates that can apply electric fields to tune the quantum dots. Such gates are typically used to affect the tunnel couplings between a quantum dot and its surroundings, or to modify the number of charge carriers that occupy a quantum dot. Therefore, an essential part of such structures is the use of a dielectric material that is deposited between the quantum dots and the gates, preventing a current from flowing from the gates to the quantum dots. The applicant of the present disclosure has taken advantage of the necessity of the dielectric layer in order to incorporate to it an auxiliary function. The auxiliary function is the influence of the Larmor frequency of the quantum dot on the substrate. Such a function can stem from using a ferromagnetic insulator as part of the dielectric material. A ferromagnetic insulator can be magnetized using an external magnetic field, thereby generating a stray magnetic field on the quantum dots that it is arranged to cover. The effect of the stray magnetic field would lead to the corresponding energy difference of the two-level system in the quantum dot to be altered. As a result, the present disclosure relates to a semiconducting structure that can have some of its quantum dots covered by a ferromagnetic insulator, thereby affecting the Larmor frequency of the corresponding quantum dots. Therefore, the proposed geometry enables individual addressability of the quantum dots.P7539PC00

[0011] Specifically, the present disclosure relates to a quantum chip for operation and manipulation of semiconductor spin qubits, the quantum chip comprising a semiconducting substrate comprising a plurality of quantum dots, each quantum dot may be configured to host a two-level system, wherein said two-level system is associated with an energy difference. The quantum chip further comprises a ferromagnetic insulator arranged in a predefined pattern to selective cover specific quantum dots, for example by means of deposition. In an embodiment the ferromagnetic insulator comprises one or more layers. Therefore, the ferromagnetic insulator may be configured to generate a stray magnetic field affecting the quantum dot(s) that it is arranged to cover, thereby possibly modifying the energy difference of the corresponding two-level system(s).

[0012] One example of having a patterned ferromagnetic insulator is having a first quantum dot covered by a ferromagnetic insulator while its surrounding quantum dots are not covered by a ferromagnetic insulator. As a result, when the ferromagnetic insulator covering the first quantum dot is magnetized, the corresponding energy difference of the two-level system will be modified, as the Larmor frequency of the first quantum dot will be affected. However, the Larmor frequency of the surrounding quantum dots will be intact. Hence, it is possible to use an external waveform source with a signal tuned to the modified Larmor frequency, in order to interact with that quantum dot and prevent any unwanted interaction with the surrounding quantum dots. Such a process may be extended along the quantum chip, using variations of patterns, such as having ferromagnetic insulator layers of varied thickness, or shape, and engineering the ferromagnetic insulator to cover specific quantum dots.

[0013] The ferromagnetic insulator can generate a stray magnetic field if it becomes magnetized. For example, an external magnetic field can be applied on the quantum chip in order to magnetize the ferromagnetic insulator. As a result, the magnetized ferromagnetic insulator can affect the quantum dots that the layer is arranged to cover, by modifying the energy difference of the corresponding two-level systems. Such a function can be highly beneficial, as it becomes possible to use a waveform source to individually address a quantum dot, without interacting with the surrounding quantum dots, due to the fact that the energy difference of the two-level system can be different for the plurality of quantum dots in a region of the quantum chip.P7539PC00

[0014] The ferromagnetic insulator can comprise a material selected from the group of: EuS, EuO, NiFe2O4, CoFe2O4, MgFe2O4, Mn3O4, or LiFe5O8. Different materials can be chosen depending on the type of application and the compatibility with the substrate. Further details are provided in the detailed description of the application. The ferromagnetic insulator may have a thickness larger than 1 nm, preferably larger than 5 nm, more preferably larger than 10 nm, even more preferably larger than 12 nm, most preferably larger than or equal to 15 nm. Depending on how large magnitude of stray magnetic field is desired, or how much the ferromagnetic insulator is to be used for its dielectric function, different thicknesses may be chosen. In addition, it is possible to use ferromagnetic insulator layers with different thicknesses, each layer covering a different set of quantum dots. Alternatively, different layers may be stacked on top of another.

[0015] Moreover, the quantum dots may be arranged in a one-dimensional, two-dimensional or three-dimensional pattern on the semiconducting substrate. The quantum dots may be defined by engineering quantum wells in the semiconducting substrate, or the quantum dots may be defined electrostatically, by utilizing a plurality of gate electrodes. In certain embodiments, a combination of the two techniques may be used. In addition, the gate electrodes may be utilized to control the number of electrons or holes on the plurality of quantum dots, and possibly to tune the couplings between adjacent quantum dots.

[0016] In an embodiment, a dielectric layer may be arranged on the semiconducting substrate. The purpose of the dielectric layer is to form an insulating barrier between the quantum dots and the gate electrodes, enabling the gate electrodes to apply local electric fields and tune the plurality of quantum dots. The ferromagnetic insulator may also be used as a dielectric layer, in addition to its ferromagnetic properties.

[0017] The present disclosure further relates to a system for manipulating quantum dots, comprising a quantum chip, the quantum chip comprising a semiconducting substrate comprising a plurality of quantum dots, each quantum dot configured to host a two-level system, wherein said two-level system is associated with an energy difference, and a ferromagnetic insulator arranged in a predefined pattern to selectively cover specific quantum dots. The quantum chip may further comprise a magnetic field generator configured to generate an external magnetic field to magnetize theP7539PC00

[0018] ferromagnetic insulator, and a waveform source configured to generate electrical pulses, thereby exciting the two-level systems of the plurality of quantum dots, and / or transporting a charge carrier from a first quantum dot to a second quantum dot, wherein the magnetized ferromagnetic insulator induces a magnetic field affecting the quantum dot(s) that is arranged to cover, thereby modifying the energy difference of the corresponding two-level system(s), and enabling the waveform source to individually excite the plurality of quantum dots.

[0019] The present disclosure further relates to a method for probing individual qubits in a spin qubit system, the method comprising the steps of obtaining a quantum chip comprising a semiconducting substrate, the semiconducting substrate comprising a plurality of quantum dots, wherein a ferromagnetic insulator is arranged in a predefined pattern to selectively cover specific quantum dots, magnetizing the ferromagnetic insulator, and exciting the plurality of quantum dots using an electric field or a magnetic field, thereby inducing spin transitions.

[0020] Description of Drawings

[0021] Various embodiments are described hereinafter with reference to the drawings. The drawings are examples of embodiments and are intended to illustrate some of the features of the presently disclosed magnetic field landscape engineering for operation of quantum dots, and are not limiting to the presently disclosed quantum chip, system and methods.

[0022] Fig. 1 shows a schematic of a quantum chip comprising a substrate with quantum dots, a dielectric layer and gate electrodes. The lower part of the figure shows a graph of the corresponding Larmor frequency of an array of quantum dots.

[0023] Fig. 2 shows a schematic of a quantum chip comprising a substrate with quantum dots, a dielectric layer, a patterned ferromagnetic insulator and gate electrodes. The lower part of the figure shows a graph of the corresponding Larmor frequency of an array of quantum dots.

[0024] Fig. 3 shows a schematic of a quantum chip having some of its quantum dots covered by a ferromagnetic insulator.

[0025] Fig. 4 shows a schematic of a quantum chip having all of its quantum dots covered by a ferromagnetic insulator.

[0026] Fig. 5 shows a schematic of a system for manipulating quantum dots.P7539PC00

[0027] Fig. 6 shows the steps of a method for probing individual qubits in a spin qubits system. Fig. 7 shows a simulation of the stray magnetic field lines generated by a ferromagnetic oxide cuboid for a chip comprising a ferromagnetic layer.

[0028] Fig. 8 shows a schematic of a scan area in the X-Y plane around a magnetic moment of a ferromagnetic oxide cuboid.

[0029] Fig. 9 shows magnetic field simulations of a magnetic moment in an X-Y plane for x, y, and z component of the stray magnetic field.

[0030] Fig. 10 shows simulations of the stray magnetic field |B|, Bx, By and Bz as a function of distance from a nanomagnet.

[0031] Fig. 11 shows data of |Bx| as a function of ferromagnetic layer length for different ferromagnetic layer thicknesses.

[0032] Detailed description

[0033] As described in the summary, one purpose of the present disclosure is to provide a technique for having individual addressability of quantum dots on a substrate.

[0034] Specifically, the present disclosure relates to a quantum chip for operation and manipulation of semiconductor spin qubits, the quantum chip comprising a semiconducting substrate comprising a plurality of quantum dots, each quantum dot configured to host a two-level system, wherein said two-level system is associated with an energy difference, and a ferromagnetic insulator arranged in a predefined pattern to selectively cover specific quantum dots. As a result, the ferromagnetic insulator is configured to generate a stray magnetic field affecting the quantum dot(s) that is arranged to cover, thereby modifying the energy difference of the corresponding two-level system(s). In an embodiment, the ferromagnetic insulator comprises one or more layers. One or more ferromagnetic insulator layers may be used to fine-tune the generated stray magnetic field affecting the plurality of quantum dots. For example, stacking multiple layers allows for adjustable field strength. In an embodiment, each layer may have different thickness or composition, in order to achieve precise magnetic field gradients. One or more ferromagnetic insulator layers may be used as it may lead to easier fabrication of such a quantum chip. For example, having multiple layers may reduce the defects that may accumulate in the ferromagnetic insulator material, or it may increase the fabrication steps yield, due to improved lift-off process. Depending on the type of application, a quantum chip may comprise a single ferromagnetic insulator layer that is patterned to selectively cover selected quantum dots, or a quantum chipP7539PC00

[0035] may comprise one or more ferromagnetic insulator layers stacked on top of each other, thereby selectively covering selected quantum dots. In an embodiment, different ferromagnetic insulator layers may be patterned to cover different quantum dots.

[0036] Further details regarding the ferromagnetic insulator are provided in the following section of the present disclosure. Fig. 1 shows an example of a schematic of a quantum chip using the state of the art technology. A semiconducting layer 100 is shown comprising a two-dimensional array of quantum dots 104. The plurality of quantum dots are covered by a dielectric material 101, and a plurality of gate electrodes 102 are designed using standard lithography techniques. The gate electrodes can be used to tune the couplings between adjacent quantum dots or tune the quantum dots and change the charge carrier number on each quantum dot. Typically, an external magnetic field Bext is used in such experiments, in order to split the degeneracy of a quantum state, such as a doublet state, and create a two-level system that can be used for qubit operations. The energy difference of the two-level system is associated with a Larmor frequency f . The Larmor frequency f is associated to the Zeeman energy via the equation:

[0037] ' fl=9B ' 9eff ’ Beff

[0038] where h is the Planck constant, / JB is the Bohr magneton, getf is the effective g-factor of a quantum dot, and Ben is the effective magnetic field affecting the quantum dot. The Zeeman energy relates to the energy difference between a spin-down and a spin-up state in a quantum dot.

[0039] In such a configuration the Larmor frequency f 105 will be constant in an array of qubits 106. Therefore, individual addressability of a single quantum dot in such a structure is not possible, since if a user applied a waveform source with frequency equal to the Larmor frequency of a quantum dot 106, that would also lead to an interaction with the surrounding quantum dots 107. Hence, in the above configuration the Larmor frequency is constant over the various qubit sites.

[0040] An objective of the present disclosure is to locally and individually influence the Beffof the plurality of quantum dots, by utilizing a ferromagnetic insulator that can be arranged to selectively cover specific quantum dots of a quantum chip. For example, fig. 2 shows a schematic of a quantum chip having a ferromagnetic insulator. Specifically, a semiconducting layer 200 comprises a two-dimensional array of quantum dots 204. The quantum dots are covered by a dielectric material 201, and a pattern of aP7539PC00

[0041] ferromagnetic insulator material 205 is arranged to cover some of the quantum dots. A plurality of gate electrodes 202 are deposited as a final layer. The gate electrodes can be used to tune the couplings between adjacent quantum dots or tune the quantum dots and change the charge carrier number on each quantum dot. An external magnetic field Bext 203 is used in such experiments, in order to split the degeneracy of a quantum state, such as a doublet state, and create a two-level system that can be used for qubit operations. In the present disclosure, the external magnetic field is also used to magnetize the ferromagnetic insulator. That magnetization has an effect on the Be / rof the quantum dots that are covered by the ferromagnetic material. It is possible to express that effect by using the below equation:

[0042] ^effext + BSfray(x,y,Z)

[0043] Where Bstray(x,y,z') is the position-dependent magnetic field generated by the magnetized ferromagnetic insulator. As a result, the magnetization of the ferromagnetic materials generates a stray magnetic field Bstray(x,y,z') which in turn affects the Larmor frequency of the corresponding qubit. Therefore, an array of qubits comprising two quantum dots that are covered by a ferromagnetic material 206 and two quantum dots that are not 207 would result into a varying Larmor frequency 208. As a result, the Larmor frequency is dependent on the site and it is possible to individually address each qubit by utilizing external probes, such as a waveform source. The present disclosure enables to design the Larmor frequency spectrum of large qubit arrays such that the various frequencies are sufficiently spread apart. In addition, that functionality paves the way for the realization of two-qubit gates, whose implementation depends on the difference between Larmor frequencies of neighboring qubits.

[0044] Fig. 2 shows one example of achieving individual addressability of quantum dots, but various other embodiments can be realized. For example, a varying thickness of the ferromagnetic insulator can also be designed, enabling a gradient change of the stray magnetic field, thereby engineering a gradient change of the Larmor frequency in an array of qubits. In addition, the shape of the deposited ferromagnetic material may also be modified, leading to variations in the Beffof each quantum dot. Further embodiments related to the ferromagnetic insulator layers are described in the sections below.

[0045] Patterning the ferromagnetic insulator to selectively cover specific quantum dots allows for localized magnetic field control, enabling individual addressability of quantum dotsP7539PC00

[0046] within the quantum chip. This approach can be particularly useful in systems requiring different magnetic environments for neighbouring quantum dots, such as when implementing qubit-specific Larmor frequencies for addressing or tuning interactions between qubits. The patterning process may involve lithography techniques, such as electron-beam or photolithography, followed by etching or lift-off processes to define the desired mask. By selectively covering certain quantum dots with a ferromagnetic insulator, the system can achieve fine-tuned magnetic fields where needed, while minimizing magnetic interference with other regions of the chip. This selective patterning enables individual addressability of qubits by tailoring the Larmor frequency of the qubits and preventing a waveform source from interacting with more than one qubit at a time.

[0047] Fig. 3 shows an example of a quantum chip having a patterned ferromagnetic insulator, selectively covering specific quantum dots. A quantum chip 300 is shown, comprising a semiconducting substrate 301, and a plurality of quantum dots 302. A dielectric layer 303 is used to electrically isolate the quantum dots from the gate electrodes 304. In this example, the gate electrodes are used to control the number of electrons or holes on the quantum dots. A ferromagnetic insulator 305 is selectively covering some of the quantum dots 306 of the quantum chip. As a result, under the application of an external magnetic field, the Beff on the quantum dots that are covered by the ferromagnetic insulator is different from the Beff of the other quantum dots, due to the stray magnetic field Bstray 307 that is induced by magnetizing the ferromagnetic insulator. Therefore, individual addressability of these quantum dots is enabled, for example by using a microwave source with a signal at a frequency equal to the Larmor frequency of the selected quantum dots. Lithography fabrication techniques such as electron-beam or photolithography may be used in order to define the masks that allow selective deposition or growth of the ferromagnetic insulator.

[0048] In an embodiment, the quantum chip comprises a plurality of gate electrodes configured to control the number of electrons or holes on the plurality of quantum dots, and / or configured to tune the couplings between adjacent quantum dots. The plurality of gate electrodes may be deposited on the ferromagnetic insulator layer, or below the ferromagnetic insulator layer. In the latter case, a dielectric layer may be deposited between the semiconducting substrate comprising the quantum dots, and the plurality of gate electrodes. It should be noted that it is implicit that any quantum chip comprisesP7539PC00

[0049] gate electrodes, as gate electrodes are an integral part of quantum chips in order to enable tunability and control of the quantum dots.

[0050] In an embodiment, the plurality of gate electrodes may be designed on a second substrate, said second substrate being different than the semiconducting substrate. Bonding techniques may be utilized in order to attach the second substrate to the semiconducting substrate, thereby obtaining a quantum chip.

[0051] Substrate characteristics

[0052] The material of the semiconducting substrate can play an important role in the realization of a quantum chip. In an embodiment, the quantum chip can be configured such that the semiconducting substrate comprises a material selected from the group of: C, InAs, InSb, Si, GaAs, AIGaAs, Ge, SiGe, or InP. The selection of substrate materials may depend on the specific requirements of the quantum chip, such as the desired coherence properties, mobility of charge carriers, g-factor, or compatibility with existing fabrication techniques. For instance, silicon (Si) is widely used due to its extensive integration in modern semiconductor processes and its low nuclear spin density, which reduces interactions with spin qubits and minimizes decoherence. Alternatively, materials such as InAs, Ge and InSb may be employed for applications where strong spin-orbit coupling is beneficial, as these materials facilitate spin-based quantum operations and support high-speed qubit manipulation.

[0053] The semiconducting substrate may be formed as a bulk wafer or as a heterostructure where thin layers of different materials are deposited to achieve specific bandgap properties or carrier confinement. For example, a substrate consisting of GaAs with an AIGaAs barrier layer can be used to confine quantum dots in a two-dimensional electron gas (2DEG). Other variations may include strained SiGe substrates to enhance carrier mobility or engineered lattice- matched materials to minimize defects and improve qubit coherence times. Therefore, the choice of the semiconducting substrate can be made depending on the needs of each application.

[0054] In an embodiment, the semiconducting substrate may have a thickness of larger than 100 pm, preferably larger than 250 pm, more preferably larger than 400 pm.

[0055] Depending on the type of application and the specifics of the various components of the quantum chip, different substrate thickness may be chosen. For example, a thickerP7539PC00

[0056] substrate may improve thermal dissipation during operation, which can be advantageous in high-density qubit arrays where power dissipation becomes a concern. In some variations, the thickness of the substrate may be chosen based on the requirements of the packaging or integration method. For instance, thinner substrates may be used when the quantum chip is mounted on a separate carrier wafer or when compatibility with flexible substrates is desired for specialized applications.

[0057] Moreover, the quantum chip can be configured, such that the plurality of quantum dots are embedded in the semiconducting substrate. Quantum dots can be embedded in a semiconducting structure by engineering a heterostructure where thin layers of different materials are deposited to achieve specific bandgap properties or carrier confinement. For example, AIGaAs or SiGe heterostructures may be chosen to engineer quantum wells in order to confine carriers and form quantum dots in the semiconducting substrate. Utilizing embedded quantum dots may lead to qubits with higher coherence, as the quantum dots can be protected during the various lithography steps to fabricate a quantum chip.

[0058] In one embodiment of the present disclosure, the plurality of quantum dots are formed by electrostatic confinement using a plurality of gate electrodes arranged on the semiconducting substrate. Electrostatic confinement allows for the precise formation and control of quantum dots by manipulating the potential landscape on the substrate. This method provides flexibility, as the geometry and size of the quantum dots can be dynamically adjusted by varying the voltages applied to the gate electrodes.

[0059] Additionally, the ability to form quantum dots without introducing physical defects or impurities enhances coherence properties, reducing noise and decoherence sources. In some variations, the gate electrodes may be fabricated using advanced lithographic techniques to achieve nanoscale precision, enabling the creation of closely spaced quantum dots suitable for two-dimensional qubit arrays. The gate electrodes may also serve dual purposes, such as tuning the tunnel coupling between adjacent quantum dots to enable coherent qubit interactions or charge transport.

[0060] Furthermore, the quantum chip can be configured, such that a plurality of gate electrodes are utilized to control the number of electrons or holes on the plurality of quantum dots. Controlling the charge occupation of quantum dots is important for defining their quantum state, as the qubit may be encoded in the spin or charge of anP7539PC00

[0061] individual electron or hole. Gate electrodes enable this control with high precision, allowing for single-electron or single-hole operations, which are crucial for quantum coherence and reliable qubit initialization. For example, gate electrodes can be used to tune a quantum dot in a doublet ground state, having an unpaired electron. When applying an external magnetic field, the degenerate states of that doublet state split in energy, separated by an energy difference which is known as Zeeman energy. As written in the sections above, the Zeeman energy is associated with a Larmor frequency, and a waveform source emitting a signal with that frequency can trigger spin transitions in the quantum dot, such as flipping a spin.

[0062] In some implementations, the gate electrodes may be integrated with charge sensors or readout mechanisms, providing real-time feedback on qubit states and enhancing overall system performance.

[0063] Moreover, the quantum chip may comprise a dielectric layer arranged on the semiconducting substrate. The ferromagnetic insulator also serves the purpose of a dielectric layer, but since in most embodiments the ferromagnetic layer covers only some of the quantum dots, a complementary dielectric layer can be used to enable gate electrodes to manipulate the quantum dots. The dielectric layer provides electrical insulation between the gate electrodes and the substrate, preventing unwanted leakage currents and ensuring stable operation of the quantum dots. The dielectric layer may be formed through processes such as atomic layer deposition (ALD), thermal oxidation or e-beam evaporation, allowing for precise control over its thickness and uniformity. In some embodiments, the dielectric material may also enhance the stability of the substrate by passivating surface states, reducing the impact of environmental noise on qubit performance.

[0064] In an embodiment, the quantum chip can be configured such that the dielectric layer has a thickness lower than 100 nm, preferably lower than 50 nm, more preferably lower than 25 nm, even more preferably lower than 10 nm, most preferably lower than or equal to 5 nm. It can be advantageous that the dielectric layer is as thin as possible, in order to increase the lever arm of a gate electrode that is deposited on top of it. The lever arm relates to the voltage required to apply on a gate electrode in order to add one charge carrier on a quantum dot. The lower the lever arm, the less voltage required, which can be beneficial as it can improve the performance of the quantumP7539PC00

[0065] chip. However, the dielectric layer shall be thick enough to prevent any current leakage between the gate electrode and the quantum dot. Therefore, depending on the type of application, different dielectric thickness may be chosen.

[0066] Moreover, the quantum chip can be configured, such that the dielectric layer comprises a material selected from the group of: AI2O3, HfC>2, SiC>2, SiaN4, or hexagonal Boron Nitride (h-BN), and Ta2Os. The choice of the dielectric layer depends on various parameters, such as dielectric constant, thermal stability and compatibility with standard semiconducting processes. For example, AI2O3and HfO2are commonly used in advanced transistors and quantum devices due to their excellent insulating properties and ability to form conformal layers using atomic layer deposition.

[0067] In some variations, h-BN may be used for its unique two-dimensional structure and high chemical stability, which can enhance the thermal and electrical performance of the quantum chip. By selecting an appropriate dielectric material, the quantum chip can balance insulation, gate control precision, and qubit coherence, ensuring reliable operation across diverse use cases.

[0068] Quantum dot characteristics

[0069] This section relates to various embodiments of the present disclosure relating to adjustments and further features of the quantum dots used. As also described in the sections above, the energy difference of the two-level system in the plurality of quantum dots can be associated with a Larmor frequency. Using waveform sources, such as electromagnetic fields, tuned to the Larmor frequency of a quantum dot, it is possible to control and manipulate the quantum dot, enabling coherent control of qubits states for quantum operations. The Larmor frequency depends on the strength of the applied external magnetic field, the g-factor of the semiconducting substrate and the properties of the spin qubit. Importantly, the Larmor frequency can be influenced by the presence of magnetized ferromagnetic materials, such as the ferromagnetic insulator layers that can be covering some of the quantum dots. Therefore, by tailoring the ferromagnetic insulator it is possible to optimize the quantum chip for scalability and compatibility with external waveform sources, such as microwave or radio-frequency fields.

[0070] In an embodiment, the quantum chip can be configured, such that the energy difference of the two-level system in the plurality of quantum dots is further tunable viaP7539PC00

[0071] an external electric or magnetic field. As also described in the paragraphs above, an external magnetic field can be used in order to tune the Zeeman energy of a two-level system. For example, if a quantum dot has one unpaired electron, that would form a doublet ground state. A doublet ground state relates to a spin-up and a spin-down state, which are degenerate when there is no applied magnetic field. By applying a magnetic field, the spin-up and spin-down states split in energy, forming a two-level system that can be used for qubit operations.

[0072] Moreover, the plurality of quantum dots may be configured to host electron spin qubits or hole spin qubits. Electron and hole spin qubits are commonly used in quantum computing due to their long coherence times and the availability of established control techniques. Electron spin qubits are typically favoured for their high fidelity in singlequbit and two-qubit gates, while hole spin qubits, having strong spin-orbit coupling, allow for fast electrical manipulation without requiring large magnetic fields.

[0073] The configuration of quantum dots to host these qubits may involve tuning the confinement potential to trap individual electrons or holes. This can be achieved using gate electrodes or by engineering the material properties of the quantum dot and substrate.

[0074] Furthermore, the quantum chip can be configured, such that at least one quantum dot of the plurality of quantum dots comprises an unpaired electron or an unpaired hole. As described in the sections above, having an unpaired electron or hole can be important as it allows the formation of a two-level system, based on the Doublet ground state. Using gate electrodes, it is possible to add or remove electrons from a quantum dot, thereby realizing a configuration where a quantum dot has an odd number of electrons or holes, which leads to having an unpaired electron or an unpaired hole. Additionally, doping of the semiconducting substrate may also form quantum dots having unpaired electrons or holes.

[0075] In an embodiment, the quantum chip can be configured, such that adjacent quantum dots are capacitively coupled or tunnel-coupled. It can be beneficial to have capacitive coupling and / or tunnel coupling between quantum dots, as that enables more complicated qubit operations, such as forming a two-level system with adjacent quantum dots. One method of tuning the capacitive or tunnel coupling is via utilizing a plurality of gate electrodes. For example, it is possible to have a gate electrodeP7539PC00

[0076] between two quantum dots, and by increasing or decreasing the applied voltage, it is possible to increase or decrease the coupling between the two quantum dots respectively. Additionally, the coupling strength may be modified by adjusting the spacing between quantum dots, as that will influence the overlap of the wavefunctions of the two quantum dots.

[0077] Moreover, the quantum chip can be configured, such that the plurality of quantum dots are arranged in a linear array, two-dimensional array or in a three-dimensional array. The arrangement of the quantum dots may be tailored to the specific requirements of the system. For example, in a two-dimensional array, quantum dots may be spaced to optimize gate coupling while minimizing crosstalk. In a three-dimensional array, vertical coupling mechanisms, such as through silicon vias or optical interconnects, may be utilized to achieve interactions between layers. By supporting various configurations, the quantum chip is adaptable to a wide range of quantum computing models, ensuring flexibility and scalability.

[0078] Ferromagnetic insulator characteristics

[0079] The quantum chip can be configured, such that the ferromagnetic insulator comprises a material selected from the group of: EuS, EuO, NiFe2O4, CoFe2O4, MgFe2O4, Mn3O4, or LiFe5O8. As described in the present disclosure, ferromagnetic insulator materials are advantageous for generating localized magnetic fields without conducting electrical currents, thereby preventing electrical currents from flowing from a gate electrode to a quantum dot. For example, EuS and EuO are particularly suitable due to their high spin polarization and compatibility with cryogenic environments. Oxides such as NiFe2O4and CoFe2O4offer strong magnetic properties, making them ideal for integration with semiconducting substrates. These materials can be deposited using techniques such as sputtering, molecular beam epitaxy (MBE), or pulsed laser deposition (PLD), ensuring precise control over the layer’s composition and quality. The selection of a specific material may depend on its Curie temperature, magnetic anisotropy, or compatibility with the fabrication processes. By using materials from this group, the ferromagnetic insulator can reliably generate localized magnetic fields and tune the quantum dots’ Larmor frequency.

[0080] In an embodiment, the quantum chip can be configured such that the ferromagnetic insulator has a thickness larger than 1 nm, preferably larger than 5 nm, more preferablyP7539PC00

[0081] larger than 10 nm, even more preferably larger than 12 nm, most preferably larger than or equal to 15 nm. The thickness of the ferromagnetic insulator influences the strength and uniformity of the stray magnetic field it generates. A thicker layer can produce stronger magnetic fields, which may be necessary for systems requiring larger Zeeman splitting in the energy levels of the quantum dots. However, overly thick layers can introduce challenges, such as strain in the substrate or increased difficulty in patterning. The thickness may therefore be optimized based on the specific material properties and the desired magnetic field strength. For instance, EuS layers in the range of 10-15 nm may achieve high magnetic field uniformity while maintaining compatibility with standard processing techniques. This thickness range ensures sufficient stray magnetic field strength for effective tuning of the quantum dots’ Larmor frequencies without introducing unnecessary fabrication complexity.

[0082] Moreover, the quantum chip can be configured, such that the ferromagnetic insulator is arranged to cover all the quantum dots of the quantum chip. A uniform ferromagnetic insulator layer can ensure that all quantum dots experience a similar magnetic field, simplifying the overall design and control of the quantum chip. This configuration may be advantageous for systems where all qubits are designed to operate at the same Larmor frequency or require the same Zeeman splitting.

[0083] Uniform deposition can be achieved using techniques like atomic layer deposition (ALD) or sputtering, which provide excellent control over the layer’s thickness and uniformity. This approach reduces complexity in the fabrication process while ensuring that the quantum dots are uniformly influenced by the generated stray magnetic field, leading to consistent qubit performance across the array.

[0084] For example, if there is a weak g-factor on the quantum dots, the presence of a global ferromagnetic insulator can assist in generating large enough local magnetic fields, preventing the need to apply a large external magnetic field to create a two-level system in the plurality of quantum dots. In an embodiment, it is possible to tune the thickness of the ferromagnetic insulator, or the thickness of individual layers of a ferromagnetic insulator, with the purpose of affecting the stray magnetic field that is generated on each quantum dot. Such a technique can both enable using small external magnetic fields and enable individual addressability. One method of tuning the thickness of the ferromagnetic layer is by designing a further lithography step after the coverage of the quantum chip with the global ferromagnetic insulator.P7539PC00

[0085] Fig. 4 shows an example of a quantum chip which is fully covered by a ferromagnetic insulator layer. A quantum chip is shown 400, comprising a semiconducting substrate 401 , and a plurality of quantum dots 402. A dielectric layer 403 is used to electrically isolate the quantum dots from the gate electrodes 404. In this example, the gate electrodes are used to control the number of electrons or holes on the quantum dots. A ferromagnetic insulator layer 405 is covering all of the quantum dots of the quantum chip. As a result, after applying an external magnetic field 406, the ferromagnetic insulator layer is magnetized, and a global stray magnetic field Bstray407 is affecting the quantum dots.

[0086] Furthermore, the quantum chip can be configured, such that the stray magnetic field generated by the ferromagnetic insulator is tunable by varying the thickness or composition of the ferromagnetic insulator. Adjusting the thickness allows for precise control over the strength of the magnetic field, with thicker layers typically generating stronger fields. Alternatively, the composition of the layer can be modified, such as by incorporating dopants or alloying with other materials, to tailor the magnetic properties, including coercivity, anisotropy, or saturation magnetization.

[0087] This tunability provides significant flexibility in designing the quantum chip for various applications. For instance, weaker fields may be sufficient for systems with high g-factor quantum dots, while stronger fields may be necessary for other spin qubit applications. In addition, stronger fields would allow a user to apply smaller external magnetic fields, simplifying the hardware requirements for performing qubit operation experiments. Such control over the magnetic field enables dynamic adaptability of the quantum chip to diverse operational requirements.

[0088] In an embodiment, the quantum chip can be configured, such that the ferromagnetic insulator has varying thickness across the semiconducting substrate. A non-uniform thickness profile can create spatially varying magnetic fields, which may be useful to enable individual addressability of quantum dots, or for implementing magnetic field gradients. These gradients can be employed to e.g. induce controlled interactions between quantum dots. The thickness variation may be achieved during deposition by using masks or by controlling the deposition parameters, such as the angle ofP7539PC00

[0089] incidence or material flux. This approach enables precise tailoring of the magnetic field landscape across the quantum chip.

[0090] In an embodiment, the ferromagnetic insulator has a varying thickness across the semiconducting substrate, wherein the thickness is larger than 1 nm, preferably larger than 5 nm, more preferably larger than 10 nm, even more preferably larger than 12 nm, most preferably larger than 15 nm. The variation in thickness of the ferromagnetic insulator allows for controlled modification of the stray magnetic field strength at different locations on the quantum chip. By increasing the thickness in certain regions, a stronger local magnetic field can be generated, which may be beneficial for selectively shifting the energy levels of specific quantum dots. In contrast, thinner regions may be used where weaker magnetic fields are required, for example to create a quantum chip where each quantum dot has a distinct Larmor frequency. Therefore, this variation enables precise tailoring of the quantum chip, ensuring optimized qubit performance and addressability.

[0091] For example, a gradient change of the ferromagnetic insulator thickness may be engineered, in order to induce a different Bstrayon each of the plurality of quantum dots in a group of quantum dots that are in a target area. Such a technique enables individual addressability of the quantum dots, as each quantum dot would correspond to a specific Larmor frequency.

[0092] Moreover, the quantum chip can be configured, such that the ferromagnetic insulator has a gradient thickness profile, such that the thickness gradually increases or decreases across at least a portion of the semiconducting substrate. A gradient thickness profile may provide a smooth transition of the stray magnetic field across the quantum chip, enabling the implementation of a controlled magnetic field landscape. This configuration may be advantageous in tuning qubit energy levels across an array, allowing for frequency-selective qubit addressing or optimized coupling between quantum dots.

[0093] The gradual variation in thickness can be engineered during deposition processes such as molecular beam epitaxy (MBE), atomic layer deposition (ALD), or pulsed laser deposition (PLD), by engineering a mask profile using lithography techniques that has a varying thickness. Additionally, another way of implementing a gradient in theP7539PC00

[0094] thickness of the ferromagnetic insulator is to do a series of lithography steps, each tailored for a specific ferromagnetic insulator layer thickness. Furthermore, the variation in thickness of the ferromagnetic insulator can be configured to produce a spatially varying stray magnetic field across the plurality of quantum dots. By tailoring the magnetic field gradient, qubits can be individually addressed using frequency-selective techniques, allowing for high-precision quantum operations.

[0095] In an embodiment, the quantum chip can be configured, such that the gradient thickness profile has steps of larger than 0.5 nm, preferably larger than 1 nm, more preferably larger than 3 nm, most preferably larger than 5 nm. A stepped gradient profile provides discrete changes in the ferromagnetic insulator thickness rather than a continuous variation, which can facilitate reproducible and well-defined magnetic field differences between quantum dots. This stepped variation can be achieved through controlled layer deposition using masked deposition techniques or lithographic patterning, ensuring that the thickness transitions occur at predefined locations on the quantum chip.

[0096] The stepwise variation in thickness of the ferromagnetic insulator is configured to produce a spatially varying stray magnetic field across the plurality of quantum dots. This enables region-specific control over qubit resonance frequencies, allowing for selective qubit addressing and tunable qubit interactions.

[0097] Furthermore, the quantum chip can be configured, such that the ferromagnetic insulator has discrete thickness regions. Discrete thickness regions enable structured control over the spatial distribution of the stray magnetic field, allowing for engineered qubit environments where each region experiences a distinct magnetic field strength. This configuration can be beneficial for systems where qubits need to be grouped into different frequency zones for selective addressing or for implementing multi-qubit coupling schemes. The discrete thickness regions can be patterned using photolithography and etching techniques, ensuring that specific areas of the quantum chip have precise magnetic properties.

[0098] In addition, the quantum chip can be configured, such that the discrete thickness regions have thickness values larger than 1 nm, preferably larger than 5 nm, more preferably larger than 10 nm, even more preferably larger than 12 nm, most preferablyP7539PC00

[0099] larger than 15 nm. Depending on the type of application, different ranges of thicknesses may be used.

[0100] Moreover, the quantum chip can be configured, such that the generated stray magnetic field is preferably larger than 0.01 T, preferably larger than 0.1 T, more preferably larger than 0.25 T, even more preferably larger than 0.5 T, most preferably larger than 1 T. Stronger stray magnetic fields are beneficial for inducing larger energy splittings in the quantum dots, which may improve the stability and coherence of spin qubits by reducing their susceptibility to noise. Generally, having larger stray magnetic fields enables a user to apply lower external magnetic fields, simplifying the need for including large superconducting magnets in the cryostats where the quantum chips are loaded and measured. The magnetic field strength can be tailored by adjusting the material properties of the ferromagnetic insulator, such as its saturation magnetization, as well as the layer’s thickness or composition.

[0101] System for manipulating quantum dots

[0102] The present disclosure further relates to a system for manipulating quantum dots that comprises the quantum chip and external components for the magnetization of the ferromagnetic insulator, and the control and operation of the plurality of quantum dots. Specifically, the system comprises a quantum chip comprising a semiconducting substrate comprising a plurality of quantum dots, each quantum dot configured to host a two-level system, wherein said two-level system is associated with an energy difference, and a ferromagnetic insulator arranged in a predefined pattern to selectively cover specific quantum dots. The system may further comprise a magnetic field generator configured to generate an external magnetic field to magnetize the ferromagnetic insulator, and a waveform source configured to generate electrical pulses, thereby exciting the two-level systems of the plurality of quantum dots, and / or transporting a charge carrier from a first quantum dot to a second quantum dot. The magnetized ferromagnetic insulator can induce a magnetic field affecting the quantum dot(s) that is arranged to cover, thereby modifying the energy difference of the corresponding two-level system(s), and enabling the waveform source to individually excite the plurality of quantum dots.

[0103] The external magnetic field provided by the magnetic field generator serves to magnetize the ferromagnetic insulator, which, in turn, modifies the Larmor frequenciesP7539PC00

[0104] of the quantum dots. This allows the waveform source to selectively target individual quantum dots by generating signals that match their modified energy difference, enabling precise control over qubit operations. Such selectivity is critical in large-scale quantum computing systems where individual addressability and minimal crosstalk between quantum dots are required.

[0105] The magnetic field generator may be any suitable magnet that can operate in cryogenic environments, such as superconducting magnets. These superconducting magnets can be positioned at a close vicinity to the quantum chip, enabling a user to control the applied external magnetic field. The waveform source may relate to various devices capable of generating tailored electromagnetic signals suitable for interacting with the two-level systems of quantum dots. Specific examples of such sources include microwave signal generators, which are often used to produce high-frequency signals for coherent control of spin qubits. These devices can generate continuous-wave (CW) signals or pulsed signals with precisely controlled amplitude, frequency, and phase to perform operations such as qubit initialization, manipulation, and readout.

[0106] Additionally, the waveform source may include arbitrary waveform generators (AWGs) capable of generating complex, time-varying electrical signals. AWGs are particularly useful for creating customized pulse sequences required for advanced qubit control, such as dynamical decoupling or multi-qubit gate operations. Such sources can generate signals in a broad frequency range, from the gigahertz regime for spin qubits to the terahertz range for other qubit systems.

[0107] Electromagnetic sources such as radio frequency (RF) signal generators may also be employed, especially in applications where lower frequencies are required for specific qubit interactions or transport mechanisms. In some variations, the waveform source may include optical signal generators, such as lasers, for systems where quantum dots are optically active or where photon-mediated interactions are needed. The waveform source could also include devices for generating hybrid signals combining RF, microwave, and optical components to address quantum dots in different energy configurations or environments.P7539PC00

[0108] The application of the various signals from the waveform source may be implemented by connecting the waveform source to a gate electrode, thereby transmitting a signal with the desired frequency towards a quantum dot.

[0109] Fig. 5 shows a schematic of a system 500 for manipulating quantum dots. The system comprises a quantum chip 501 , a magnetic field generator 502 and a waveform source 503. The magnetic field generator may be a superconducting coil, generating an external magnetic field Bext, which interacts with the plurality of quantum dots 504 and magnetizes the ferromagnetic insulator layer 505. The waveform source may have probes that are connected to the gate electrodes 506. An example of interaction with quantum dots is shown, where a first probe is connected to a quantum dot that is covered by a ferromagnetic insulator. In this case, the transmitted signal has a frequency fi507, corresponding to the Larmor frequency of the targeted quantum dot. Interacting with a second quantum dot that is not covered by a ferromagnetic material requires a different frequency, namely f 2508, which corresponds to the Larmor frequency of the second quantum dot.

[0110] In addition, the system can be configured, such that the ferromagnetic insulator is patterned to selectively cover specific quantum dots. As also described in the sections above, patterning the ferromagnetic insulator to selectively cover specific quantum dots allows for localized magnetic field control, enabling individual addressability of quantum dots within the quantum chip. This approach can be particularly useful in systems requiring different magnetic environments for neighbouring quantum dots, such as when implementing qubit-specific Larmor frequencies for addressing or tuning interactions between qubits. The patterning process may involve lithography techniques, such as electron-beam or photolithography, followed by etching or lift-off processes to define the desired mask. By selectively covering certain quantum dots with a ferromagnetic insulator, the system can achieve fine-tuned magnetic fields where needed, while minimizing magnetic interference with other regions of the chip. This selective patterning enables individual addressability of qubits by tailoring the Larmor frequency of the qubits and preventing a waveform source from interacting with more than one qubit at a time.P7539PC00

[0111] The system for manipulating quantum dots can be configured according to any of the embodiments described herein.

[0112] Moreover, the system can be configured, such that the external magnetic field is larger than 5 mT, more preferably larger than 10 mT, most preferably larger than 15 mT, such as 20 mT. Depending on the saturation magnetization of the ferromagnetic insulator, different magnitudes of external magnetic field may be chosen. That magnitude may depend on the type of ferromagnetic material chosen, its thickness, and the g-factor of the quantum dots. Therefore, depending on the type of application, different ranges of external magnetic field may be applied.

[0113] The present disclosure further relates to a method for probing individual qubits in a spin qubits system. The method, which is also shown in Fig. 6, comprising the steps of obtaining a quantum chip comprising a semiconducting substrate, the semiconducting substrate comprising a plurality of quantum dots, wherein a ferromagnetic insulator is arranged in a predefined pattern to selectively cover specific quantum dots 600, magnetizing the ferromagnetic insulator layer 601, and exciting the plurality of quantum dots using an electric field or a magnetic field, thereby inducing spin transitions 602.

[0114] The steps of the method for probing individual qubits in a spin qubit system can be according to any one of the embodiments described herein.

[0115] Method for manufacturing a quantum chip

[0116] The present disclosure further relates to a method for manufacturing a quantum chip, the method comprising the steps of obtaining a semiconducting substrate, the semiconducting substrate comprising a plurality of quantum dots, depositing a plurality of electrodes on the semiconducting substrate, and depositing a ferromagnetic insulator in a predefined pattern to selectively cover specific quantum dots. The method may further comprise the step of depositing a dielectric layer between the gate electrodes and the semiconducting substrate.

[0117] In an embodiment, the step of depositing a plurality of electrodes may be performed by electron beam lithography or photolithography fabrication. In addition, the step of arranging a ferromagnetic insulator may be performed by electron beam lithography orP7539PC00

[0118] photolithography fabrication.

[0119] In an embodiment, the step of arranging a ferromagnetic insulator relates to forming a pattern to selectively cover specific quantum dots. In an embodiment, the pattern may be formed by depositing a mask covering the semiconducting substrate, said mask is optionally fabricated using electron beam lithography of photolithography fabrication.

[0120] For example, standard electron beam lithography or photolithography techniques can be employed to realize the gate electrodes and the ferromagnetic insulator. In an embodiment, the patterning process may begin with the deposition of a resist layer, which serves as a temporary protective coating to define the regions where material will be selectively deposited or etched. The resist layer may be applied using standard spin-coating techniques to achieve a uniform thickness across the substrate.

[0121] Following resist deposition, the quantum chip may be exposed to a lithographic patterning process, such as photolithography or electron-beam lithography (EBL), depending on the required feature size and resolution. In the case of photolithography, a photomask containing the desired pattern is aligned with the substrate, and the resist is exposed to a specific wavelength of light. Alternatively, EBL may be used for nanoscale patterning by directly writing the desired pattern onto the resist using a focused electron beam.

[0122] Once the resist is exposed, the chip undergoes a developing process, where the exposed (or unexposed) portions of the resist are removed, depending on whether a positive or negative resist is used. This developing step creates a patterned resist mask that defines the areas for subsequent material deposition or etching.

[0123] In an embodiment, a ferromagnetic insulator may be arranged to cover (via deposition or growth) using a suitable thin-film deposition technique, such as sputtering, atomic layer deposition (ALD), pulsed laser deposition (PLD), or molecular beam epitaxy (MBE). The deposition or growth process is performed under controlled vacuum conditions to ensure high purity and uniformity of the ferromagnetic material. The thickness of the deposited layer may be tuned based on process parameters such as deposition rate, substrate temperature, or precursor exposure time in the case of ALD.P7539PC00

[0124] Following the step of depositing or growing the ferromagnetic insulator, a lift-off process may be performed to remove the remaining resist and any unwanted ferromagnetic material deposited on top of the resist. The lift-off process typically involves immersing the chip in a solvent or developer solution, such as acetone or N-methyl-2-pyrrolidone (NMP), to dissolve the resist layer and lift away the unwanted material, leaving behind the patterned ferromagnetic insulator regions on the substrate. In some embodiments, ultrasonic agitation or heating may be used to enhance the liftoff efficiency.

[0125] Alternatively, instead of a lift-off process, the ferromagnetic insulator may be deposited uniformly across the substrate, and etching techniques such as reactive ion etching (RIE) or wet chemical etching may be used to remove the unwanted material in a subsequent step. The etching process may be performed using a selective etchant that removes the ferromagnetic material while preserving the underlying semiconductor substrate.

[0126] Throughout these fabrication steps, the quantum chip may be processed in a cleanroom environment to minimize contamination and ensure high-quality device performance. Standard cleanroom protocols, such as substrate cleaning using oxygen plasma or solvent rinsing, may be employed before and after each processing step to maintain the integrity of the patterned features.

[0127] In an embodiment, it can be beneficial to fabricate certain features of the device on a second substrate, in order to minimize the fabrication steps performed on the semiconducting substrate. Such a process is beneficial, as the fewer fabrication steps performed on the device substrate, the higher the quality of the quantum dots, as lithography and chemical etchants can damage the surface of the semiconducting substrate. Specifically, the method may comprise the step of obtaining a second substrate, the second substrate comprising a plurality of electrodes, and attaching the second substrate to a surface of the semiconducting substrate. For example, the second substrate can have a pattern of electrodes, such as gate electrodes, arranged such that the electrodes have a terminal on a surface of the second substrate. That surface can be attached on a surface of the semiconducting substrate, thereby forming a quantum chip.P7539PC00

[0128] By utilizing these lithographic techniques and thin-film deposition processes, precise control over the spatial distribution and thickness of the ferromagnetic insulator can be achieved, enabling the desired magnetic field modulation across the quantum chip for qubit control and operation. The one or more ferromagnetic insulator layers may also be defined utilizing consecutive lithography steps.

[0129] The method for manufacturing a quantum chip may be according to any one of the embodiments described herein.

[0130] Examples

[0131] Fig. 7 shows a simulation 700 of the stray magnetic field lines generated by a ferromagnetic oxide cuboid for a quantum chip 701 comprising a ferromagnetic insulator. As described herein, the ferromagnetic insulator can comprise one or more layers. The simulation estimates the magnetic flux density along the X, Y, and Z dimensions 702. In order to display the magnetic field generated by the ferromagnetic insulator, a scan of the X-Y plane at a depth 50 nm below the ferromagnetic insulator is prepared 800. Fig. 8 shows a schematic of a scan area 801 on the X-Y plane in the vicinity of a magnetic moment 802 of a ferromagnetic oxide cuboid.

[0132] Fig. 9 shows magnetic field simulations of a magnetic moment in an X-Y plane for the Bx 900, By 901 , and Bz 902 component of the stray magnetic field. Each simulation is prepared as a function of a displacement on the X axis 903 and as a function of a displacement on the Y axis 904. Each simulation is generated at a distance 50 nm below the ferromagnetic insulator, in order to simulate the actual position of quantum dots in quantum chips. The colour-bar 905 indicates the value of the simulated magnetic field on each X-Y position.

[0133] For the Bx 900, it is evident that a significant magnetic field of approximately -25 mT is generated by the ferromagnetic insulator, for X, Y = 0, corresponding to coordinates below the magnetic moment. Even at small Z displacement of 50 nm, significant magnetic fields can still be generated and can have an effect on the quantum dots. For example, even if a quantum dot is positioned 50 nm off the center, for example at (X, Y)=(-40 nm, -40 nm), a magnetic field of magnitude 15 mT can be generated.

[0134] Depending on the g-factor of the quantum dot, such a magnetic field can be enough in order to create a finite Zeeman splitting on a state of the quantum dot, thereby enablingP7539PC00

[0135] individual addressability, since the quantum dots in the proximity will not be affected by the generated magnetic field. For example, if a second quantum dot is positioned at Y=-75 nm, then the effective magnetic field is insignificant, and close to 0 mT. Different types of ferromagnetic materials can be chosen, as well as different thicknesses, in order to tune the magnitude of the generated magnetic fields, and how the generated magnetic fields affect the quantum dots.

[0136] Depending on the type of quantum dots, different magnetic field components can be leveraged to enable addressability, since various quantum materials exhibit different g-factors depending on the direction of the magnetic field. For example, the effect of the By 901 and Bz 902 component is significantly different to Bx 900, as shown in Fig. 9. However, the Bz magnetic fields reach up to 30 mT in magnitude, while the By reaches up to 8 mT. As a result, the dominant vector is the Bx, but different conditions can be created depending on the magnetization of the ferromagnetic insulator. Therefore, depending on the type of application and the details of the quantum chip, the ferromagnetic insulator can be engineered such that the intended magnetic fields are generated on the intended locations of the semiconducting substrate. Naturally, the magnitude and direction of the generated magnetic fields depend on the magnetization of the ferromagnetic insulator.

[0137] Hence, it is clear that a magnetic field gradient can be engineered, enabling the quantum chip to create different effective magnetic fields on target locations. As a result, certain quantum dots can require different excitation signals compared to other quantum dots in their vicinity, thereby enabling selective control of the quantum dots. Specifically, the Larmor frequency of certain quantum dots can be affected by selectively depositing a ferromagnetic insulator on specific quantum dots. As a result, such a geometry enables individual addressability of the quantum dots.

[0138] Fig. 10 shows simulations of the stray magnetic field |B| 1000, Bx 1001, By 1002 and Bz 1003 as a function of distance from a magnetic moment 1004.

[0139] Fig. 11 shows simulations of generated |Bx| 1100 as a function of ferromagnetic insulator length 1101 for four different ferromagnetic insulator thicknesses 1102, fora distance 50 nm below the ferromagnetic insulator. It is evident that the thicker theP7539PC00

[0140] ferromagnetic insulator, the stronger the generated magnetic field. Further, the longer the side length of the ferromagnetic insulator, the stronger the generated magnetic fields. In this simulation, the ferromagnetic insulator is EuO, magnetized along the X axis Mx= 1.9-106A / m. Such simulations shown in the Figs. 9-11 can be prepared prior to fabricating any quantum chip, in order to optimize the thickness and the pattern of the ferromagnetic insulator. For example, the thickness of the deposited ferromagnetic insulator can be optimized, by performing such simulations and estimating a range of thickness that is suitable for each application.

Claims

P7539PC00Claims1. A quantum chip for operation and manipulation of semiconductor spin qubits, the quantum chip comprising• a semiconducting substrate comprising a plurality of quantum dots, each quantum dot configured to host a two-level system, wherein said two- level system is associated with an energy difference, and • a ferromagnetic insulator arranged in a predefined pattern to selectively cover specific quantum dots.

2. The quantum chip according to claim 1 , wherein the semiconducting substrate comprises a material selected from the group of: C, InAs, InSb, Si, GaAs, AIGaAs, Ge, SiGe, or InP.

3. The quantum chip according to any one of the preceding claims, wherein the ferromagnetic insulator comprises one or more layers.

4. The quantum chip according to any one of the preceding claims, wherein the semiconducting substrate has a thickness of larger than 100 pm, preferably larger than 250 pm, more preferably larger than 400 pm.

5. The quantum chip according to any one of the preceding claims, wherein the plurality of quantum dots are embedded in the semiconducting substrate.

6. The quantum chip according to any one of the preceding claims, wherein the plurality of quantum dots are formed by electrostatic confinement using a plurality of gate electrodes arranged on the semiconducting substrate.

7. The quantum chip according to any one of the preceding claims, wherein a plurality of gate electrodes are utilized to control the number of electrons or holes on the plurality of quantum dots.

8. The quantum chip according to any one of the preceding claims, wherein the quantum chip comprises a dielectric layer arranged on the semiconducting substrate.29P7539PC009. The quantum chip according to claim 8, wherein the dielectric layer has a thickness lower than 100 nm, preferably lower than 50 nm, more preferably lower than 25 nm, even more preferably lower than 10 nm, most preferably lower than or equal to 5 nm.

10. The quantum chip according to any one of the claims 8-9, wherein the dielectric layer comprises a material selected from the group of: AI2O3, HfC>2, SiC>2, SiaN4, or hexagonal Boron Nitride (h-BN), and Ta2Os.

11. The quantum chip according to any one of the preceding claims, wherein the energy difference of the two-level system in the plurality of quantum dots is associated with a Larmor frequency.

12. The quantum chip according to any one of the preceding claims, wherein the energy difference of the two-level system in the plurality of quantum dots is further tunable via an external electric or magnetic field.

13. The quantum chip according to any one of the preceding claims, wherein the plurality of quantum dots are configured to host electron spin qubits or hole spin qubits.

14. The quantum chip according to any one of the preceding claims, wherein at least one quantum dot of the plurality of quantum dots comprises an unpaired electron or an unpaired hole.

15. The quantum chip according to any one of the preceding claims, wherein adjacent quantum dots are capacitively coupled or tunnel-coupled.

16. The quantum chip according to any one of the preceding claims, wherein the plurality of quantum dots are arranged in a linear array, two-dimensional array or in a three-dimensional array.

17. The quantum chip according to any one of the preceding claims, wherein the ferromagnetic insulator comprises a material selected from the group of: EuS,30P7539PC00EuO, NiFe2O4, CoFe2O4, MgFe2O4, Mn3O4, or LiFe5O818. The quantum chip according to any one of the preceding claims, wherein the ferromagnetic insulator has a thickness larger than 1 nm, preferably larger than 5 nm, more preferably larger than 10 nm, even more preferably larger than 12 nm, most preferably larger than 15 nm.

19. The quantum chip according to any one of the preceding claims, wherein the ferromagnetic insulator is arranged to cover all the quantum dots of the quantum chip.

20. The quantum chip according to any one of the preceding claims, wherein the stray magnetic field generated by the ferromagnetic insulator is tunable by varying the thickness or composition of the ferromagnetic insulator.

21. The quantum chip according to any one of the preceding claims, wherein the ferromagnetic insulator has varying thickness across the semiconducting substrate.

22. The quantum chip according to claim 21, wherein the ferromagnetic insulator has a varying thickness across the semiconducting substrate, wherein the thickness is larger than 1 nm, preferably larger than 5 nm, more preferably larger than 10 nm, even more preferably larger than 12 nm, most preferably larger than 15 nm.

23. The quantum chip according to any one of claims 21-22, wherein the ferromagnetic insulator has a gradient thickness profile, such that the thickness gradually increases or decreases across at least a portion of the semiconducting substrate.

24. The quantum chip according to claim 23, wherein the gradient thickness profile has steps of larger than 0.5 nm, preferably larger than 1 nm, more preferably larger than 3 nm, most preferably larger than 5 nm.P7539PC0025. The quantum chip according to any one of claims 21-24, wherein the ferromagnetic insulator has discrete thickness regions.

26. The quantum chip according to claim 25, wherein the discrete thickness regions have thickness values larger than 1 nm, preferably larger than 5 nm, more preferably larger than 10 nm, even more preferably larger than 12 nm, most preferably larger than 15 nm.

27. The quantum chip according to any one of the preceding claims, wherein the generated stray magnetic field is larger than 0.01 T, preferably larger than 0.1 T, more preferably larger than 0.25 T, even more preferably larger than 0.5 T, most preferably larger than 1 T.

28. The quantum chip according to any one of the preceding claims, comprising a second substrate attached on the semiconducting substrate, wherein a plurality of gate electrodes are arranged on the second substrate such that the plurality of gate electrodes interact with the plurality of quantum dots.

29. A system for manipulating quantum dots, comprising• a quantum chip according to any one of the preceding claims,• a magnetic field generator configured to generate an external magnetic field to magnetize the ferromagnetic insulator, and• a waveform source configured to generate electrical pulses, thereby exciting the two-level systems of the plurality of quantum dots, and / or transporting a charge carrier from a first quantum dot to a second quantum dot,wherein the magnetized ferromagnetic insulator induces a magnetic field affecting the quantum dot(s) that it is arranged to cover, thereby modifying the energy difference of the corresponding two-level system(s), and enabling the waveform source to individually excite the plurality of quantum dots.

30. The system according to claim 29, wherein the quantum chip is the quantum chip according to any one of claims 1-28.P7539PC0031. The system according to any one of the claims 29-30, wherein the external magnetic field is larger than 5 mT, more preferably larger than 10 mT, most preferably larger than 15 mT, such as 20 mT.

32. A method for probing individual qubits in a spin qubit system, the method comprising the steps of• Obtaining a quantum chip comprising a semiconducting substrate, the semiconducting substrate comprising a plurality of quantum dots, wherein a ferromagnetic insulator is arranged in a predefined pattern to selectively cover specific quantum dots,• magnetizing the ferromagnetic insulator, and• exciting the plurality of quantum dots using an electric field or a magnetic field, thereby inducing spin transitions.

33. The method according to claim 32, wherein the quantum chip is the quantum chip according to any one of claims 1-28.

34. A method for manufacturing a quantum chip, the method comprising the steps of• obtaining a semiconducting substrate, the semiconducting substrate comprising a plurality of quantum dots,• depositing a plurality of electrodes on the semiconducting substrate, and • arranging a ferromagnetic insulator in a predefined pattern to selectively cover specific quantum dots.

35. The method according to claim 34 wherein the step of depositing a plurality of electrodes is performed by electron beam lithography or photolithography fabrication.

36. The method according to any one of the claims 34-35, wherein the step of arranging a ferromagnetic insulator is performed by electron beam lithography or photolithography fabrication.

37. The method according to any one of the claims 34-36, wherein the step of arranging a ferromagnetic insulator relates to forming a pattern to selectively33P7539PC00cover specific quantum dots.

38. The method according to claim 37, wherein the pattern is formed by depositing a mask covering the semiconducting substrate, said mask is optionally fabricated using electron beam lithography or photolithography fabrication.

39. The method according to any one of the claims 34-38, further comprising the step of obtaining a second substrate, the second substrate comprising a plurality of electrodes, and attaching the second substrate to a surface of the semiconducting substrate.

40. The method according to any one of claims 34-39, wherein the quantum chip is the quantum chip according to any one of claims 1-28.

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