Method of producing an optoelectronic component and optoelectronic component
Patent Information
- Application Number
- PCT/EP2026/054973
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-24
- Filing Date
- 2026-02-24
- Publication Date
- 2026-08-27
Smart Images
Figure EP2026054973_27082026_PF_FP_ABST
Abstract
Description
[0001] 2024PF00955 1
[0002] METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT AND OPTOELECTRONIC COMPONENT
[0003] DESCRIPTION
[0004] The present invention refers to a method of producing an optoelectronic component and an optoelectronic component .
[0005] This patent application claims the priority of the German patent application DE 10 2025 106 818. 6, the disclosure of which is hereby incorporated by reference .
[0006] From the state of the art, light emitting diode chips (LED chips) with a reflector comprising silver (Ag) are known. However, it is difficult to process Ag thin films without unwanted contaminations and a creation of leakage channels through diffusion or electro-migration of the reflector material at temperatures just above approximately 100°C in an atmosphere containing oxygen and / or water .
[0007] It is also known to structure reflector materials by wet etching or by lift-off . Wet etching has an inherent drawback in that always some under etching occurs that needs to be accounted for in tolerance chains . This can cause a significant loss of a reflectivity in the under etched region which also represents a weak spot for a chemical attack by gases, liquids or diffusing metal atoms with respect to the reflector material causing reliability problems .
[0008] From the state of the art, sputtering of reflector materials in combination with lithography and lift-off is also known. This solution has a different tolerance drawback defined by a photoresist undercut which causes a reflector edge that gradually gets thinner, effectively resulting in a lower reflectivity of the outmost edge of the reflector .
[0009] A vapor phase deposition of Ag could resolve some of these issues, but is usually also associated with a gradually thin-2024PF00955 2
[0010] ning layer at the edge of the deposition region. Also, vapor phase deposition through a mask opening causes the Ag vapor to impinge on a substrate at different angles and therefore causing a slight misalignment of a deposited structure with respect to the mask opening. Furthermore, sputtering often produces higher reflectivity Ag layers which is crucial for an overall chip brightness .
[0011] In all of the described cases, there is a practical minimum distance between an edge of the ref lector / mirror and an edge of the optoelectronic component or a blind hole or a via that needs to be etched through the LED chip in order to contact semiconductor layers of the LED chip, typically n-side semiconductor layers . As structuring of the reflector is a critical issue as described and not reproducible, it requires a safety margin, leading to the separating area between the reflector and the edge of the optoelectronic component or the blind hole or the via being larger than desired. This lateral distance between the Ag reflector and the edge of the optoelectronic component or the blind hole or the via can be several pm, e . g. 2-3pm.
[0012] When later filling the blind hole with a reflective metal, there is a lateral gap between n- and p-metal reflectors, where light is trapped and absorbed, leading to a loss of brightness of the LED. State-of-the-art to reduce these negative effects is to overlap the n-contact reflecting part with the p-contact reflector .
[0013] Direct plasma etching of Ag could solve some of the mentioned problems, but is rather difficult to perform and it is challenging to avoid any Ag residues in the etched areas .
[0014] An obj ective of the present invention is to specify an improved method of producing an optoelectronic component and to provide an improved optoelectronic component . This obj ective is solved by a method of producing an optoelectronic component and an optoelectronic component comprising the features2024PF00955 3
[0015] of the respective independent claims . Advantageous embodiments are specified in dependent claims .
[0016] A method of producing an optoelectronic component comprises the following method steps . An optoelectronic semiconductor chip designed to emit electromagnetic radiation and comprising a top side and a bottom side opposite the top side is provided. A first layer is arranged at the top side of the optoelectronic semiconductor chip . A second layer is arranged at the first layer such that the first layer is arranged between the optoelectronic semiconductor chip and the second layer . The first layer and the second layer are structured laterally to form a first mask layer and a second mask layer, respectively, and to form an undercut between the top side of the optoelectronic semiconductor chip and the second mask layer such that the second mask layer protrudes over the first mask layer in a direction parallel to the top side of the optoelectronic semiconductor chip . A reflective material is arranged at the top side of the optoelectronic semiconductor chip and at the second mask layer . The reflective material arranged at the top side of the optoelectronic semiconductor chip is arranged in a region of the undercut and is in direct contact with the first mask layer . The second mask layer is removed with the reflective material arranged at the second mask layer .
[0017] The method is based on the idea to produce an optoelectronic component which comprises a reflector which is encapsulated at least laterally. The reflector can also be called a mirror and is formed by the reflective material . The reflector is encapsulated laterally by arranging the reflective material at the top side of the optoelectronic semiconductor chip, whereby the reflective material is also arranged in the region of the undercut, i . e . between the top side of the optoelectronic semiconductor chip and the and the second mask lay-er .2024PF00955 4
[0018] Furthermore, the reflective material is in direct contact with the first mask layer after arranging the reflective material, particularly in direct contact with side walls of the first mask layer extending between the top side of the optoelectronic semiconductor chip and the second mask layer . A direct contact can also be called a mechanical contact or a cohesive connection.
[0019] Thus, the reflective material can be structured precisely and comprises a vertical edge with respect to the top side of the optoelectronic semiconductor chip since the reflective material is enclosed or encapsulated laterally by the first mask layer . Advantageously, diffusion or electro-migration leakage channels can be avoided by encapsulating the reflective material laterally as the reflective material does not comprise any undercuts or voids in the region of the edge .
[0020] Also, a significant loss of reflectivity of the reflective material in the region of the first mask layer can be avoided since the reflective material comprises a thickness which is not decreasing significantly with a decreasing distance to the edge, i . e . to the first mask layer, enabling a maximum reflectivity all the way to the edge of the reflective material in the region of the first mask layer .
[0021] Apart from that, no additional lithography step is required to structure the reflective material . The first mask layer remains as a part of the optoelectronic component after production and may only be removed partially to create blind holes or vias extending through the first mask layer .
[0022] The first mask layer and the second mask layer form a dual mask comprising the undercut . In an embodiment the first layer comprises a dielectric material and / or the second layer comprises a photoresist . For example, the first layer comprises silicon dioxide (SiCt) . Alternatively, the first mask layer can comprise another dielectric material, for example AI2O3. The second layer can comprise a positive or a negative2024PF00955 5
[0023] photoresist . However, any other suitable material may be used, e . g. a salt . Structuring of the second layer to form the second mask layer is performed by lithography and / or structuring of the first layer to form the first mask layer is performed by etching. Etching of the first layer comprises a step of etching the first layer perpendicularly to the top side of the optoelectronic semiconductor chip to form the first mask layer and a step of etching the first mask layer parallel to the top side of the optoelectronic semiconductor chip to form the undercut .
[0024] In this embodiment the dual mask comprises a dielectric hard mask and a photoresist mask. The dielectric hard mask remains as a part of the optoelectronic component whereas the photoresist mask is removed during the production of the optoelectronic component . Etching of the first layer can be performed by direct plasma etching or alternatively by wet chemical etching. As an example, etching the first layer perpendicu-larly / vertically can be performed by plasma etching, whereas etching the first mask layer parallel to the top side of the optoelectronic semiconductor chip to form the undercut can be performed by wet chemical etching. However, both etching steps can be performed by using the same etching method, e . g. direct plasma etching.
[0025] Advantageously, lateral dimension of the dielectric mask can be well defined, particularly by directional plasma etching, followed by a slower and more controlled under-etching step to form the undercut of the dual mask. Thus, the reflective material follows the dielectric mask exactly enabling an improved reproducibility of the edge of the reflective material compared to structuring of the reflective material by wet chemical etching or sputtering of the reflective material with a conventional photoresist mask.
[0026] In an embodiment a gap remains between the reflective material and the second mask layer in the region of the undercut after arranging the reflective material . Removing of the sec-2024PF00955 6
[0027] ond mask layer is performed by dissolving the second mask layer . Advantageously, the second mask layer is accessible through the gap such that the second mask layer can be exposed to a solvent and removed easily.
[0028] In an embodiment the following additional method step is performed after removing the second mask layer . The first mask layer is planarized. Planarization can be performed by chemical mechanical polishing (CMP) , as an example . Advantageously, a planarization of a dielectric hard mask is facilitated compared to a planarization of a metal, which is currently state-of-the-art for thin solder wafer bonding. The first mask layer can be planarized such that reflective material is flush with the first mask layer . Such a planar configuration can advantageously facilitate an implementation of thin solder wafer bonding techniques .
[0029] In an embodiment a dielectric mirror is arranged between the top side of the optoelectronic semiconductor chip and the first layer . The dielectric mirror can also be called a Bragg-mirror . Advantageously, the reflective material can comprise a vertical edge and a homogenous thickness without an undercut even when arranged at or on the dielectric mirror . Typically, an Ag film comprises an undercut when deposited on a dielectric mirror and etched by wet chemical etching. However, by applying the dual mask for the deposition of the reflective material solves this problem.
[0030] It is also possible that an indium tin oxide ( ITO) layer is arranged between the optoelectronic semiconductor chip and the dielectric mirror . Advantageously ITO is transparent and electrically conductive enabling a spreading of an electrical current when contacting the optoelectronic semiconductor chip while simultaneously being at least partially transparent for electromagnetic radiation emitted by the optoelectronic semiconductor chip .2024PF00955 7
[0031] In an embodiment the reflective material comprises a metallic material, particularly silver . Advantageously, Ag has a high reflectivity. Also, the reflective and metallic material enables a current spreading, for example of the p-side of the optoelectronic semiconductor chip which enables a more homogenous emission of electromagnetic radiation. Alternatively, the reflective material can comprise another metallic material such as aluminium (Al) or gold (Au) .
[0032] In an embodiment arranging of the reflective material is performed by sputtering. Advantageously, the reflective material comprises a high reflectivity when sputtered on the optoelectronic semiconductor chip . However, the reflective material can be arranged by vapor phase deposition instead or by another deposition method.
[0033] In an embodiment the following method step is performed before or after removing the second mask layer . A diffusion barrier is arranged at a surface of the reflective material averted from the top side of the optoelectronic semiconductor chip . The diffusion barrier can be arranged between the reflective material and the encapsulation layer, for example . The diffusion barrier can comprise a metallic material, e . g. titanium (Ti) . Advantageously, the diffusion barrier additionally protects the reflective material . This protection can be established before or after the second mask layer is removed. After arranging the diffusion barrier, a planarization step can be performed to planarize the diffusion barrier, wherein the first mask layer can be planarized simultaneously.
[0034] In an embodiment the following method step is performed after removing the second mask layer . An encapsulation layer is arranged at a surface of the reflective material averted from the top side of the optoelectronic semiconductor chip and at the first mask layer . The encapsulation layer advantageously encapsulates the reflective material vertically in addition to the lateral encapsulation by the first mask layer . Thus,2024PF00955 8
[0035] the reflective material is sealed and protected against diffusion and also against electro-migration, additionally. This improved encapsulation of the reflective material can allow for chip designs using only the reflective material, such as Ag, as both reflector and current spreader . The encapsulation layer comprises AI2O3 or SiCt or another dielectric material . After arranging the encapsulation layer, a planarization step can be performed to planarize the encapsulation layer, wherein the first mask layer can be planarized simultaneously.
[0036] In an embodiment the following method step is performed after removing the second mask layer . A via extending in a direction perpendicular to the top side of the optoelectronic semiconductor chip through the first mask layer and at least to the top side of the optoelectronic semiconductor chip is created. The via is designed to contact the optoelectronic semiconductor chip electrically. The optoelectronic semiconductor chip comprises a semiconductor layer sequence with an active region. The active region is formed between n-side and p-side semiconductor layers . After the creation of the via also a planarization step can be performed to planarize the encapsulation layer and optionally the first mask layer .
[0037] For example, the p-side layers can be arranged in the region of the top side of the optoelectronic semiconductor chip and the n-side layers can be arranged in the region of the bottom side of the optoelectronic semiconductor chip . In order to contact the n-side semiconductor layers electrically, the via is created. In this case, the via extends perpendicularly to the top side of the optoelectronic semiconductor chip completely through the first mask layer and through the optoelectronic semiconductor chip to the n-side semiconductor layers . The via can also be called a blind hole as it doesn' t have to extend through the whole optoelectronic semiconductor chip .
[0038] The via can be filled with an electrically conductive material . Preferably, this filler material comprises a high reflec-2024PF00955 9
[0039] tivity. Advantageously, a lateral distance between the reflective material and the filler material arranged in the via measured in a direction parallel to the top side of the optoelectronic semiconductor chip can reproduced with high accuracy. Furthermore, this distance can comprise just several hundreds of nanometres, as an example, which is significantly smaller than a distance of 2-3pm known from the state of the art .
[0040] Advantageously, a brightness loss in a region between the reflective material and the filler material, which can be designed as p- and n-type reflectors, respectively, can be reduced significantly due to the relatively small distance between the reflective material and the filler material . Thereby, the optoelectronic component comprises a higher brightness and / or enables the usage of a higher number of (n-) contact vias while maintaining the contact area by designing the vias smaller .
[0041] The via can be created directly after removing the second mask layer . Alternatively, the via can be created after arranging the encapsulation layer . In this case, the via extends vertically through the whole encapsulation layer, optionally through the diffusion barrier, through the whole first mask layer and at least partially through the optoelectronic semiconductor chip .
[0042] In an embodiment the following method step is performed after creating the via . An insulation is arranged on side walls of the via . Advantageously, the insulation passivates the semiconductor layer sequence of the optoelectronic semiconductor chip, i . e . the p / n-junction and also remaining parts of the first mask layer after creating the via laterally. The insulation can extend from a bottom of the via to the encapsulation, for example, whereby the whole layer system of the optoelectronic component is passivated or insulated. The insulation can comprise silicon dioxide (SiCt) or aluminium oxide2024PF00955 10
[0043] (AI2O3) , as an example, or any other suitable dielectric material .
[0044] An optoelectronic component comprises an optoelectronic semiconductor chip designed to emit electromagnetic radiation comprising a top side and a bottom side opposite the top side . A first mask layer is arranged at the top side of the optoelectronic semiconductor chip . A reflective material is arranged at the top side of the optoelectronic semiconductor chip laterally next to the first mask layer . The reflective material is in direct contact with the first mask layer .
[0045] Advantageously, the optoelectronic component comprises a reflector structure formed by the reflective material which is structured with high precision and which can comprise a minimum thickness all the way to the region of its edge, whereby the reflectivity of the reflective material is not reduced in the region of the edge . Also, the reflective material is sealed laterally against contaminations .
[0046] In an embodiment an encapsulation layer is arranged at a surface of the reflective material averted from the top side of the optoelectronic semiconductor chip and arranged the first mask layer . Advantageously, the reflective material is also sealed vertically by the encapsulation layer additionally to being sealed by the first mask layer laterally.
[0047] In another embodiment a via is extending in a direction perpendicular to the top side of the optoelectronic semiconductor chip through the first mask layer and at least to the top side of the optoelectronic semiconductor chip . Advantageously, the optoelectronic component comprises only a small lateral distance between the reflective material and the via . By keeping this distance small the reflectivity of the optoelectronic component can be additionally improved.
[0048] In yet another embodiment an insulation arranged on side walls of the via . Advantageously, the optoelectronic semicon-2024PF00955 11
[0049] ductor chip and the reflective material are insulated additionally.
[0050] The above-described properties, features and advantages of this invention and the way in which they are achieved will become clearer and more clearly understood in association with the following description of the exemplary embodiments which are explained in greater detail in association with the drawings . Here in schematic illustration in each case :
[0051] Fig. 1 : an optoelectronic component according to the state of the art in a cross-sectional side view;
[0052] Fig. 2 : another optoelectronic component according to the state of the art in a cross-sectional side view;
[0053] Fig. 3 : an optoelectronic component according to the present invention in an exemplary embodiment in a cross-sectional side view;
[0054] Fig. 4 to 12 : method steps of a method of producing the optoelectronic component according to Fig. 3.
[0055] Fig. 1 schematically shows an optoelectronic component 1 according to the state of the art in a cross-sectional side view .
[0056] The optoelectronic component 1 comprises an optoelectronic semiconductor chip 2 and a reflective material 3 arranged on the optoelectronic semiconductor chip 2. As an example, the reflective material 3 has been arranged on the optoelectronic semiconductor chip 2 by sputtering. Furthermore, the reflective material 3 has been structured by wet chemical etching.
[0057] The reflective material 3 comprises an under etched edge 4. In the region of the edge 4 the reflective material 3 comprises a lower reflectivity since a thickness of the reflective material 3 is modified in the region of the under etched2024PF00955 12
[0058] edge 4. Apart from a reflectivity loss, the reflective material 3 is also susceptible for contaminations and leakage channels created by diffusion and / or electro-migration in the region of the edge 4 of the reflective material 3.
[0059] Fig. 2 schematically shows another optoelectronic component 1 according to the state of the art in a cross-sectional side view. The optoelectronic components 1 according to Fig. 1 and Fig. 2 comprise similarities . In the following description only differences of the optoelectronic component 1 according to Fig. 2 are described with respect to the optoelectronic component 1 according to Fig. 1. The reference numerals are maintained for identical or similar elements .
[0060] In contrast to the optoelectronic component 1 according to Fig. 1 the optoelectronic component 1 according to Fig. 2 comprises a reflective material 3 which has been structured by arranging the reflective material 3 on the optoelectronic semiconductor chip 2 by sputtering using a mask. The mask is removed after deposition of the reflective material 3.
[0061] In this case, the reflective material 3 comprises an edge 4 which is gradually getting thinner . Due to the change of the thickness of the reflective material 3, the reflective material 3 comprises a reduced reflectivity in the region of the edge 4 .
[0062] The optoelectronic components 1 of Fig. 1 and Fig. 2 both comprise a via 5 extending vertically through the optoelectronic semiconductor chip 2 in order to contact the optoelectronic semiconductor chip 2 electrically. In both cases, a distance 6 between the reflective material 3, i . e . the edge 4 of the reflective material 3 and the via 5 comprises 2-3pm. This large distance 6 additionally creates a loss in reflectivity of the optoelectronic component 1.2024PF00955 13
[0063] Fig. 3 schematically shows an optoelectronic component 100 according to the state of the art in a cross-sectional side view .
[0064] The optoelectronic component 100 comprises an optoelectronic semiconductor chip 101 with a top side 102 and a bottom side 103 opposite the top side 102. The optoelectronic semiconductor chip 101 is designed to emit electromagnetic radiation. The optoelectronic semiconductor chip 101 comprises a semiconductor layer sequence comprising a top layer sequence 104 and a bottom layer sequence 105. The top layer sequence 104 is arranged at the top side 102 of the optoelectronic semiconductor chip 101. The bottom layer sequence 105 is arranged at the bottom side 103 of the optoelectronic semiconductor chip 101. Between the top layer sequence 104 and the bottom layer sequence 105 an active region 106 is formed. In the active region electromagnetic radiation can be generated by a recombination of charge carriers . As an example, the top layer sequence 104 is designed as a p-type layer sequence whereas the bottom layer sequence 105 is designed as an n-type layer sequence . The top layer sequence 104 and the bottom layer sequence 105 exemplarily comprise GaN, InGaN, InGaAlP or InAlGaAs . However, the top and the bottom layer sequences 104, 105 can comprise a different semiconductor . If InAlGaAs is used, the optoelectronic semiconductor chip 101 is designed to emit electromagnetic radiation from the infrared spectral range . In this case, Au can be used as the reflective material rather than Ag.
[0065] A dielectric mirror 107 is arranged at the top side 102 of the optoelectronic semiconductor chip 101. Between the top side 102 of the optoelectronic semiconductor chip 101 and the dielectric mirror 107 a transparent and electrically conductive material is arranged, for example indium tin oxide ( ITO) , which is at least partially transparent for electromagnetic radiation emitted by the optoelectronic semiconductor chip 101. The ITO layer is not shown in Fig. 3 for the sake of simplicity. The dielectric mirror comprises AI2O3 as2024PF00955 14
[0066] an example at a side of the dielectric mirror 107 averted from the top side 102 of the optoelectronic semiconductor chip 101. However, the transparent and electrically conductive material and the dielectric mirror 107 are only optional and can be omitted, respectively.
[0067] A reflective material 108 is arranged at the top side 102 of the optoelectronic semiconductor chip 101. In the exemplary embodiment of Fig. 3, the reflective material 108 is arranged at the dielectric mirror 107 such that the dielectric mirror 107 is arranged between the top side 102 of the optoelectronic semiconductor chip 101 and the reflective material 108. The reflective material 108 comprises Ag, as an example . The reflective material 108 forms a reflector 108 of the optoelectronic component 100. The reflective material 108 therefore can be called reflector 108 or mirror 108.
[0068] Apart from the reflective material 108, a first mask layer 109 is arranged laterally next to the reflective material 108 at the top side 102 of the optoelectronic semiconductor chip 101. The first mask layer 109 comprises SiCt, as an example . The reflective material 108 is in direct contact with the first mask layer 109, i . e . the top side 102 of the optoelectronic semiconductor chip 101 or the optional dielectric mirror 107 are not exposed and covered either by the reflective material 108 or by the first mask layer 109. Since the reflective material 108 is in direct contact with the first mask layer, the reflective material 108 comprises a vertical edge 110. Also, the reflective material 108 is sealed laterally by the first mask layer 109.
[0069] This is in vertical contrast to the reflective material 3 of the optoelectronic components 1 of Fig. 1 and Fig. 2 where the edge 4 is not as vertical and defined as the edge 110 of the reflective material 108 of the optoelectronic component 101 of Fig. 3. For this reason, the reflective material 108 of the optoelectronic component 101 of Fig. 3 comprises a more homogenous reflectivity to the edge 110. Also, the re-2024PF00955 15
[0070] flective material 108 is not as susceptible to contaminations since it is sealed laterally by the first mask layer 108.
[0071] In order to contact the bottom layer sequence 105 of the optoelectronic semiconductor chip 101 the optoelectronic component 100 comprises a via 111. The via 111 extends in a direction perpendicular to the top side 102 of the optoelectronic semiconductor chip 101 through the whole first mask layer 109 and through the optoelectronic semiconductor chip 101 to the bottom layer sequence 105.
[0072] An electrically conductive filler material can be arranged in the via 110 to electrically contact the bottom layer sequence 105. Preferably, the filler material also comprises a high reflectivity. A lateral distance 6 between the reflective material 108 and the via 111 measured in a direction parallel to the top side 102 of the optoelectronic semiconductor chip 101 can be significantly smaller than the distance of 2-3pm shown in Fig. 1 and Fig. 2. In Fig. 3, as an example, this distance 6 can comprise just several hundreds of nm. Particularly, the distance 6 can comprise 500nm or even smaller, e . g. 300nm or even 200nm. Due to this small distance 6 between the reflective material 108 and the filler material which can be arranged in the via 111 a loss of reflectivity can be reduced significantly.
[0073] The reflective material 108 is also sealed vertically by an encapsulation layer 112. The encapsulation layer 112 is arranged at a side of the reflective material 108 averted from the top side 102 of the optoelectronic semiconductor chip 101. The encapsulation layer 112 comprises a dielectric material, e . g. AI2O3 or SiCt . Alternatively, a plurality of dielectric layers can be arranged at the reflective material 108 forming an encapsulation. Such a stack of dielectric layers can comprise both, AI2O3 and SiCt layers and / or at least another dielectric material . The encapsulation layer 112 is not arranged in the region of the via 111. Also, a diffusion barrier 113 is arranged between the reflective material 108 and2024PF00955 16
[0074] the encapsulation layer 112. The diffusion barrier 113 can comprise a metal, for example Ti . However, the encapsulation layer 112 and the diffusion barrier 113 are only optional and can be omitted.
[0075] To protect the top and the bottom layer sequences 104, 105 against a short circuit, side walls of the via 111 extending obliquely with respect to the top side 102 of the optoelectronic semiconductor chip 101 are passivated with an insulation 114. The insulation 114 passivates the bottom layer sequence 105, the active region 106, the top layer sequence 104, the optional dielectric mirror 107, the first mask layer 109 and the optional encapsulation layer 112. In an embodiment the encapsulation layer 112 and the insulation 114 can be formed by a single dielectric layer .
[0076] Fig. 4 to 12 schematically show method steps of a method of producing the optoelectronic component 101 according to Fig.
[0077] 3. All elements are shown in cress sectional side views similarly to Fig. 1 to 3 . The reference numerals of Fig. 3 are maintained for Fig. 4 to 12.
[0078] Fig. 4 shows the optoelectronic semiconductor chip 101 which exemplarily has been provided with the dielectric mirror 107 arranged at its top side 102. The optional ITO layer between the top side 102 and the dielectric mirror 107 is not shown in Fig. 4 for the sake of simplicity, again.
[0079] Fig. 5 shows a state following the state of Fig. 4 during the production of the optoelectronic component 100. A first layer 115 has been arranged at the top side 102 of the optoelectronic semiconductor chip 101. The first layer 115 comprises SiC>2, as an example . However, the first layer 115 can also comprise another material, particularly another dielectric material . The first layer 115 can be arranged by any suitable method .2024PF00955 17
[0080] Fig. 6 shows a state following the state of Fig. 5 during the production of the optoelectronic component 100. A second layer 116 has been arranged at the first layer 115. The second layer 116 has been arranged at a surface of the first layer 115 averted from the top side 102 of the optoelectronic semiconductor chip 101. Thus, the first layer 115 is arranged between the top side 102 of the optoelectronic semiconductor chip 101 and the second layer 116.
[0081] The second layer 116 exemplarily comprises a photoresist . The second layer can comprise either a positive or a negative photoresist . A positive photoresist comprises the characteristic that it can be structured such that parts that have been exposed to electromagnetic radiation can be removed, while unexposed parts remain. A negative photoresist can be structured such that parts that don' t have been exposed to electromagnetic radiation can be removed, while exposed parts remain .
[0082] Fig. 7 shows a state following the state of Fig. 6 during the production of the optoelectronic component 100. The first layer 115 and the second layer 116 have been laterally structured to form the first mask layer 109 and a second mask layer 117, respectively. Apart from that, the first layer 115 has also been structured to form an undercut 118 between the top side 102 of the optoelectronic semiconductor chip 101 and the second mask layer 117 such that the second mask layer 117 protrudes over the first mask layer 109 in a direction parallel to the top side 102 of the optoelectronic semiconductor chip 101 .
[0083] The first mask layer 109 and the second mask layer 117 form a dual mask 119 comprising the undercut 118. The first mask layer 109 can comprise a thickness of 100-300nm, as an example . Ideally, the first mask layer 117 comprises a thickness which is similar to the thickness of the reflective material 108 or a combined thickness of the reflective material 108, the diffusion barrier 113 and / or thew encapsulation layer2024PF00955 18
[0084] 112. This helps to keep the topography as flat as possible . If the reflective material 108 is designed thicker for carrying more electric current, the first mask layer 117 also can be thicker, e . g. , even up to 1pm. The second mask layer 117 can comprise a thickness of l-3pm, as an example .
[0085] The second layer 116 can be structured by lithography. Here, the second layer 116 is illuminated with electromagnetic radiation using a mask which defines an area of the dual mask 119, particularly an area of the second mask layer 117. After exposure, either the exposed part or the unexposed part of the second layer 116 is removed while a remaining part of the second layer 116 forms the second mask layer 117.
[0086] After structuring the second layer 116 the first layer 115 is accessible and also can be structured. Structuring the first layer 115 to form the first mask layer 109 can be performed by direct plasma etching, for example . In a first step, etching of the first layer 115 is performed vertically with respect to the top side 102 of the optoelectronic semiconductor chip 101. In a second step, etching is performed to form the undercut 118, wherein remaining parts of the first layer 115 after the vertical etch step are etched in a direction parallel to the top side 102 of the optoelectronic semiconductor chip 101. Both, vertical and parallel etching steps can be performed by direct plasma etching, for example . However, the vertical and the parallel etching step can also be performed by wet chemical etching. The second etching step to form the undercut can require more time, e . g. if etching shall be performed with high precision.
[0087] By structuring the first layer 115 and the second layer 116 the dielectric mirror 107 is exposed in a region outside the dual mask 119. If the dielectric mirror 107 and other optional layers such as the ITO layer are not provided, the top side 102 of the optoelectronic semiconductor chip 101 is exposed after structuring the first layer 115 and the second layer 116.2024PF00955 19
[0088] Fig. 8 shows a state following the state of Fig. 7 during the production of the optoelectronic component 100. The reflective material 108 has been arranged at the top side 102 of the optoelectronic semiconductor chip 101 and at the second mask layer 117. Since the dielectric mirror 107 is exemplarily arranged at the top side 102 of the optoelectronic semiconductor chip 101, the reflective material 108 is arranged on the dielectric mirror 107 such that the dielectric mirror 107 is arranged between the top side 102 of the optoelectronic semiconductor chip 101 and the reflective material 108.
[0089] The reflective material 108 can be arranged at the top side 102 of the optoelectronic semiconductor chip 101 by sputtering, for example, whereby the reflective material 108 comprises a particularly high reflectivity. In other embodiments, the reflective material 108 can be arranged by means of another deposition method at the top side 102 of the optoelectronic semiconductor chip 101, e . g. by gas phase deposition. The reflective material 108 can comprise a thickness of 100-500nm, as an example . However, the thickness of the reflective material 108 is not limited to the specified values . The reflective material 108 can also be up to 1pm thick or even thicker for current transport if necessary.
[0090] The reflective material 108 is also arranged at a surface of the second mask layer 117 averted from the first mask layer 109. Particularly, the reflective material 108 is also arranged in the undercut 108 such that the reflective material 108 is in a direct mechanical contact with the first mask layer . In other words, there is no lateral gap between the reflective material 108 and the first mask layer 109. Consequently, the reflective material 108 comprises a vertical edge 110. In other words, the reflective material 108 is enclosed laterally, i . e . in a direction parallel to the top side 102 of the optoelectronic semiconductor chip 101 by the first mask layer 109 and / or vice versa, while the reflective material 108 is in direct contact with side walls of the2024PF00955 20
[0091] first mask layer 109 extending between the top side 102 of the optoelectronic semiconductor chip 101 and the second mask layer 117 .
[0092] After arranging the reflective material 108 which is also arranged in the undercut 118 a gap 120 remains between the reflective material 108 and the second mask layer 117 in the region of the undercut 118. This gap 120 enables a lift-off of the second mask layer 117 together with the reflective material 108 arranged at the second mask layer 117.
[0093] Fig. 9 shows a state following the state of Fig. 8 during the production of the optoelectronic component 100. The second mask layer 117 has been removed with the reflective material 108 arranged at the second mask layer 117. The second mask layer 117 can be remove by dissolving the second mask layer 117. Thus, also the reflective material 108 arranged at the second mask layer 117 is removed.
[0094] After removing the second mask layer 117 the first mask layer 109 is exposed. The exposed first mask layer 109 and the reflective material 108 can be planarized after the second mask layer 117 has been removed, which, however, is not absolutely necessary .
[0095] Fig. 10 shows a state following the state of Fig. 9 during the production of the optoelectronic component 100. The encapsulation layer 112 has been arranged at the reflective material 108. The encapsulation layer 112 comprises a thickness of 100-300nm, for example . However, the thickness of the encapsulation layer 112 can also comprise a thickness between 50nm and lOOOnm, as an example . Prior to the arrangement of the encapsulation layer 112, the diffusion barrier 113 has been arranged at the reflective material 108. The reflective material 108 is arranged between the optoelectronic semiconductor chips 101 and the encapsulation material 112. The optional diffusion barrier 113 is arranged between the reflective material 108 and the encapsulation layer 112. However,2024PF00955 21
[0096] the encapsulation layer 112 and the diffusion barrier 113 can be omitted, respectively.
[0097] Fig. 11 shows a state following the state of Fig. 10 during the production of the optoelectronic component 100. A via 111 has been created extending perpendicularly through the optional encapsulation layer 112, the optional diffusion barrier 113 if it is arranged after removing the second mask layer, the reflective material 108, the optional dielectric mirror 107 and through the optoelectronic semiconductor chip 101, particularly to the bottom layer sequence 105 of the optoelectronic semiconductor chip 101 to electrically contact the bottom layer sequence 105, e . g. the n-side semiconductor layers .
[0098] Fig. 12 shows a state following the state of Fig. 11 during the production of the optoelectronic component 100. An insulation 114 has been arranged on side walls of the via 111. The insulation 114 can be arranged in the via 111 by filling the via with a dielectric material, such as SiCt or AI2O3, and an etching step, to remove the dielectric material, wherein a part of the dielectric material remains on the side walls of the via 111 and forms the insulation 114.
[0099] The via 111 can be filled with an electrically conductive and preferably high reflectivity material to contact the bottom layer sequence 105.
[0100] The invention has been illustrated and described in detail with the aid of the preferred exemplary embodiments . Nevertheless, the invention is not restricted to the examples disclosed. Rather, other variants may be derived therefrom by a person skilled in the art without departing from the protective scope of the invention.2024PF00955 22
[0101] REFERENCE SYMBOLS
[0102] 1 optoelectronic component according to the state of the art
[0103] 2 optoelectronic semiconductor chip
[0104] 3 reflective material
[0105] 4 edge of the reflective material
[0106] 5 via
[0107] 6 lateral distance between the reflective material and the via
[0108] 100 optoelectronic component
[0109] 101 optoelectronic semiconductor chip
[0110] 102 top side of the optoelectronic semiconductor chip 103 bottom side of the optoelectronic semiconductor chip
[0111] 104 top layer sequence of the semiconductor layer sequence of the optoelectronic semiconductor chip 105 bottom layer sequence of the semiconductor layer sequence of the optoelectronic semiconductor chip 106 active region of the optoelectronic semiconductor chip
[0112] 107 dielectric mirror
[0113] 108 reflective material
[0114] 109 first mask layer
[0115] 110 edge of the reflective material
[0116] 111 via
[0117] 112 encapsulation layer
[0118] 113 diffusion barrier
[0119] 114 insulation
[0120] 115 first layer
[0121] 116 second layer
[0122] 117 second mask layer
[0123] 118 undercut between the optoelectronic semiconductor chip and the second mask layer
[0124] 119 dual mask
[0125] 120 gap between reflective material and second mask layer
Claims
2024PF00955 23CLAIMS1 . Method of producing an optoelectronic component ( 100 ) comprising the following method steps :- providing an optoelectronic semiconductor chip ( 101 ) designed to emit electromagnetic radiation and comprising a top side ( 102 ) and a bottom side ( 103 ) opposite the top side ( 102 ) ,- arranging a first layer ( 115 ) at the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) ,- arranging a second layer ( 116 ) at the first layer ( 115 ) such that the first layer ( 115 ) is arranged between the optoelectronic semiconductor chip ( 101 ) and the second layer ( 116 ) ,- structuring the first layer ( 115 ) and the second layer ( 116 ) laterally to form a first mask layer ( 109 ) and a second mask layer ( 117 ) , respectively, and to form an undercut ( 118 ) between the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) and the second mask layer ( 117 ) such that the second mask layer ( 117 ) protrudes over the first mask layer ( 109 ) in a direction parallel to the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) ,- arranging a reflective material ( 108 ) at the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) and at the second mask layer ( 117 ) ,wherein the reflective material ( 108 ) arranged at the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) is arranged in a region of the undercut ( 118 ) and is in direct contact with the first mask layer ( 109 ) ,- removing the second mask layer ( 117 ) with the reflective material ( 108 ) arranged at the second mask layer ( 117 ) .2 . The method according to claim 1 ,wherein the first layer ( 115 ) comprises a dielectric material and / or the second layer ( 116 ) comprises a photoresist , wherein the structuring of the second layer ( 116 ) to form the second mask layer ( 117 ) is performed by lithography and / or structuring of the first layer ( 116 ) to form the first mask2024PF00955 24layer ( 109 ) is performed by etching, wherein etching of the first layer ( 115 ) comprises a step of etching the first layer ( 115 ) perpendicularly to the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) to form the first mask layer ( 109 ) and a step of etching the first mask layer ( 109 ) parallel to the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) to form the undercut ( 118 ) .3 . The method according to claim 1 or 2 ,wherein a gap ( 120 ) remains between the reflective material ( 108 ) and the second mask layer ( 117 ) in the region of the undercut ( 118 ) after arranging the reflective material ( 108 ) , wherein removing of the second mask layer ( 117 ) is performed by dissolving the second mask layer ( 117 ) .4 . The method according to one of the preceding claims comprising the following additional method step after removing the second mask layer ( 117 ) ,- planari zing the first mask layer ( 116 ) .5 . The method according to one of the preceding claims , wherein a dielectric mirror ( 107 ) is arranged between the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) and the first layer ( 115 ) .6 . The method according to one of the preceding claims , wherein arranging of the reflective material ( 108 ) is performed by sputtering .7 . The method according to one of the preceding claims , wherein the reflective material ( 108 ) comprises a metallic material , particularly silver .8 . The method according to one of the preceding claims comprising the following method step after removing the second mask layer ( 117 ) :- arranging an encapsulation layer ( 112 ) at a surface of the reflective material ( 108 ) averted from the top side ( 102 ) of2024PF00955 25the optoelectronic semiconductor chip ( 101 ) and at the first mask layer ( 109 ) .9 . The method according to one of the preceding claims comprising the following method step after removing the second mask layer ( 117 ) :- arranging a di f fusion barrier ( 113 ) at a surface of the reflective material ( 108 ) averted from the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) .10 . The method according to one of the previous claims comprising the following method step after removing the second mask layer ( 117 ) :- creating a via ( 111 ) extending in a direction perpendicular to the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) through the first mask layer ( 109 ) and at least to the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) .11 . The method according to claim 10 comprising the following method step after creating the via ( 111 ) :- arranging an insulation ( 114 ) on side walls of the via ( 111 ) .12 . Optoelectronic component ( 100 )comprising an optoelectronic semiconductor chip ( 101 ) designed to emit electromagnetic radiation and comprising a top side ( 102 ) and a bottom side ( 103 ) opposite the top side ( 102 ) ,wherein a first mask layer ( 109 ) is arranged at the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) , wherein a reflective material ( 108 ) is arranged at the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) laterally next to the first mask layer ( 109 ) ,wherein the reflective material ( 108 ) is in direct contact with the first mask layer ( 109 ) .13 . Optoelectronic component ( 100 ) according to claim 12 ,2024PF00955 26comprising an encapsulation layer ( 112 ) arranged at a surface of the reflective material ( 108 ) averted from the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) and arranged the first mask layer ( 109 ) .14 . Optoelectronic component ( 100 ) according to claim 12 or 13 ,comprising a via ( 111 ) extending in a direction perpendicular to the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) through the first mask layer ( 109 ) and at least to the top side ( 102 ) of the optoelectronic semiconductor chip ( 101 ) .15 . Optoelectronic component ( 100 ) according to claim 14 , comprising an insulation ( 114 ) arranged on side walls of the via ( 111 ) .