Semiconductor device

Abstract

The present invention provides a semiconductor device having a transistor with high field-effect mobility. This semiconductor device has a transistor. The transistor has a semiconductor layer, a gate electrode, and a gate insulating layer. The gate electrode has a region overlapping the semiconductor layer with the gate insulating layer interposed therebetween. The semiconductor layer contains indium and oxygen. The semiconductor layer has a crystalline part. The semiconductor layer is between 1 nm and 10 nm thick, inclusive. The transistor has a channel length between 5 μm and 12 μm, inclusive. In the transistor, when the gate voltage is 5 V and the drain voltage changes from 5.4 V to 6.0 V, the absolute value of the rate of change of the drain current is 4% / V or less.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a display device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, there has been a growing demand for high-resolution display devices. Devices requiring high-resolution displays include those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), all of which are being actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electroluminescence) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using organic EL elements.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Examples of oxide semiconductors applicable to transistors include indium oxide and indium gallium zinc oxide. Non-patent document 1 discloses a thin-film transistor using polycrystalline indium hydrogenate formed by low-temperature solid-phase crystallization.

[0008] International Publication No. 2016 / 038508

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022)

[0010] One aspect of the present invention aims to provide a semiconductor device having a transistor with high field-effect mobility. Alternatively, it aims to provide a semiconductor device having a transistor with high on-current. Alternatively, it aims to provide a semiconductor device having a transistor of a very small size. Alternatively, it aims to provide a semiconductor device having a transistor with a short channel length. Alternatively, it aims to provide a semiconductor device having a transistor with good electrical characteristics. Alternatively, it aims to provide a semiconductor device that operates at high speed. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device with low wiring resistance. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a highly reliable transistor, semiconductor device, or display device. Alternatively, it aims to provide a high-definition display device. Alternatively, it aims to provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, it aims to provide a highly productive method for manufacturing a transistor, semiconductor device, or display device. Alternatively, it aims to provide a novel transistor, semiconductor device, display device, or method for manufacturing the same.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a semiconductor device having a transistor. The transistor has a semiconductor layer, a gate electrode, and a gate insulating layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer. The semiconductor layer contains indium and oxygen. The semiconductor layer has a crystalline portion. The thickness of the semiconductor layer is 1 nm or more and 10 nm or less. The channel length of the transistor is 5 μm or more and 12 μm or less. In the transistor, the gate voltage is 5 V, and the absolute value of the rate of change of the drain current when the drain voltage changes from 5.4 V to 6.0 V is 4% / V or less.

[0013] In the aforementioned semiconductor device, the semiconductor layer is preferably polycrystalline. In the semiconductor layer, the barrier height of the grain boundary is preferably 50 meV or less.

[0014] In the aforementioned semiconductor device, the semiconductor layer preferably comprises a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The second metal oxide layer preferably has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively.

[0015] In the aforementioned semiconductor device, the second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ Preferably, the following regions are present: The first metal oxide layer and the third metal oxide layer each preferably have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer.

[0016] In the semiconductor device described above, it is preferable that the second metal oxide layer has a region with a lower film density than the first metal oxide layer and the third metal oxide layer, respectively.

[0017] In the aforementioned semiconductor device, it is preferable that the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer.

[0018] One aspect of the present invention is a semiconductor device having a transistor. The transistor has a semiconductor layer, a gate electrode, and a gate insulating layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer. The semiconductor layer has a first metal oxide layer and a second metal oxide layer on the first metal oxide layer. The first metal oxide layer has indium, element M, and oxygen. The second metal oxide layer has indium and oxygen. Element M is one or more of gallium, aluminum, and tin. The channel length of the transistor is 5 μm or more and 12 μm or less. In the transistor, the gate voltage is 5 V, and the absolute value of the rate of change of the drain current when the drain voltage changes from 5.4 V to 6.0 V is 4% / V or less.

[0019] One aspect of the present invention is a semiconductor device having a transistor. The transistor has a semiconductor layer, a gate electrode, and a gate insulating layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer. The semiconductor layer has a crystalline portion. The thickness of the semiconductor layer is 1 nm or more and 10 nm or less. The semiconductor layer has a first metal oxide layer and a second metal oxide layer on the first metal oxide layer. The first metal oxide layer has indium, element M, and oxygen. The second metal oxide layer has indium and oxygen. Element M is one or more of gallium, aluminum, and tin. The channel length of the transistor is 5 μm or more and 12 μm or less. In the transistor, the gate voltage is 5 V, and the absolute value of the rate of change of the drain current when the drain voltage changes from 5.4 V to 6.0 V is 4% / V or less.

[0020] In the aforementioned semiconductor device, it is preferable that the content of element M in the first metal oxide layer is higher than the content of element M in the second metal oxide layer.

[0021] In the aforementioned semiconductor device, the content of element M in the first metal oxide layer is preferably 1% or more and 35% or less.

[0022] In the aforementioned semiconductor device, it is preferable that the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

[0023] In the semiconductor device described above, the semiconductor layer preferably has a third metal oxide layer. The third metal oxide layer is preferably located between the second metal oxide layer and the gate insulating layer. The third metal oxide layer preferably contains indium and oxygen. The content of element M in the first metal oxide layer is preferably higher than the content of element M in the third metal oxide layer.

[0024] In the aforementioned semiconductor device, the second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ It is preferable that the third metal oxide layer has the following region: The third metal oxide layer preferably has a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer.

[0025] In the aforementioned semiconductor device, it is preferable that the thickness of the second metal oxide layer is greater than the thickness of the third metal oxide layer.

[0026] In the semiconductor device described above, the semiconductor layer preferably has a third metal oxide layer. The third metal oxide layer is preferably located between the second metal oxide layer and the gate insulating layer. The third metal oxide layer preferably contains indium, element M, and oxygen. The content of element M in the third metal oxide layer is preferably higher than the content of element M in the second metal oxide layer.

[0027] In the aforementioned semiconductor device, the content of element M in the third metal oxide layer is preferably 1% or more and 35% or less.

[0028] In the aforementioned semiconductor device, it is preferable that the thickness of the second metal oxide layer is greater than the thickness of the third metal oxide layer.

[0029] One aspect of the present invention can provide a semiconductor device having a transistor with high field-effect mobility. Or, a semiconductor device having a transistor with high on-current can be provided. Or, a semiconductor device having a transistor of a very small size can be provided. Or, a semiconductor device having a transistor with a short channel length can be provided. Or, a semiconductor device having a transistor with good electrical characteristics can be provided. Or, a semiconductor device that operates at high speed can be provided. Or, a semiconductor device with a small footprint can be provided. Or, a semiconductor device with low wiring resistance can be provided. Or, a semiconductor device or display device with low power consumption can be provided. Or, a highly reliable transistor, semiconductor device, or display device can be provided. Or, a high-definition display device can be provided. Or, a method for manufacturing the aforementioned transistor, semiconductor device, or display device can be provided. Or, a highly productive method for manufacturing a transistor, semiconductor device, or display device can be provided. Or, a novel transistor, semiconductor device, display device, or a method for manufacturing the same can be provided.

[0030] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0031] Figure 1A is a top view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figure 2A is a top view showing an example of a semiconductor device. Figures 2B and 2C are cross-sectional views showing an example of a semiconductor device. Figures 3A and 3B are cross-sectional views showing an example of a semiconductor device. Figures 4A, 4B, 4C, and 4D are cross-sectional views showing an example of a semiconductor device. Figure 5A is a top view showing an example of a semiconductor device. Figure 5B is a cross-sectional view showing an example of a semiconductor device. Figures 6A and 6B are cross-sectional views showing an example of a semiconductor device. Figure 7 is a cross-sectional view showing an example of a semiconductor device. Figures 8A and 8B are cross-sectional views showing an example of a semiconductor device. Figures 9A and 9B are cross-sectional views showing an example of a semiconductor device. Figure 10A is a top view showing an example of a semiconductor device. Figures 10B and 10C are cross-sectional views showing an example of a semiconductor device. Figures 11A, 11B, 11C, and 11D are perspective views showing an example of a semiconductor device. Figures 12A and 12B are cross-sectional views showing an example of a semiconductor device. Figure 13A is a top view showing an example of a semiconductor device. Figure 13B is a cross-sectional view showing an example of a semiconductor device. Figures 14A and 14B are cross-sectional views showing an example of a semiconductor device. Figure 15A is a top view showing an example of a semiconductor device. Figures 15B and 15C are cross-sectional views showing an example of a semiconductor device. Figures 16A and 16B are cross-sectional views showing an example of a semiconductor device. Figure 17A is a top view showing an example of a semiconductor device. Figures 17B and 17C are cross-sectional views showing an example of a semiconductor device. Figures 18A and 18B are cross-sectional views showing an example of a semiconductor device. Figure 19A is a top view showing an example of a semiconductor device. Figure 19B is a cross-sectional view showing an example of a semiconductor device. Figure 20A is a top view showing an example of a semiconductor device. Figure 20B is a cross-sectional view showing an example of a semiconductor device. Figures 21A, 21B, 21C, 21D, 21E, and 21F are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 22A, 22B, 22C, 22D, and 22E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 23A, 23B, 23C, 23D, and 23E are cross-sectional views showing an example of a semiconductor device manufacturing method.Figures 24A, 24B, 24C, and 24D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 25A, 25B, and 25C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 26A and 26B are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 27A is a perspective view showing an example of a display device. Figures 27B and 27C are circuit diagrams showing an example of a sub-pixel. Figures 28A and 28B are circuit diagrams showing an example of a sub-pixel. Figures 29A and 29B are cross-sectional views showing an example of a display device. Figure 30 is a cross-sectional view showing an example of a display device. Figure 31 is a cross-sectional view showing an example of a display device. Figure 32 is a cross-sectional view showing an example of a display device. Figure 33 is a cross-sectional view showing an example of a display device. Figures 34A, 34B, and 34C are cross-sectional views showing an example of a display device. Figures 35A and 35B are cross-sectional views showing an example of a display device. Figure 36 is a cross-sectional view showing an example of a display device. Figure 37 is a cross-sectional view showing an example of a display device. Figure 38 is a cross-sectional view showing an example of a display device. Figure 39 is a cross-sectional view showing an example of a display device. Figures 40A, 40B, 40C, and 40D show examples of electronic devices. Figures 41A, 41B, 41C, 41D, 41E, and 41F show examples of electronic devices. Figures 42A, 42B, 42C, 42D, 42E, 42F, and 42G show examples of electronic devices. Figures 43A, 43B, and 43C show the XRD and EBSD measurement results of the indium oxide film according to the example. Figures 44A, 44B, and 44C show the XRD and EBSD measurement results of the indium oxide film according to the example. Figure 45 is an SEM image of the indium oxide film according to the example. Figure 46 shows the Hall effect measurement results of the indium oxide film according to the example. Figure 47 shows the simulation results according to the example. Figures 48A, 48B, 48C, and 48D show the Id-Vg characteristics of the transistor according to the embodiment. Figures 49A, 49B, 49C, and 49D show the Id-Vd characteristics of the transistor according to the embodiment. Figure 50A is a photograph of the display state of the OLED panel according to the embodiment. Figure 50B shows the brightness of the OLED panel according to the embodiment.Figure 51 is a diagram showing a scan line driving circuit according to an embodiment. Figures 52A, 52B, and 52C are cross-sectional views showing the configuration of a sample according to an embodiment. Figure 53 is a photograph of the external appearance of a sample according to an embodiment. Figures 54A, 54B, and 54C are diagrams showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 55A is a diagram showing the electrical characteristics of a transistor according to an embodiment. Figure 55B is a diagram showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 56 is a diagram showing the reliability of a transistor according to an embodiment.

[0032] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0033] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for parts that are identical or have similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0034] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0035] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0036] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0037] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0038] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0039] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0040] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0041] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0042] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0043] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0044] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0045] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0046] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0047] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0049] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, it may also be said that the "matching or roughly matching top shapes" apply. Furthermore, when the top shapes match or roughly match, it can also be said that the "edges match or roughly match," or "the edges are aligned or roughly aligned."

[0050] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as the taper angle.

[0051] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0052] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0053] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0054] In this specification, a structure in which different light-emitting layers are created using light-emitting devices with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

[0055] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0056] In this specification, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element includes a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other as a common electrode.

[0057] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to return to its original shape.

[0058] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, used after repeated deformation, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by the average adult's hand without requiring excessive force. Flexibleness can be evaluated using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.). In stress-strain measurement, the flexibility of an object can be quantified by applying an external force to the object and measuring the strain of the object caused by the resulting stress.

[0059] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may have parts that are not flexible.

[0060] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1A to 26B. The semiconductor device according to one aspect of the present invention can be suitably used, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0061] <Configuration Example 1> [Configuration Example 1-1] Figure 1A shows a top view (also called a plan view) of a semiconductor device 10, which is one embodiment of the present invention. Figure 1B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 1A, and Figure 1C shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2. Note that in Figure 1A, some of the components of the semiconductor device 10 (such as the gate insulating layer) are omitted. In the top view of the semiconductor device, as in Figure 1A, some of the components are omitted in the following drawings as well.

[0062] The semiconductor device 10 has a transistor 100. The transistor 100 has an insulating layer 105 on a substrate 102, a semiconductor layer 108 on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108, and a conductive layer 104 on the insulating layer 106. The conductive layer 104 has a region that faces the semiconductor layer 108 via the insulating layer 106. The conductive layer 104 functions as the gate electrode of the transistor 100, and the insulating layer 106 functions as a gate insulating layer. An insulating layer 195 is provided on the conductive layer 104 and the insulating layer 106.

[0063] The semiconductor layer 108 has regions 108P and 108Q that do not overlap with the conductive layer 104. In the transistor 100, region 108P functions as one of the source region and drain region, and region 108Q functions as the other of the source region and drain region. In the semiconductor layer 108, the region located between the source region and drain region and overlapping with the conductive layer 104 via the insulating layer 106 functions as a channel-forming region.

[0064] The semiconductor layer 108 preferably has a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties. The band gap of the metal oxide is preferably 2.0 eV or more, and more preferably 2.5 eV or more. Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, the power consumption of semiconductor devices can be reduced by applying OS transistors. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0065] The metal oxide preferably contains at least indium. The semiconductor layer 108 preferably has indium and oxygen. For the semiconductor layer 108, indium oxide (IO, also referred to as indium oxide) can be preferably used, for example. Hereinafter, there may be cases where a configuration using indium oxide for the semiconductor layer 108 is taken as an example for explanation. In addition, a transistor using indium oxide may be referred to as an IO transistor.

[0066] By increasing the thickness T108 of the channel formation region of the semiconductor layer 108, the on-current of the transistor can be increased. However, if the thickness T108 is too thick, oxygen vacancies (V Ｏ ), and the amount of defects in which hydrogen enters the oxygen vacancies (hereinafter, also referred to as V Ｏ H) increases. V Ｏ H functions as a donor, and electrons as carriers may be generated. As a result, the transistor may become normally on. Also, the reliability may decrease. The thickness T108 is preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 40 nm or less, more preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, and even more preferably 1 nm or more and 10 nm or less. By setting the thickness T108 within the above range, a transistor having good electrical characteristics and high reliability can be obtained. The thickness T108 can be the shortest distance between the formed surface of the semiconductor layer 108 (here, the upper surface of the insulating layer 105) and the upper surface of the semiconductor layer 108 in the region where the semiconductor layer 108 overlaps the conductive layer 104 of the semiconductor layer 108 in a cross-sectional view. In FIG. 1B, the thickness T108 is indicated by a solid arrow. Note that the thickness T108 is not limited to the above range.

[0067] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor having a crystal region in part) can be used. Using a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0068] The semiconductor layer 108 is preferably crystalline. Using a crystalline oxide semiconductor for the semiconductor layer 108 is preferable because it suppresses the degradation of transistor characteristics. The semiconductor layer 108 is preferably highly crystalline, and preferably polycrystalline or monocrystalline. A polycrystalline indium oxide film is preferably used as the semiconductor layer 108, and a monocrystalline indium oxide film is more preferably used. Note that indium oxide having crystalline grains may be referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO).

[0069] Single-crystal films are particularly preferred because they do not have grain boundaries, thus suppressing carrier scattering at grain boundaries and enabling transistors with high field-effect mobility. Compared to microcrystalline and amorphous films, polycrystalline films can reduce carrier scattering and enable transistors with high field-effect mobility. When a polycrystalline film is used for semiconductor layer 108, it is preferable that the grain size of the crystal grains contained in semiconductor layer 108 is large. By using a polycrystalline film with large grain size, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, thus enabling transistors with high field-effect mobility. Furthermore, it is preferable that there are few crystal grain boundaries in the channel formation region that intersect with the direction of drain current flow (also known as the channel length direction). Note that even with a polycrystalline film, if there are no crystal grain boundaries located in the channel formation region, the same effects as a single-crystal film can be achieved.

[0070] When a non-single-crystal (e.g., polycrystalline) film is used as the semiconductor layer 108, it is preferable that the barrier height at the grain boundaries is low. A low barrier height at the grain boundaries reduces the effect of grain boundary scattering, making it possible to create a transistor with high field-effect mobility. Generally, the barrier height at the grain boundaries of low-temperature polysilicon (LTPS) is 60 meV to 80 meV. When polycrystalline indium oxide is used as the semiconductor layer 108, it is preferable that the barrier height at the grain boundaries is lower than that of LTPS. For example, the barrier height at the grain boundaries of indium oxide is preferably greater than 0 meV and less than 60 meV, more preferably greater than 0 meV and 55 meV or less, and even more preferably greater than 0 meV and 50 meV or less. A low barrier height at the grain boundaries is preferable. Furthermore, the barrier height at the grain boundaries of indium oxide is not limited to the range mentioned above. Also, transistors using LTPS in the channel formation region are sometimes referred to as LTPS transistors.

[0071] For example, Kelvin probe force microscopy (KFM) can be used to measure the barrier height at grain boundaries. KFM is a type of scanning probe microscopy (SPM) measurement mode in which the potential distribution on the sample surface can be evaluated by scanning the sample surface with a conductive probe and detecting the electrostatic force between the probe and the sample surface.

[0072] Due to the low barrier height at the grain boundaries of indium oxide, IO transistors have high field-effect mobility and can operate at high speeds. Furthermore, IO transistors have high saturation (also known as high constant current). Even with short channel lengths, IO transistors exhibit high saturation, enabling both large on-current and high saturation. Additionally, IO transistors have low electrical hysteresis. Therefore, IO transistors can be suitably used as both selector and drive transistors in pixel circuits. By using IO transistors with high saturation and high current controllability as drive transistors, a display device with high display quality can be created. Furthermore, using IO transistors with low hysteresis can improve display quality.

[0073] In this specification, the term "high saturation" may be used to describe a transistor where the change in current in the saturation region of the Id-Vd characteristic is small.

[0074] The degree of saturation can be evaluated by the rate of change of the drain current (ΔId / ΔVd). The smaller the absolute value of the rate of change of the drain current (ΔId / ΔVd), the higher the saturation. The rate of change of the drain current (ΔId / ΔVd) can be expressed as the ratio of the change in drain current (ΔId) to the change in drain voltage (ΔVd), for example, as shown in equation (1). Equation (1) shows the rate of change of drain current (ΔId / ΔVd) when the drain voltage changes from 5.4V to 6.0V. Specifically, the rate of change of drain current (ΔId) is the ratio of the difference between the drain current (Id) at a drain voltage (Vd) of 5.4V and the drain current (Id) at 6.0V to the drain current (Id) at a drain voltage (Vd) of 5.4V. The change in drain voltage (ΔVd) is assumed to be 0.6V, which is the difference between 6.0V and 5.4V.

[0075]

[0076] For example, in a transistor with a channel length of 5 μm or more and 12 μm or less, when the gate voltage is 5.0 V and the drain voltage changes from 5.4 V to 6.0 V, the absolute value of the rate of change of the drain current (ΔId / ΔVd) is preferably 4% / V or less, more preferably 3% / V or less, more preferably 2% / V or less, and more preferably 1% / V or less.

[0077] Note that the rate of change of the drain current (ΔId / ΔVd) is not limited to equation (1).

[0078] The magnitude of hysteresis can be evaluated by the difference between the characteristics of the transistor's Id-Vg characteristic when scanning the gate voltage (Vg) from a negative voltage to a positive voltage (hereinafter also referred to as forward scan) and when scanning the gate voltage (Vg) from a positive voltage to a negative voltage (hereinafter also referred to as reverse scan). For example, the smaller the absolute value of the threshold voltage fluctuation (ΔVth) between forward scan and reverse scan, the smaller the hysteresis.

[0079] In the Id-Vg characteristics, the absolute value of the threshold voltage fluctuation (ΔVth) between the forward scan and the reverse scan is preferably less than 0.04V, more preferably 0.03V or less, and more preferably 0.02V or less. As the threshold voltage (Vth), for example, a value calculated by the constant current method can be used.

[0080] A semiconductor layer 108 can be formed by depositing a metal oxide film and processing the metal oxide film into island-like structures. The metal oxide film can be deposited using sputtering, atomic layer deposition (ALD), or chemical vapor deposition (CVD).

[0081] It is preferable to crystallize the metal oxide film by heat treatment after it has been formed or after it has been processed into an island shape. Heat treatment can increase the grain size of the crystal grains contained in the semiconductor layer 108 and improve the crystallinity of the semiconductor layer 108. Heat treatment can also reduce defects in the semiconductor layer 108 (e.g., defects within the crystal grains). By reducing defects within the crystal grains, the influence of scattering factors within the crystal grains is reduced, making it possible to create a transistor with high field-effect mobility. Furthermore, heat treatment can remove impurities (e.g., atmospheric components) contained in or adsorbed on the surface of the semiconductor layer 108.

[0082] When forming a metal oxide film, it is preferable to use conditions that result in low crystallinity of the metal oxide film. After forming a metal oxide film with low crystallinity, heat treatment is performed to crystallize it, thereby increasing the grain size. When forming a metal oxide film, it is preferable to use a gas containing hydrogen (for example, H ２ or H ２ It is preferable to use O). This reduces the number of crystal grains generated during the formation of the metal oxide film, resulting in a metal oxide film with low crystallinity. Furthermore, the inclusion of hydrogen in the metal oxide film can cause the grain boundaries to be terminated with hydrogen (hereinafter also referred to as hydrogen termination), which can have the effect of lowering the barrier height at the grain boundaries. However, if the amount of hydrogen in the metal oxide film (especially in the channel formation region) is too high, oxygen vacancies and V in the channel formation region may occur. Ｏ An increase in H may cause a shift in the transistor's threshold voltage. The ratio of hydrogen gas flow rate to the total deposition gas flow rate when depositing a metal oxide film (hereinafter also referred to as the hydrogen flow rate ratio) is preferably higher than 0% and 20% or less, more preferably higher than 0% and 15% or less, and even more preferably higher than 0% and 10% or less. By setting the hydrogen flow rate ratio within the above range, a transistor with high field-effect mobility can be obtained. Note that the hydrogen flow rate ratio is not limited to the above range.

[0083] By using oxygen gas as the deposition gas for metal oxide films, oxygen vacancies (V) can be created in the metal oxide film. ＯThis can suppress the occurrence of ) and V Ｏ H can be reduced. Also, the amount of oxygen contained in the metal oxide film can be increased, thereby promoting crystallization in the subsequent heat treatment. However, if the ratio of the flow rate of oxygen gas to the total film formation gas when forming the metal oxide film 108f (hereinafter also referred to as the oxygen flow rate ratio) is too high, there is a risk that the number of crystal grains contained in the metal oxide film 108f will increase at the stage when the metal oxide film 108f is formed. The oxygen flow rate ratio is preferably higher than 0% and 10% or less, more preferably higher than 0% and 5% or less, and even more preferably higher than 0% and 3% or less. By setting the oxygen flow rate ratio within the above range, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This method can reduce H and lower the crystallinity of the metal oxide film 108f. Note that the oxygen flow rate ratio is not limited to the range described above.

[0084] It is preferable to use hydrogen gas, oxygen gas, and argon gas as the film-forming gas for the metal oxide film. This makes it possible to obtain a semiconductor layer 108 with large grain size and few defects.

[0085] It is preferable to maintain a low substrate temperature when depositing a metal oxide film. For example, it is preferable to deposit the metal oxide film without heating the substrate. This reduces the number of crystal grains generated during the deposition of the metal oxide film, resulting in a metal oxide film with low crystallinity.

[0086] The temperature for the heat treatment is preferably 100°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 670°C or lower, more preferably 300°C or higher and 670°C or lower, more preferably 350°C or higher and 670°C or lower, more preferably 400°C or higher and 670°C or lower, and more preferably 450°C or higher and 670°C or lower. It is preferable that the temperature of the substrate during the heat treatment falls within the above temperature range. However, the temperature of the substrate during the heat treatment is not limited to the above range.

[0087] A high heat treatment temperature is preferable. By increasing the heat treatment temperature, the crystallinity of the semiconductor layer 108 can be efficiently increased. In the semiconductor layer 108, regions with low crystallinity (e.g., amorphous regions) may exist between crystal grains. In particular, if regions with low crystallinity exist in the channel formation region, there is a risk that the field-effect mobility of the transistor will be reduced due to carrier scattering. By increasing the heat treatment temperature, the grain size of the crystal grains increases, and the regions with low crystallinity between crystal grains can be reduced. This makes it possible to create a transistor with high field-effect mobility. In addition, by increasing the heat treatment temperature, the grain size of the crystal grains contained in the semiconductor layer 108 may increase. By increasing the heat treatment temperature, defects in the semiconductor layer 108 can be further reduced. Furthermore, impurities contained in the semiconductor layer 108 or adsorbed on the surface can be efficiently removed by heat treatment. Alternatively, impurities contained in the semiconductor layer 108 (e.g., impurities caused by the film formation gas) can be efficiently removed by heat treatment. Alternatively, extending the heat treatment time can produce the same effect as increasing the heat treatment temperature. For example, if the heat treatment temperature is low, the crystallinity of the semiconductor layer 108 can be further enhanced by increasing the heat treatment time. On the other hand, if the heat treatment temperature is high, the heat treatment time required to sufficiently enhance the crystallinity of the semiconductor layer 108 can be shortened. For example, when the heat treatment temperature is 500°C or lower (typically 450°C), the heat treatment time is preferably 1 hour or more, more preferably 4 hours or more, more preferably 8 hours or more, more preferably 12 hours or more, and more preferably 24 hours or more.

[0088] The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing or oxygen-containing atmosphere. It is preferable to carry out the heat treatment in an oxygen-containing atmosphere. Performing the heat treatment in an oxygen-containing atmosphere may enhance effects such as defect reduction and increased grain size. CDA can be suitably used as the atmosphere for the heat treatment. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the semiconductor layer 108 as much as possible.

[0089] The apparatus used for the heat treatment is not particularly limited, and for example, an apparatus that heats by heat conduction or thermal radiation from a heating element can be used. For example, an oven or a rapid thermal annealing (RTA) apparatus can be used for the heat treatment. As an RTA apparatus, an LRTA (Lamp RTA) apparatus that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp can be used. Examples of such lamps include halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Alternatively, as an RTA apparatus, a GRTA (Gas RTA) apparatus that heats the workpiece using high-temperature gas can be used. By using an RTA apparatus, the heat treatment time can be shortened. The treatment time is preferably 1 minute or more and 10 minutes or less, more preferably 3 minutes or more and 10 minutes or less, and more preferably 5 minutes or more and 10 minutes or less. Furthermore, when using an RTA device and requiring a short heating time, the heating temperature can be set above the substrate's strain point. This further reduces the heating time. In the case of a GRTA device, a typical heating treatment of 6 minutes at 650°C can be used. Alternatively, in the case of an oven, a typical heating treatment of 12 hours at 450°C can be used.

[0090] The grain size of the crystal grains contained in the semiconductor layer 108 is preferably 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferable, no particular upper limit is set for the grain size. Note that the grain size of the crystal grains is not limited to the above range.

[0091] The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0092] The grain size of the crystal grains contained in the semiconductor layer 108 can be analyzed, for example, by transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), or electron backscatter diffraction (EBSD or EBSP). Alternatively, a combination of these methods can be used for analysis. For example, the average grain size of multiple crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be defined as, for example, the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter of a circle.

[0093] In this specification, a grain boundary refers to, for example, the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two grains in a TEM image, if the crystal orientations of those two grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same grain.

[0094] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual planes indicating crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axis is defined.

[0095] For example, in the cubic system, ２ O ３ The crystal structure belongs to space group Ia-3 (space group number 206).

[0096] The grain size of the crystal grains can also be confirmed, for example, using an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating irregularities on the surface of the semiconductor layer 108 using etchants with different etching rates depending on the crystal plane or crystallinity, the crystal grains can be more easily observed with an optical microscope or a scanning electron microscope (SEM). When an indium oxide film is used as the semiconductor layer 108, the crystal grains of indium oxide can be more easily observed by using an etchant containing an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid. However, if the etching rate is too fast, a part of the semiconductor layer 108 may disappear, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by controlling the concentration, temperature, and processing time of the etchant so that the semiconductor layer 108 does not disappear but its thickness is reduced (also called half-etching). By performing half-etching, it becomes possible to easily observe the crystal grains.

[0097] Furthermore, if the thickness T108 is thin, it may not be possible to evaluate the crystallinity and grain size of the semiconductor layer 108.

[0098] As mentioned above, by using indium oxide in the semiconductor layer, a transistor with a large on-current can be made. Therefore, a semiconductor device that operates at high speed can be made. When a semiconductor device according to one aspect of the present invention is applied to a display device, a display device that operates at high speed and has high display quality can be made. In addition, because the I / O transistor has high field-effect mobility, a large on-current can be obtained even with a small channel width. Therefore, the area occupied by the transistor can be reduced, and thus the area occupied by the semiconductor device can be reduced. When a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be made. Furthermore, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of the gate line drive circuit and the source line drive circuit), the area occupied by the drive circuit can be reduced, and a narrow-bezel display device can be made.

[0099] In the semiconductor layer 108, the length of the region located between the source region and the drain region, and overlapping with the conductive layer 104 via the insulating layer 106, is the channel length L of the transistor 100. In Figures 1A and 1B, the channel length L is indicated by a dashed double arrow. Furthermore, the width of the region where the semiconductor layer 108 and the conductive layer 104 overlap in a direction perpendicular to the channel length direction is the channel width W of the transistor 100. In Figures 1A and 1C, the channel width W is indicated by a solid double arrow.

[0100] Transistor 100 is a so-called top-gate type transistor, having a gate electrode above the semiconductor layer 108. Furthermore, by supplying impurities to the semiconductor layer 108 using the conductive layer 104, which functions as the gate electrode, as a mask, regions 108P and 108Q, which function as the source and drain regions respectively, can be formed in a self-aligned manner. Transistor 100 can be described as a TGSA (Top Gate Self-Aligned) type transistor.

[0101] Regions 108P and 108Q contain impurities. By supplying impurities to the semiconductor layer 108, the electrical resistance of regions 108P and 108Q can be lowered. The concentration of impurities in regions 108P and 108Q is higher than the concentration of impurities in the channel-forming region. The elements contained in the impurities (hereinafter also referred to as the first element) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the first element.

[0102] Ion implantation is suitably used for supplying impurities. Ion implantation allows for highly precise control of the concentration profile in the depth direction by controlling the ion acceleration energy and dose amount. Furthermore, by using an ion implantation method that ionizes the source gas and supplies the ions after mass separation, it is possible to supply ions of a specific mass, thereby increasing the purity of the supplied impurities. Alternatively, productivity can be increased by using an ion implantation method that supplies ions without mass separation. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that the method of supplying ions after mass separation is sometimes called ion implantation, and the method of supplying ions without mass separation is sometimes called ion doping.

[0103] When an element that readily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 108 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V) exist in the semiconductor layer 108. Ｏ ) occurs. If an element that becomes stable when bonded with oxygen is used as the first element, the first element in the semiconductor layer 108 exists stably in an oxidized state, so it is less likely to desorb due to heat applied during the semiconductor device manufacturing process, and the electrical resistance of regions 108P and 108Q can be kept low. For this reason, it is preferable to use an element as the first element in which its oxide can exist as a solid at least at the temperature during the manufacturing process. Boron and phosphorus, or both, can be suitably used as the first element.

[0104] When boron is used as the first element, boron contained in regions 108P and 108Q can exist in a state bonded with oxygen. This is evident in X-ray photoelectron spectroscopy (XPS) analysis, B ２ O ３This can be confirmed by observing peaks caused by bonding. Furthermore, in XPS analysis, peaks caused by the element boron in its elemental state may not be observed, or their peak intensity may be extremely low, almost at background levels. XPS is sometimes referred to as ESCA (Electron Spectrometry for Chemical Analysis).

[0105] Hydrogen, through its supply, can fill oxygen deficiencies (V Ｏ ) occurs, along with oxygen deficiency (V Ｏ By entering V Ｏ Because H is generated, the electrical resistance of regions 108P and 108Q can be efficiently reduced. Therefore, hydrogen can be suitably used as the first element.

[0106] In supplying impurities, it is preferable to adjust the supply conditions so that the concentration of impurities is highest on the surface of the semiconductor layer 108, or in a region close to the surface.

[0107] The raw material used to supply impurities can, for example, be a gas containing the first element. When supplying boron, typically B ２ H ６ Gas, or BF ３ One or more gases can be used. Also, when supplying phosphorus, typically pH ３ Gases can be used. Furthermore, gases obtained by diluting these raw material gases with noble gases can also be used. Note that the raw materials are not limited to gases; solids or liquids can also be heated and vaporized for use.

[0108] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 108. When supplying impurities to the semiconductor layer 108 via the insulating layer 106 using the conductive layer 104 as a mask, impurities may be supplied to areas of the insulating layer 106 that do not overlap with the conductive layer 104, resulting in those areas containing impurities. Similarly, impurities may be supplied to areas of the insulating layer 105 that do not overlap with the conductive layer 104, resulting in those areas containing impurities.

[0109] The method of supplying impurities is not limited to this; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0110] For example, by performing plasma processing in an atmosphere containing a gas that includes the element hydrogen using a plasma CVD apparatus, hydrogen can be supplied as an impurity to regions of the semiconductor layer 108 that do not overlap with the conductive layer 104.

[0111] The insulating layer 195 and the insulating layer 106 have an opening 147a that reaches region 108P and an opening 147b that reaches region 108Q.

[0112] A conductive layer 112a is provided so as to cover the opening 147a. At the opening 147a, the conductive layer 112a is in contact with region 108P and connected to region 108P. A conductive layer 112b is provided so as to cover the opening 147b. At the opening 147b, the conductive layer 112b is in contact with region 108Q and connected to region 108Q. The conductive layer 112a functions as one of the source electrode and drain electrode of the transistor 100, and the conductive layer 112b functions as the other of the source electrode and drain electrode.

[0113] An insulating layer 218 is provided on the conductive layer 112a, the conductive layer 112b, and the insulating layer 195. The insulating layer 195 and the insulating layer 218 each function as protective layers for the transistor 100.

[0114] In a TGSA-type transistor, the physical distance between the conductive layers 112a and 112b, which function as the source and drain electrodes, and the conductive layer 104, which functions as the gate electrode, can be increased, thereby reducing the parasitic capacitance between them.

[0115] [Semiconductor Layer 108] The metal oxides that can be used in the semiconductor layer 108 will be described in detail. As mentioned above, it is preferable that the metal oxide contains at least indium. Indium oxide can be suitably used as the metal oxide. Alternatively, for example, gallium oxide (also written as gallium oxide) or zinc oxide (also written as zinc oxide) can be used as the metal oxide. Alternatively, it is preferable that the metal oxide contains one or both of indium and element M. Alternatively, it is preferable that the metal oxide contains one or both of indium and zinc. Alternatively, it is preferable that the metal oxide has one or more selected from indium, element M, and zinc. Element M is a metallic element or metalloid with a high bond energy with oxygen, for example, a metallic element or metalloid with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferable because they have high bonding energy with oxygen and similar ionic radii to indium or zinc. Furthermore, tin is more preferable because its tetravalent state enhances carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the term "metallic elements" as used here may include metalloid elements.

[0116] The semiconductor layer 108 is, for example, made of indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide (Al-Zn oxide). Other suitable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also known as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO, IGZAO, or IAGZO). Alternatively, silicon-containing indium tin oxide (In-Sn-Si oxide, also known as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0117] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0118] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0119] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a high on-current can be realized.

[0120] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0121] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0122] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be obtained. Furthermore, oxygen vacancies (V) can be added to the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed, Ｏ This suppresses carrier generation caused by (), thereby preventing a shift in the transistor's threshold voltage. As a result, the drain current (hereinafter also referred to as the cutoff current) that flows when the gate voltage (Vg) is 0V can be reduced, making it possible to create a normally-off transistor. Furthermore, it is possible to create a transistor with a small off-current. In addition, fluctuations in the transistor's electrical characteristics are suppressed, improving reliability.

[0123] The composition of the metal oxide applied to the semiconductor layer 108 affects the electrical characteristics and reliability of the transistor. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, it is possible to create a semiconductor device that achieves both excellent electrical characteristics and high reliability.

[0124] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, and In:M Compositions such as Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. In this specification, "nearby composition" includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0125] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0126] A metal oxide that does not contain element M can be applied to the semiconductor layer 108. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0127] A metal oxide containing indium and element M can be applied to the semiconductor layer 108. The presence of element M allows for oxygen deficiency (V Ｏ This can suppress the formation of ). However, if the content of element M in the metal oxide is too high, the content of indium will decrease, and the field effect mobility may decrease. Therefore, it is preferable that the atomic ratio of In in the metal oxide is greater than or equal to the atomic ratio of element M. The content of element M in the metal oxide (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 1% to 35%, more preferably 1% to 30%, more preferably 1% to 25%, more preferably 1% to 20%, more preferably 2% to 20%, more preferably 4% to 20%, more preferably 6% to 20%, and more preferably 8% to 20%. This makes it possible to make a transistor with good electrical properties. Note that the content of element M in the semiconductor layer 108 is not limited to the above range.

[0128] When the metal oxide is an In-M oxide, it is preferable to use metal oxides with atomic ratios of metal elements such as In:M = 99:1, In:M = 98:2 (49:1), In:M = 97:3, In:M = 95:5 (19:1), In:M = 10:1, In:M = 5:1, In:M = 4:1, In:M = 3:1, In:M = 2:1, or near these ratios. Typically, metal oxides with any of these atomic ratios and in which element M is Ga can be suitably used.

[0129] When the metal oxide is an In-M-Zn oxide, it is preferable to use a metal oxide with an atomic ratio of metal elements of, for example, In:M:Zn = 40:1:10, or close to that ratio. Typically, a metal oxide with any of these atomic ratios and in which element M is Ga can be suitably used.

[0130] For analyzing the composition of the semiconductor layer 108, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of the analysis accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0131] The semiconductor layer 108 can be a single layer or a stacked structure of two or more layers. When the semiconductor layer 108 has a stacked structure, the aforementioned metal oxides can be suitably used in each layer of the semiconductor layer 108. The same material can be used for each layer of the semiconductor layer 108. Alternatively, different materials can be used for one or more layers of the semiconductor layer 108.

[0132] In this specification, "different materials" refers to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0133] Sputtering or ALD (Advanced Laser Deposition) can be suitably used to deposit metal oxide films. However, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% of the content in the sputtering target.

[0134] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structure, polycrystalline structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0135] It is preferable to use CAAC-OS or nc-OS for the semiconductor layer 108.

[0136] CAAC-OS has multiple layered crystals. The c-axis of the crystals is oriented in the direction normal to the surface to be formed. It is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the surface to be formed. For example, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the upper surface of the conductive layer 112b in the region in contact with the upper surface of the conductive layer 112b, and layered crystals that are parallel or approximately parallel to the side surface in the region in contact with the side surface of the conductive layer 112b. In particular, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the side surface that is the surface to be formed in the region in contact with the side surface of the insulating layer 110. With this configuration, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, so that a transistor with a large on-current can be made.

[0137] OS transistors exhibit minimal fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton beams, and neutron beams).

[0138] The semiconductor layer 108 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0139] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel-forming region is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0140] [Insulating layer 106, insulating layer 105] It is preferable that insulating layer 106 and insulating layer 105 each have one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0141] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0142] The insulating layer 106 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 106 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 106. Specifically, it is preferable that the region of the insulating layer 106 that is in contact with the channel-forming region contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 106 that is in contact with the channel-forming region. The same applies to the insulating layer 105. For example, it is preferable that the insulating layer 106 and the insulating layer 105 each contain silicon and oxygen, respectively. Silicon oxide or silicon oxiditride can be suitably used for the insulating layer 106 and the insulating layer 105, respectively.

[0143] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxiditrides having aluminum and hafnium, oxides having silicon and hafnium, oxiditrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0144] In Figure 1B and other figures, the insulating layer 106 and insulating layer 105 are shown as single-layer structures, but the present invention is not limited to this. One or both of the insulating layer 106 and insulating layer 105 can be made into a laminated structure of two or more layers. When the insulating layer 106 is made into a laminated structure, it is preferable that the insulating layer on the semiconductor layer 108 side has an oxide or oxidizride. Similarly, when the insulating layer 105 is made into a laminated structure, it is preferable that the insulating layer on the semiconductor layer 108 side has an oxide or oxidizride. For example, silicon oxide, silicon oxidizride, or aluminum oxide can be suitably used as the insulating layer on the semiconductor layer 108 side.

[0145] It is preferable to use a material that is difficult for substances to permeate in one or more of the layers constituting the insulating layer 106. This layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layer formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the semiconductor layer 108 into the conductive layer 104 side via the insulating layer 106. As a result, oxygen deficiencies (V) in the semiconductor layer 108 are suppressed. Ｏ This can suppress the formation of ( ). Furthermore, it can suppress oxidation of the conductive layer 104 by oxygen contained in the semiconductor layer 108, which would increase the electrical resistance of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be obtained. Similarly, it is preferable to provide a layer that functions as a barrier film on one or more of the layers constituting the insulating layer 105.

[0146] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for the target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability), and a function that captures or fixes the substance (also known as gettering).

[0147] The barrier film can be, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, an oxidized nitride having silicon, and an oxide nitride having silicon. Typically, the barrier film can preferably be one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, silicon oxidized nitride, and silicon oxide nitride. The barrier film of the insulating layer 106 can be one or more of oxides and oxidized nitrides, for example, aluminum oxide can be preferably used. Also, the barrier film of the insulating layer 105 can be one or more of nitrides and oxide nitrides, for example, silicon nitride can be preferably used.

[0148] The insulating layer 106 can be, for example, a laminated structure of a silicon oxidizide film and a silicon nitride film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of a silicon oxidizide film and an aluminum oxide film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon oxidizide film on the aluminum oxide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film. Here, an example is shown in which the insulating layer 106 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 106 can also have a laminated structure of three or more layers.

[0149] The insulating layer 105 can, for example, be a laminated structure of a silicon nitride film and a silicon oxynitride film on the silicon nitride film. Here, an example is shown in which the insulating layer 105 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 105 can also have a laminated structure of three or more layers.

[0150] [Conductive layer 112a, conductive layer 112b, conductive layer 104] Conductive layer 112a, conductive layer 112b, and conductive layer 104 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for conductive layer 112a, conductive layer 112b, and conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive layers 112a, conductive layer 112b, and conductive layer 104 can preferably be conductive materials with low electrical resistivity that include one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred because they are easy to mass-produce.

[0151] Conductive layers 112a, 112b, and 104 can each be made of a conductive metal oxide (also called an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, ITSO, zinc oxide with added gallium, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0152] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0153] The conductive layer 112a, conductive layer 112b, and conductive layer 104 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0154] The conductive layer 112a, conductive layer 112b, and conductive layer 104 can each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0155] The conductive layers 112a, 112b, and 104 can each be made of a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). Using a Cu-X alloy film allows for processing by wet etching, thus reducing manufacturing costs.

[0156] The conductive layer 112a, conductive layer 112b, and conductive layer 104 may be made of the same material. Alternatively, at least one of them may be made of a different material.

[0157] [Insulating layer 195] The insulating layer 195 preferably has one or more inorganic insulating layers. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105.

[0158] The insulating layer 195 preferably functions as a barrier film. This effectively suppresses the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside, thereby improving the reliability of the semiconductor device. For example, silicon nitride and silicon nitride oxide, or both, can be suitably used as the insulating layer 195. Refer to the above description for details regarding the barrier film.

[0159] [Insulating layer 218] As the insulating layer 218, either an inorganic insulating layer or an organic insulating layer, or both, can be used. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The organic insulating layer functions as a planarizing layer that reduces irregularities caused by the transistor.

[0160] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates can be used as the substrate 102. In addition, a substrate on which a semiconductor element is provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0161] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0162] The following describes a configuration example that differs in some aspects from the aforementioned Configuration Example 1-1. Note that in the following, explanations of parts that overlap with Configuration Example 1-1 may be omitted. Furthermore, in the drawings shown below, parts having the same function as Configuration Example 1-1 may use the same hatching pattern and may not be labeled.

[0163] Furthermore, the structure of the transistor that can be applied to a semiconductor device according to one aspect of the present invention is not particularly limited.

[0164] [Configuration Example 1-2] Figure 2A shows a top view of a semiconductor device 10A, which is one embodiment of the present invention. Figure 2B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 2A, and Figure 2C shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2.

[0165] The semiconductor device 10A has a transistor 100A. Transistor 100A differs from transistor 100 shown in Figure 1B, etc., in that it has a conductive layer 103.

[0166] The conductive layer 103 is provided between the substrate 102 and the insulating layer 105. The conductive layer 103 functions as the back gate electrode of the transistor 100A. The conductive layer 103 has a region that overlaps with the conductive layer 104 via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106. The insulating layer 105 functions as the back gate insulating layer of the transistor 100A.

[0167] By providing a back gate electrode, the potential on the back gate electrode side (also called the back channel side) of the semiconductor layer 108 is fixed, which can improve the saturation in the Id-Vd characteristics. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 108, the threshold voltage shift can be suppressed. Therefore, a transistor with a small cutoff current can be made, resulting in a semiconductor device with low power consumption.

[0168] The conductive layer 103 preferably has a region that protrudes from the edge of the conductive layer 104. This enhances the effect of making it difficult for electric fields generated outside the transistor to act on the channel formation region (also known as the electric field shielding effect).

[0169] The conductive layer 103 can be configured to be connected to either the conductive layer 112a or the conductive layer 112b. For example, by providing openings in the insulating layer 195, insulating layer 106, and insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 112a so as to cover these openings, the conductive layer 103 and the conductive layer 112a can be in contact. By connecting the conductive layer 112a and the conductive layer 103, the source electrode and the drain electrode and the back gate electrode can be brought to the same potential. For example, when the conductive layer 112a functions as the source electrode, a shift in the threshold voltage of the transistor 100A can be suppressed. Furthermore, the reliability of the transistor 100A can be improved.

[0170] The conductive layer 103 can be configured to be connected to the conductive layer 104. For example, by providing openings in the insulating layer 106 and the insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 104 so as to cover the openings, the conductive layer 103 and the conductive layer 104 can be in contact. By connecting the gate electrode and the back gate electrode, the back gate electrode and the gate electrode can be brought to the same potential, and the on-current of the transistor 100A can be increased.

[0171] The conductive layer 103 can be made from the materials listed for conductive layer 104, conductive layer 112a, and conductive layer 112b. Since the conductive layer 103 is formed before the semiconductor layer 108, it is preferable to use a material that can withstand the heat treatment involved in the formation of the semiconductor layer 108. It is preferable to use a high melting point material (for example, tungsten and molybdenum) that provides both heat resistance and conductivity for the conductive layer 103. For example, tungsten can be suitably used for the conductive layer 103.

[0172] [Configuration Example 1-3] Figures 3A and 3B show cross-sectional views of a semiconductor device 10B, which is one embodiment of the present invention. A top view of the semiconductor device 10B can be found in Figure 2A. Figure 3A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 3B is a cross-sectional view of the section along the dashed line B1-B2.

[0173] The semiconductor device 10B has a transistor 100B. Transistor 100B differs from transistor 100A shown in Figure 2B, etc., in that its insulating layer 105 has a multilayer structure.

[0174] Figures 3A and 3B show an example in which the insulating layer 105 has an insulating layer 105a and an insulating layer 105b on top of the insulating layer 105a.

[0175] The insulating layer 105b has a region that is in contact with the semiconductor layer 108. As mentioned above, it is preferable that the insulating layer 105b in contact with the semiconductor layer 108 contains oxygen.

[0176] The insulating layer 105a located on the substrate 102 and conductive layer 103 side preferably functions as a barrier film. By providing a barrier film, the diffusion of components (e.g., metals) contained in the substrate 102 and conductive layer 103 into the semiconductor layer 108 can be suppressed, resulting in a highly reliable semiconductor device. The barrier film can be described in the above description. The insulating layer 105a preferably contains nitrogen.

[0177] The insulating layer 105a preferably contains silicon and nitrogen. The insulating layer 105b preferably contains silicon and oxygen. For example, silicon nitride can be suitably used for the insulating layer 105a and silicon oxynitride can be suitably used for the insulating layer 105b.

[0178] [Configuration Example 1-4] Figures 4A and 4B show cross-sectional views of a semiconductor device 10C, which is one embodiment of the present invention. A top view of the semiconductor device 10C can be found in Figure 2A. Figure 4A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 4B is a cross-sectional view of the section along the dashed line B1-B2.

[0179] The semiconductor device 10C has a transistor 100C. Transistor 100C differs from transistor 100A shown in Figure 2B, etc., in that the edge of the insulating layer 106 coincides with, or approximately coincides with, the edge of the conductive layer 104.

[0180] The edges of the insulating layer 106 are located on the semiconductor layer 108. Furthermore, the insulating layer 106 does not overlap with either region 108P or region 108Q. It can also be said that the upper surface shape of the insulating layer 106 matches, or roughly matches, that of the conductive layer 104. The insulating layer 106 can be formed, for example, by processing it using a resist mask for processing the conductive layer 104.

[0181] The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 106, and the upper and side surfaces of the conductive layer 104. The insulating layer 195 has an opening 147a that reaches region 108P and an opening 147b that reaches region 108Q. Conductive layers 112a and 112b are formed to cover openings 147a and 147b. Conductive layer 112a is in contact with region 108P at opening 147a and is connected to region 108P. Conductive layer 112b is in contact with region 108Q at opening 147b and is connected to region 108Q.

[0182] By using a plasma CVD apparatus for supplying impurities to regions 108P and 108Q, and for forming the insulating layer 195, the supply of impurities and the formation of the insulating layer 195 can be performed continuously within the apparatus, thereby increasing productivity. For example, by performing plasma processing in an atmosphere containing a gas containing hydrogen element using a plasma CVD apparatus, hydrogen can be supplied as an impurity to regions of the semiconductor layer 108 that do not overlap with the conductive layer 104.

[0183] Figures 4C and 4D show configuration examples different from those shown in Figures 4A and 4B. Figures 4C and 4D are cross-sectional views of a semiconductor device 10D according to one embodiment of the present invention. A top view of the semiconductor device 10D can be found in Figure 2A. Figure 4C is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 4D is a cross-sectional view of the section along the dashed line B1-B2.

[0184] The semiconductor device 10D has a transistor 100D. Transistor 100D differs from transistor 100C shown in Figure 4A in that the insulating layer 106 has a region that protrudes more than the conductive layer 104.

[0185] The edges of the insulating layer 106 are located on the semiconductor layer 108, and the edges of the conductive layer 104 are located on the insulating layer 106. It can also be said that the edges of the insulating layer 106 are located outside the edges of the conductive layer 104. The insulating layer 106 has a region that overlaps with the conductive layer 104 and a region that does not overlap with the conductive layer 104 on the semiconductor layer 108.

[0186] The semiconductor layer 108 has a channel formation region, regions 108R and 108S that sandwich the channel formation region, and regions 108P and 108Q located outside of them. Regions 108R and 108S are regions of the semiconductor layer 108 that overlap with the insulating layer 106 and do not overlap with the conductive layer 104. Region 108R is located between the channel formation region and region 108P, and region 108S is located between the channel formation region and region 108Q.

[0187] Regions 108R and 108S function as buffer regions to mitigate the drain electric field. Since regions 108R and 108S do not overlap with the conductive layer 104, channels are hardly formed in these regions even when a gate voltage is applied to the conductive layer 104. It is preferable that the carrier concentration in regions 108R and 108S is higher than that in the channel formation region. This allows regions 108R and 108S to function as LDD (Lightly Doped Drain) regions.

[0188] Regions 108R and 108S can also be described as regions with similar or lower electrical resistance, similar or higher carrier concentration, similar or higher oxygen defect density, and similar or higher impurity concentration compared to the channel-forming region.

[0189] Regions 108R and 108S can also be described as regions with similar or higher electrical resistance, similar or lower carrier concentration, similar or lower oxygen defect density, and similar or lower impurity concentration, compared to regions 108P and 108Q.

[0190] The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108, the upper and side surfaces of the insulating layer 106, and the upper and side surfaces of the conductive layer 104.

[0191] [Configuration Example 1-5] Figure 5A shows a top view of a semiconductor device 10E, which is one embodiment of the present invention. Figure 5B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 5A. For a cross-sectional view of the cross-section along the dashed-dotted line B1-B2, please refer to Figure 2C.

[0192] The semiconductor device 10E has a transistor 100E. Transistor 100E differs from transistor 100D shown in Figure 4C, etc., in that conductive layers 112a and 112b are formed in the same process as conductive layer 104.

[0193] The insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 108. Conductive layers 112a and 112b are provided so as to cover a portion of opening 147a and a portion of opening 147b. Conductive layer 112a has a region that contacts the semiconductor layer 108 at opening 147a, and conductive layer 112b has a region that contacts the semiconductor layer 108 at opening 147b.

[0194] Conductive layers 104, 112a, and 112b can be formed using the same material and the same process. For example, an insulating film is deposited on a semiconductor layer 108, and the insulating film is processed to form an insulating layer 106 having openings 147a and 147b. Then, a conductive film is deposited to cover the insulating layer 106, openings 147a and 147b, and the conductive film is processed to form conductive layers 104, 112a, and 112b. By forming conductive layers 112a and 112b using the same process as conductive layer 104, the process can be simplified.

[0195] By supplying the first element to the semiconductor layer 108 using conductive layers 104, 112a, and 112b as a mask, regions 108P and 108Q can be formed in a self-aligned manner. Regions 108P and 108Q are formed in regions of the semiconductor layer 108 that do not overlap with any of the conductive layers 104, 112a, 112b, and insulating layer 106. In addition, regions 108R and 108S are formed in regions of the semiconductor layer 108 that do not overlap with any of the conductive layers 104, 112a, and 112b, but overlap with the insulating layer 106.

[0196] The region of the semiconductor layer 108 that is in contact with the conductive layer 112a, and the region 108P in contact with said region, function as one of the source region and the drain region. The region of the semiconductor layer 108 that is in contact with the conductive layer 112b, and the region 108Q in contact with said region, function as the other of the source region and the drain region.

[0197] An insulating layer 195 is provided on the transistor 100E. Although Figure 5B shows an example configuration in which an insulating layer 218 is not provided, the present invention is not limited to this. An insulating layer 218 can also be provided on the insulating layer 195.

[0198] [Configuration Example 1-6] Figures 6A and 6B show cross-sectional views of a semiconductor device 10F according to one aspect of the present invention. A top view of the semiconductor device 10F can be found in Figure 2A. Figure 6A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 6B is a cross-sectional view of the section along the dashed line B1-B2.

[0199] The semiconductor device 10F has a transistor 100F. Transistor 100F differs from transistor 100C shown in Figure 4A, etc., in that its semiconductor layer 108 has a stacked structure.

[0200] Figure 6A and others show a configuration in which the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108a, semiconductor layer 108b on semiconductor layer 108a, and semiconductor layer 108c on semiconductor layer 108b. Semiconductor layer 108b is in contact with and sandwiched between semiconductor layers 108a and 108c.

[0201] The semiconductor layers 108a, 108b, and 108c can each be made from the materials listed for semiconductor layer 108. The semiconductor layers 108a, 108b, and 108c can each be made from the same material. Indium oxide can be suitably used for each of the semiconductor layers 108a, 108b, and 108c. Alternatively, In-M oxide can be suitably used for each of the semiconductor layers 108a, 108b, and 108c. For example, gallium can be used as element M. Different materials can be used for one or more of the semiconductor layers 108a, 108b, and 108c.

[0202] In some cases, the boundaries between semiconductor layer 108a and semiconductor layer 108b, and between semiconductor layer 108b and semiconductor layer 108c, cannot be clearly identified. Therefore, in Figure 6A and other figures, these boundaries are shown with dashed lines.

[0203] It is preferable that the conductivity of semiconductor layer 108b is higher than that of either semiconductor layer 108a or semiconductor layer 108c. This ensures that the main current path in transistor 100F is semiconductor layer 108b. On the other hand, in semiconductor layer 108, it is preferable that semiconductor layer 108a, which is in contact with insulating layer 105, and semiconductor layer 108c, which is in contact with insulating layer 106, are denser and have fewer defects than semiconductor layer 108b.

[0204] Trap levels caused by impurities or defects may form at the interface between the insulating layer 106, which functions as a gate insulating layer, and the semiconductor layer 108, and at the interface between the insulating layer 105, which functions as a back gate insulating layer, and the semiconductor layer 108, and at the interface at the interface at the interface at the interface. Furthermore, when the insulating layer 106 is deposited, damage may be inflicted on the interface between the insulating layer 106 and the semiconductor layer 108, causing trap levels to form at the interface

[0205] Here, when a high potential is applied to the conductive layer 104, which functions as the gate electrode, trap levels may be formed at and near the interface between the insulating layer 106 and the semiconductor layer 108. Similarly, when a high potential is applied to the conductive layer 103, which functions as the back gate electrode, trap levels may be formed at and near the interface between the insulating layer 105 and the semiconductor layer 108. If electrons are trapped in these trap levels, the threshold voltage of the transistor may shift to the positive side, potentially reducing reliability. By providing a semiconductor layer 108c with few defects in contact with the insulating layer 106, the formation of trap levels at and near the interface between the insulating layer 106 and the semiconductor layer 108 can be suppressed. Similarly, by providing a semiconductor layer 108a with few defects in contact with the insulating layer 105, the formation of trap levels at and near the interface between the insulating layer 105 and the semiconductor layer 108 can be suppressed. This makes it possible to create a highly reliable transistor.

[0206] In this way, by sandwiching the highly conductive semiconductor layer 108b between the less defective semiconductor layers 108a and 108c, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0207] In the channel formation region, it is preferable that the carrier mobility of semiconductor layer 108b is higher than that of semiconductor layer 108a and semiconductor layer 108c. Here, when a non-single-crystal (e.g., polycrystalline) metal oxide is used for the semiconductor layer, the carrier mobility can be increased by increasing the carrier concentration. It is preferable that the carrier concentration of semiconductor layer 108b is higher than that of semiconductor layer 108a and semiconductor layer 108c. As a result, the conductivity of semiconductor layer 108b, which is the main current path, is increased, and a transistor with high field-effect mobility can be made.

[0208] It is preferable that semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c each contain an element that increases the carrier concentration (hereinafter also referred to as the second element). For example, one or more of hydrogen, carbon, and nitrogen can be used as the second element. Hydrogen can be suitably used as the second element. Hydrogen reacts with oxygen bonded to the metal atoms of the metal oxide to form water, thereby creating oxygen vacancies (V) in the metal oxide. Ｏ ) is formed. Furthermore, oxygen deficiency (V Ｏ A defect (V) into which hydrogen has entered Ｏ H) functions as a donor, generating electrons, which are carriers, thereby increasing the carrier concentration in the metal oxide. Note that in the following explanation, hydrogen may be used as an example of the second element.

[0209] In the channel formation region, it is preferable that semiconductor layer 108b has a region with a higher concentration of the second element compared to semiconductor layer 108a and semiconductor layer 108c. Typically, it is preferable that semiconductor layer 108b has a region with a higher hydrogen concentration compared to semiconductor layer 108a and semiconductor layer 108c. In the channel formation region, semiconductor layer 108b has a concentration of the second element (for example, hydrogen) of 1 × 10⁻¹⁶. １９ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 1 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３It is preferable to have the following regions. If the concentration of the second element in the semiconductor layer 108b is too low, the carrier concentration will be low, and there is a risk that the carrier mobility will be low. On the other hand, if the concentration of the second element in the semiconductor layer 108b is too high, the V of the channel formation region Ｏ An increase in the amount of H may cause a shift in the threshold voltage and a larger cutoff current. By setting the concentration of the second element in the semiconductor layer 108b within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and a small cutoff current. Note that the concentration of the second element in the semiconductor layer 108 may have a gradient in the thickness direction of the semiconductor layer 108. It is preferable that the maximum value of the concentration of the second element in the semiconductor layer 108b is within the aforementioned range. Note that the concentration of the second element in the semiconductor layer 108b is not limited to the aforementioned range.

[0210] In the channel formation region, it is preferable that semiconductor layer 108a and semiconductor layer 108c each have regions where the concentration of the second element is lower compared to semiconductor layer 108b. In the channel formation region, it is preferable that semiconductor layer 108a and semiconductor layer 108c each have regions where the concentration of the second element (e.g., hydrogen) is 1 / 100 to 1 / 2 of the concentration of the second element in semiconductor layer 108b, more preferably 1 / 100 to 1 / 4, more preferably 1 / 100 to 1 / 6, more preferably 1 / 100 to 1 / 8, and more preferably 1 / 100 to 1 / 10. If the concentration of the second element in semiconductor layer 108a and semiconductor layer 108c is too high, the film density will be low, and there is a risk of many defects. On the other hand, if the concentration of the second element in semiconductor layer 108a and semiconductor layer 108c is too low, the carrier concentration will be low, resulting in low carrier mobility, which may lead to low field-effect mobility. By setting the concentration of the second element in semiconductor layer 108a and semiconductor layer 108c within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and high reliability. As mentioned above, the concentration of the second element in semiconductor layer 108 may have a gradient in the thickness direction of semiconductor layer 108. It is preferable that the minimum value of the concentration of the second element in semiconductor layer 108a and the minimum value of the concentration of the second element in semiconductor layer 108c are within the aforementioned range. However, the concentration of the second element in semiconductor layer 108a and semiconductor layer 108c is not limited to the aforementioned range.

[0211] For analyzing the concentration of the second element in the semiconductor layer 108, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. For example, SIMS can be suitably used for analyzing hydrogen concentration. However, the reliability of measurement values ​​may be low at the interface between the semiconductor layer 108 and the layer in contact with the semiconductor layer 108, and in its vicinity, due to the matrix effect. For example, when measuring in the direction from the insulating layer 106 toward the semiconductor layer 108, the reliability of measurement values ​​may be low at the interface between the insulating layer 106 and the semiconductor layer 108, and in its vicinity. Measurement values ​​in unreliable regions should not be treated as the concentration of the second element in the semiconductor layer 108. Furthermore, by combining measurements taken from the insulating layer 106 towards the semiconductor layer 108 and measurements taken from the insulating layer 105 towards the semiconductor layer 108, the accuracy of the analysis of the concentration of the second element in the semiconductor layer 108 can sometimes be improved.

[0212] In concentration analysis, the intensity of the constituent elements of the metal oxide can sometimes be used to estimate the location of the interface between the insulating layer 106 and the semiconductor layer 108, and the location of the interface between the insulating layer 105 and the semiconductor layer 108. For example, the range in which the intensity of the constituent elements of the metal oxide present in the semiconductor layer 108 is 1 / 2 or more of its maximum value can be called the semiconductor layer 108. When indium oxide is used for the semiconductor layer 108 and SIMS is used for the concentration analysis of the second element, the range in which the secondary ion intensity of indium is 1 / 2 or more of its maximum value can be called the semiconductor layer 108, and the range in which it is less than 1 / 2 of its maximum value can be called layers other than the semiconductor layer 108 (e.g., insulating layer 105 and insulating layer 106). Alternatively, the range in which the secondary ion intensity of an indium-containing cluster (e.g., an indium-oxygen cluster) is 1 / 2 or more of its maximum value can be called the semiconductor layer 108, and the range in which it is less than 1 / 2 of its maximum value can be called layers other than the semiconductor layer 108 (e.g., insulating layer 105 and insulating layer 106).

[0213] Preferably, the film density of semiconductor layer 108a and semiconductor layer 108c is higher than the film density of semiconductor layer 108b. This reduces defects in semiconductor layer 108a and semiconductor layer 108c. Furthermore, by providing a semiconductor layer 108c with a high film density on semiconductor layer 108b, damage to semiconductor layer 108b during the deposition of the insulating layer 106 can be suppressed. For example, film density can be evaluated using Rutherford backscattering spectrum (RBS) or X-ray reflectivity (XRR).

[0214] Differences in film density can sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, even when the same material, such as indium oxide, is used for semiconductor layers 108a, 108b, and 108c, differences in film density among these layers can sometimes be observed as differences in contrast in cross-sectional TEM observations. Specifically, in the TE image, semiconductor layers 108a and 108c may have darker (darker) regions compared to semiconductor layer 108b. Also, semiconductor layer 108b may have lighter (brighter) regions compared to semiconductor layers 108a and 108c.

[0215] Furthermore, the film densities of semiconductor layer 108a and semiconductor layer 108c can be configured to be the same as, or lower than, the film densities of semiconductor layer 108b.

[0216] Even when using the same material, the etching rate may be slower if the film is denser and has a higher film density. It is preferable that the etching rate in one etchant of semiconductor layer 108a and semiconductor layer 108c is slower than the etching rate of semiconductor layer 108b. It is also preferable to provide a semiconductor layer 108c with a slow etching rate on top of semiconductor layer 108b. This makes it possible to suppress the disappearance of semiconductor layer 108c in the etching process after the formation of semiconductor layer 108, and to suppress the thinning of the thickness of semiconductor layer 108.

[0217] The semiconductor layer 108 can be formed by depositing a metal oxide film and processing the metal oxide film into island shapes. It is preferable to perform a heat treatment to crystallize the metal oxide film after depositing it or after processing the metal oxide film into island shapes. By performing the heat treatment, the particle size of the crystal grains contained in the semiconductor layer 108 can be increased and the crystallinity of the semiconductor layer 108 can be improved. Furthermore, the heat treatment can reduce defects in the semiconductor layer 108. In addition, the heat treatment can remove impurities contained in the semiconductor layer 108 or adsorbed on its surface.

[0218] When the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c, the metal oxide films are formed in the following order: a first metal oxide film to become semiconductor layer 108a, a second metal oxide film to become semiconductor layer 108b, and a third metal oxide film to become semiconductor layer 108c.

[0219] The first, second, and third metal oxide films are preferably deposited by sputtering using a metal target or a metal oxide target. Alternatively, the first, second, and third metal oxide films are preferably deposited by atomic layer deposition (ALD). ALD allows for easy control of the deposition rate, enabling the deposition of thin films with good yield. Therefore, ALD is particularly suitable when the metal oxide film is thin. Alternatively, chemical vapor deposition (CVD) can also be used.

[0220] Examples of power supplies used in sputtering apparatuses include DC (Direct Current) power supplies, RF (Radio Frequency) power supplies, and AC (Alternating Current) power supplies. A pulsed DC power supply that applies a pulsed voltage to the target can also be used. Furthermore, the magnetron sputtering method, which utilizes the magnetic field of a magnet, offers a high deposition rate, thus increasing productivity. The deposition of the first, second, and third metal oxide films can be suitably performed using sputtering methods, particularly magnetron sputtering. In the following, the magnetron sputtering method may be used as an example to describe the deposition methods for the first, second, and third metal oxide films.

[0221] When forming the first metal oxide film, the second metal oxide film, and the third metal oxide film, noble gases (for example, helium gas, argon gas, xenon gas, etc.) can be used.

[0222] It is preferable to deposit a second metal oxide film in a vacuum after depositing a first metal oxide film, without exposing the surface of the first metal oxide film to the atmosphere. Similarly, it is preferable to deposit a third metal oxide film in a vacuum after depositing a second metal oxide film, without exposing the surface of the second metal oxide film to the atmosphere. By depositing the first, second, and third metal oxide films in succession, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first and second metal oxide films. Examples of such impurities include water and organic matter.

[0223] When the same material is used for two or more of the first, second, and third metal oxide films, the films can be deposited in the same processing chamber using the same sputtering target.

[0224] It is preferable that semiconductor layers 108a, 108b, and 108c use the same material. The first metal oxide film, the second metal oxide film, and the third metal oxide film can be deposited continuously in the same processing chamber using the same sputtering target. This increases the productivity of semiconductor devices and reduces manufacturing costs. Furthermore, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first metal oxide film and the second metal oxide film.

[0225] Alternatively, it is preferable to use one or more different materials for semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c. Two or more sputtering targets can be used to deposit the first metal oxide film, the second metal oxide film, and the third metal oxide film. In this case as well, it is preferable to deposit the metal oxide films continuously in a vacuum within the same apparatus without exposing the surface of the metal oxide films to the atmosphere. For example, it is preferable to deposit each metal oxide film in different processing chambers continuously in a vacuum within the same apparatus.

[0226] As mentioned above, there are cases where the boundary between semiconductor layer 108a and semiconductor layer 108b, and the boundary between semiconductor layer 108b and semiconductor layer 108c cannot be clearly identified. In particular, in configurations where the same material is used for semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c, these boundaries may not be clearly identified. Furthermore, by continuously depositing the first metal oxide film, the second metal oxide film, and the third metal oxide film in a vacuum, no interface may be formed between each metal oxide film, and these boundaries may not be identified. In such cases, semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c can be read as the first region, the second region, and the third region. Semiconductor layer 108 has a first region (corresponding to semiconductor layer 108a) on the insulating layer 105 side, a third region (corresponding to semiconductor layer 108c) on the insulating layer 106 side, and a second region (corresponding to semiconductor layer 108b) between the first region and the third region.

[0227] Preferably, the concentration of the second element in the second region is higher than the concentration of the second element in the first region and higher than the concentration of the second element in the third region. The concentration of the second element in the second region can be determined by referring to the description of the concentration of the second element in semiconductor layer 108b described above. The concentrations of the second element in the first region and the third region can be determined by referring to the descriptions of the concentrations of the second element in semiconductor layer 108a and semiconductor layer 108c described above, respectively. Note that the concentrations of the second element in the first region, the second region, and the third region are not limited to the ranges described above.

[0228] Preferably, the film density of the first region and the third region is higher than the film density of the second region. When observing the cross-section of the semiconductor layer 108 using TEM, the first region and the third region may have darker areas in the TE image compared to the second region. Also, the second region may have lighter areas compared to the first and third regions.

[0229] Here, by varying the deposition conditions for the metal oxide film, the film quality of the metal oxide film (later the semiconductor layer) can be varied. Examples of film quality include conductivity, band gap, defect amount, impurity concentration, and crystallinity. Examples of deposition conditions include power density, pressure, gas type, gas flow rate, substrate temperature, and the distance between the sputtering target and the substrate (also called T-S distance or TS distance). When varying the deposition conditions, one or more of the power density, pressure, gas type, gas flow rate, substrate temperature, and T-S distance can be varied. Note that changing the substrate temperature and T-S distance may take time. Therefore, when depositing two or more metal oxide films in the same processing chamber, it is preferable to keep the substrate temperature and T-S distance the same. Note that even when using the same material, the band gap may differ by varying the deposition conditions.

[0230] It is preferable that the deposition conditions for the first metal oxide film (hereinafter also referred to as the first deposition conditions) are different from those for the second metal oxide film (hereinafter also referred to as the second deposition conditions). It is preferable that the deposition conditions for the third metal oxide film (hereinafter also referred to as the third deposition conditions) are different from those for the second deposition conditions. For example, it is preferable that one or both of the power density and pressure in the first deposition conditions are different from those in the second deposition conditions. Similarly, it is preferable that one or both of the power density and pressure in the third deposition conditions are different from those in the second deposition conditions. It is particularly preferable that the power density and pressure in the first deposition conditions are different from those in the second deposition conditions, and that the power density and pressure in the third deposition conditions are different from those in the second deposition conditions.

[0231] The power density under the first and third film deposition conditions is preferably higher than the power density under the second film deposition condition. By increasing the power density, dense semiconductor layers 108a and 108c with few defects can be obtained. The power density under the first and third film deposition conditions is preferably 0.3 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.4 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.5 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ 1W / cm or more ２ The following is preferable. If the power density is too low, there is a risk of an increase in defects in the semiconductor layer 108a and semiconductor layer 108c, while if the power density is too high, there is a risk of an increased load on the device. By setting the power density in the first and third film deposition conditions within the aforementioned range, it is possible to obtain dense semiconductor layers 108a and 108c with few defects, while also reducing the load on the device. Note that the power density in the first and third film deposition conditions is not limited to the aforementioned ranges.

[0232] Power density is calculated by dividing the power applied to the substrate by the magnet area. The magnet area is the area of ​​the surface of the magnet that overlaps with the sputtering target.

[0233] The power density under the second film deposition condition was 0.1 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.8W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.6W / cm or more ２ The following is preferable, and more preferably 0.3 W / cm². ２ 0.6W / cm or more ２ The following is preferable. Furthermore, it is preferable that the power density under the second film deposition condition is lower than the power density under the first and third film deposition conditions. If the power density is too high, the conductivity of the semiconductor layer 108b may be low, while if the power density is too low, the film deposition rate will be slow, which may reduce productivity. Also, if the power density is too low, the discharge may become unstable. By setting the power density under the second film deposition condition within the above range, it is possible to obtain a semiconductor layer 108b with high conductivity and to increase productivity. Note that the power density under the second film deposition condition is not limited to the above range.

[0234] The pressure in the first and third film deposition conditions is preferably lower than the pressure in the second film deposition condition. By lowering the pressure, dense semiconductor layers 108a and 108c with few defects can be obtained. The pressure in the first and third film deposition conditions is preferably 0.1 Pa or more and 0.8 Pa or less, more preferably 0.1 Pa or more and 0.6 Pa or less, more preferably 0.1 Pa or more and 0.4 Pa or less, and more preferably 0.1 Pa or more and 0.3 Pa or less. If the pressure is too high, there is a risk of an increase in defects in the semiconductor layer 108a and semiconductor layer 108c, while if the pressure is too low, it may take a long time to adjust the pressure in the processing chamber, which may reduce productivity. In addition, if the pressure is too low, arcing may occur, making it difficult to discharge. By setting the pressure in the first and third film deposition conditions within the aforementioned ranges, it is possible to produce dense semiconductor layers 108a and 108c with few defects, and to increase productivity. However, the pressure in the first and third film deposition conditions is not limited to the aforementioned ranges.

[0235] The pressure in the second film deposition condition is preferably 0.2 Pa or more and 1 Pa or less, more preferably 0.3 Pa or more and 1 Pa or less, more preferably 0.4 Pa or more and 1 Pa or less, and more preferably 0.4 Pa or more and 0.8 Pa or less. Furthermore, the pressure in the second film deposition condition is preferably higher than the pressure in the first and third film deposition conditions. If the pressure is too low, the conductivity of the semiconductor layer 108b may be low. On the other hand, if the pressure is too high, the film deposition rate will be slow, which may reduce productivity. Also, if the pressure is too high, discharge may become difficult. By setting the pressure in the second film deposition condition within the above range, it is possible to obtain a semiconductor layer 108b with high conductivity and increase productivity. Note that the pressure in the second film deposition condition is not limited to the above range.

[0236] It is particularly preferable that the power density under the first and third film deposition conditions is higher than the power density under the second film deposition condition, and that the pressure under the first and third film deposition conditions is lower than the pressure under the second film deposition condition. This makes it possible to increase the conductivity of the semiconductor layer 108b and to make the semiconductor layers 108a and 108c denser and reduce defects.

[0237] Here, a configuration is shown in which the power density and pressure in the first and third film deposition conditions are different from those in the second film deposition condition; however, the present invention is not limited to this. It is also possible to differ other parameters (for example, gas flow rate) between the first and third film deposition conditions and the second film deposition condition.

[0238] Furthermore, the first film deposition conditions and the third film deposition conditions can be the same or different. By making the first and third film deposition conditions the same, that is, by making the film quality of semiconductor layer 108a and semiconductor layer 108c the same, the number of film types that need to be controlled in the manufacturing of semiconductor devices can be reduced. This can increase productivity. Alternatively, the first and third film deposition conditions can be different, that is, by making the film quality of semiconductor layer 108a and semiconductor layer 108c different. Since damage may occur to the semiconductor layer 108c when depositing the insulating layer 106, it is preferable that the third film deposition conditions be denser and less prone to defects compared to the first film deposition conditions. For example, one or both of the power density and pressure in the third film deposition conditions can be different from the power density and pressure in the first film deposition conditions. Specifically, the power density under the third film deposition condition can be made higher than the power density under the first film deposition condition. Furthermore, the pressure under the third film deposition condition can be made lower than the pressure under the first film deposition condition.

[0239] Figure 7 shows an enlarged view of the semiconductor layer 108 and its vicinity, as shown in Figure 6A. In Figure 7, the thickness T108a of semiconductor layer 108a, the thickness T108b of semiconductor layer 108b, and the thickness T108c of semiconductor layer 108c are indicated by solid arrows. Thicknesses T108a, T108b, and T108c are the thicknesses of each layer in the region of semiconductor layer 108 that overlaps with the conductive layer 104 in a cross-sectional view. Note that the thicknesses T108a, T108b, and T108c can be controlled by the processing time (also referred to as deposition time) during the deposition of semiconductor layers 108a, 108b, and 108c, respectively.

[0240] A thickness T108b is preferable. A thickness T108b is preferable to both thickness T108a and thickness T108c. By increasing the thickness T108b of the semiconductor layer 108b, which is the main current path, a transistor with a large on-current can be made. However, if the thickness T108b is too thick, oxygen vacancies (V) in the semiconductor layer 108b may occur. Ｏ ) and V Ｏ An increase in the amount of H can cause a shift in the transistor's threshold voltage, potentially leading to a larger cutoff current. The thickness T108b is preferably 1 nm to 30 nm, more preferably 2 nm to 30 nm, more preferably 2 nm to 20 nm, more preferably 4 nm to 20 nm, and more preferably 4 nm to 10 nm. By setting the thickness T108b within the above range, a transistor with a large on-current can be made. Furthermore, by suppressing the shift in the threshold voltage, the cutoff current can be reduced, and a normally-off transistor can be made. Note that the thickness T108b is not limited to the above range.

[0241] It is preferable that thicknesses T108a and T108c are each thinner than thickness T108b. Furthermore, thicknesses T108a and T108c are preferably 0.5 nm to 10 nm, more preferably 0.5 nm to 6 nm, more preferably 0.5 nm to 4 nm, more preferably 0.5 nm to 3 nm, and more preferably 1 nm to 3 nm. If thickness T108c is too thick, the physical distance between the conductive layer 104, which functions as the first gate electrode, and the semiconductor layer 108b becomes longer, which may result in a decrease in field-effect mobility. On the other hand, if thickness T108c is too thin, the physical distance between the interface and vicinity of the interface between the insulating layer 106 and the semiconductor layer 108, where trap levels can be formed, and the semiconductor layer 108b, which is the main current path, becomes shorter, which may result in a decrease in field-effect mobility. In addition, reliability may decrease. The same applies to thickness T108a. By setting the thicknesses T108a and T108c within the aforementioned ranges, a transistor with high field-effect mobility and high reliability can be obtained. Note that the thicknesses T108a and T108c are not limited to the aforementioned ranges.

[0242] Here, the semiconductor layer 108 is shown as a three-layer stacked structure, but the present invention is not limited to this. The semiconductor layer 108 can be a single layer, a two-layer, or a four-layer or more stacked structure. When the semiconductor layer 108 has a stacked structure, it is preferable that the semiconductor layer 108 has at least one semiconductor layer 108b.

[0243] Figures 8A and 8B show cross-sectional views of a semiconductor device 10G according to one aspect of the present invention. A top view of the semiconductor device 10G can be found in Figure 2A. Figure 8A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 8B is a cross-sectional view of the section along the dashed line B1-B2.

[0244] The semiconductor device 10G has a transistor 100G. Transistor 100G differs from transistor 100F shown in Figure 6A, etc., in that its semiconductor layer 108 has a two-layer structure consisting of semiconductor layer 108a and semiconductor layer 108b. By omitting the semiconductor layer 108c, the manufacturing process can be simplified and productivity can be increased.

[0245] Figures 9A and 9B show cross-sectional views of a semiconductor device 10H according to one aspect of the present invention. A top view of the semiconductor device 10H can be found in Figure 2A. Figure 9A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 9B is a cross-sectional view of the section along the dashed line B1-B2.

[0246] The semiconductor device 10H has a transistor 100H. Transistor 100H differs from transistor 100F shown in Figure 6A, etc., in that its semiconductor layer 108 has a two-layer structure consisting of semiconductor layer 108b and semiconductor layer 108c. By omitting the semiconductor layer 108a, the manufacturing process can be simplified and productivity can be increased.

[0247] As mentioned above, the same material can be used for each layer of the semiconductor layer 108. Alternatively, different materials can be used for one or more of the layers of the semiconductor layer 108.

[0248] An example of a configuration in which one or more layers of the semiconductor layer 108 are made of different materials will be described.

[0249] In the semiconductor layer 108 shown in Figures 8A and 8B, it is preferable that semiconductor layer 108a contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b contains indium and oxygen. It is preferable that the content of element M in semiconductor layer 108a is higher than the content of element M in semiconductor layer 108b. For example, In-M oxide can be suitably used in semiconductor layer 108a and indium oxide in semiconductor layer 108b.

[0250] For element M, please refer to the description above. Gallium can be suitably used as element M, for example. In the following, gallium may be used as an example of element M in the explanation.

[0251] The semiconductor layer 108a preferably contains indium, gallium, and oxygen. The semiconductor layer 108b preferably contains indium and oxygen. The gallium content in the semiconductor layer 108a is preferably higher than the gallium content in the semiconductor layer 108b. For example, indium-gallium oxide can be preferably used for the semiconductor layer 108a, and indium oxide can be preferably used for the semiconductor layer 108b.

[0252] Since the semiconductor layer 108a contains an element M (for example, gallium) having a high binding energy with oxygen, oxygen vacancies (V Ｏ ) and V Ｏ H in the semiconductor layer 108 can be suppressed from increasing. By providing the semiconductor layer 108a with few oxygen vacancies (V Ｏ ) and V Ｏ H on the side of the conductive layer 103 that functions as the back gate electrode, a highly reliable transistor can be obtained.

[0253] When forming a metal oxide film serving as the semiconductor layer 108 on the insulating layer 105, components (for example, hydrogen) contained in the insulating layer 105 may be mixed into the metal oxide film, resulting in oxygen vacancies (V Ｏ [[ID=第十六行]] Ｏ H in the semiconductor layer 108. As a result, if the oxygen vacancies and V Ｏ H in the channel formation region become too many, the threshold voltage of the transistor may shift. In addition, the reliability of the transistor may decrease. Particularly in a transistor with a short channel length, the influence of oxygen vacancies (V Ｏ ) and V Ｏ H in the channel formation region on the electrical characteristics is greater, and it is more likely to become normally-on. Therefore, by using a metal oxide containing the element M for the semiconductor layer 108a provided in contact with the insulating layer 105, oxygen vacancies (V Ｏ ) and V Ｏ ​This suppresses the increase in H. As a result, even transistors with short channel lengths can be made normally off. Furthermore, it suppresses threshold voltage fluctuations caused by drain-induced barrier lowering (DIBL). This allows for the creation of highly reliable transistors.

[0254] Hydrogen contained in semiconductor layer 108a diffuses into semiconductor layer 108b, causing oxygen vacancies and V in the channel formation region of semiconductor layer 108b. Ｏ If the amount of H becomes too high, there is a risk that the threshold voltage of the transistor will shift. Here, the bond energy between gallium and hydrogen is higher than that between indium and hydrogen. Therefore, hydrogen mixed into the metal oxide film that becomes the semiconductor layer 108a can exist stably in the gallium-containing semiconductor layer 108a. As a result, the diffusion of hydrogen from semiconductor layer 108a to semiconductor layer 108b is suppressed, thus preventing oxygen vacancies and V in semiconductor layer 108b. Ｏ This allows for the suppression of the increase in H. As a result, it is possible to create a normally-off transistor and suppress variations in the threshold voltage.

[0255] It is preferable that the content of element M in semiconductor layer 108b is lower than the content of element M in semiconductor layer 108a. In other words, it is preferable that the indium content in semiconductor layer 108b is higher than the indium content in semiconductor layer 108a. By increasing the indium content in semiconductor layer 108b, which is the main current path, a transistor with high field-effect mobility can be made.

[0256] When using sputtering to deposit a first metal oxide film that will become semiconductor layer 108a and a second metal oxide film that will become semiconductor layer 108b, it is preferable to use different sputtering targets and deposit the metal oxide films continuously in a vacuum within the same apparatus without exposing the surface of the metal oxide films to the atmosphere. For example, it is preferable to deposit each metal oxide film in different processing chambers continuously in a vacuum within the same apparatus. For example, a sputtering target having indium, element M, and oxygen can be used to deposit the first metal oxide film. For example, an In-M oxide sputtering target can be used as the sputtering target. A sputtering target having indium and oxygen can be used to deposit the second metal oxide film. For example, an indium oxide sputtering target can be used as the sputtering target.

[0257] Alternatively, the first and second metal oxide films can be deposited using the same sputtering target, and element M (e.g., gallium) can be supplied to the first metal oxide film. For supplying element M, for example, ion implantation can be used. For details on ion implantation, please refer to the above description. For example, a sputtering target containing indium can be used for depositing the first metal oxide film and the second metal oxide film. As such a sputtering target, for example, an indium oxide sputtering target can be used. Since the first and second metal oxide films can be deposited continuously in the same processing chamber using the same sputtering target, the productivity of semiconductor devices can be increased. It is preferable to set the acceleration energy for supplying element M so that the concentration of element M is highest in the semiconductor layer 108a, or at or near the interface between the insulating layer 105 and the semiconductor layer 108a. Note that by supplying element M after depositing the first and second metal oxide films, the semiconductor layer 108b may also contain element M. In this case as well, it is preferable that the content of element M in semiconductor layer 108b is lower than the content of element M in semiconductor layer 108a. Alternatively, element M can be supplied after the first metal oxide film is formed, and then the second metal oxide film can be formed. Note that the supply of element M is not limited to ion implantation. For information on the supply of element M, please refer to the description of the supply of impurities mentioned above.

[0258] In the semiconductor layer 108 shown in Figures 9A and 9B, it is preferable that semiconductor layer 108c contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b contains indium and oxygen. It is preferable that the content of element M in semiconductor layer 108c is higher than the content of element M in semiconductor layer 108b. For example, In-M oxide can be suitably used in semiconductor layer 108c and indium oxide in semiconductor layer 108b.

[0259] For example, the semiconductor layer 108c preferably contains indium, gallium, and oxygen. The semiconductor layer 108b preferably contains indium and oxygen. It is preferable that the gallium content in the semiconductor layer 108c is higher than the gallium content in the semiconductor layer 108b. For example, In-Ga oxide can be suitably used for the semiconductor layer 108c and indium oxide for the semiconductor layer 108b.

[0260] Because the semiconductor layer 108c has an element M with a high bonding energy with oxygen, oxygen vacancies (V) are formed in the semiconductor layer 108. Ｏ ) and V Ｏ The increase in H can be suppressed. On the conductive layer 104 side which functions as the gate electrode, an oxygen deficiency (V Ｏ ) and V Ｏ By providing a semiconductor layer 108c with a low H content, a highly reliable transistor can be made.

[0261] When forming an insulating layer 106 on a semiconductor layer 108, damage may occur to the semiconductor layer 108, or components contained in the deposition gas for the insulating layer 106 (e.g., hydrogen) may be mixed into the semiconductor layer 108, resulting in oxygen vacancies (V) in the semiconductor layer 108. Ｏ ) and V Ｏ H can occur. This may cause the threshold voltage of the transistor to shift. Also, the reliability of the transistor may decrease. Therefore, by using a metal oxide containing element M in the semiconductor layer 108c that has a region in contact with the insulating layer 106, oxygen vacancies (V) can be created in the semiconductor layer 108. Ｏ ) and V Ｏ This suppresses the increase in H. As a result, even transistors with short channel lengths can be made normally off. Furthermore, variations in threshold voltage due to drain-induced barrier lowering (DIBL) can be suppressed. This allows for the creation of highly reliable transistors.

[0262] Hydrogen contained in semiconductor layer 108c diffuses into semiconductor layer 108b, causing oxygen vacancies and V in the channel formation region of semiconductor layer 108b.Ｏ If the amount of H becomes too high, there is a risk that the threshold voltage of the transistor will shift. However, hydrogen mixed into semiconductor layer 108c can exist stably in semiconductor layer 108c containing gallium. As a result, the diffusion of hydrogen from semiconductor layer 108c to semiconductor layer 108b is suppressed, thus preventing oxygen deficiencies and V in semiconductor layer 108b. Ｏ This allows for the suppression of the increase in H. As a result, it is possible to create a normally-off transistor and suppress variations in the threshold voltage.

[0263] It is preferable that the content of element M in semiconductor layer 108b is lower than the content of element M in semiconductor layer 108c. In other words, it is preferable that the indium content in semiconductor layer 108b is higher than the indium content in semiconductor layer 108c. By increasing the indium content in semiconductor layer 108b, which is the main current path, a transistor with high field-effect mobility can be made.

[0264] In the semiconductor layer 108 shown in Figures 9A and 9B, one of the semiconductor layer 108a and semiconductor layer 108c can be made of a different material than semiconductor layer 108b, while the other of semiconductor layer 108a and semiconductor layer 108c can be made of the same material as semiconductor layer 108b.

[0265] A different material can be used for semiconductor layer 108a than for semiconductor layer 108b, and the same material can be used for semiconductor layer 108c. For example, it is preferable that semiconductor layer 108a contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108c each contain indium and oxygen. It is preferable that the content of element M in semiconductor layer 108a is higher than the content of element M in semiconductor layer 108b and semiconductor layer 108c. For example, In-M oxide can be suitably used for semiconductor layer 108a, and indium oxide can be suitably used for semiconductor layer 108b and semiconductor layer 108c.

[0266] For example, it is preferable that semiconductor layer 108a contains indium, gallium, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108c each contain indium and oxygen. It is preferable that the gallium content in semiconductor layer 108a is higher than the gallium content in semiconductor layer 108b and semiconductor layer 108c. For example, In-Ga oxide can be suitably used in semiconductor layer 108a, and indium oxide can be suitably used in semiconductor layer 108b and semiconductor layer 108c, respectively.

[0267] When the same material (for example, indium oxide) is used for semiconductor layer 108b and semiconductor layer 108c, it is preferable that semiconductor layer 108b has a region with a higher concentration of the second element compared to semiconductor layer 108c in the channel formation region. Typically, it is preferable that semiconductor layer 108b has a region with a higher hydrogen concentration compared to semiconductor layer 108c. For semiconductor layer 108b and semiconductor layer 108c, please refer to the above description.

[0268] Alternatively, in the semiconductor layer 108 shown in Figures 9A and 9B, a different material may be used for semiconductor layer 108c than for semiconductor layer 108b, and the same material as semiconductor layer 108b may be used for semiconductor layer 108a. For example, it is preferable that semiconductor layer 108c contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108a each contain indium and oxygen. It is preferable that the content of element M in semiconductor layer 108c is higher than the content of element M in semiconductor layer 108b and semiconductor layer 108a. For example, In-M oxide can be suitably used for semiconductor layer 108c, and indium oxide can be suitably used for semiconductor layer 108b and semiconductor layer 108a, respectively.

[0269] For example, it is preferable that semiconductor layer 108c contains indium, gallium, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108a each contain indium and oxygen. It is preferable that the gallium content in semiconductor layer 108c is higher than the gallium content in semiconductor layer 108b and semiconductor layer 108a. For example, In-Ga oxide can be suitably used in semiconductor layer 108c, and indium oxide can be suitably used in semiconductor layer 108b and semiconductor layer 108a, respectively.

[0270] When the same material (for example, indium oxide) is used for semiconductor layer 108b and semiconductor layer 108a, it is preferable that semiconductor layer 108b has a region with a higher concentration of the second element compared to semiconductor layer 108a in the channel formation region. Typically, it is preferable that semiconductor layer 108b has a region with a higher hydrogen concentration compared to semiconductor layer 108a. For semiconductor layer 108a and semiconductor layer 108b, please refer to the above description.

[0271] Alternatively, in the semiconductor layer 108 shown in Figures 9A and 9B, different materials can be used for both semiconductor layer 108a and semiconductor layer 108c compared to semiconductor layer 108b. Furthermore, semiconductor layer 108a can be made of the same material as semiconductor layer 108c or a different material.

[0272] For example, it is preferable that semiconductor layer 108a and semiconductor layer 108c each contain indium, element M, and oxygen. It is preferable that semiconductor layer 108b contains indium and oxygen. It is preferable that the content of element M in semiconductor layer 108a and semiconductor layer 108c is higher than the content of element M in semiconductor layer 108b. For example, In-M oxide can be suitably used in semiconductor layer 108a and semiconductor layer 108c, and indium oxide can be suitably used in semiconductor layer 108b.

[0273] For example, it is preferable that semiconductor layer 108a and semiconductor layer 108c each contain indium, gallium, and oxygen. It is preferable that semiconductor layer 108b contains indium and oxygen. It is preferable that the gallium content in semiconductor layer 108a and semiconductor layer 108c is higher than the gallium content in semiconductor layer 108b. For example, In-Ga oxide can be suitably used for semiconductor layer 108a and semiconductor layer 108c, and indium oxide can be suitably used for semiconductor layer 108b.

[0274] <Configuration Example 2> [Configuration Example 2-1] A top view of the semiconductor device 20 is shown in Figure 10A. A cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 10A is shown in Figure 10B, and a cross-sectional view of the cross-section along the dashed-dotted line B1-B2 is shown in Figure 10C. Perspective views of the semiconductor device 20 are shown in Figures 11A to 11D. Figure 11B shows the cross-section along the dashed-dotted line C1-C2 shown in Figure 11A. In Figure 11C, the insulating layer shown in Figure 11A is made transparent, and the outline is shown with a dashed line. Similarly, in Figure 11D, the insulating layer shown in Figure 11B is made transparent, and the outline is shown with a dashed line.

[0275] The semiconductor device 20 includes a transistor 200 and an insulating layer 110. Figure 10B and others show a configuration in which the semiconductor device 20 is provided on a substrate 102 having an insulating surface. Alternatively, an insulating film can be provided on the substrate 102, and the semiconductor device 20 can be provided on the insulating film.

[0276] The transistor 200 includes a conductive layer 204, an insulating layer 206, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 206 functions as a gate insulating layer. The conductive layer 212a functions as one of the source electrode and the drain electrode, and the conductive layer 212b functions as the other. Of the semiconductor layer 208, the region between the source electrode and the drain electrode that overlaps with the gate electrode via the gate insulating layer functions as a channel-forming region. Furthermore, of the semiconductor layer 208, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region. In the semiconductor layer 208, the channel-forming region is located between the source region and the drain region.

[0277] A conductive layer 212a is provided on the substrate 102, an insulating layer 110 is provided on the conductive layer 212a, and a conductive layer 212b is provided on the insulating layer 110. The insulating layer 110 has a region that is in contact with and sandwiched between the conductive layers 212a and 212b. The conductive layer 212a has a region that overlaps with the conductive layer 212b via the insulating layer 110. The insulating layer 110 has an opening 141 that reaches the conductive layer 212a. It can also be said that the conductive layer 212a is exposed at the opening 141. The conductive layer 212b has an opening 143 in the region that overlaps with the conductive layer 212a. The opening 143 is provided in the region that overlaps with the opening 141. Note that in Figure 10A, etc., the opening 141 of the insulating layer 110 and the opening 143 of the conductive layer 212b are given different reference numerals, but these openings can be collectively referred to as a single opening. In other words, the insulating layer 110 and the conductive layer 212b have openings that reach the conductive layer 212a.

[0278] The semiconductor layer 208 is provided so as to cover the openings 141 and 143. The semiconductor layer 208 has a region in contact with the upper surface of the conductive layer 212a and the side surface of the insulating layer 110 at the opening 141, and a region in contact with the side surface of the conductive layer 212b at the opening 143. Furthermore, it is preferable that the semiconductor layer 208 has a region in contact with the upper surface of the conductive layer 212b. The semiconductor layer 208 has a shape that conforms to the shape of the upper and side surfaces of the conductive layer 212b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 212a.

[0279] The semiconductor layer 208 can be made from any of the materials listed for semiconductor layer 108. For details regarding semiconductor layer 208, please refer to the description for semiconductor layer 108. For example, indium oxide can be suitably used for semiconductor layer 208.

[0280] The insulating layer 206, which functions as a gate insulating layer for transistor 200, is provided so as to cover openings 141 and 143. The insulating layer 206 is provided on semiconductor layer 208, conductive layer 212b, and insulating layer 110. The insulating layer 206 has regions that are in contact with the upper and side surfaces of semiconductor layer 208, the upper and side surfaces of conductive layer 212b, and the upper surface of insulating layer 110. The insulating layer 206 has a shape that conforms to the shape of the upper surface of insulating layer 110, the upper and side surfaces of conductive layer 212b, the upper and side surfaces of semiconductor layer 208, and the upper surface of conductive layer 212a.

[0281] The insulating layer 206 can be made from the materials listed for insulating layer 106. For details regarding insulating layer 206, please refer to the description for insulating layer 106.

[0282] The conductive layer 204, which functions as the gate electrode of the transistor 200, is provided on the insulating layer 206 and has a region in contact with the upper surface of the insulating layer 206. The conductive layer 204 has a region facing the semiconductor layer 208 via the insulating layer 206. The conductive layer 204 has a shape that conforms to the shape of the upper surface of the insulating layer 206.

[0283] The conductive layer 204 can be made from the materials listed for conductive layer 104. For details on conductive layer 204, please refer to the description for conductive layer 104.

[0284] The conductive layers 212a and 212b can be made from the materials listed for conductive layers 112a, 112b, and 104. For conductive layers 212a and 212b, refer to the descriptions for conductive layers 112a, 112b, and 104.

[0285] Each conductive layer 212a and conductive layer 212b has a region in contact with the semiconductor layer 208. When an oxide semiconductor is used for the semiconductor layer 208, if an easily oxidized metal (e.g., aluminum) is used for the conductive layer 212a or conductive layer 212b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 212a or conductive layer 212b and the semiconductor layer 208, potentially hindering conductivity. Therefore, it is preferable to use conductive materials that are not easily oxidized, or conductive materials that maintain low electrical resistance even when oxidized, for the conductive layers 212a and conductive layer 212b. Oxide conductors can be suitably used for each of the conductive layers 212a and conductive layer 212b. Alternatively, nitride conductors can be used for each of the conductive layers 212a and conductive layer 212b. Refer to the above description for information on oxide conductors and nitride conductors.

[0286] The conductive layer 212a and the conductive layer 212b can each be, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain low electrical resistance even when oxidized.

[0287] When the conductive layer 212a or conductive layer 212b has a laminated structure, it is preferable to use a conductive material that is resistant to oxidation, or a conductive material that maintains low electrical resistance even when oxidized, in at least the layer in contact with the semiconductor layer 208.

[0288] Since the conductive layers 212a and 212b are formed before the semiconductor layer 208, it is preferable to use materials that can withstand the heat treatment involved in the formation of the semiconductor layer 208. ITO or ITSO can preferably be used for the conductive layers 212a and 212b, respectively.

[0289] As the insulating layer 110, either an inorganic insulating layer or an organic insulating layer, or both, can be used. For materials that can be used for the organic insulating layer, please refer to the above description. It is preferable that the insulating layer 110 has one or more inorganic insulating layers. For the inorganic insulating layer, the materials listed for insulating layer 106 and insulating layer 105 can be used.

[0290] The insulating layer 110 has a region that is in contact with the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 208, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with the semiconductor layer 208 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 208 and the insulating layer 110. Specifically, it is preferable that the region of the insulating layer 110 that is in contact with the channel-forming region of the semiconductor layer 208 contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 110 that is in contact with the channel-forming region of the semiconductor layer 208.

[0291] When a metal oxide is used for the semiconductor layer 208, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with the semiconductor layer 208 releases oxygen when heat is applied. This supplies oxygen from the insulating layer 110 to the semiconductor layer 208, and reduces oxygen deficiencies (V) in the semiconductor layer 208. Ｏ ), and V Ｏ H can be reduced.

[0292] Figure 13B shows an enlarged view of the transistor 200 and its vicinity, as shown in Figure 10C. The thickness T208 in the channel formation region of the semiconductor layer 208 is preferably within the range of the thickness T108 of the semiconductor layer 108. This allows for a transistor with good electrical characteristics. The thickness T208 can be the shortest distance between the side surface of the insulating layer 110 and the side surface of the semiconductor layer 208 in a cross-sectional view. Specifically, it can be the thickness of the semiconductor layer 208 at the midpoint between the height of the upper surface and the height of the lower surface of the insulating layer 110. In Figure 13B, the thickness T208 is indicated by a solid arrow. Note that the thickness T208 is not limited to the range described above.

[0293] In transistor 200, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, which is the surface to be formed, and the drain current flows perpendicular to, or approximately perpendicular to, the surface of the substrate 102. In transistor 200, it can also be said that the drain current flows in the vertical direction. Therefore, a transistor according to one aspect of the present invention can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor. Furthermore, the conductive layer 212a can be called the lower electrode of the transistor, and the conductive layer 212b can be called the upper electrode. Since the source electrode, semiconductor layer, and drain electrode of a VFET can be stacked, the occupied area can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar manner.

[0294] The channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 212a and the conductive layer 212b. Therefore, transistors with a channel length shorter than the minimum exposure dimension of the exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, the variation in characteristics between multiple transistors 200 is reduced. As a result, the operation of the semiconductor device 20 becomes more stable and its reliability is improved. In addition, when the variation in transistor characteristics is reduced, the degree of freedom in circuit design increases, and the operating voltage of the semiconductor device can be lowered. As a result, the power consumption of the semiconductor device can be reduced.

[0295] By using a metal oxide with a high indium content (e.g., indium oxide) in the semiconductor layer 208 of a transistor 200 with a short channel length, the on-current can be further increased. Therefore, a semiconductor device that operates at high speed can be created. Furthermore, since a large on-current can be obtained even with a small channel width, the area occupied by the transistor can be further reduced. Therefore, the area occupied by the semiconductor device can be further reduced.

[0296] The conductive layers 212a, 212b, and 204 can each function as wiring, and the transistor 200 can be placed in the region where these wirings overlap. In other words, in a circuit having the transistor 200 and wiring, the area occupied by the transistor 200 and wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, resulting in a compact semiconductor device. Furthermore, when the semiconductor device is applied to the pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when the semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the area occupied by the drive circuit can be reduced, resulting in a narrow-bezel display device.

[0297] Although Figure 10B and other figures show an example in which the semiconductor layer 208, insulating layer 206, and conductive layer 204 cover the openings 141 and 143, the present invention is not limited to this. A step can be formed by the insulating layer 110 and conductive layer 212b and the conductive layer 212a, and the semiconductor layer 208, insulating layer 206, and conductive layer 204 can be provided along this step.

[0298] [Insulating layer 110] The insulating layer 110 preferably has a laminated structure. Figure 10A and the like show an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, insulating layer 110b, and insulating layer 110c can each be made from the materials listed for insulating layer 110.

[0299] The region of the semiconductor layer 208 that is in contact with the insulating layer 110b functions as a channel-forming region. The insulating layer 110b preferably contains oxygen, and it is preferable to use one or more of the aforementioned oxides and oxiditrides. Specifically, silicon oxide and silicon oxiditride, or both, can be suitably used for the insulating layer 110b.

[0300] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 110b. The heat applied during the manufacturing process of the semiconductor device 20 causes the insulating layer 110b to release oxygen, thereby supplying oxygen to the semiconductor layer 208. By supplying oxygen from the insulating layer 110b to the semiconductor layer 208, particularly to the channel formation region, oxygen deficiencies (V) can be reduced. Ｏ ) is repaired, and oxygen deficiency (V Ｏ This can reduce the V in the channel formation region. Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0301] For example, oxygen can be supplied to the insulating layer 110b by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the upper surface of the insulating layer 110b by forming a film in an oxygen-containing atmosphere using a sputtering method. After that, the film can be removed.

[0302] For forming the insulating layer 110b, it is preferable to use sputtering or PECVD. In particular, it is preferable to use a gas containing hydrogen (for example, H) as the deposition gas. ２ and NH ３ By forming the film using a method that does not involve the use of ), a film with an extremely low hydrogen content can be obtained. For forming the insulating layer 110b, sputtering is particularly preferable. This suppresses the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 200.

[0303] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 212a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 212b. It is preferable that the insulating layer 110a and the insulating layer 110c each release small amounts of impurities (e.g., water and hydrogen). Furthermore, it is preferable that the insulating layer 110a and the insulating layer 110c each impede substances (e.g., atoms, molecules and ions) to be impermeable. It can also be said that the insulating layer 110a and the insulating layer 110c function as barrier films. Specifically, it is preferable that the insulating layer 110a and the insulating layer 110c each impede substances to be impermeable to. This suppresses the diffusion of impurities contained in the insulating layer 110a and the insulating layer 110c into the channel formation region. Therefore, it is possible to produce a transistor that exhibits good electrical characteristics and is highly reliable.

[0304] It is preferable that insulating layer 110a and insulating layer 110c each use materials that are impermeable to oxygen. This suppresses the diffusion of oxygen contained in insulating layer 110b to the conductive layer 212a side via insulating layer 110a. Similarly, it suppresses the diffusion of oxygen contained in insulating layer 110b to the conductive layer 212b side via insulating layer 110c. This increases the amount of oxygen supplied from insulating layer 110b to the channel formation region of semiconductor layer 208, thereby reducing oxygen deficiencies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. In addition, oxidation of the conductive layer 212a by oxygen contained in the insulating layer 110b and an increase in the electrical resistance of the conductive layer 212a can be suppressed. Similarly, oxidation of the conductive layer 212b by oxygen contained in the insulating layer 110b and an increase in the electrical resistance of the conductive layer 212b can be suppressed. Therefore, a transistor with a large on-current can be obtained.

[0305] For materials that can be used for the barrier film, please refer to the above description. For insulating layer 110a and insulating layer 110c, one or more of the following can be suitably used, for example: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. Note that insulating layer 110a and insulating layer 110c can be made of the same material, or different materials can be used for insulating layer 110a and insulating layer 110c.

[0306] By using an oxide or oxiditride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b (or the insulating film that becomes the insulating layer 110b) when the insulating layer 110c (or the insulating film that becomes the insulating layer 110c) is formed.

[0307] One or more of the insulating layers 110a, 110b, and 110c can be arranged in a laminated structure.

[0308] When the insulating layer 110c has a laminated structure, each layer constituting the insulating layer 110c can use the materials listed for insulating layer 110c. Oxides or oxiditrides can preferably be used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using oxides or oxiditrides for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that becomes the insulating layer 110b) when the layer (or the film that becomes the layer) is formed, which is preferable. The insulating layer 110c can have a laminated structure of, for example, a first film having an oxide or oxiditride and a second film having a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0309] Figures 12A and 12B show cross-sectional views of a semiconductor device 20A, which is one embodiment of the present invention. A top view of the semiconductor device 20A can be found in Figure 10A. Figure 12A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 10A, and Figure 12B is a cross-sectional view of the section along the dashed line A1-A2.

[0310] The semiconductor device 20A includes a transistor 200 and an insulating layer 110. The semiconductor device 20A mainly differs from the semiconductor device 20 shown in Figure 10B, etc., in that the insulating layer 110 has insulating layers 110d and 110e.

[0311] The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c.

[0312] The insulating layer 110d is provided between the conductive layer 212a and the insulating layer 110a. The insulating layer 110d is provided so as to cover the conductive layer 212a. The insulating layer 110d has regions that are in contact with the upper and side surfaces of the conductive layer 212a, the upper surface of the substrate 102, and the side surfaces of the semiconductor layer 208.

[0313] The insulating layer 110e is provided between the conductive layer 212b and the insulating layer 110c. The insulating layer 110e has regions that are in contact with the upper surface of the insulating layer 110c, the lower surface of the conductive layer 212a, and the side surface of the semiconductor layer 208.

[0314] It is more preferable that insulating layers 110d and 110e each use materials that release impurities (e.g., water and hydrogen) that lower the electrical resistance of the semiconductor layer 208. Impurities are released from insulating layer 110d and diffuse into the region of the semiconductor layer 208 that is in contact with insulating layer 110d. As a result, the region of the semiconductor layer 208 that is in contact with insulating layer 110d contains impurities, and this region can be made a low-resistance region. The semiconductor layer 208 can be configured to have a low-resistance region between the region in contact with the conductive layer 212a (either the source region or the drain region) and the channel-forming region. Similarly, by using an impurity-releasing material for insulating layer 110e, impurities are released from insulating layer 110e and diffuse into the region of the semiconductor layer 208 that is in contact with insulating layer 110e. The region of the semiconductor layer 208 that is in contact with insulating layer 110e contains impurities, and this region can be made a low-resistance region. The semiconductor layer 208 may have a low-resistance region between the region in contact with the conductive layer 212b (the other of the source region and the drain region) and the channel-forming region. The low-resistance region can function as a buffer region to mitigate the drain electric field. These low-resistance regions may also function as the source region or the drain region.

[0315] By providing a low-resistance region between the drain region and the channel-forming region, a high electric field is less likely to occur near the drain region, suppressing the generation of hot carriers and thus suppressing transistor degradation. For example, when the conductive layer 212a functions as the drain electrode and the conductive layer 212b functions as the source electrode, by making the region of the semiconductor layer 208 in contact with the insulating layer 110d a low-resistance region, a high electric field is less likely to occur near the drain region, suppressing the generation of hot carriers and thus suppressing transistor degradation. When the conductive layer 212a functions as the source electrode and the conductive layer 212b functions as the drain electrode, by making the region of the semiconductor layer 208 in contact with the insulating layer 110e a low-resistance region, a high electric field is less likely to occur near the drain region, suppressing the generation of hot carriers and thus suppressing transistor degradation.

[0316] When the region of the semiconductor layer 208 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region of the semiconductor layer 208 to the gate electrode and the distance from the drain region to the gate electrode can be made more uniform. This makes the electric field of the gate electrode acting on the channel formation region more uniform.

[0317] When a metal oxide is used for the semiconductor layer 208, it is more preferable that the impurities released by the insulating layer 110d and insulating layer 110e include hydrogen. Hydrogen reacts with oxygen bonded to the metal atoms of the metal oxide to form water, creating an oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen deficiency (V Ｏ A defect (V) into which hydrogen has entered Ｏ H) functions as a donor, generating electrons, which are carriers. This increases the carrier concentration in the region of the semiconductor layer 208 that is in contact with the insulating layer 110d and the region that is in contact with the insulating layer 110e, thereby lowering the electrical resistance.

[0318] It is preferable that the insulating layer 110d has a region with a higher hydrogen content than the insulating layer 110a. For example, secondary ion mass spectrometry (SIMS) can be used to analyze the hydrogen content of the insulating layer 110.

[0319] The amount of hydrogen released can be adjusted by using different film deposition conditions for insulating layer 110d and insulating layer 110a. Specifically, it is preferable to use different film deposition power (film deposition power density), film deposition pressure, film deposition gas type, film deposition gas flow rate ratio, film deposition temperature, and the distance between the substrate and the electrode for insulating layer 110d and insulating layer 110a. For example, by making the film deposition power density of insulating layer 110d lower than that of insulating layer 110a, the hydrogen content in insulating layer 110d can be increased compared to that of insulating layer 110a. This increases the amount of hydrogen released from insulating layer 110d due to the heat applied to it.

[0320] It is preferable that the hydrogen content in the film-forming gas used for forming the insulating layer 110d is greater than the hydrogen content in the film-forming gas used for forming the insulating layer 110a. Specifically, when forming silicon nitride or silicon oxide nitride films as insulating layers 110d and 110a using the PECVD method, it is preferable that the ratio of the flow rate of ammonia gas to the total film-forming gas used for forming the insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is higher than the ammonia flow rate ratio of the film-forming gas used for forming the insulating layer 110a. By forming the insulating layer 110d under conditions of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 110d can be increased. In addition, the amount of hydrogen released from the insulating layer 110d due to the heat applied to it can be increased.

[0321] It is more preferable that the film density of the insulating layer 110a is higher than that of the insulating layer 110d. This suppresses the diffusion of hydrogen contained in the insulating layer 110d into the channel-forming region of the semiconductor layer 208 via the insulating layers 110a and 110b. For evaluation of film density, please refer to the above description.

[0322] The insulating layer 110e preferably has a region with a higher hydrogen content than the insulating layer 110c. More preferably, the film density of the insulating layer 110c is higher than that of the insulating layer 110e. For details on the insulating layers 110c and 110e, refer to the descriptions relating to the insulating layers 110a and 110d.

[0323] Here, the insulating layer 110 is shown as a laminated structure of three or five layers, but the present invention is not limited to these. Preferably, the insulating layer 110 has at least insulating layer 110b. It is also possible to have a configuration that does not have one or more insulating layers 110d, 110a, 110c, and 110e. The insulating layer 110 can be a laminated structure of two, four, or six or more layers. Alternatively, the insulating layer 110 can be a single layer structure.

[0324] [Opening 141, Opening 143] There are no limitations on the upper surface shape of opening 141 and opening 143. They can be, for example, circular, elliptical, triangular, quadrilateral (including rectangle, rhombus, and square), pentagonal, or other polygonal shapes, or polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles of 180 degrees or less). As shown in Figure 10A, it is preferable that the upper surface shapes of opening 141 and opening 143 are circular. By making the upper surface shape of the opening circular, the processing accuracy when forming the opening can be improved, and openings of a fine size can be formed. In this specification, circular is not limited to a perfect circle.

[0325] In this specification, the upper shape of the opening 141 refers to the shape of the upper end of the insulating layer 110 on the opening 141 side. The upper shape of the opening 143 refers to the shape of the lower end of the conductive layer 212b on the opening 143 side.

[0326] As shown in Figure 10A, etc., the upper surface shape of opening 141 and the upper surface shape of opening 143 can be made to coincide or approximately coincide with each other. In this case, as shown in Figures 10B and 10C, etc., it is preferable that the lower end of the conductive layer 212b on the opening 143 side coincides or approximately coincides with the upper end of the insulating layer 110 on the opening 141 side. The lower surface of the conductive layer 212b refers to the surface on the insulating layer 110 side. The upper surface of the insulating layer 110 refers to the surface on the conductive layer 212b side. Note that the upper surface shapes of opening 141 and the upper surface shape of opening 143 can also be configured not to coincide with each other. Note that when the upper surface shapes of opening 141 and opening 143 are circular, opening 141 and opening 143 can be made concentric. Alternatively, opening 141 and opening 143 can be configured not to be concentric.

[0327] The channel length and channel width of transistor 200 will be explained using Figures 13A and 13B. Here, the region of the semiconductor layer 208 that is in contact with the insulating layer 110b will be described as the channel formation region. Figure 13A is a top view of the semiconductor device 20.

[0328] In Figure 13B, the channel length L of transistor 200 is indicated by a dashed double arrow. The channel length L of transistor 200 corresponds to the length of the side surface of the insulating layer 110b on the side of the opening 141 in a cross-sectional view. In other words, the channel length L is determined by the thickness T110 of the insulating layer 110b and the angle θ110 between the side surface of the insulating layer 110b on the side of the opening 141 and the surface of the insulating layer 110b to be formed (in this case, the upper surface of the insulating layer 110a). Therefore, the channel length L can be set to a value smaller than the minimum exposure dimension of the exposure apparatus, enabling the realization of minute transistors. Specifically, it is possible to realize transistors with extremely short channel lengths that could not be realized with conventional exposure apparatuses for mass production of flat panel displays (for example, with a minimum dimension of about 2 μm or 1.5 μm). Furthermore, it is possible to realize transistors with channel lengths of less than 10 nm without using extremely expensive exposure apparatuses used in state-of-the-art LSI technology.

[0329] The channel length L can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L can also be 10 nm or more and 1 μm or less.

[0330] By shortening the channel length L, the on-current of transistor 200 can be increased. Using transistor 200, a circuit capable of high-speed operation can be fabricated. Furthermore, the circuit's occupied area can be reduced. Therefore, a compact semiconductor device can be made. For example, when a semiconductor device according to one aspect of the present invention is applied to a large display device or a high-resolution display device, even when the number of wires increases, the signal delay in each wire can be reduced, and display unevenness can be suppressed. Also, because the circuit's occupied area can be reduced, the bezel of the display device can be narrowed.

[0331] The channel length L can be controlled by adjusting the thickness T110 and angle θ110 of the insulating layer 110b.

[0332] The thickness T110 of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. In FIG. 13B, the thickness T110 is indicated by double arrows of a solid line. The thickness T110 can be the shortest distance between the formation surface of the insulating layer 110b (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view.

[0333] In addition, when the angle θ110 is 90 degrees or less, the smaller the angle θ110, the longer the channel length L can be, and the larger the angle θ110, the shorter the channel length L can be. [[ID=A]]

[0334] In FIG. 13B and the like, the angle θ110 is shown to be less than 90 degrees, but one aspect of the present invention is not limited to this. The angle θ110 can be 90 degrees or approximately 90 degrees. Thereby, the channel length L of the transistor 200 can be shortened.

[0335] In FIG. 10B and the like, in a cross-sectional view, a configuration is shown in which the shape of the side surface on the opening 141 side of the insulating layer 110 is a straight line, but one aspect of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface on the opening 141 side of the insulating layer 110 can be a curve. Or, it can also be set as the structure which has both the area | region where the shape of a side surface is a straight line and the area | region which is a curve.

[0336] Here, it is preferable that the conductive layer 212b is not provided inside the opening 141. Specifically, it is preferable that the conductive layer 212b does not have a region in contact with the side surface on the opening 141 side of the insulating layer 110. When the conductive layer 212b is also provided inside the opening 141, the channel length L of the transistor 200 may become shorter than the length of the side surface of the insulating layer 110b, and it may become difficult to control the channel length L. Therefore, it is preferable that the upper surface shape of the opening 143 coincides with the upper surface shape of the opening 141, or that the opening 143 includes the opening 141 in a top view (also referred to as a plan view).

[0337] In Figures 13A and 13B, the width D141 of the opening 141 is indicated by a double-headed arrow. Figure 13A shows an example where the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W of the transistor 200 is the circumference of the circle. That is, the channel width W is π × D141. Thus, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W can be realized compared to other shapes.

[0338] The width D141 of the opening 141 may vary in the depth direction. As the width D141 of the opening 141, for example, the average value of three points in a cross-sectional view of the insulating layer 110b (or insulating layer 110): the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these points. Alternatively, as the diameter of the opening 141, for example, the diameter at the highest point, the diameter at the lowest point, or the diameter at the midpoint between these points in a cross-sectional view of the insulating layer 110b (or insulating layer 110) may be used.

[0339] When forming the aperture 141 using lithography, the width D141 of the aperture 141 is greater than or equal to the minimum exposure dimension of the exposure apparatus. The width D141 can be, for example, 20 nm or more, 50 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more, and less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0340] In this explanation, we have used as an example a configuration in which the region of the semiconductor layer 208 in contact with the insulating layer 110b functions as a channel-forming region, but the present invention is not limited to this. The region of the semiconductor layer 208 in contact with the insulating layer 110a may also function as a channel-forming region. Similarly, the region in contact with the insulating layer 110c may also function as a channel-forming region.

[0341] [Configuration Example 2-2] Figures 14A and 14B show cross-sectional views of a semiconductor device 20B, which is one embodiment of the present invention. A top view of the semiconductor device 20B can be seen in Figure 10A. Figure 14A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 10A, and Figure 14B is a cross-sectional view of the section along the dashed line B1-B2 shown in Figure 10A.

[0342] The semiconductor device 20B includes a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 20B mainly differs from the semiconductor device 20 shown in Figure 10B, etc., in that it has an insulating layer 109.

[0343] The insulating layer 109 is located between the substrate 102 and the conductive layer 212a. The insulating layer 109 is provided on the substrate 102, the conductive layer 212a is provided on the insulating layer 109, and the insulating layer 110 is provided on the conductive layer 212a. The insulating layer 109 has regions that are in contact with the lower surface of the conductive layer 212a and the lower surface of the insulating layer 110. The conductive layer 212a has regions that are in contact with and sandwiched between the insulating layer 109 and the insulating layer 110. The insulating layer 110 has regions that are in contact with the upper and side surfaces of the conductive layer 212a, the upper surface of the insulating layer 109, the side surfaces of the semiconductor layer 208, the lower surface of the conductive layer 212b, and the lower surface of the insulating layer 206.

[0344] The insulating layer 109 preferably has barrier properties. It is preferable to use a material for the insulating layer 109 that does not easily allow impurities (e.g., water and hydrogen) contained in the substrate 102 to diffuse. This suppresses the diffusion of impurities from the substrate 102 to the transistor 200.

[0345] For the insulating layer 109, refer to the description relating to the barrier film. The insulating layer 109 can be, for example, one or more of the following: an oxide having one or both aluminum and hafnium, an oxide having magnesium, an oxide having gallium, an aluminum nitride, an aluminum nitride, an aluminum nitride, and an oxide silicon nitride. Specifically, the insulating layer 109 can preferably be, for example, one or more of the following: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0346] The insulating layer 109 is preferably made of a material that releases impurities (e.g., water and hydrogen) that lower the electrical resistance of the semiconductor layer 208. The insulating layer 109 can be made of the same material that can be used for the insulating layer 110d and the insulating layer 110e. The insulating layer 109 can preferably be made of, for example, silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

[0347] Impurities released from the insulating layer 109 diffuse into the region of the conductive layer 212a that is in contact with the insulating layer 109. Furthermore, impurities diffused into the conductive layer 212a diffuse into the region of the semiconductor layer 208 that is in contact with the conductive layer 212a. This allows for a reduction in the electrical resistance of one of the regions of the semiconductor layer 208 that is in contact with the conductive layer 212a, i.e., the source region and the drain region. Therefore, a transistor with a large on-current can be created, resulting in a semiconductor device that operates at high speed.

[0348] When a metal oxide is used for the semiconductor layer 208, it is more preferable that the impurities released by the insulating layer 109 include hydrogen. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 208 via the conductive layer 212a increases the carrier concentration in the region of the semiconductor layer 208 in contact with the conductive layer 212a, thereby lowering the electrical resistance of either the source region or the drain region.

[0349] It is more preferable that the insulating layer 109 is made of a material that releases impurities that lower the electrical resistance of the conductive layer 212a. This makes it possible to lower the electrical resistance of the conductive layer 212a. For example, when a metal oxide is used for the conductive layer 212a, it is more preferable that the impurities include hydrogen. This increases the carrier concentration of the conductive layer 212a, which lowers the electrical resistance. Furthermore, the conductive layer 212a can function as wiring, resulting in a semiconductor device with low wiring resistance. The impurities that lower the electrical resistance of the conductive layer 212a may be the same as or different from the impurities that lower the electrical resistance of the semiconductor layer 208.

[0350] The materials that can be used for the conductive layer 212a are as described above. It is more preferable that the conductive layer 212a is permeable to impurities. It is more preferable that the conductive layer 212a does not easily adsorb impurities.

[0351] The insulating layer 110a has regions that are in contact with the upper surface of the insulating layer 109 and the upper and side surfaces of the conductive layer 212a. This suppresses the diffusion of impurities contained in the insulating layer 109 and the conductive layer 212a into the channel formation region of the semiconductor layer 208 via the insulating layer 110b.

[0352] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For details regarding the insulating layer 109, refer to the descriptions relating to the insulating layer 110d and the insulating layer 110e.

[0353] Furthermore, impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 212a and either the source region or the drain region of the semiconductor layer 208. However, at least the region of the semiconductor layer 208 in contact with the insulating layer 110b receives oxygen from the insulating layer 110b, thus preventing oxygen deficiency (V) in the channel formation region. Ｏ ) and V Ｏ The H value can be reduced. This suppresses the shift in the threshold voltage, allowing for a transistor that achieves both a small cutoff current and a large on-current. Therefore, a semiconductor device that achieves both low power consumption and high performance can be created.

[0354] Figure 14A and others show a configuration in which the insulating layer 110 has a four-layer structure consisting of insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110e, but the present invention is not limited to this. For example, the insulating layer 110 can have a five-layer structure consisting of insulating layer 110d, insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110e. Alternatively, the insulating layer 110 can have a three-layer structure consisting of insulating layer 110a, insulating layer 110b, and insulating layer 110c.

[0355] <Configuration Example 3> [Configuration Example 3-1] Figure 15A shows a top view of a semiconductor device 30, which is one embodiment of the present invention. Figure 15B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 15A, and Figure 15C shows a cross-sectional view of the cross-section along the dashed-dotted line A3-A4.

[0356] The semiconductor device 30 has a transistor 300. The transistor 300 has a conductive layer 180 on a substrate 102, an insulating layer 182 on the conductive layer 180, a semiconductor layer 184 on the insulating layer 182, and conductive layers 186a and 186b on the semiconductor layer 184. The conductive layer 180 has a region that overlaps with the semiconductor layer 184 via the insulating layer 182. The conductive layer 180 functions as the gate electrode of the transistor 300, and the insulating layer 182 functions as a gate insulating layer. The conductive layer 186a functions as one of the source electrode and drain electrode of the transistor 300, and the conductive layer 186b functions as the other of the source electrode and drain electrode.

[0357] The semiconductor layer 184 can be made from any of the materials listed for semiconductor layer 108. For details regarding semiconductor layer 184, please refer to the description for semiconductor layer 108. For example, indium oxide can be suitably used for semiconductor layer 184.

[0358] The conductive layers 186a and 186b have regions that are in contact with the semiconductor layer 184. The region of the semiconductor layer 184 in contact with the conductive layer 186a functions as either a source region or a drain region. The region of the semiconductor layer 184 in contact with the conductive layer 186b functions as the other source region or drain region. Of the semiconductor layer 184, the region between the source region and the drain region that overlaps with the conductive layer 180 via the insulating layer 182 functions as a channel-forming region.

[0359] In the region where the semiconductor layer 184 and the conductive layer 180 overlap, the shortest distance between the source region and the drain region is the channel length L of the transistor 300 (see Figure 15B). Also, the width of the overlapping region of the semiconductor layer 184 and the conductive layer 180 in a direction perpendicular to the channel length direction is the channel width W of the transistor 300 (see Figure 15C).

[0360] The transistor 300 is a so-called bottom-gate type transistor, having a gate electrode below the semiconductor layer 184. Furthermore, conductive layers 186a and 186b, which function as source and drain electrodes, are provided on the semiconductor layer 184. The transistor 300 can be described as a BGTC (Bottom Gate Top Contact) type transistor.

[0361] BGTC type transistors can reduce the number of masks used in their fabrication, thus lowering the manufacturing cost of semiconductor devices.

[0362] Furthermore, the semiconductor layer 184 may have recesses in areas that do not overlap with either the conductive layer 186a or the conductive layer 186b. For example, conductive layers 186a and 186b can be formed by depositing a conductive film on the semiconductor layer 184 and then processing the conductive film. When processing the conductive film, a portion of the semiconductor layer 184 may be removed, which may result in the formation of recesses in the semiconductor layer 184.

[0363] An insulating layer 188 is provided on the transistor 300, and an insulating layer 189 is provided on the insulating layer 188. The insulating layers 188 and 189 function as protective layers for the transistor 300. The insulating layer 188 has a region that overlaps with the conductive layer 180 via the semiconductor layer 184 and the insulating layer 182 between the conductive layer 186a and the conductive layer 186b. Since the insulating layer 188 has a region that is in contact with the channel formation region, it is preferable that it contains oxygen. The insulating layer 188 can preferably use one or more oxides and oxidnitrides. The insulating layer 188 can preferably use the materials listed for insulating layer 110b. The insulating layer 189 preferably functions as a barrier film. By providing a barrier film, the diffusion of impurities from the outside into the transistor can be effectively suppressed, resulting in a highly reliable semiconductor device. For details on the barrier film, please refer to the above description. Note that the insulating layer 188 can also function as a barrier film.

[0364] The insulating layer 182 has a region in contact with the semiconductor layer 184. When a metal oxide is used for the semiconductor layer 184, at least a part of the region of the insulating layer 182 in contact with the semiconductor layer 184 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 184 and the insulating layer 182. Specifically, the region of the insulating layer 182 in contact with the channel formation region of the semiconductor layer 184 preferably contains oxygen. One or more of oxides and oxynitrides can be suitably used for the region of the insulating layer 182 in contact with the channel formation region of the semiconductor layer 184. The same applies to the insulating layer 188. For example, each of the insulating layer 182 and the insulating layer 188 preferably contains silicon and oxygen. Each of the insulating layer 182 and the insulating layer 188 can be suitably formed of silicon oxide or silicon oxynitride.

[0365] Configuration examples different from the configuration shown in FIGS. 15A to 15C are shown in FIGS. 16A and 16B. FIGS. 16A and 16B are cross-sectional views of a semiconductor device 30A which is one aspect of the present invention. A top view of the semiconductor device 30A can be referred to FIG. 15A. FIG. 16A is a cross-sectional view of a cut surface along the dashed-dotted line A1 - A2 shown in FIG. 15A, and FIG. 16B is a cross-sectional view of a cut surface along the dashed-dotted line A3 - A4.

[0366] The semiconductor device 30A includes a transistor 300A. The transistor 300A is mainly different from the transistor 300 in that the insulating layer 182 has a stacked structure.

[0367] In FIGS. 16A and 16B, an example is shown in which the insulating layer 182 includes an insulating layer 182a and an insulating layer 182b on the insulating layer 182a.

[0368] The insulating layer 182b has a region in contact with the semiconductor layer 184. As described above, the insulating layer 182b in contact with the semiconductor layer 184 preferably contains oxygen.

[0369] The insulating layer 182a located on the conductive layer 180 side preferably functions as a barrier film. By providing a barrier film, the diffusion of components (e.g., metal) contained in the conductive layer 180 or substrate 102 into the semiconductor layer 184 can be suppressed, resulting in a highly reliable semiconductor device. For details on the barrier film, please refer to the above description. The insulating layer 182a preferably contains nitrogen.

[0370] The insulating layer 182a preferably contains silicon and nitrogen. The insulating layer 182b preferably contains silicon and oxygen. For example, silicon nitride can be suitably used for the insulating layer 182a, and silicon oxynitride can be suitably used for the insulating layer 182b.

[0371] Figures 17A to 17C show examples of configurations different from those shown in Figures 15A to 15C. Figure 17A is a top view of a semiconductor device 30B, which is one embodiment of the present invention. Figure 17B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 17A, and Figure 17C is a cross-sectional view of the section along the dashed line A3-A4.

[0372] The semiconductor device 30B has a transistor 300B. Transistor 300B differs from transistor 300 mainly in that it has a conductive layer 185.

[0373] The conductive layer 185 is provided on the insulating layer 188. The conductive layer 185 functions as the back gate electrode of the transistor 300B. The conductive layer 185 is provided in a position that overlaps with the conductive layer 180 via the semiconductor layer 184. Furthermore, it is preferable that the conductive layer 185 is provided so as to cover the entire channel formation region. This enhances the effect of making it difficult for electric fields generated outside the transistor to act on the channel formation region (also called the electric field shielding effect). The insulating layer 188 functions as the back gate insulating layer of the transistor 300B.

[0374] [Configuration Example 3-2] Figures 18A and 18B show cross-sectional views of a semiconductor device 30C, which is one embodiment of the present invention. A top view of the semiconductor device 30C can be found in Figure 15A. Figure 18A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 15A, and Figure 18B is a cross-sectional view of the section along the dashed line A3-A4.

[0375] The semiconductor device 30C has a transistor 300C. The transistor 300C mainly differs from the transistor 300 shown in Figure 15B, etc., in that it has an insulating layer 187.

[0376] The insulating layer 187 is provided on the semiconductor layer 184. The insulating layer 187 has a region that overlaps with the conductive layer 180 via the semiconductor layer 184 and the insulating layer 182. Part of the conductive layer 186a and part of the conductive layer 186b are provided on the insulating layer 187.

[0377] The insulating layer 187 functions as a channel protection film that protects the channel formation region when forming the conductive layers 186a and 186b. The conductive layers 186a and 186b can be formed by providing the insulating layer 187 on the semiconductor layer 184, depositing a conductive film on the insulating layer 187, and processing the conductive film. Since the channel formation region is not exposed during the deposition and processing of the conductive film, damage to the channel formation region can be suppressed. Therefore, a transistor with good electrical characteristics can be obtained. A transistor having a channel protection film (for example, transistor 300C) can be called a channel-protected transistor. On the other hand, a transistor without a channel protection film (for example, transistors 300 and 300B) can be called a channel-etched transistor.

[0378] Figures 19A and 19B show configuration examples different from those shown in Figures 18A and 18B. Figure 19A is a top view of a semiconductor device 30D, which is one embodiment of the present invention. Figure 19B is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 19A. For a cross-sectional view of the section along the dashed-dotted line A3-A4, refer to Figure 18B.

[0379] The semiconductor device 30D has a transistor 300D. Transistor 300D differs from transistor 300C shown in Figure 18A, etc., in that its insulating layer 187 has openings 181a and 181b.

[0380] The insulating layer 187 has openings 181a and 181b that reach the semiconductor layer 184. Conductive layers 186a and 186b are provided so as to cover openings 181a and 181b. Conductive layer 186a has a region that contacts the semiconductor layer 184 at opening 181a, and conductive layer 186b has a region that contacts the semiconductor layer 184 at opening 181b.

[0381] The insulating layer 187 has a region that is in contact with the semiconductor layer 184. Preferably, at least a portion of the region of the insulating layer 187 that is in contact with the semiconductor layer 184 contains oxygen. For example, the insulating layer 187 preferably contains silicon and oxygen. The insulating layer 187 can preferably be made of silicon oxide or silicon oxynitride.

[0382] [Configuration Example 3-3] Figure 20A shows a top view of a semiconductor device 30E, which is one embodiment of the present invention. Figure 20B shows a cross-sectional view of the cross-section along the dashed line A1-A2 shown in Figure 20A. For a cross-sectional view of the cross-section along the dashed line A3-A4, refer to Figure 15C.

[0383] The semiconductor device 30E has a transistor 300E. Transistor 300E differs from transistor 300 shown in Figure 15B, etc., in that the conductive layers 186a and 186b are located between the semiconductor layer 184 and the insulating layer 182.

[0384] Transistor 300E is a so-called bottom-gate type transistor. Furthermore, a semiconductor layer 184 is provided on conductive layers 186a and 186b, which function as source and drain electrodes. Transistor 300E can be described as a BGBC (Bottom Gate Bottom Contact) type transistor.

[0385] Since the semiconductor layer 184 is formed after the conductive layers 186a and 186b are formed, damage to the semiconductor layer 184 during the formation of the conductive layers 186a and 186b can be avoided.

[0386] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0387] A method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Note that explanations regarding the materials and formation methods of each element may be omitted if they have already been described.

[0388] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), ALD, and other methods. CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal-organic chemical vapor deposition (MOCVD).

[0389] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0390] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by deposition methods using shielding masks such as metal masks.

[0391] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0392] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of the light source. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0393] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0394] <Example of Manufacturing Method 1> Here, an example of a manufacturing method for the semiconductor device 10A shown in Figures 2A to 2C will be explained using Figures 21A to 22C. Figures 21A to 22C show side by side the cross-sectional view between the dashed lines A1 and A2 shown in Figure 2B and the cross-sectional view between the dashed lines B1 and B2 shown in Figure 2C.

[0395] First, a conductive film is formed on the substrate 102, and the conductive film is processed to form a conductive layer 103 (Figure 21A). Sputtering is preferably used to form the conductive film.

[0396] Next, an insulating layer 105 is formed on the conductive layer 103 and the substrate 102 (Figure 21A). The insulating layer 105 can preferably be formed by sputtering or PECVD.

[0397] Next, a metal oxide film 108f, which will become the semiconductor layer 108, is deposited on the insulating layer 105 (Figure 21B). The metal oxide film 108f is preferably deposited by sputtering using a metal target or a metal oxide target. Alternatively, the metal oxide film 108f is preferably deposited by the ALD method. The ALD method allows for easy control of the deposition rate, enabling the deposition of thin films with good yield. Therefore, the ALD method is particularly suitable when the thickness of the metal oxide film 108f is thin. Furthermore, the CVD method can be used to deposit the metal oxide film 108f.

[0398] When forming the metal oxide film 108f, noble gases (for example, helium gas, argon gas, xenon gas, etc.) can be used.

[0399] When forming the metal oxide film 108f, it is preferable to use conditions that result in a low crystallinity of the metal oxide film 108f. For example, hydrogen gas, oxygen gas, and argon gas can be suitably used as the film-forming gas for the metal oxide film 108f. For details on forming the metal oxide film 108f, please refer to the above description.

[0400] It is preferable to use a low substrate temperature when depositing the metal oxide film 108f. This allows for lower crystallinity of the metal oxide film 108f. The substrate temperature during deposition of the metal oxide film 108f is preferably between room temperature (e.g., 25°C) and 150°C, more preferably between room temperature and 100°C, more preferably between room temperature and 80°C, and more preferably between room temperature and 50°C. In particular, it is preferable to deposit the metal oxide film 108f at room temperature or without heating the substrate. However, the substrate temperature during deposition of the metal oxide film 108f is not limited to the above range.

[0401] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0402] The metal oxide film 108f can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0403] For example, when forming an indium oxide film, an indium-containing precursor can be used. Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, [3-(dimethylamino)propyl]dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0404] Examples of oxidizing agents include ozone, oxygen, hydrogen peroxide, and water.

[0405] Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gases, the duration for which the raw material gases are flowed, and the order in which the raw material gases are flowed. By adjusting these factors, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these factors, it is also possible to deposit a metal oxide film 108f with a continuously changing composition.

[0406] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 105, and a treatment to supply oxygen into the insulating layer 105. For example, a heat treatment can be performed in a vacuum at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Plasma treatment in an atmosphere containing an oxidizing gas such as 0) can supply oxygen to the insulating layer 105. Plasma treatment in an atmosphere containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 105 while supplying oxygen. After such treatment, it is preferable to continuously form a metal oxide film 108f without exposing the surface of the insulating layer 105 to the atmosphere.

[0407] Next, the metal oxide film 108f is processed into an island shape to form the metal oxide layer 108F (Figure 21C). When indium oxide is used for the semiconductor layer 108, the metal oxide film 108f and the metal oxide layer 108F can be referred to as the indium oxide layer or indium oxide film.

[0408] The metal oxide layer 108F can be suitably formed using a wet etching method. In this case, a portion of the insulating layer 105 in areas that do not overlap with the metal oxide layer 108F may be etched and thinned. However, by using a material with a high selectivity ratio for the insulating layer 105 during etching of the metal oxide film 108f, the thinning of the insulating layer 105 can be suppressed.

[0409] Next, a heat treatment is performed. The heat treatment causes the metal oxide layer 108F to crystallize, forming the semiconductor layer 108 (Figure 21D). The temperature, atmosphere, and apparatus used for the heat treatment can be found in the previously mentioned description.

[0410] A semiconductor layer 108 can be obtained by forming a metal oxide layer 108F by depositing a metal oxide film 108f with low crystallinity and processing the metal oxide film 108f into island shapes, and then crystallizing it by heat treatment. This makes it possible to increase the grain size of the crystal grains contained in the semiconductor layer 108. Furthermore, since the metal oxide film 108f can be processed into island shapes at a low crystallinity stage, processing becomes easier, and the productivity of semiconductor devices can be increased. However, the present invention is not limited to this embodiment, and a semiconductor layer 108 can be formed by depositing a metal oxide film 108f with low crystallinity, crystallizing it by heat treatment, and then processing it into island shapes.

[0411] Heat treatment can also supply oxygen from the insulating layer 105 to the metal oxide film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing the semiconductor layer 108.

[0412] Note that heat treatment is not performed at this stage, and can be combined with heat treatment performed in a later step. In addition, a heat treatment in a later step (for example, a film formation step) may also serve as this heat treatment.

[0413] Next, an insulating film 106f is formed to cover the semiconductor layer 108 and the insulating layer 105, becoming the insulating layer 106 (Figure 21E). The insulating film 106f can be formed using, for example, the PECVD method, the sputtering method, or the ALD method.

[0414] By increasing the temperature during the formation of the insulating film 106f, a gate insulating layer with fewer defects can be made. However, if the temperature during the formation of the insulating film 106f is high, oxygen will be detached from the semiconductor layer 108, resulting in oxygen vacancies and V in the semiconductor layer 108. Ｏ In some cases, H may increase. The substrate temperature when forming the insulating layer 106 is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature when forming the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0415] Before depositing the insulating film 106f, the surface of the semiconductor layer 108 can be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. This reduces impurities at the interface between the semiconductor layer 108 and the insulating layer 106, enabling the realization of a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating film 106f. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the deposition of the insulating film 106f are performed continuously without exposure to the atmosphere.

[0416] After the insulating film 106f is formed, oxygen can be supplied to the insulating film 106f. As a method of supplying oxygen, for example, ion implantation or plasma treatment can be used. As the plasma treatment, a device that turns a gas into plasma using high-frequency power can be suitably used. Examples of devices that turn a gas into plasma using high-frequency power include a PECVD device, a plasma etching device, and a plasma ashing device. Plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: carbon monoxide and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0417] It is preferable to deposit a film 139 on the insulating film 106f (Figure 21F). Sputtering is preferably used to deposit the film 139. By depositing the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f.

[0418] The conductivity of the film 139 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, ITO, or ITSO can be used as the film 139.

[0419] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108 as the film 139. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108.

[0420] When forming the film 139, the higher the oxygen flow rate ratio of the film-forming gas introduced into the processing chamber of the film-forming apparatus, or the higher the oxygen partial pressure inside the processing chamber, the greater the amount of oxygen supplied to the insulating film 106f. The oxygen flow rate ratio is preferably 50% to 100%, more preferably 60% to 100%, more preferably 70% to 100%, more preferably 80% to 100%, and more preferably 90% to 100%. Typically, the oxygen flow rate ratio can be set to 100%. Note that the oxygen flow rate ratio can be interpreted as the ratio of the oxygen partial pressure to the pressure inside the processing chamber.

[0421] In this way, by depositing the film 139 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f during the deposition of the film 139, and the detachment of oxygen from the insulating film 106f can be prevented. As a result, a large amount of oxygen can be trapped in the insulating film 106f. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0422] Furthermore, if there is too much oxygen in the insulating layer 106, defect levels may easily form at and near the interface between the semiconductor layer 108 and the insulating layer 106. In this case, if a high potential is applied to the conductive layer 104, which functions as the gate electrode, electrons, which are carriers, may be trapped in these defect levels, causing the transistor's threshold voltage to shift positively. In such cases, it is preferable to lower the oxygen flow rate ratio or oxygen partial pressure during film formation of the film 139 to reduce the amount of oxygen supplied to the insulating film 106f. The oxygen flow rate ratio is preferably, for example, 10% to 60%, more preferably 20% to 60%, more preferably 30% to 60%, and more preferably 30% to 50%. This suppresses fluctuations in the threshold voltage, resulting in a highly reliable transistor.

[0423] It is preferable to perform a heat treatment after forming the film 139. By performing a heat treatment after forming the film 139, oxygen can be effectively supplied from the insulating film 106f to the semiconductor layer 108. In addition, oxygen can be supplied from the film 139 to the insulating film 106f.

[0424] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 106f as much as possible. The heat treatment can be carried out using an oven, RTA device, etc.

[0425] After the film 139 is formed, or after the aforementioned heat treatment, oxygen can be supplied to the insulating film 106f via the film 139. For example, ion implantation or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0426] Next, the film 139 is removed. Removing the film 139 exposes the insulating film 106f. There are no particular limitations on the method for removing the film 139, but a wet etching method can be preferably used. By using a wet etching method, etching of the insulating film 106f during the removal of the film 139 can be suppressed. This prevents the thickness of the insulating film 106f from becoming thinner, and the thickness of the insulating layer 106 can be made uniform.

[0427] The process of supplying oxygen to the insulating film 106f is not limited to the methods described above. For example, ion implantation or plasma treatment can be used. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 106f, and then oxygen can be supplied to the insulating film 106f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0428] Next, a conductive layer 104 is formed on the insulating film 106f (Figure 22A). For forming the conductive film that will become the conductive layer 104, sputtering, thermal CVD (including MOCVD), or ALD can be suitably used.

[0429] Next, using the conductive layer 104 as a mask, impurities 190 are supplied (also called added or implanted) to the semiconductor layer 108 (Figure 22B). As a result, regions 108P and 108Q are formed in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104. At this time, it is preferable to determine the conditions for supplying impurities by considering the material and thickness of the conductive layer 104 that serves as the mask, so that as little impurities 190 as possible are supplied to the region of the semiconductor layer 108 that overlaps with the conductive layer 104. This makes it possible to form a channel-forming region with a sufficiently reduced impurity concentration in the region of the semiconductor layer 108 that overlaps with the conductive layer 104.

[0430] Figure 22B schematically shows, with arrows, how impurities 190 are supplied to the semiconductor layer 108. While Figure 22B shows a configuration in which impurities 190 are supplied to the semiconductor layer 108 via an insulating film 106f, the present invention is not limited to this configuration. For example, in the transistor 100D shown in Figure 4C, after forming the insulating layer 106 and the conductive layer 104, impurities can be supplied to the semiconductor layer 108 using the conductive layer 104 as a mask. In this case, impurities are supplied to regions 108P and 108Q without going through the insulating layer 106. Furthermore, impurities are supplied to regions 108R and 108S via the insulating layer 106.

[0431] Furthermore, a resist mask can be formed on the conductive film that will become the conductive layer 104, and the conductive film can be processed using the resist mask as a mask to form the conductive layer 104. Then, by supplying impurities 190 to the semiconductor layer 108 using the resist mask and the conductive layer 104 as masks, regions 108P and 108Q can be formed. After that, the resist mask is removed.

[0432] Next, an insulating film 195f is formed to cover the conductive layer 104, the insulating layer 106, and the semiconductor layer 108, forming the insulating layer 195 (Figure 22C). The PECVD method can be suitably used to form the insulating film 195f.

[0433] If the deposition temperature of the insulating film 195f is too high, impurities contained in regions 108P and 108Q may diffuse into the peripheral areas of the semiconductor layer 108, including the channel formation region. Furthermore, the electrical resistance of regions 108P and 108Q may increase. Therefore, it is preferable to determine the deposition temperature of the insulating film 195f considering the diffusion of impurities.

[0434] The deposition temperature for the insulating film 195f is preferably, for example, 150°C to 400°C, more preferably 180°C to 360°C, and more preferably 200°C to 250°C. By depositing the insulating film 195f at a low temperature, a transistor with good electrical characteristics can be obtained even with a short channel length.

[0435] After forming the insulating film 195f, a heat treatment can be performed. This heat treatment may further reduce the electrical resistance of regions 108P and 108Q. Since details of the heat treatment can be found in the previous description, a detailed explanation is omitted here. Note that if the heat treatment temperature is too high (for example, above 500°C), impurities may diffuse into the channel formation region, potentially leading to a decrease in the electrical characteristics and reliability of the transistor.

[0436] Note that this heat treatment is not required. Furthermore, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Also, if there is a heat treatment in a later step (e.g., a film formation process), this heat treatment may be combined with that step.

[0437] Next, portions of the insulating film 195f and insulating film 106f are removed to form openings 147a and 147b that reach regions 108P and 108Q (Figure 22D). This forms the insulating layer 195 and insulating layer 106. For example, a dry etching method can be suitably used to form openings 147a and 147b.

[0438] Next, conductive layers 112a and 112b are formed to cover openings 147a and 147b (Figure 22E).

[0439] Next, an insulating layer 218 is formed on the insulating layer 195, conductive layer 112a, and conductive layer 112b (Figures 2B and 2C). The PECVD method can be suitably used to form the insulating layer 218.

[0440] By following the above steps, a semiconductor device 10A according to one aspect of the present invention can be manufactured.

[0441] <Example of Manufacturing Method 2> Here, an example of a manufacturing method for the semiconductor device 20B shown in Figures 14A and 14B will be explained using Figures 23A to 26B. Figures 23A to 26B show side by side the cross-sectional view between the dashed-dotted lines A1-A2 and the cross-sectional view between the dashed-dotted lines B1-B2 shown in Figure 10A.

[0442] First, an insulating layer 109 is formed on the substrate 102 (Figure 23A). The insulating layer 109 can be formed using sputtering or PECVD.

[0443] Next, a conductive film is formed on the insulating layer 109, and the conductive film is processed to form a conductive layer 212a (Figure 23A). Sputtering can be suitably used to form the conductive film.

[0444] Next, an insulating film 110af, which will become the insulating layer 110a, and an insulating film 110bf, which will become the insulating layer 110b, are formed on the conductive layer 212a (Figure 23B).

[0445] The insulating film 110af and insulating film 110bf can preferably be deposited using sputtering or PECVD. It is preferable to deposit insulating film 110bf without exposing the surface of insulating film 110af to the atmosphere after depositing insulating film 110af. This suppresses the adhesion of airborne impurities to the surface of insulating film 110af. Examples of such impurities include water and organic matter. For example, it is preferable to deposit insulating film 110bf continuously using the same apparatus after depositing insulating film 110af.

[0446] The substrate temperature during the deposition of the insulating film 110af and insulating film 110bf is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. By setting the substrate temperature during the deposition of the insulating film 110af and insulating film 110bf within the above range, the amount of impurities (e.g., water and hydrogen) released from the film itself can be reduced, and the diffusion of impurities into the semiconductor layer 208 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0447] Furthermore, since the insulating film 110af and insulating film 110bf are formed before the semiconductor layer 208, there is no need to worry about oxygen being released from the semiconductor layer 208 due to the heat applied during the formation of the insulating film 110af and insulating film 110bf.

[0448] After forming the insulating film 110af and insulating film 110bf, a heat treatment can be performed. By performing the heat treatment, impurities (e.g., water and hydrogen) can be removed from the insulating film 110af and from the insulating film 110bf and from its surface.

[0449] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For details on the method of supplying oxygen, please refer to the previously mentioned description.

[0450] After the insulating film 110bf is formed, nitrogen can be supplied to the insulating film 110bf. For the method of supplying nitrogen, refer to the description of the oxygen supply method described above. Plasma treatment in a nitrogen-containing atmosphere is suitably used as the nitrogen supply method. For example, nitrogen, nitrous oxide (N) ２ O), and nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following. The amount of nitrogen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0451] In the insulating layer (here, insulating film 110bf or the later insulating layer 110b), nitrogen oxides (NOx) are formed by the reaction of nitrogen and oxygen. Ｘ (where X is a real number greater than 0) is produced. For example, nitrogen oxides are produced. ２ O, NO and NO ２ For example, in the insulating layer, nitrogen oxides form energy levels, which are located within the band gap of the metal oxide. ２ The transition level at which the charge of nitrogen oxides transitions between a state of 0 and a state of -1 lies within the band gap of indium oxide. Therefore, when nitrogen oxides diffuse to or near the interface between the insulating layer and the semiconductor layer containing the metal oxide, these levels trap electrons. As a result, the trapped electrons remain at or near the interface between the insulating and semiconductor layers, allowing the transistor's threshold voltage to be increased in the positive direction. This enables a normally-off transistor and a semiconductor device with low power consumption.

[0452] The order in which oxygen is supplied and nitrogen is supplied is not particularly limited. Oxygen can be supplied after nitrogen. Nitrogen can be supplied after oxygen. Alternatively, oxygen and nitrogen can be supplied in the same process. For example, oxygen and nitrogen can be supplied by performing plasma treatment in an atmosphere containing nitrogen and oxygen. For example, nitrous oxide (N)２ Plasma treatment using O) is preferable because it allows for efficient generation of nitrogen oxides.

[0453] Furthermore, after the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity. Specifically, after forming the insulating film 110bf in the PECVD apparatus, N ２ It can perform plasma processing.

[0454] Next, it is preferable to form a film 139 on the insulating film 110bf (Figure 23D). Figure 23C schematically shows how oxygen is supplied to the insulating film 110bf using solid arrows. For details on film 139, please refer to the previous description.

[0455] It is preferable to perform a heat treatment after forming the film 139. By performing a heat treatment after forming the film 139, oxygen can be effectively supplied from the film 139 to the insulating film 110bf. For details on the heat treatment, please refer to the above description.

[0456] After the film 139 is formed, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating film 110bf via the film 139. For details on the method of supplying oxygen, please refer to the description above.

[0457] Next, the film 139 is removed (Figure 23E). There are no particular limitations on the method for removing the film 139, but a wet etching method can be preferably used. By using a wet etching method, etching of the insulating film 110bf during the removal of the film 139 can be suppressed. This prevents the thickness of the insulating film 110bf from becoming thinner, and the thickness of the insulating layer 110b can be made uniform.

[0458] For the process of supplying oxygen to the insulating film 110bf, refer to the description relating to the process of supplying oxygen to the insulating film 106f.

[0459] Next, an insulating film 110cf, which will become the insulating layer 110c, and an insulating film 110ef, which will become the insulating layer 110e, are deposited on the insulating film 110bf (Figure 24A). The deposition of insulating films 110cf and 110ef can be described by referring to the description of deposition of insulating film 110af and insulating layer 109, so a detailed explanation is omitted.

[0460] Next, a conductive film 212bf, which will become the conductive layer 212b, is deposited on the insulating film 110ef (Figure 24B). Sputtering is preferably used to deposit the conductive film 212bf.

[0461] Next, the conductive film 212bf is processed to form the conductive layer 212b (Figure 24C). The conductive layer 212b later becomes the conductive layer 212b. For example, a wet etching method can be suitably used to form the conductive layer 212b.

[0462] Next, a portion of the conductive layer 212b is removed to form a conductive layer 212b having an opening 143 (Figure 24D). A wet etching method can be suitably used to form the conductive layer 212b.

[0463] Next, a portion of the insulating film 110af, insulating film 110bf, and insulating film 110cf is removed to form an insulating layer 110 having an opening 141 (Figure 24D). The opening 141 is provided in a region that overlaps with the opening 143. The formation of the opening 141 exposes the conductive layer 212a. Dry etching can be preferably used to form the insulating layer 110.

[0464] The opening 141 can be formed, for example, using the resist mask used to form the opening 143. Specifically, a resist mask can be formed on the conductive layer 212b, a portion of the conductive layer 212b can be removed using the resist mask to form the opening 143, and a portion of the insulating film 110af, insulating film 110bf, and insulating film 110cf can be removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the one used to form the opening 143.

[0465] Next, a metal oxide film 208f, which will become the semiconductor layer 208, is formed to cover the openings 141 and 143 (Figure 25A). The metal oxide film 208f is provided in contact with the upper and side surfaces of the conductive layer 212b, the upper and side surfaces of the insulating layer 110, and the upper surface of the conductive layer 212a.

[0466] For information on the deposition of the metal oxide film 208f, please refer to the description relating to the metal oxide film 108f.

[0467] Before forming the metal oxide film 208f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 110, and a treatment to supply oxygen into the insulating layer 110. For example, a heat treatment can be performed in a vacuum at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Plasma treatment in an atmosphere containing an oxidizing gas such as 0) can supply oxygen to the insulating layer 110. Plasma treatment in an atmosphere containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 110 while supplying oxygen. After such treatment, it is preferable to continuously deposit a metal oxide film 208f without exposing the surface of the insulating layer 110 to the atmosphere.

[0468] Next, the metal oxide film 208f is processed into an island shape to form the metal oxide layer 208F (Figure 25B). For details on the formation of the metal oxide layer 208F, please refer to the description related to the formation of the metal oxide layer 108F.

[0469] Next, a heat treatment is performed. The heat treatment causes the metal oxide layer 208F to crystallize, forming the semiconductor layer 208 (Figure 25C). The heat treatment can reduce defects in the semiconductor layer 208. In addition, the heat treatment can remove hydrogen and water contained in or adsorbed on the surface of the semiconductor layer 208. For details on this heat treatment, please refer to the description of the heat treatment of the metal oxide layer 108F.

[0470] Heat treatment can also supply oxygen from the insulating layer 110b to the metal oxide film 208f or the semiconductor layer 208. In this case, it is more preferable to perform the heat treatment before processing the semiconductor layer 208.

[0471] Note that heat treatment is not performed at this stage, and can be combined with heat treatment performed in a later step. In addition, a heat treatment in a later step (for example, a film formation step) may also serve as this heat treatment.

[0472] Next, the insulating layer 206 is formed, covering the semiconductor layer 208, the conductive layer 212b, and the insulating layer 110 (Figure 26A).

[0473] Before forming the insulating layer 206, the surface of the semiconductor layer 208 can be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 208. Therefore, impurities at the interface between the semiconductor layer 208 and the insulating layer 206 can be reduced, enabling the realization of a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 208 is exposed to the atmosphere between the formation of the semiconductor layer 208 and the formation of the insulating layer 206. For details on plasma treatment, please refer to the above description.

[0474] Next, a conductive layer 204 is formed on the insulating layer 206 (Figure 26B).

[0475] Next, an insulating layer 218 is formed on the insulating layer 206 and the conductive layer 204 (Figures 14A and 14B).

[0476] By following the above steps, a semiconductor device 20B according to one aspect of the present invention can be manufactured.

[0477] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0478] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0479] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0480] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (IGZO) and zinc oxide.

[0481] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0482] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0483] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0484] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0485] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0486] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is especially preferable to use elements in which the oxide is conductive or semiconducting.

[0487] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0488] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0489] Polycrystalline films are preferred over microcrystalline or amorphous films because they can reduce carrier scattering and exhibit high field-effect mobility. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0490] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0491] In this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0492] In the channel formation region, crystal grains, grain boundaries, crystal axes, crystal orientation, etc., can be confirmed by cross-sectional observation along the channel length direction of the semiconductor layer (for example, cross-sectional observation including the semiconductor layer, source electrode, and drain electrode).

[0493] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in greater quantities than the above impurities. ppm stands for "parts per million," and 1 ppm is equal to 1 × 10⁻⁶ −６ That is the case.

[0494] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0495] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V・s) or more is possible.

[0496] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0497] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0498] Indium oxide films allow hydrogen to diffuse. Hydrogen diffusing into an indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0499] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a transistor using silicon in the channel formation region (hereinafter also referred to as a Si transistor).

[0500] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0501] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0502] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0503] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0504] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0505] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0506] (Embodiment 3) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 27A to 39.

[0507] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0508] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0509] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a flexible printed circuit board (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an integrated circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0510] The display device of this embodiment may also function as a touch panel. For example, the display device can be fitted with various detection elements (also called sensor elements) that can detect the proximity or contact of an object to be detected, such as a finger.

[0511] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0512] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0513] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0514] <Example of Display Device Configuration 1> Figure 27A shows a perspective view of the display device 50A.

[0515] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 27A, substrate 152 is shown with a dashed line.

[0516] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Figure 27A shows an example in which the IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 27A can also be described as a display module having the display device 50A, an IC, and an FPC.

[0517] The connection portion 140 is provided on the outside of the display unit 162. The connection portion 140 can be provided along one or more sides of the display unit 162. There may be one or more connection portions 140. Figure 27A shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit 162. The common electrode of the display element and the conductive layer are connected at the connection portion 140, and a potential can be supplied to the common electrode.

[0518] The circuit section 164 may include, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 may include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0519] The circuit section 164 can utilize various circuits, including shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexer circuits, and logic circuits. The circuit section 164 can also utilize transistors and capacitive elements. The transistors in the circuit section 164 can be formed using the same process as the transistors in the pixel circuit.

[0520] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. These signals and power are input to the conductive layer 165 from the outside via the FPC 172, or from the IC 173.

[0521] Figure 27A shows an example in which IC 173 is provided on the substrate 151 using the COG method. IC 173 can be an IC having, for example, one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module may be configured without an IC. Alternatively, the IC may be mounted on the FPC using the COF method or the like.

[0522] A semiconductor device according to one aspect of the present invention can be applied, for example, to one or both of the display unit 162 and the circuit unit 164 of a display device 50A. Oxide semiconductors (OS) can preferably be used in the channel formation region of the transistors in the display device. By using OS transistors, a display device with low power consumption can be made. Furthermore, the semiconductor device according to one aspect of the present invention can be used in both the display unit 162 and the circuit unit 164, that is, all of the transistors in the display device can be OS transistors. By making all of the transistors in the display device OS transistors in this way, manufacturing costs can be kept low.

[0523] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0524] The display unit 162 is the area in the display device 50A that displays images, and has a plurality of pixels 201 arranged periodically. Figure 27A shows a magnified view of one pixel 201.

[0525] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0526] The pixel 201 shown in Figure 27A has sub-pixels 11R that emit red light, sub-pixels 11G that emit green light, and sub-pixels 11B that emit blue light. Note that sub-pixels 11R, 11G, and 11B are sometimes collectively referred to as sub-pixel 11. Furthermore, the number of sub-pixels a single pixel may have is not particularly limited.

[0527] Each sub-pixel 11R, 11G, and 11B includes a display element and a pixel circuit that controls the driving of the display element.

[0528] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials can also be used.

[0529] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0530] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and Guest Host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0531] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0532] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0533] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0534] Examples of quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Furthermore, quantum dot materials containing elemental groups of Group 2 and Group 16, Group 13 and Group 15, Group 13 and Group 17, Group 11 and Group 17, or Group 14 and Group 15 can be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0535] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0536] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0537] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0538] One embodiment of the present invention is a semiconductor device having a transistor with a high on-current. A suitable material for the channel formation region of the transistor can be an oxide semiconductor (OS), resulting in a transistor with a low off-current. This semiconductor device can be suitably used in either or both of the display unit 162 and the circuit unit 164. Furthermore, this semiconductor device can be used in both the display unit 162 and the circuit unit 164, meaning all transistors in the display device can be OS transistors. By using OS transistors for all transistors in the display device in this way, manufacturing costs can be kept low.

[0539] The transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures.

[0540] The display device of this embodiment may have, for example, one or more of planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be top-gate or bottom-gate types. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0541] The display device of this embodiment may have a Si transistor.

[0542] The transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 may all be the same or there may be two or more different structures. Similarly, the structures of the multiple transistors in the display unit 162 may all be the same or there may be two or more different structures.

[0543] All transistors in the display device may be OS transistors, all transistors in the display device may be Si transistors, or some of the transistors in the display device may be OS transistors and the rest may be Si transistors. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). LTPS transistors have high field-effect mobility and can operate at high speeds.

[0544] For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for transistors that function as switches to control conduction and non-conduction between wires, and an LTPS transistor is used for transistors that control current.

[0545] <Example of sub-pixel configuration> An example of the configuration of a sub-pixel 11 is shown in Figure 27B. The sub-pixel 11 includes a pixel circuit 51 and a light-emitting device 61.

[0546] The pixel circuit 51 includes a transistor 52A, a transistor 52B, and a capacitive element 53. The pixel circuit 51 is a 2Tr1C type pixel circuit having two transistors and one capacitive element. The pixel circuit that can be applied to the display device according to one embodiment of the present invention is not particularly limited.

[0547] The anode of the light-emitting device 61 is connected to one of the source and drain electrodes of transistor 52B and one electrode of the capacitive element 53. The other source and drain of transistor 52B is connected to wiring ANO. The gate of transistor 52B is connected to one of the source and drain electrodes of transistor 52A and the other electrode of the capacitive element 53. The other source and drain of transistor 52A is connected to wiring SL. The gate of transistor 52A is connected to wiring GL. The cathode of the light-emitting device 61 is connected to wiring VCOM.

[0548] Wiring VCOM is a wire that provides a potential for supplying current to the light-emitting device 61. Transistor 52A has the function of controlling the conduction or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO and VSS is supplied to wiring VCOM.

[0549] In this specification, the high power supply potential VDD (also simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS. The low power supply potential VSS (also simply referred to as "VSS") refers to a power supply potential that is lower than the high power supply potential VDD. Furthermore, the ground potential GND (also simply referred to as "GND") can also be used as VDD or VSS. For example, if VDD is GND, then VSS is at a lower potential than GND, and if VSS is GND, then VDD is at a higher potential than GND.

[0550] Transistor 52A functions as a selection transistor for controlling the selected state of the sub-pixel 11. Transistor 52B functions as a drive transistor for controlling the amount of current flowing to the light-emitting device 61. Capacitive element 53 has the function of holding the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting device 61 is controlled according to the image signal supplied to the gate of transistor 52B. A semiconductor device according to one aspect of the present invention can be used in the pixel circuit 51. One or both of transistors 52A and transistor 52B can preferably be one or more of the aforementioned transistors.

[0551] For the drive transistor, a transistor with high saturation and high current controllability can be suitably used. This makes it possible to create a display device with high display quality. As the drive transistor, an OS transistor with high saturation can be suitably used.

[0552] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thereby allowing control of the current flowing to the light-emitting element. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0553] In terms of the saturation of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, OS transistors can stabilize the luminescence brightness of a light-emitting element because the change in source-drain current is small even when the source-drain voltage is changed.

[0554] To increase the luminescence brightness of a light-emitting element, it is necessary to increase the amount of current flowing through the element. To achieve this, the source-drain voltage of the driving transistor must be increased. OS transistors have a higher breakdown voltage between their source and drain compared to Si transistors, allowing for a higher voltage to be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the driving transistor, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the element. In particular, IO transistors, which have a large on-current and high saturation, can be suitably used as driving transistors.

[0555] For the selection transistor, an OS transistor with a low off-current (e.g., an I / O transistor) can be suitably used. This allows the pixel gradation to be maintained even when the frame frequency is significantly low (e.g., 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying still images.

[0556] By using an I / O transistor with high field-effect mobility as the selection transistor, the time required for charging and discharging the floating node FN can be shortened. This allows for a higher frame frequency in the display, resulting in a display device with high display quality.

[0557] By using multiple transistors and capacitive elements in a pixel circuit, a high-performance display device can be created. By applying a semiconductor device according to one aspect of the present invention, the occupied area can be reduced even if the number of transistors and capacitive elements increases, resulting in a high-performance and high-resolution display device. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0558] A semiconductor device according to one aspect of the present invention can reduce the occupied area, thereby increasing the aperture ratio of pixels in a display device with a bottom emission structure. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0559] In this specification, the aperture ratio refers to the ratio of the area of ​​the region from which light is emitted to the area of ​​the pixel.

[0560] Table 1 shows a comparison of configurations applicable to the backplane of a display device. Table 1 shows configurations using LTPS transistors ("LTPS"), LTPO transistors ("LTPO"), transistors with an IGZO semiconductor layer ("IGZO"), and transistors with a crystalline indium oxide semiconductor layer ("Crystal IO"). In Table 1, a checkmark indicates applicability, and N / A indicates not applicable.

[0561]

[0562] Table 1 shows the electrical characteristics of transistors (FET characteristics), including channel length, field-effect mobility, reliability, on-state current, off-state current, and degradation of device characteristics on flexible substrates, which yield good electrical characteristics. As shown in Table 1, LTPO, IGZO, and Crystal IO, which use metal oxides, have very low off-currents compared to LTPS. Furthermore, IGZO and Crystal IO can achieve normally-off characteristics even in transistors with a short channel length of 2 μm. In particular, Crystal IO has a typical field-effect mobility of 50 cm. ２ / Vs or more 100cm ２ The voltage is high, below / Vs. Furthermore, Crystal IO has an on-current similar to LTPS and is highly reliable. In addition, because IGZO and Crystal IO can be processed at low temperatures, the variation in the electrical characteristics of the transistor is small, and degradation is minimal, even when using a flexible substrate.

[0563] Table 1 shows productivity in terms of the size of glass substrates applicable to mass production, the presence or absence of laser crystallization of the semiconductor layer, and the number of masks (compared with LTPS). IGZO and Crystal IO do not require a laser crystallization process and can be applied to large glass substrates (e.g., G8.5). Furthermore, compared to LTPO, IGZO and Crystal IO require fewer masks and thus reduce the number of processes.

[0564] As described above, transistors having crystalline indium oxide can achieve high electrical characteristics, high reliability, and high productivity. Therefore, transistors having crystalline indium oxide can be suitably used in the backplane of a display device.

[0565] Figure 27C shows an example of a configuration different from that of the sub-pixel 11 shown in Figure 27B. The sub-pixel 11 has a pixel circuit 51A and a light-emitting device 61.

[0566] Pixel circuit 51A differs from pixel circuit 51 mainly in that transistor 52B is a p-channel type transistor. One electrode of capacitive element 53 is connected to wiring ANO.

[0567] In the pixel circuit 51A, an n-channel OS transistor can be suitably used for transistor 52A, and a p-channel LTPS transistor can be suitably used for transistor 52B.

[0568] In the pixel circuit 51 shown in Figure 27B, IO transistors can be suitably used for both transistor 52A and transistor 52B. This allows transistors 52A and 52B to be formed in the same process. Therefore, compared to a configuration using LTPO, the process can be simplified and manufacturing costs can be reduced. Also, as mentioned above, when increasing the luminescence brightness of the light-emitting element, it is necessary to increase the source-drain voltage of the driving transistor. When the source-drain voltage is high, the drain current of an LTPS transistor may increase due to the Kink effect. On the other hand, transistors using indium oxide show only a small increase in drain current even when the source-drain voltage is high, making them suitable for use as driving transistors. Furthermore, compared to LTPS transistors, IO transistors have smaller hysteresis, making them suitable for use as both selection transistors and driving transistors.

[0569] Figure 28A shows an example of a configuration different from the sub-pixel 11 shown in Figure 27B. The sub-pixel 11 has a pixel circuit 51B and a light-emitting device 61.

[0570] Pixel circuit 51B differs from pixel circuit 51 mainly in that it has a transistor 52C. Pixel circuit 51B has transistors 52A, 52B, 52C, and a capacitive element 53. Pixel circuit 51B is a 3Tr1C type pixel circuit having three transistors and one capacitive element.

[0571] Pixel circuit 51B has a configuration in which a transistor 52C is added to the pixel circuit 51 shown in Figure...

Claims

It has a transistor, The transistor has a semiconductor layer, a gate electrode, and a gate insulating layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer, The semiconductor layer comprises indium and oxygen. The semiconductor layer has a crystalline portion, The thickness of the semiconductor layer is 1 nm or more and 10 nm or less. The channel length of the transistor is 5 μm or more and 12 μm or less. A semiconductor device comprising the transistor, wherein the gate voltage is 5V, and the absolute value of the rate of change of the drain current when the drain voltage changes from 5.4V to 6.0V is 4% / V or less. 　 In claim 1, The semiconductor layer is polycrystalline, A semiconductor device in which the barrier height of the crystal grain boundary in the semiconductor layer is 50 meV or less. 　 In claim 1 or claim 2, The semiconductor layer comprises a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. A semiconductor device wherein the second metal oxide layer has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively. 　 In claim 3, The second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ The region has the following characteristics: A semiconductor device wherein the first metal oxide layer and the third metal oxide layer each have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer. 　 In claim 3, A semiconductor device wherein the second metal oxide layer has regions with lower film density than the first metal oxide layer and the third metal oxide layer, respectively. 　 In claim 3, A semiconductor device wherein the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer, respectively. 　 It has a transistor, The transistor has a semiconductor layer, a gate electrode, and a gate insulating layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer, The semiconductor layer comprises a first metal oxide layer and a second metal oxide layer on the first metal oxide layer. The first metal oxide layer comprises indium, element M, and oxygen. The second metal oxide layer comprises indium and oxygen, The element M is one or more of gallium, aluminum, and tin. The channel length of the transistor is 5 μm or more and 12 μm or less. A semiconductor device comprising the transistor, wherein the gate voltage is 5V, and the absolute value of the rate of change of the drain current when the drain voltage changes from 5.4V to 6.0V is 4% / V or less. 　 In claim 7, A semiconductor device wherein the content of element M in the first metal oxide layer is higher than the content of element M in the second metal oxide layer. 　 In claim 7, A semiconductor device wherein the content of element M in the first metal oxide layer is 1% or more and 35% or less. 　 In claim 7, A semiconductor device wherein the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer. 　 It has a transistor, The transistor has a semiconductor layer, a gate electrode, and a gate insulating layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer, The semiconductor layer has a crystalline portion, The thickness of the semiconductor layer is 1 nm or more and 10 nm or less. The semiconductor layer comprises a first metal oxide layer and a second metal oxide layer on the first metal oxide layer. The first metal oxide layer comprises indium, element M, and oxygen. The second metal oxide layer comprises indium and oxygen, The element M is one or more of gallium, aluminum, and tin. The channel length of the transistor is 5 μm or more and 12 μm or less. A semiconductor device comprising the transistor, wherein the gate voltage is 5V, and the absolute value of the rate of change of the drain current when the drain voltage changes from 5.4V to 6.0V is 4% / V or less. 　 In claim 11, A semiconductor device wherein the content of element M in the first metal oxide layer is higher than the content of element M in the second metal oxide layer. 　 In claim 7, A semiconductor device wherein the content of element M in the first metal oxide layer is 1% or more and 35% or less. 　 In claim 11, A semiconductor device wherein the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer. 　 In any one of claims 7 to 14, The semiconductor layer has a third metal oxide layer, The third metal oxide layer is located between the second metal oxide layer and the gate insulating layer. The third metal oxide layer comprises indium and oxygen, A semiconductor device wherein the content of element M in the first metal oxide layer is higher than the content of element M in the third metal oxide layer. 　 In claim 15, The second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ The region has the following characteristics: A semiconductor device wherein the third metal oxide layer has a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer. 　 In claim 15, A semiconductor device wherein the thickness of the second metal oxide layer is greater than the thickness of the third metal oxide layer. 　 In any one of claims 7 to 14, The semiconductor layer has a third metal oxide layer, The third metal oxide layer is located between the second metal oxide layer and the gate insulating layer. The third metal oxide layer comprises indium, the element M, and oxygen. A semiconductor device wherein the content of element M in the third metal oxide layer is higher than the content of element M in the second metal oxide layer. 　 In claim 18, A semiconductor device wherein the content of element M in the third metal oxide layer is 1% or more and 35% or less. 　 In claim 18, A semiconductor device wherein the thickness of the second metal oxide layer is greater than the thickness of the third metal oxide layer.

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