Semiconductor device

Abstract

This semiconductor device comprises: a power supply switch circuit having a first transistor formed on a first surface of a substrate; and first to third power supply lines and a first signal line formed on a second surface of the substrate. The first transistor has a first semiconductor layer, a second semiconductor layer, and a first gate electrode lined up in a first direction in plan view. A first via that is formed in the substrate and that connects the first signal line and the lower surface of the first gate electrode is positioned so as to be shifted in a second direction different from the first direction in plan view with respect to the first and second semiconductor layers. Thus, when laying out a power switch circuit within a predetermined size, the via can be appropriately positioned in the power switch circuit.

Description

Semiconductor device , ,

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[0001] The present invention relates to a semiconductor device.

[0002] There is a power switch circuit that controls the on / off of power supply to circuits such as standard cells. There are DC (Direct Contact) technology and DGC (Direct Gate Contact) technology in which vias are provided on a substrate to directly connect wiring on the back surface of a semiconductor substrate and the source or gate electrode of a transistor on the surface of the semiconductor substrate, and power and signals are supplied from the back surface of the semiconductor substrate to the transistor.

[0003] U.S. Patent No. 11637067, U.S. Patent No. 11423204, U.S. Patent No. 11107805, U.S. Patent Application Publication No. 2024 / 0266349, U.S. Patent No. 11764154, U.S. Patent No. 11923297, U.S. Patent Application Publication No. 2024 / 0162118, U.S. Patent Application Publication No. 2023 / 0040094, U.S. Patent Application Publication No. 2020 / 0328201

[0004] In the case where power supply lines or the like extend in one direction in a plan view in a standard cell or the like, the arrangement pitch of transistors arranged along a direction intersecting in one direction is defined as "Row". At this time, for example, when a power switch circuit is arranged in regions of two Rows, there has been no consideration of how to arrange DC or DGC.

[0005] The present invention has been made in view of the above points, and an object thereof is to appropriately arrange vias in a power switch circuit when laying out the power switch circuit in a determined size.

[0006] In one aspect of the present invention, the semiconductor device includes a substrate having a first surface and a second surface facing the first surface, a first power line formed on the second surface, a second power line formed on the second surface, a third power line formed on the second surface, a first signal line formed on the second surface, a first semiconductor layer, a second semiconductor layer, and a first gate electrode formed on the first surface and arranged in a first direction in a plan view, a first transistor electrically provided between the first power line and the second power line, a power switch circuit having the first transistor, and a first via formed on the substrate and connecting the first signal line and the lower surface of the first gate electrode, wherein the first via is positioned offset from the first semiconductor layer and the second semiconductor layer in a second direction different from the first direction in a plan view.

[0007] According to the disclosed technology, vias can be appropriately placed in a power switch circuit when laying out a power switch circuit to a predetermined size.

[0008] This is a plan view showing an example of the layout of a semiconductor device in each embodiment. This is a circuit diagram showing an example of a circuit arranged in the standard cell block of Figure 1. This is a diagram showing a legend of the circuit elements used in the plan views of the circuits described below. This is a plan view showing an example of the circuit layout of the bottom layer in the region where the power switch circuit of Figure 2 is formed in the semiconductor device of the first embodiment. This is a plan view showing an example of the circuit layout of the top layer formed on top of the bottom layer circuit of Figure 4. This is a cross-sectional view showing an example of a cross section along the line Y1-Y1' in Figures 4 and 5. This is a cross-sectional view showing an example of a cross section along the line Y2-Y2' in Figures 4 and 5. This is a cross-sectional view showing an example of a cross section along the line X1-X1' in Figures 4 and 5. This is a cross-sectional view showing an example of a cross section along the line X2-X2' in Figures 4 and 5. This is a plan view showing a modified version of Figure 4. This is a plan view showing a modified version of Figure 5. This is a plan view showing an example of the circuit layout of the bottom layer in the region where the power switch circuit of Figure 2 is formed in the semiconductor device of the second embodiment. This is a plan view showing an example of the circuit layout of the top layer formed on top of the bottom layer circuit of Figure 12. This is a plan view showing an example of the circuit layout of the bottom layer in the region where the power switch circuit of Figure 2 is formed in the semiconductor device of the third embodiment. This is a plan view showing an example of the circuit layout of the top layer formed on top of the bottom layer circuit of Figure 14. This is a plan view showing a modified example of Figure 14. This is a plan view showing a modified example of Figure 15.

[0009] The embodiments will be described below with reference to the drawings. In the following, symbols indicating signals will also be used to indicate signal lines or signal terminals. Symbols indicating power supply potential will also be used to indicate power lines or power supply terminals to which power supply potential is supplied. Note that the plan and cross-sectional views used in the following description may be simplified, and the shape, size, thickness, positional relationships, etc. of the components in the drawings may differ from the actual configuration.

[0010] Figure 1 shows an example of the layout of a semiconductor device in each embodiment. For example, the semiconductor device 100 shown in Figure 1 may be a SoC (System on Chip), or a standalone FPGA (Field-Programmable Gate Array), etc.

[0011] The semiconductor device 100 has a plurality of I / O cells IOC, IOCP and an internal circuit region INTR. The I / O cell IOC is an interface circuit for signals SGNL such as input signals, output signals, or input / output signals. The I / O cell IOCP is an interface circuit for power supply potential or ground potential.

[0012] Each I / O cell IOC, IOCP is connected to the internal circuit region INTR. For example, the internal circuit region INTR has one or more standard cell blocks SCB, where standard cells are provided. The internal circuit region INTR may also contain logic circuits other than standard cells, and may contain memory. The memory may be contained within the standard cell block SCB.

[0013] Figure 2 shows an example of the circuitry arranged in the standard cell block SCB of Figure 1. The standard cell block SCB has a power switch circuit PSW and a standard cell SC. The standard cell SC is connected to the virtual power line VVDD and the ground line VSS, and operates by receiving the virtual power potential VVDD from the virtual power line VVDD. The standard cell SC has various logic circuits.

[0014] The power switch circuit PSW is connected to the power line TVDD and the ground line VSS, and operates by receiving the power potential TVDD supplied to the power line TVDD and the ground potential VSS supplied to the ground line VSS. The power switch circuit PSW has a control circuit CNTL and a switch transistor SWT. For example, the control circuit CNTL has inverters INV1 and INV2 connected in order between the input signal line IN and the output signal line OUT via a control signal line SWCNT. Inverter INV1 receives the input signal IN and generates the control signal line SWCNT. Inverter INV2 receives the control signal line SWCNT and generates the output signal OUT.

[0015] Power line TVDD is an example of either the first power line or the second power line, and virtual power line VVDD is an example of the other of the first power line or the second power line. Ground line VSS is an example of a third power line. Control signal line SWCNT is an example of a first signal line.

[0016] A switch transistor (SWT) has a PMOS transistor whose source is connected to the power line TVDD and whose drain is connected to the virtual power line VVDD, and operates by receiving the potential of the control signal SWCNT from the control circuit CNTL as its gate potential. The switch transistor (SWT) is an example of a first transistor.

[0017] While the switch transistor SWT is ON, the power line TVDD and the virtual power line VVDD are electrically connected, and the power potential TVDD is supplied to the standard cell SC via the virtual power line VVDD. While the switch transistor SWT is OFF, the electrical connection between the power line TVDD and the virtual power line VVDD is interrupted, and the virtual power line VVDD is set to a floating state.

[0018] Figure 3 shows the legend for the circuit elements used in the plan view of the circuit described below. In the legend, various vias are shown as solid lines, but in the plan views shown from Figure 4 onward, vias that are hidden by wiring or semiconductor layers placed above them are shown as dashed lines.

[0019] (First Embodiment) Figure 4 shows an example of the circuit layout of the bottom layer BTM in the region where the power switch circuit PSW in Figure 2 is formed in the semiconductor device 100 of the first embodiment. The bottom layer BTM is provided on the substrate SUB and is the layer on which the bottom semiconductor layer and bottom wiring BTMW are formed. In Figure 4, for the sake of clarity, the wiring of the wiring layer BSM1 and wiring layer BSM2 formed on the back surface of the substrate SUB is also shown. Hereinafter, the wiring layer BSM1 and wiring layer BSM2 will also be referred to as the BSM1 layer and the BSM2 layer, respectively.

[0020] In the example shown in Figure 4, a PMOS transistor is formed in the bottom layer BTM, which includes a P-type semiconductor layer Pdiff, which is the bottom semiconductor layer. The symbols S and D in the semiconductor layer Pdiff represent the source and drain, respectively. Note that in the plan views from Figure 4 onward, the positions of vias that overlap in the plan view may be shifted to make them easier to identify.

[0021] The BSM1 layer (BSM stands for Back Side Metal) is provided on the back surface of the substrate SUB via an insulating film. The wiring formed on the BSM1 layer can be spaced apart in the Y direction and extends in the X direction. In the example shown in Figure 4, the ground wire VSS, virtual power line VVDD, power line TVDD, control signal line SWCNT, virtual power line VVDD, and ground wire VSS are arranged in this order in the Y direction on the BSM1 layer.

[0022] On the side of the BSM1 layer opposite the substrate SUB, another wiring layer, the BSM2 layer, is provided. The wiring formed on the BSM2 layer can be spaced apart in the X direction and extends in the Y direction. The surface of the substrate SUB is an example of a first surface, and the back surface of the substrate SUB is an example of a second surface opposite the first surface. The X direction is an example of a first direction, and the Y direction is an example of a second direction.

[0023] For example, the power switch circuit PSW is predetermined to be placed within a range of two interval rows aligned in the Y direction. Note that the number of interval rows in which the power switch circuit PSW is placed is not limited to two, but may be three or more. An interval row indicates the reference width in the Y direction in the standard cell block SCB in Figure 2, where the standard cell SC is placed. Hereafter, the range indicated by each interval row will also be referred to as a region row. In Figure 4, three BSM1 layer wirings can be placed in each region row in the Y direction, and a total of six BSM1 layer wirings can be placed in the Y direction by combining two region rows.

[0024] In the region of the power switch circuit PSW, the switch transistor SWT has a gate electrode GT and a plurality of PMOS transistors, each containing a source S and a drain D adjacent to the gate electrode GT in the X direction. In Figure 4, the switch transistor SWT has four PMOS transistors aligned in the X direction for each region row, and two PMOS transistors aligned in the Y direction using two region rows.

[0025] Two adjacent PMOS transistors, arranged in the X direction, share a common source S. Two PMOS transistors, arranged in the Y direction, share a common gate electrode GT. That is, two PMOS transistors arranged in the Y direction are integrally formed. The gate electrode GT of each PMOS transistor is located between the source S and drain D of the switch transistor SWT, arranged in the X direction, in a plan view. The source S of the PMOS transistors of the switch transistor SWT is an example of either the first semiconductor layer or the second semiconductor layer. The drain D of the PMOS transistors of the switch transistor SWT is an example of either the first semiconductor layer or the other semiconductor layer.

[0026] In Figure 4, the source S and drain D are in contact with the gate electrode GT. However, in an actual layout, as shown in Figure 8, there is a gap between the source S and drain D and the gate electrode GT, and these gaps are electrically isolated by an insulating film or the like.

[0027] As shown in Figure 2, the switch transistor SWT is electrically positioned between the power supply line TVDD and the virtual power supply line VVDD. The source S of the PMOS transistor of the switch transistor SWT is connected to the power supply line TVDD formed in the BSM1 layer via the bottom wiring BTMW and via VIA2. The bottom wiring BTMW connected to the source S of the PMOS transistor of the switch transistor SWT is an example of a first or second wiring. The via VIA2 connected to the source S of the PMOS transistor of the switch transistor SWT via the bottom wiring BTMW is an example of a third via.

[0028] The virtual power line VVDD of the BSM1 layer is formed in the PMOS transistor of the switch transistor SWT at a position that overlaps in a plan view with the source S, drain D, and gate electrode GT, which are aligned in the X direction. This allows the drain D of the PMOS transistor of the switch transistor SWT to be directly connected to via VIA2 (Direct Contact, hereafter DC). In this case, the drain D and via VIA2 are positioned to overlap in a plan view. Via VIA2 connected to the drain D of the PMOS transistor of the switch transistor SWT is an example of a second via.

[0029] The via VIA2 connected to the gate electrode GT of the PMOS transistor of the switch transistor SWT is positioned in a location offset in the Y direction in a plan view relative to the source S and drain D of the PMOS transistor of the switch transistor SWT, and is positioned in a location that overlaps in a plan view with the control signal line SWCNT of the BSM1 layer. This allows via VIA2, which is connected to the control signal line SWCNT of the BSM1 layer located below the gate electrode GT, to be directly connected to the gate electrode GT of the PMOS transistor of the switch transistor SWT (Direct Gate Contact, hereafter DGC). The gate electrode GT of the switch transistor SWT is an example of a first gate electrode. The via VIA2 connected to the gate electrode GT of the switch transistor SWT is an example of a first via.

[0030] In the first embodiment, via VIA2 can be arranged that is directly connected to the drain D of the PMOS transistor of the switch transistor SWT (DC) and connected to the virtual power line VVDD of the BSM1 layer, while also being arranged that is directly connected to the gate electrode GT of the switch transistor SWT (DGC) and connected to the control signal line SWCNT of the BSM1 layer. This allows for the appropriate arrangement of via VIA2 in the power switch circuit PSW when laying out the power switch circuit PSW in two regions Row of a predetermined size.

[0031] In the region of the control circuit CNTL, PMOS transistors for inverters INV1 and INV2 are formed. The sources S of the PMOS transistors of inverters INV1 and INV2 are connected to the power line TVDD of the BSM1 layer via a common bottom trace BTMW and via VIA2. The gate electrode GT of inverter INV1 is connected to the input signal line IN, as shown in Figure 5.

[0032] The drain D of the PMOS transistor of inverter INV1 is connected via via VIA3 to the drain D of the NMOS transistor of inverter INV1 shown in Figure 5. Furthermore, the drain D of the PMOS transistor of inverter INV1 is connected via the bottom wiring BTMW and via VIA2 to the control signal line SWCNT of the BSM1 layer, which extends to the switch transistor SWT.

[0033] Furthermore, the control signal line SWCNT of the BSM1 layer is connected to the gate electrode GT of the inverter INV2 via via VIA1, wiring of the BSM2 layer, via VIA1, wiring of the BSM1 layer, and via VIA2 (DGC). The gate electrode GT of the inverter INV2 is an example of a second gate electrode. Via VIA2 connected to the gate electrode GT of the inverter INV2 is an example of a fourth via. The wiring of the BSM1 layer connected to the gate electrode GT of the inverter INV2 via via VIA2 is an example of a third wiring.

[0034] As shown in Figure 4, via VIA2 connected to the gate electrode GT of inverter INV2 is connected to the control signal line SWCNT of the BSM1 layer at a position offset in the Y direction from the source S and drain D of the PMOS transistor of inverter INV2. This allows for the placement of a via VIA2 (DGC) that directly connects the gate electrode GT of inverter INV2 to the control signal line SWCNT of the BSM1 layer, while positioning the virtual power supply line VVDD of the BSM1 layer to overlap with the drain D of the PMOS transistor of inverter INV2 in a plan view. Power supply lines TVDD of the BSM1 layer are positioned on both sides in the X direction of the control signal line SWCNT of the BSM1 layer that is connected to the gate electrode GT of inverter INV2 via via VIA2.

[0035] The drain D of the PMOS transistor of inverter INV2 is connected via via VIA3 to the drain D of the NMOS transistor of inverter INV2 shown in Figure 5. The drain D of the PMOS transistor of inverter INV2 is an example of the third semiconductor layer or the other of the fourth semiconductor layer. The source S of the PMOS transistor of inverter INV2 is an example of the third semiconductor layer or the other of the fourth semiconductor layer.

[0036] In Figure 4, an example is shown in which a virtual power line VVDD of the BSM1 layer is placed below the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT, and the drain D of the PMOS transistor and the virtual power line VVDD of the BSM1 layer are connected via via VIA2 (DC). However, a power line TVDD of the BSM1 layer may also be placed below the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT, and the source S of the PMOS transistor and the power line TVDD of the BSM1 layer may be connected via via VIA2 (DC).

[0037] In Figures 12, 14, and 16, which will be described later, the power line TVDD of the BSM1 layer may be placed below the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT, and the source S of the PMOS transistor and the power line TVDD of the BSM1 layer may be connected via via VIA2 (DC).

[0038] Figure 5 shows an example of the circuit layout of the top layer TOP, which is formed on top of the bottom layer BTM circuit in Figure 4. The top layer TOP is located above the bottom layer BTM and is the layer on which the top semiconductor layer and top wiring TOPW are formed. A CFET (Complementary Field Effect Transistor) is formed by the semiconductor layer Pdiff formed on the bottom layer BTM and the semiconductor layer Ndiff formed on the top layer TOP. In Figure 5, for the sake of clarity, the wiring of the BSM1 and BSM2 layers formed on the back surface of the substrate SUB, and the wiring of the wiring layer FSM1 (FSM stands for Front Side Metal) formed above the top layer TOP are also shown. Hereafter, the wiring layer FSM1 will also be referred to as the FSM1 layer.

[0039] In the example shown in Figure 5, an NMOS transistor is formed on the top layer TOP, which includes an N-type semiconductor layer Ndiff, which is the top semiconductor layer. The NMOS transistor is an example of a second type of transistor. The symbols S and D shown on the semiconductor layer Ndiff indicate the source and drain, respectively. The semiconductor layer Ndiff without either the symbols S or D indicates that it does not function as a transistor. For example, the semiconductor layer Ndiff of the NMOS transistor formed in the region corresponding to the switch transistor SWT shown in Figure 4 does not function as an NMOS transistor. The N-type semiconductor layer Ndiff formed in the region corresponding to the switch transistor SWT is connected to the ground wire VSS formed on the BSM1 layer via the top wiring TOPW.

[0040] NMOS transistors for inverters INV1 and INV2 are formed in the region of the control circuit CNTL. The sources S of the NMOS transistors for inverters INV1 and INV2 are connected to the ground line VSS of the BSM1 layer via the top wiring TOPW and via VIA2, respectively. The gate electrode GT of inverter INV1 is connected to the input signal line IN formed in the FSM1 layer via VIA4.

[0041] The gate electrode GT of the inverter INV2 is connected to the drains D of the PMOS transistor and the NMOS transistor of the inverter INV1 from which the control signal line SWCNT is output, via vias VIA2, wiring of the BSM1 layer, via VIA1, wiring of the BSM2 layer, etc. The drain D of the PMOS transistor of the inverter INV2 is connected to the output signal line OUT formed in the FSM1 layer via the via VIA4.

[0042] In FIG. 5, the gate electrode GT of the inverter INV1 is connected to the input signal line IN of the FSM1 layer via the via VIA4, and the gate electrode GT of the inverter INV2 is connected to the drain D of the inverter INV1 via the via VIA2 (DGC). Thereby, for example, it is possible to facilitate the manufacture of the power switch circuit PSW as compared with the case where DGCs are provided for both of the gate electrodes GT of the inverters INV1 and INV2.

[0043] FIG. 6 shows an example of a cross section along the line Y1 - Y1' of FIGS. 4 and 5 (FIG. 6(a)). In the cross-sectional views shown after FIG. 6, regions where wirings and vias are not formed have an interlayer insulating film. In the inverter INV1 of the control circuit CNTL, the drains D (Ndiff) of the NMOS transistors and the drains D (Pdiff) of the PMOS transistors, which are interconnected via the via VIA3, are connected to the control signal line SWCNT of the BSM2 via the bottom wiring BTMW, via VIA2, the control signal line SWCNT of the BSM1 layer, and via VIA1.

[0044] In the inverter INV2 of the control circuit CNTL, the drains D (Ndiff) of the NMOS transistors and the drains D (Pdiff) of the PMOS transistors, which are interconnected via the via VIA3 and output the output signal OUT, are connected to the output signal line OUT formed in the FSM1 layer via the via VIA4.

[0045] Note that in FIG. 6(a), the drain D (Ndiff) of the NMOS transistor and the drain D (Pdiff) of the PMOS transistor are interconnected via via VIA3. However, as shown in FIG. 6(b), the drain D of the NMOS transistor and the drain D of the PMOS transistor may be interconnected via top wiring TOPW, via VIA3, and bottom wiring BTMW.

[0046] Also, as shown in FIG. 6(c), the drain D of the NMOS transistor and the drain D of the PMOS transistor may be interconnected via top wiring TOPW, conductor COND, and bottom wiring BTMW. For example, the conductor COND is connected to the side portions of the top wiring TOPW and the bottom wiring BTMW and extends in the Z direction. Further, the formation of the top wiring TOPW and the bottom wiring BTMW may be omitted, and the conductor COND may be directly connected to the drain D of the NMOS transistor and the drain D of the PMOS transistor.

[0047] FIG. 7 shows an example of a cross-section along the Y2 - Y2' line in FIGS. 4 and 5. The gate electrode GT and the gate insulating film (not shown) are formed so as to surround the nanosheet NS that interconnects the source S and the drain D of the switch transistor SWT that does not appear in the cross-section of FIG. 7. The gate insulating film is formed around the nanosheet NS to electrically separate the gate electrode GT and the nanosheet NS.

[0048] Also, one end of via VIA2 such as TSV (Through Silicon Via) formed in the substrate SUB is directly connected (DGC) to the lower surface of the gate electrode GT, and the other end of via VIA2 is connected to the control signal line SWCNT of the BSM1 layer. Then, the on / off of the switch transistor SWT (PMOS) is controlled by the control signal SWCNT transmitted from the back surface of the substrate SUB to the gate electrode GT via via VIA2, and the on / off of the supply of the power voltage to the virtual power line VVDD is controlled.

[0049] Figure 8 shows an example of a cross-section along the line X1-X1' in Figures 4 and 5. The P-type semiconductor layer Pdiff formed in the bottom layer BTM functions as the source S or drain D of a PMOS transistor. The semiconductor layer Ndiff of the control circuit CNTL formed in the top layer TOP functions as the source S or drain D of an NMOS transistor.

[0050] In the bottom layer BTM, the P-type semiconductor layers Pdiff, positioned on both sides of the gate electrode GT, are interconnected via nanosheets NS that penetrate the gate electrode GT. Similarly, in the top layer TOP, the N-type semiconductor layers Ndiff, positioned on both sides of the gate electrode GT, are interconnected via nanosheets NS that penetrate the gate electrode GT. Within the gate electrode GT, the nanosheets NS are surrounded by a gate insulating film (not shown) and are electrically isolated from the gate electrode GT.

[0051] In the switch transistor SWT, via VIA2, located below the drain D of the PMOS transistor and connected to the virtual power line VVDD of the BSM1 layer, is directly connected to the drain D (DC). In the control circuit CNTL, the gate electrode GT of the inverter INV1 is connected to the input signal line IN formed on the FSM1 layer via via VIA4. In the switch transistor SWT, the drain D of the PMOS transistor is electrically connected to the virtual power line VVDD of the BSM1 layer located below the drain D via via VIA2 formed on the substrate SUB.

[0052] Figure 9 shows an example of a cross-section along the line X2-X2' in Figures 4 and 5. As explained in Figure 7, one end of via VIA2 is directly connected to the underside of the gate electrode GT of the switch transistor SWT (DGC), and the other end of via VIA2 is connected to the control signal line SWCNT of the BSM1 layer.

[0053] In the control circuit CNTL, one end of via VIA2 is connected to the underside of bottom wiring BTMW, which is connected to the drain D (not shown) of the PMOS transistor of inverter INV1, and the other end of via VIA2 is connected to the control signal line SWCNT of the BSM1 layer. Furthermore, the control signal line SWCNT of the BSM1 layer is connected to the control signal line SWCNT of the BSM2 layer via via VIA1.

[0054] The control signal SWCNT output from inverter INV1 is supplied to the gate electrode GT of switch transistor SWT via the control signal line SWCNT of the BSM1 layer, thereby controlling the on / off state of switch transistor SWT. Furthermore, the control signal SWCNT output from inverter INV1 is supplied to the gate electrode GT of inverter INV2 (not shown) via the control signal line SWCNT of the BSM2 layer.

[0055] Figure 10 shows a modified version of Figure 4. Elements similar to those in Figures 4 and 5 are given the same reference numerals, and detailed explanations are omitted. In Figure 10, an NMOS transistor is formed in the bottom layer BTM. Also, the arrangement of the power lines TVDD, virtual power lines VVDD, ground line VSS, and control signal lines SWCNT in the BSM1 layer differs from that in Figure 4.

[0056] In Figure 10, the ground wire VSS of the BSM1 layer is formed below the semiconductor layer Ndiff, which is the bottom semiconductor layer, in the region where the switch transistor SWT is formed. The lower surface of the semiconductor layer Ndiff is directly connected (DC) to one end of via VIA2. The other end of via VIA2 is connected to the ground wire VSS of the BSM1 layer. The semiconductor layer Ndiff is then connected to the ground wire VSS of the BSM1 layer via via VIA2.

[0057] The sources S of the NMOS transistors of inverters INV1 and INV2 in the control circuit CNTL are directly connected (DC) to via VIA2, and via VIA2 to the ground wire VSS of the BSM1 layer.

[0058] Figure 11 shows a modified example of Figure 5. Elements similar to those in Figures 4 and 5 are given the same reference numerals, and detailed explanations are omitted. Figure 11 differs from Figure 5 in that a PMOS transistor is formed on the top layer (TOP).

[0059] In a switch transistor (SWT), the drain D of the PMOS transistor in the top semiconductor layer is connected to the virtual power line VVDD of the BSM1 layer via the top wiring TOPW and via VIA2. Similar to Figure 4, the source S of the PMOS transistor in the switch transistor (SWT) is connected to the power line TVDD of the BSM1 layer via the top wiring TOPW and via VIA2.

[0060] In the first embodiment described above, the virtual power line VVDD of the BSM1 layer is positioned to overlap with the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT in a plan view. In addition, the control signal line SWCNT of the BSM1 layer, which is connected to the gate electrode GT, is positioned to be offset from the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT in a plan view.

[0061] This allows for the placement of via VIA2 (DC), which directly connects the drain D of the PMOS transistor of the switch transistor SWT to the virtual power line VVDD of the BSM1 layer, while also allowing for the placement of via VIA2 (DGC), which directly connects the gate electrode GT of the switch transistor SWT to the control signal line SWCNT of the BSM1 layer. As a result, when laying out the power switch circuit PSW in two regions Row of a predetermined size, via VIA2 can be appropriately placed in the power switch circuit PSW.

[0062] (Second Embodiment) Figure 12 shows an example of the circuit layout of the bottom layer BTM in the region where the power switch circuit PSW in Figure 2 is formed in the semiconductor device 100 of the second embodiment. The same reference numerals are used for elements similar to those in Figure 4, and detailed explanations are omitted.

[0063] In the first embodiment, the grounding wire VSS is located on both sides of the BSM1 layer in the Y direction, while in the second embodiment, it is located in the center of the Y direction and shared by the two region rows. By sharing the grounding wire VSS of the BSM1 layer between the two region rows, the number of BSM1 layer wires located in the two region rows can be reduced from six in the first embodiment to five. This allows for a reduction in the circuit width in the Y direction compared to the first embodiment, and thus reduces the circuit size of the power switch circuit PSW in the Y direction.

[0064] The control signal line SWCNT of the BSM1 layer, which transmits the control signal SWCNT from the control circuit CNTL to the gate electrode GT of the switch transistor SWT, is located on the upper side in the Y direction of the region where the inverter INV1 is formed in a plan view. The source S of the PMOS transistor of the switch transistor SWT is connected to the power line TVDD of the BSM1 layer, which is located on the lower side in the Y direction in a plan view, via the bottom wiring BTMW and via VIA2.

[0065] In the control circuit CNTL, the drain D of the PMOS transistor of inverter INV1 is connected to the gate electrode GT of inverter INV2 via the bottom wiring BTMW, via VIA2, wiring of the BSM1 layer (SWCNT), via VIA1, wiring of the BSM2 layer, via VIA1, wiring of the BSM1 layer, and via VIA2. In the control circuit CNTL, the sources S of the PMOS transistors of inverters INV1 and INV2 are connected to the power lines TVDD of the BSM1 layer, which are located on both sides in the Y direction in a plan view, via the bottom wiring BTMW and via VIA2.

[0066] Figure 13 shows an example of the circuit layout of the top layer TOP formed on top of the bottom layer BTM circuit in Figure 12. The same reference numerals are used for elements similar to those in Figure 5, and detailed explanations are omitted. In the region corresponding to the switch transistor SWT, two semiconductor layers Ndiff arranged side by side in the Y direction are interconnected via top wiring TOPW. Of the multiple top wirings TOPW connected to each of the two semiconductor layers Ndiff arranged in the Y direction, the top wirings TOPW that do not overlap with the bottom wiring BTMW in Figure 12 in a plan view are connected to the ground wire VSS of the BSM1 layer via via VIA2.

[0067] Of the multiple top wirings TOPW connected to the two semiconductor layers Ndiff aligned in the Y direction, the top wirings TOPW that overlap with the bottom wiring BTMW in Figure 12 in a plan view are not connected to via VIA2, and are therefore set to a floating state together with the semiconductor layers Ndiff to which these top wirings TOPW are connected. However, for example, wiring of an FSM1 layer (not shown) extending in the X direction on the semiconductor layer Ndiff may be formed and connected to each semiconductor layer Ndiff via via VIA4, thereby electrically connecting all semiconductor layers Ndiff of the switch transistor SWT to the ground line VSS.

[0068] In the control circuit CNTL, the source S of the NMOS transistor of inverter INV1 is connected to the ground wire VSS of the BSM1 layer, which is located in the center in the Y direction, via a common top trace TOPW and via VIA2.

[0069] In the second embodiment, unlike the first embodiment, the control signal line SWCNT and power line TVDD arranged on the BSM1 layer are not adjacent in the Y direction, but they may be arranged adjacent in the Y direction. Also, in the second embodiment, as shown in the modified examples in Figures 10 and 11, an NMOS transistor may be formed on the bottom layer BTM and a PMOS transistor may be formed on the top layer TOP.

[0070] As described above, in the second embodiment as in the first embodiment, via VIA2 can be arranged that is directly connected to the drain D of the PMOS transistor of the switch transistor SWT (DC) and connected to the virtual power line VVDD of the BSM1 layer, while also being arranged that is directly connected to the gate electrode GT of the switch transistor SWT (DGC) and connected to the control wiring SWCNT of the BSM1 layer. This makes it possible to appropriately arrange via VIA2 in the power switch circuit PSW when laying out the power switch circuit PSW in two regions Row of a predetermined size.

[0071] Furthermore, in the second embodiment, by positioning the grounding wire VSS of the BSM1 layer in the center in the Y direction and sharing it between the two region Rows, the number of BSM1 layer wires arranged in the two region Rows can be reduced from six in the first embodiment to five. As a result, the circuit width in the Y direction can be reduced compared to the first embodiment, and the circuit size of the power switch circuit PSW in the Y direction can be reduced.

[0072] (Third Embodiment) Figure 14 shows an example of the circuit layout of the bottom layer BTM in the region where the power switch circuit PSW in Figure 2 is formed in the semiconductor device 100 of the third embodiment. The same reference numerals are used for elements similar to those in Figure 4, and detailed explanations are omitted.

[0073] Figure 14 differs from other embodiments in that, in the BSM1 layer, the power line TVDD is located on the central side in the X direction, and the grounding lines VSS are located on both sides of the power line TVDD in the X direction. Because the power line TVDD is located on the central side in the X direction, the positions of the source S and drain D of the PMOS transistors in inverters INV1 and INV2 of the control circuit CNTL are swapped compared to Figure 4.

[0074] In the region of the switch transistor SWT, a power line TVDD is placed on the lower side in the Y direction using a BSM1 layer. The power line TVDD of the BSM1 layer placed on the lower side in the Y direction is connected to the source S of the PMOS transistor of the switch transistor SWT located in the lower region Row in the Y direction via via VIA2 and bottom wiring BTMW. As a result, the power supply potential TVDD can be supplied to the source S of the PMOS transistor of the switch transistor SWT by the two power lines TVDD extending in the X direction, thereby reducing the power supply resistance and improving the power supply capability to the virtual power line VVDD.

[0075] Figure 15 shows an example of the circuit layout of the top layer TOP, which is formed on top of the bottom layer BTM circuit in Figure 14. The same reference numerals are used for elements similar to those in Figure 5, and detailed explanations are omitted. In Figure 15, the positions of the source S and drain D of the NMOS transistors in inverters INV1 and INV2 of the control circuit CNTL are swapped compared to Figure 5.

[0076] In the third embodiment, as shown in the modified examples in Figures 10 and 11, an NMOS transistor may be formed in the bottom layer BTM and a PMOS transistor may be formed in the top layer TOP.

[0077] Figure 16 shows a modified example of Figure 14. Elements similar to those in Figures 4 and 14 are denoted by the same reference numerals, and detailed explanations are omitted. In Figure 16, similar to the second embodiment (Figure 12), five wirings of the BSM1 layer are arranged in two regions, Row.

[0078] The control signal line SWCNT of the BSM1 layer, which supplies the control signal SWCNT from the control circuit CNTL to the gate electrode GT of the switch transistor SWT, is located on the lower side in the Y direction of the region where the inverter INV2 is formed in a plan view. The gate electrode GT of the switch transistor SWT is then connected to the control signal line SWCNT of the BSM1 layer via via VIA2 on the lower side in the Y direction (DGC).

[0079] Figure 17 shows a modified example of Figure 15. Elements similar to those in Figures 5 and 15 are denoted by the same reference numerals, and detailed explanations are omitted. The semiconductor layer Ndiff, which is the drain D (SWCNT) of the PMOS transistor of inverter INV1, is connected to the wiring of the FSM2 layer extending in the Y direction via via VIA4, the wiring of the FSM1 layer, and via VIA5. The FSM2 layer is a wiring layer located above the FSM1 layer.

[0080] The FSM2 layer wiring is connected to the gate electrode GT of inverter INV2 via via VIA5, FSM1 layer wiring, and via VIA4. Furthermore, the FSM2 layer wiring is connected to the BSM1 layer control signal line SWCNT via via VIA5, FSM1 layer wiring, via VIA4, top wiring TOPW, and via VIA2.

[0081] As described above, in the third embodiment, as in the first embodiment, via VIA2 can be arranged that is directly connected to the drain D of the PMOS transistor of the switch transistor SWT (DC) and connected to the virtual power line VVDD of the BSM1 layer, while also being arranged that is directly connected to the gate electrode GT of the switch transistor SWT (DGC) and connected to the control wiring SWCNT of the BSM1 layer. This allows for the appropriate arrangement of via VIA2 in the power switch circuit PSW when laying out the power switch circuit PSW in two regions Row of a predetermined size.

[0082] Furthermore, in the third embodiment, a plurality of power lines TVDD of the BSM1 layer arranged in the region of the switch transistor SWT can supply the power potential TVDD to the source S of the PMOS transistor of the switch transistor SWT, thereby reducing the power supply resistance and improving the power supply capability to the virtual power line VVDD.

[0083] Furthermore, as shown in Figures 16 and 17, by positioning the power line TVDD of the BSM1 layer in the center in the Y direction and sharing it between the two regions Row, the number of BSM1 layer wires arranged in the two regions Row can be reduced from six in the first embodiment to five. As a result, the circuit width in the Y direction can be reduced compared to the first embodiment, and the circuit size of the power switch circuit PSW in the Y direction can be reduced.

[0084] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application.

[0085] 100 Semiconductor device BSM1, BSM2 Wiring layer BTM Bottom layer BTMW Bottom wiring COND Conductor CNTL Control circuit D Drain FSM1, FSM2 Wiring layer GT Guard gate IN Input signal line INTR Internal circuit region INV1, INV2 Inverter IOC, IOCP I / O cell Ndiff Semiconductor layer NS Nanosheet OUT Output signal line Pdiff Semiconductor layer PSW Power switch circuit Row Spacing S Source SC Standard cell SCB Standard cell block SGNL Signal SUB Substrate SWCNT Control signal SWT Switch transistor TOP Top layer TOPW Top wiring TVDD Power line VIA1, VIA2, VIA3, VIA4, VIA5 Via VSS Grounding wire VVDD Virtual power line

Claims

1. A semiconductor device comprising: a substrate having a first surface and a second surface facing the first surface; a first power line formed on the second surface; a second power line formed on the second surface; a third power line formed on the second surface; a first signal line formed on the second surface; a first transistor having a first semiconductor layer, a second semiconductor layer, and a first gate electrode formed on the first surface and arranged in a first direction in a plan view, and electrically provided between the first power line and the second power line; a power switch circuit having the first transistor; and a first via formed on the substrate and connecting the first signal line and the lower surface of the first gate electrode, wherein the first via is positioned in a second direction different from the first direction in a plan view from the first semiconductor layer and the second semiconductor layer.

2. The semiconductor device according to claim 1, having a second via formed on the substrate, which connects the lower surface of one of the first semiconductor layer or the second semiconductor layer to the first power line or the second power line.

3. The semiconductor device according to claim 2, comprising: a first wiring connected to the other of the first semiconductor layer or the second semiconductor layer; and a third via formed on the substrate and connecting the first wiring to the first power line, wherein the second via connects the one of the first semiconductor layer or the second semiconductor layer to the second power line.

4. The semiconductor device according to claim 1, wherein the power switch circuit has a plurality of the first transistors arranged in the second direction.

5. The semiconductor device according to claim 4, comprising a plurality of the second power lines and a plurality of the third power lines.

6. The semiconductor device according to claim 4, having a second wiring extending in the second direction and connecting the first semiconductor layers of a plurality of the first transistors, or a second wiring connecting the second semiconductor layers of a plurality of the first transistors.

7. The semiconductor device according to any one of claims 1 to 6, wherein the power switch circuit has a control circuit for controlling the first transistor, the control circuit having a second transistor having a third semiconductor layer, a fourth semiconductor layer, and a second gate electrode arranged in a first direction in a plan view, and a fourth via positioned offset in a second direction in a plan view relative to the third and fourth semiconductor layers, and connecting the lower surface of the second gate electrode to a third wiring formed on the second surface.

8. The semiconductor device according to claim 7, wherein the second gate electrode is electrically connected to the first signal line.

9. The semiconductor device according to claim 1, wherein the first power line, the second power line, the third power line, and the first signal line extend in the first direction.

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