Semiconductor device

Abstract

This semiconductor device comprises: a power switch circuit having a first transistor formed on a first surface of a substrate; first and second power supply lines and a first signal line formed on a second surface of the substrate; and a third power supply line formed on the first transistor. The first transistor has a first semiconductor layer, a second semiconductor layer, and a first gate electrode arranged along a first direction in a plan view. A first via formed in the substrate and connecting the first signal line and the lower surface of the first gate electrode is disposed at a position offset from the first and second semiconductor layers in a second direction different from the first direction in a plan view. Thus, when the power switch circuit is laid out in a determined size, the via can be appropriately disposed in the power switch circuit.

Description

Semiconductor device

[0001] The present invention relates to a semiconductor device.

[0002] There is a power switch circuit that controls the on / off of power supply to circuits such as standard cells. There are DC (Direct Contact) technology and DGC (Direct Gate Contact) technology in which vias are provided on a substrate to directly connect wiring on the back surface of a semiconductor substrate to the source or gate electrode of a transistor on the front surface of the semiconductor substrate, and power and signals are supplied from the back surface of the semiconductor substrate to the transistor.

[0003] U.S. Patent No. 11637067, U.S. Patent No. 11423204, U.S. Patent No. 11107805, U.S. Patent Application Publication No. 2024 / 0266349, U.S. Patent No. 11764154, U.S. Patent No. 11923297, U.S. Patent Application Publication No. 2024 / 0162118, U.S. Patent Application Publication No. 2023 / 0040094, U.S. Patent Application Publication No. 2020 / 0328201

[0004] In the case where power supply lines or the like extend in one direction in a plan view in a standard cell or the like, the arrangement pitch of transistors arranged along a direction intersecting the one direction is defined as "Row". At this time, for example, when power switch circuits are arranged in two Row regions, there has been no consideration of how to arrange DC or DGC.

[0005] The present invention has been made in view of the above points, and an object thereof is to appropriately arrange vias in a power switch circuit when laying out the power switch circuit in a determined size.

[0006] In one aspect of the present invention, the semiconductor device includes a substrate having a first surface and a second surface facing the first surface; a first power line formed on the second surface; a second power line formed on the second surface; a first signal line formed on the second surface; a first transistor formed on the first surface and having a first semiconductor layer, a second semiconductor layer, and a first gate electrode arranged in a first direction in a plan view, and electrically provided between the first power line and the second power line; a third power line formed on the first transistor and extending in the first direction in a plan view; a power switch circuit having the first transistor; and a first via formed on the substrate and connecting the first signal line and the lower surface of the first gate electrode, wherein the first via is positioned offset from the first semiconductor layer and the second semiconductor layer in a second direction different from the first direction in a plan view.

[0007] According to the disclosed technology, vias can be appropriately placed in a power switch circuit when laying out a power switch circuit to a predetermined size.

[0008] This is a plan view showing an example of the layout of a semiconductor device in each embodiment. This is a circuit diagram showing an example of a circuit arranged in the standard cell block of Figure 1. This is a diagram showing a legend of the circuit elements used in the plan views of the circuits described below. This is a plan view showing an example of the circuit layout of the bottom layer in the region where the power switch circuit of Figure 2 is formed in the semiconductor device of the first embodiment. This is a plan view showing an example of the circuit layout of the top layer formed on the bottom layer circuit of Figure 4. This is a cross-sectional view showing an example of a cross section along the line Y1-Y1' in Figures 4 and 5. This is a cross-sectional view showing an example of a cross section along the line X1-X1' in Figures 4 and 5. This is a cross-sectional view showing an example of a cross section along the line X2-X2' in Figures 4 and 5. This is a plan view showing a modified version of Figure 4. This is a plan view showing a modified version of Figure 5. This is a plan view showing an example of the circuit layout of the bottom layer in the region where the power switch circuit of Figure 2 is formed in the semiconductor device of the second embodiment. This is a plan view showing an example of the circuit layout of the top layer formed on the bottom layer circuit of Figure 11.

[0009] The embodiments will be described below with reference to the drawings. In the following, symbols indicating signals will also be used to indicate signal lines or signal terminals. Symbols indicating power supply potential will also be used to indicate power lines or power supply terminals to which power supply potential is supplied. Note that the plan and cross-sectional views used in the following description may be simplified, and the shape, size, thickness, positional relationships, etc. of the components in the drawings may differ from the actual configuration.

[0010] Figure 1 shows an example of the layout of a semiconductor device in each embodiment. For example, the semiconductor device 100 shown in Figure 1 may be a SoC (System on Chip), or a standalone FPGA (Field-Programmable Gate Array), etc.

[0011] The semiconductor device 100 has a plurality of I / O cells IOC, IOCP and an internal circuit region INTR. The I / O cell IOC is an interface circuit for signals SGNL such as input signals, output signals, or input / output signals. The I / O cell IOCP is an interface circuit for power supply potential or ground potential.

[0012] Each I / O cell IOC, IOCP is connected to the internal circuit region INTR. For example, the internal circuit region INTR has one or more standard cell blocks SCB, where standard cells are provided. The internal circuit region INTR may also contain logic circuits other than standard cells, and may contain memory. The memory may be contained within the standard cell block SCB.

[0013] Figure 2 shows an example of the circuitry arranged in the standard cell block SCB of Figure 1. The standard cell block SCB has a power switch circuit PSW and a standard cell SC. The standard cell SC is connected to the virtual power line VVDD and the ground line VSS, and operates by receiving the virtual power potential VVDD from the virtual power line VVDD. The standard cell SC has various logic circuits.

[0014] The power switch circuit PSW is connected to the power line TVDD and the ground line VSS, and operates by receiving the power potential TVDD supplied to the power line TVDD and the ground potential VSS supplied to the ground line VSS. The power switch circuit PSW has a control circuit CNTL and a switch transistor SWT. For example, the control circuit CNTL has inverters INV1 and INV2 connected in order between the input signal line IN and the output signal line OUT via a control signal line SWCNT. Inverter INV1 receives the input signal IN and generates the control signal line SWCNT. Inverter INV2 receives the control signal line SWCNT and generates the output signal OUT.

[0015] Power line TVDD is an example of either the first power line or the second power line, and the power potential TVDD supplied to power line TVDD is an example of the first power potential. Virtual power line VVDD is an example of the other of the first power line or the second power line. Ground line VSS is an example of the third power line, and the ground potential VSS supplied to ground line VSS is an example of the second power potential. Control signal line SWCNT is an example of the first signal line.

[0016] A switch transistor (SWT) has a PMOS transistor whose source is connected to the power line TVDD and whose drain is connected to the virtual power line VVDD, and operates by receiving the potential of the control signal SWCNT from the control circuit CNTL as its gate potential. The switch transistor (SWT) is an example of a first transistor.

[0017] While the switch transistor SWT is ON, the power line TVDD and the virtual power line VVDD are electrically connected, and the power potential TVDD is supplied to the standard cell SC via the virtual power line VVDD. While the switch transistor SWT is OFF, the electrical connection between the power line TVDD and the virtual power line VVDD is interrupted, and the virtual power line VVDD is set to a floating state.

[0018] Figure 3 shows the legend for the circuit elements used in the plan view of the circuit described below. In the legend, various vias are shown as solid lines, but in the plan views shown from Figure 4 onward, vias that are hidden by wiring or semiconductor layers placed above them are shown as dashed lines.

[0019] (First Embodiment) Figure 4 shows an example of the circuit layout of the bottom layer BTM in the region where the power switch circuit PSW in Figure 2 is formed in the semiconductor device 100 of the first embodiment. The bottom layer BTM is provided on the substrate SUB and is the layer on which the bottom semiconductor layer and bottom wiring BTMW are formed. In Figure 4, for the sake of clarity, the wiring of the BSM1 layer and BSM2 layer formed on the back surface of the substrate SUB is also shown.

[0020] In the example shown in Figure 4, a PMOS transistor is formed in the bottom layer BTM, which includes a P-type semiconductor layer Pdiff, which is the bottom semiconductor layer. The symbols S and D in the semiconductor layer Pdiff represent the source and drain, respectively. Note that in the plan views from Figure 4 onward, the positions of vias that overlap in the plan view may be shifted to make them easier to identify.

[0021] The BSM1 layer (BSM stands for Back Side Metal) is a wiring layer provided on the back surface of the substrate SUB via an insulating film. Wiring formed on the BSM1 layer can be spaced apart in the Y direction and extend in the X direction. In the example shown in Figure 4, the power line TVDD, virtual power line VVDD, control signal line SWCNT, virtual power line VVDD, and power line TVDD are arranged in this order in the Y direction on the BSM1 layer. Note that the ground line VSS is not formed on the BSM1 layer, but is formed on the FSM1 layer (FSM stands for Front Side Metal) as shown in Figure 5.

[0022] On the side of the BSM1 layer opposite the substrate SUB, another wiring layer, the BSM2 layer, is provided. The wiring formed on the BSM2 layer can be spaced apart in the X direction and extends in the Y direction. The surface of the substrate SUB is an example of a first surface, and the back surface of the substrate SUB is an example of a second surface opposite the first surface. The X direction is an example of a first direction, and the Y direction is an example of a second direction.

[0023] For example, the power switch circuit PSW is predetermined to be placed within a range of two interval rows aligned in the Y direction. Note that the number of interval rows in which the power switch circuit PSW is placed is not limited to two, but may be three or more. An interval row indicates the reference width in the Y direction in the standard cell block SCB in Figure 2, where the standard cell SC is placed. Hereafter, the range indicated by each interval row will also be referred to as a region row. In Figure 4, three BSM1 layer wirings can be placed in each region row in the Y direction, and a total of six BSM1 layer wirings can be placed in the Y direction by combining two region rows.

[0024] In the region of the power switch circuit PSW, the switch transistor SWT has a gate electrode GT and a plurality of PMOS transistors, each containing a source S and a drain D adjacent to the gate electrode GT in the X direction. In Figure 4, the switch transistor SWT has four PMOS transistors aligned in the X direction for each region row, and two PMOS transistors aligned in the Y direction using two region rows.

[0025] Two adjacent PMOS transistors, arranged in the X direction, share a common source S. Two PMOS transistors, arranged in the Y direction, share a common gate electrode GT. That is, two PMOS transistors arranged in the Y direction are integrally formed. The gate electrode GT of each PMOS transistor is located between the source S and drain D of the switch transistor SWT, arranged in the X direction, in a plan view. The source S of the PMOS transistors of the switch transistor SWT is an example of either the first semiconductor layer or the second semiconductor layer. The drain D of the PMOS transistors of the switch transistor SWT is an example of either the first semiconductor layer or the other semiconductor layer.

[0026] In Figure 4, the source S and drain D are in contact with the gate electrode GT. However, in an actual layout, as shown in Figure 7, there is a gap between the source S and drain D and the gate electrode GT, and these gaps are electrically isolated by an insulating film or the like.

[0027] As shown in Figure 2, the switch transistor SWT is electrically positioned between the power supply line TVDD and the virtual power supply line VVDD. The source S of the PMOS transistor of the switch transistor SWT is connected to the power supply line TVDD formed in the BSM1 layer via the bottom wiring BTMW and via VIA2. The bottom wiring BTMW connected to the source S of the PMOS transistor of the switch transistor SWT is an example of a first wiring. The via VIA2 connected to the source S of the PMOS transistor of the switch transistor SWT via the bottom wiring BTMW is an example of a third via.

[0028] The virtual power line VVDD of the BSM1 layer is formed in the PMOS transistor of the switch transistor SWT at a position that overlaps in a plan view with the source S, drain D, and gate electrode GT, which are aligned in the X direction. This allows the drain D of the PMOS transistor of the switch transistor SWT to be directly connected to via VIA2 located below the drain D (Direct Contact, hereafter DC), and connected to the virtual power line VVDD of the BSM1 layer via via VIA2. In this case, the drain D and via VIA2 are positioned to overlap in a plan view. Via VIA2 connected to the drain D of the PMOS transistor of the switch transistor SWT is an example of a second via.

[0029] The via VIA2 connected to the gate electrode GT of the PMOS transistor of the switch transistor SWT is positioned offset in the Y direction in a plan view relative to the source S and drain D of the PMOS transistor of the switch transistor SWT, and is positioned to overlap in a plan view with the gate electrode GT of the PMOS transistor and the control signal line SWCNT of the BSM1 layer. This allows the gate electrode GT of the PMOS transistor of the switch transistor SWT to be directly connected to the via VIA2 located below the gate electrode GT (Direct Gate Contact, hereafter DGC). The gate electrode GT of the switch transistor SWT is an example of a first gate electrode. The via VIA2 connected to the gate electrode GT of the switch transistor SWT is an example of a first via.

[0030] In the first embodiment, via VIA2 can be arranged that is directly connected to the drain D of the PMOS transistor of the switch transistor SWT (DC) and connected to the virtual power line VVDD of the BSM1 layer, while also being arranged that is directly connected to the gate electrode GT of the switch transistor SWT (DGC) and connected to the control signal line SWCNT of the BSM1 layer. This allows for the appropriate arrangement of via VIA2 in the power switch circuit PSW when laying out the power switch circuit PSW in two regions Row of a predetermined size.

[0031] In the region of the control circuit CNTL, PMOS transistors for inverters INV1 and INV2 are formed. The sources S of the PMOS transistors of inverters INV1 and INV2 are connected to the power line TVDD of the BSM1 layer via the bottom wiring BTMW and via VIA2, respectively. The gate electrode GT of inverter INV1 is connected to the input signal line IN, as shown in Figure 5.

[0032] The drain D of the PMOS transistor of inverter INV1 is connected via via VIA3 to the drain D of the NMOS transistor of inverter INV1 shown in Figure 5. Furthermore, the drain D of the PMOS transistor of inverter INV1 is connected via the bottom wiring BTMW and via VIA2 to the control signal line SWCNT of the BSM1 layer, which extends to the switch transistor SWT. The PMOS transistor of inverter INV1 is an example of a second transistor, and the NMOS transistor of inverter INV1 is an example of a third transistor. The source S of the PMOS transistor of inverter INV1 is an example of either the fifth semiconductor layer or the sixth semiconductor layer, and the drain D of the PMOS transistor of inverter INV1 is an example of the other of the fifth or sixth semiconductor layer. The gate electrode GT of inverter INV1 is an example of a second gate electrode.

[0033] Furthermore, the control signal line SWCNT of the BSM1 layer is connected to the gate electrode GT of the inverter INV2 via via VIA1, wiring of the BSM2 layer, via VIA1, wiring of the BSM1 layer, and via VIA2 (DGC). In the control circuit CNTL and switch transistor SWT, by connecting the control signal line SWCNT via the back surface of the substrate SUB, the wiring on the front surface of the substrate SUB can be reduced.

[0034] As shown in Figure 4, via VIA2 connected to the gate electrode GT of inverter INV2 is connected to the control signal line SWCNT of the BSM1 layer at a position offset in the Y direction relative to the source S and drain D of the PMOS transistor of inverter INV2. This allows for the placement of a via VIA2 (DGC) that directly connects the gate electrode GT of inverter INV2 to the control signal line SWCNT of the BSM1 layer, while positioning the virtual power supply line VVDD of the BSM1 layer to overlap with the drain D of the PMOS transistor of inverter INV2 in a plan view. The power supply line TVDD of the BSM1 layer is located on the switch transistor SWT side of the control signal line SWCNT of the BSM1 layer that is connected to the gate electrode GT of inverter INV2 via via VIA2.

[0035] The drain D of the PMOS transistor of inverter INV2 is connected via via VIA3 to the drain D of the NMOS transistor of inverter INV2 shown in Figure 5. The drain D of the PMOS transistor of inverter INV2 is an example of the third semiconductor layer or the other of the fourth semiconductor layer. The source S of the PMOS transistor of inverter INV2 is an example of the third semiconductor layer or the other of the fourth semiconductor layer.

[0036] In Figure 4, an example is shown in which a virtual power line VVDD of the BSM1 layer is placed below the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT, and the drain D of the PMOS transistor and the virtual power line VVDD of the BSM1 layer are connected via via VIA2 (DC). However, a power line TVDD of the BSM1 layer may also be placed below the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT, and the source S of the PMOS transistor and the power line TVDD of the BSM1 layer may be connected via via VIA2 (DC).

[0037] In Figure 11, which will be described later, the power line TVDD of the BSM1 layer may be placed below the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT, and the source S of the PMOS transistor and the power line TVDD of the BSM1 layer may be connected via via VIA2 (DC).

[0038] Figure 5 shows an example of the circuit layout of the top layer TOP, which is formed on top of the bottom layer BTM circuit in Figure 4. The top layer TOP is located above the bottom layer BTM and is the layer on which the top semiconductor layer and top wiring TOPW are formed. In Figure 5, for the sake of clarity, the wiring of the FSM1 layer formed above the top layer TOP is also shown.

[0039] In the example shown in Figure 5, an NMOS transistor is formed on the top layer TOP, which includes an N-type semiconductor layer Ndiff, which is the top semiconductor layer. A CFET (Complementary Field Effect Transistor) is formed by the semiconductor layer Pdiff formed on the bottom layer BTM and the semiconductor layer Ndiff formed on the top layer TOP. The symbols S and D shown on the semiconductor layer Ndiff indicate the source and drain, respectively. A semiconductor layer Ndiff that does not have either the symbol S or D indicates that it does not function as a transistor. For example, the semiconductor layer Ndiff of the NMOS transistor formed in the region corresponding to the switch transistor SWT shown in Figure 4 does not function as an NMOS transistor. The N-type semiconductor layer Ndiff formed in the region corresponding to the switch transistor SWT is connected to the ground wire VSS formed on the FMS1 layer via via VIA4 located on the semiconductor layer Ndiff.

[0040] NMOS transistors for inverters INV1 and INV2 are formed in the region of the control circuit CNTL. The sources S of the NMOS transistors of inverters INV1 and INV2 are connected via via VIA4 to the ground line VSS formed on the FMS1 layer located above the source S. The gate electrode GT of inverter INV1 is connected via via VIA4 to the input signal line IN formed on the FSM1 layer.

[0041] As explained in Figure 4, the gate electrode GT of inverter INV2 is connected to the drain D of the PMOS transistor and NMOS transistor of inverter INV1, which output the control signal line SWCNT. The drain D of the PMOS transistor of inverter INV2 is connected to the output signal line OUT formed in the FSM1 layer via the top wiring TOPW and via VIA4. The source S of the NMOS transistor of inverter INV1 is an example of one of the seventh semiconductor layer and the eighth semiconductor layer, and the drain D of the NMOS transistor of inverter INV1 is an example of the other of the seventh semiconductor layer and the eighth semiconductor layer.

[0042] In the first embodiment, by disposing the ground line VSS on the surface side of the substrate SUB, the supply of the ground potential VSS to the top layer TOP can be efficiently performed. Further, by disposing the power line TVDD and the virtual power line VVDD on the back surface side of the substrate SUB, the supply of the power supply voltage TVDD and the virtual power supply potential VVDD to the bottom layer BTM can be efficiently performed.

[0043] Also, in FIG. 5, the gate electrode GT of the inverter INV1 is connected to the input signal line IN of the FSM1 layer via the via VIA4, and the gate electrode GT of the inverter INV2 is connected to the drain D of the inverter INV1 via the via VIA2 (DGC). Thereby, for example, compared with the case where DGC is provided for both of the gate electrodes GT of the inverters INV1 and INV2, the power switch circuit PSW can be easily manufactured.

[0044] FIG. 6 shows an example of a cross section along the Y1 - Y1' line of FIGS. 4 and 5 (FIG. 6(a)). In the cross-sectional views shown after FIG. 6, regions where wirings, vias, etc. are not formed have an interlayer insulating film. In the inverter INV1 of the control circuit CNTL, the drains D (Ndiff) of the NMOS transistors and the drains D (Pdiff) of the PMOS transistors, which are interconnected via the via VIA3, are connected to the control signal line SWCNT of the BSM2 via the bottom wiring BTMW, the via VIA2, the control signal line SWCNT of the BSM1 layer, and the via VIA1.

[0045] In the inverter INV2 of the control circuit CNTL, the drains D (Ndiff) of the NMOS transistors and the drains D (Pdiff) of the PMOS transistors, which are interconnected via the via VIA3 and output the output signal OUT, are connected to the output signal line OUT formed in the FSM1 layer via the top wiring TOPW and the via VIA4.

[0046] Note that, in Fig. 6(a), the drain D (Ndiff) of the NMOS transistor and the drain D (Pdiff) of the PMOS transistor are interconnected via via VIA3. However, as shown in Fig. 6(b), the drain D of the NMOS transistor and the drain D of the PMOS transistor may be interconnected via top wiring TOPW, via VIA3, and bottom wiring BTMW. Further, instead of via VIA3, the drain D (Ndiff) of the NMOS transistor and the drain D (Pdiff) of the PMOS transistor may be connected by a conductor to which the top wiring TOPW and the bottom wiring BTMW are connected on its side surface. Also, a conductor directly connected to the drain D (Ndiff) of the NMOS transistor and the drain D (Pdiff) of the PMOS transistor may be provided.

[0047] Fig. 7 shows an example of a cross-section along the X1-X1' line in Figs. 4 and 5. The P-type semiconductor layer Pdiff formed in the bottom layer BTM functions as the source S or drain D of the PMOS transistor. The semiconductor layer Ndiff of the control circuit CNTL formed in the top layer TOP functions as the source S or drain D of the NMOS transistor.

[0048] In the bottom layer BTM, the P-type semiconductor layers Pdiff arranged on both sides of the gate electrode GT are interconnected via the nanosheet NS penetrating the gate electrode GT. Similarly, in the top layer TOP, the N-type semiconductor layers Ndiff arranged on both sides of the gate electrode GT are interconnected via the nanosheet NS penetrating the gate electrode GT. Inside the gate electrode GT, the periphery of the nanosheet NS is covered with a gate insulating film not shown and is electrically separated from the gate electrode GT.

[0049] In the control circuit CNTL, the source S of the NMOS transistor of inverter INV1 is connected to the ground line VSS formed in the FSM1 layer via via VIA4 located above the source S. In the switch transistor SWT, the semiconductor layer Ndiff of the NMOS transistor is connected to the ground line VSS formed in the FSM1 layer via via VIA4 located above the semiconductor layer Ndiff. In the switch transistor SWT, the drain D of the PMOS transistor is connected to the virtual power line VVDD of the BSM1 layer via via VIA2 located below the drain D.

[0050] As shown in Figures 4, 5, and 7, by arranging the power line TVDD and virtual power line VVDD on the BSM1 layer on the back side of the substrate SUB, and arranging the ground line VSS on the FSM1 layer on the front side of the substrate SUB, each transistor in the power switch circuit PSW can be easily connected to the various power lines.

[0051] Figure 8 shows an example of a cross-section along the line X2-X2' in Figures 4 and 5. One end of via VIA2 is directly connected to the underside of the gate electrode GT of the switch transistor SWT (DGC), and the other end of via VIA2 is connected to the control signal line SWCNT of the BSM1 layer.

[0052] In the control circuit CNTL, one end of via VIA2 is connected to the underside of bottom wiring BTMW, which is connected to the drain D (not shown) of the PMOS transistor of inverter INV1, and the other end of via VIA2 is connected to the control signal line SWCNT of the BSM1 layer. Furthermore, the control signal line SWCNT of the BSM1 layer is connected to the control signal line SWCNT of the BSM2 layer via via VIA1.

[0053] The control signal SWCNT output from inverter INV1 is supplied to the gate electrode GT of switch transistor SWT via the control signal line SWCNT of the BSM1 layer, thereby controlling the on / off state of switch transistor SWT. Furthermore, the control signal SWCNT output from inverter INV1 is supplied to the gate electrode GT of inverter INV2 (not shown) via the control signal line SWCNT of the BSM2 layer.

[0054] Figures 9 and 10 show modified versions of Figures 4 and 5. In Figures 4 and 5, the semiconductor layer Pdiff is formed on the bottom semiconductor layer and the semiconductor layer Ndiff is formed on the top semiconductor layer, whereas in Figures 9 and 10, the semiconductor layer Ndiff is formed on the bottom semiconductor layer and the semiconductor layer Pdiff is formed on the top semiconductor layer. For this reason, Figures 9 and 10 are modified as a set from Figures 4 and 5. The same reference numerals are used for elements similar to those in Figures 4 and 5, and detailed explanations are omitted.

[0055] In Figure 9, an NMOS transistor is formed in the bottom layer BTM. In addition, in the BSM1 layer, a ground wire VSS extending to the region of the switch transistor SWT, a control signal line SWCNT, and another ground wire VSS are arranged in this order in the Y direction. In Figure 9, the ground wire VSS of the BSM1 layer is formed below the semiconductor layer Ndiff, which is the bottom semiconductor layer, in the region where the switch transistor SWT is formed, and the lower surface of the semiconductor layer Ndiff is directly connected to one end of via VIA2 (DC). The other end of via VIA2 is connected to the ground wire VSS of the BSM1 layer. The semiconductor layer Ndiff is then connected to the ground wire VSS of the BSM1 layer via via VIA2.

[0056] The sources S of the NMOS transistors of inverters INV1 and INV2 in the control circuit CNTL are directly connected (DC) to via VIA2, and via VIA2 to the ground wire VSS of the BSM1 layer.

[0057] In Figure 10, a PMOS transistor is formed on the top layer TOP. In addition, in the FSM1 layer, power lines TVD, virtual power lines VVDD, virtual power lines VVDD, and power line TVD are arranged in this order in the Y direction, extending to the region of the switch transistor SWT.

[0058] In the switch transistor SWT, the drain D of the PMOS transistor, which is the top semiconductor layer, is connected to the virtual power line VVDD of the FSM1 layer via via VIA4 located above the drain D. The source S of the PMOS transistor in the switch transistor SWT is connected to the power line TVDD of the FSM1 layer via the top wiring TOPW and via VIA4. In the control circuit CNTL, the source S of the PMOS transistor is connected to the virtual power line VVDD of the FSM1 layer via the top wiring TOPW and via VIA4.

[0059] In the first embodiment described above, the virtual power line VVDD of the BSM1 layer is positioned to overlap with the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT in a plan view. In addition, the control signal line SWCNT of the BSM1 layer, which is connected to the gate electrode GT, is positioned to be offset from the source S, drain D, and gate electrode GT of the PMOS transistor of the switch transistor SWT in a plan view.

[0060] This allows for the placement of via VIA2 (DC), which directly connects the drain D of the PMOS transistor of the switch transistor SWT to the virtual power line VVDD of the BSM1 layer, while also allowing for the placement of via VIA2 (DGC), which directly connects the gate electrode GT of the switch transistor SWT to the control signal line SWCNT of the BSM1 layer. As a result, when laying out the power switch circuit PSW in two regions Row of a predetermined size, via VIA2 can be appropriately placed in the power switch circuit PSW.

[0061] (Second Embodiment) Figure 11 shows an example of the circuit layout of the bottom layer BTM in the region where the power switch circuit PSW in Figure 2 is formed in the semiconductor device 100 of the second embodiment. The same reference numerals are used for elements similar to those in Figure 4, and detailed explanations are omitted.

[0062] In the second embodiment, the gate electrode GT of the inverter INV2 of the control circuit CNTL extends above the control signal line SWCNT of the BSM1 layer, and the gate electrode GT of inverter INV2 is directly connected to via VIA2 located below the gate electrode GT (DGC). Therefore, the wiring of the BSM2 layer, via VIA1, and BSM1 layer that were arranged in Figure 4 to connect the drain D of inverter INV1 to the gate electrode GT of inverter INV2 can be eliminated in Figure 11.

[0063] As a result, the control signal line SWCNT of the BSM1 layer, which transmits the control signal SWCNT from the control circuit CNTL to the gate electrode GT of the switch transistor SWT, can be positioned in the center in the Y direction, and the ground line VSS of the BSM1 layer can be shared by the two regions Row. Consequently, the number of BSM1 layer wires arranged in the two regions Row can be reduced from six in the first embodiment to five, the circuit width in the Y direction can be reduced compared to the first embodiment, and the circuit size of the power switch circuit PSW in the Y direction can be reduced.

[0064] In the switch transistor SWT, the sources S of two PMOS transistors arranged side by side in the second direction are connected via the bottom wiring BTMW and via VIA2 to the power lines TVDD of the BSM1 layer, which are located on both sides in the Y direction in a plan view.

[0065] Figure 12 shows an example of the circuit layout of the top layer TOP, which is formed on top of the bottom layer BTM circuit of Figure 11. The same reference numerals are used for elements similar to those in Figure 5, and detailed explanations are omitted. In Figure 12, the drain D of inverter INV1 of the control circuit CNTL is connected to the gate electrode GT of inverter INV2 via top wiring TOPW, via VIA4, FSM1 layer wiring (SWCNT), and via VIA4. The layout of the switch transistor SWT is the same as the circuit layout shown in Figure 5, except that the width in the Y direction of the two regions Row is set from six lines of BSM1 layer wiring to five lines.

[0066] As described above, in the second embodiment, as in the first embodiment, via VIA2 (DC) can be arranged to be directly connected to the drain D of the PMOS transistor of the switch transistor SWT, while via VIA2 (DGC) can be arranged to be directly connected to the gate electrode GT of the switch transistor SWT. This makes it possible to appropriately arrange via VIA2 in the power switch circuit PSW when laying out the power switch circuit PSW in two regions Row of a predetermined size.

[0067] Furthermore, in the second embodiment, the gate electrode GT of the inverter INV2 is extended above the control signal line SWCNT of the BSM1 layer, and connected to the control signal line SWCNT of the BSM1 layer via a via VIA2 located below the gate electrode GT, thereby allowing the control signal line SWCNT of the BSM1 layer to be positioned in the center in the Y direction. This reduces the number of BSM1 layer wirings arranged in the two regions Row from six in the first embodiment to five. As a result, the circuit width in the Y direction can be reduced compared to the first embodiment, and the circuit size of the power switch circuit PSW in the Y direction can be reduced.

[0068] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application.

[0069] 100 Semiconductor equipment BSM1, BSM2 Wiring layer BTM Bottom layer BTMW Bottom wiring CNTL Control circuit D Drain FSM1 Wiring layer GT Guard gate IN Input signal line INTR Internal circuit region INV1, INV2 Inverter IOC, IOCP I / O cell Ndiff Semiconductor layer NS Nanosheet OUT Output signal line Pdiff Semiconductor layer PSW Power switch circuit Row Spacing S Source SC Standard cell SCB Standard cell block SGNL Signal SUB Substrate SWCNT Control signal SWT Switch transistor TOP Top layer TOPW Top wiring TVDD Power line VIA1, VIA2, VIA3, VIA4 Via VSS Ground line VVDD Virtual power line

Claims

1. A semiconductor device comprising: a substrate having a first surface and a second surface facing the first surface; a first power line formed on the second surface; a second power line formed on the second surface; a first signal line formed on the second surface; a first transistor formed on the first surface and having a first semiconductor layer, a second semiconductor layer, and a first gate electrode arranged in a first direction in a plan view, and electrically provided between the first power line and the second power line; a third power line formed on the first transistor and extending in the first direction in a plan view; a power switch circuit having the first transistor; and a first via formed on the substrate and connecting the first signal line and the lower surface of the first gate electrode, wherein the first via is positioned in a second direction different from the first direction in a plan view from the first semiconductor layer and the second semiconductor layer.

2. The semiconductor device according to claim 1, having a second via formed on the substrate, which connects the lower surface of one of the first semiconductor layer or the second semiconductor layer to the first power line or the second power line.

3. The semiconductor device according to claim 2, comprising: a first wiring connected to the other of the first semiconductor layer or the second semiconductor layer; and a third via formed on the substrate and connecting the first wiring and the first power line, wherein the second via connects the one of the first semiconductor layer or the second semiconductor layer to the second power line.

4. The semiconductor device according to claim 1, wherein the power switch circuit includes an inverter that generates a control signal for controlling the first transistor, and has a control circuit formed on the first surface, and the inverter operates in response to a first power potential supplied from the first power line formed on the second surface and a second power potential supplied from the third power line formed on the control circuit.

5. The semiconductor device according to claim 4, wherein the first signal line is connected to the output of the inverter, and the control signal output from the inverter is supplied to the first gate electrode via the first signal line and the first via.

6. The semiconductor device according to claim 1, wherein the first signal line extends in the first direction, and the power switch circuit has a plurality of the first transistors arranged in the second direction with respect to the first signal line in a plan view.

7. The semiconductor device according to claim 6, wherein the first gate electrodes of the plurality of first transistors arranged in the second direction are integrally formed.

8. The semiconductor device according to claim 6, comprising a plurality of first power lines and a plurality of second power lines, wherein one of the plurality of first transistors arranged in a second direction is connected to one of the plurality of first power lines and one of the plurality of second power lines, and another of the plurality of first transistors arranged in a second direction is connected to another of the plurality of first power lines and another of the plurality of second power lines.

9. The semiconductor device according to claim 1, further comprising a third semiconductor layer and a fourth semiconductor layer arranged on the first transistor in a first direction in a plan view, with the first gate electrode sandwiched between them, wherein the third semiconductor layer and the fourth semiconductor layer are connected to the third power line.

10. The semiconductor device according to claim 9, wherein the first semiconductor layer and the second semiconductor layer are P-type semiconductor layers, and the third semiconductor layer and the fourth semiconductor layer are N-type semiconductor layers.

11. The power switch circuit includes an inverter that generates a control signal for controlling the first transistor, and has a control circuit formed on the first surface, the inverter having a second transistor arranged in a first direction in a plan view and having a fifth semiconductor layer, a sixth semiconductor layer and a second gate electrode formed on the first surface of the substrate, and a third transistor arranged in a first direction in a plan view and having a seventh semiconductor layer, an eighth semiconductor layer and a second gate electrode formed on the second transistor, one of the fifth semiconductor layer and the sixth semiconductor layer being connected to the first power line, the other of the fifth semiconductor layer and the sixth semiconductor layer being connected to the first signal line, and one of the seventh semiconductor layer and the eighth semiconductor layer being connected to the third power line, the semiconductor device according to claim 9.

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