Method for manufacturing semiconductor device, cleaning member, and cleaning apparatus

Abstract

The present invention provides a method for reducing connection failures of semiconductor chips in hybrid bonding used in CoW bonding or C2C bonding. In this method, a semiconductor substrate 100 having a polished surface is diced into individual pieces to obtain a plurality of semiconductor chips 110 each having an insulating portion 102A and electrodes 103. After individualization, the surfaces of the plurality of semiconductor chips 110 are cleaned using a cleaning member 160 having a sponge roller part 162 which is a porous elastic body. For example, a PVA brush is used as the cleaning member 160. After cleaning, the insulating portions 102A of the semiconductor chips 110 are bonded to an insulating layer 202 of a semiconductor substrate 200, and the electrodes 103 of the semiconductor chips 110 are bonded to electrodes 203 of the semiconductor substrate 200. Debris D adhering to the surfaces of the semiconductor chips 110 is effectively removed by cleaning using the cleaning member 160 having the sponge roller part 162.

Description

Method for manufacturing semiconductor device, cleaning member, and cleaning apparatus

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, a cleaning member, and a cleaning apparatus. More specifically, the present disclosure relates to a method for manufacturing a semiconductor device that joins an individualized semiconductor chip to a semiconductor substrate (such as a semiconductor wafer or another semiconductor chip), a cleaning member used therefor, and a cleaning apparatus.

[0002] In recent years, with the rapid increase in functionality of electronic devices represented by AI / HPC, etc., the size and density of semiconductor packages have been rapidly increasing. The package structure is not limited to the high density of surface mounting, and the package structure and mounting process are becoming more complex and diverse, such as inorganic (silicon) or organic interposer (Bridge die / RDL) technology, 2.xD mounting using the same, and 3D mounting (HBM / Chiplet) technology using TSV. For example, Resonac Co., Ltd. is mainly based on the 'Packaging Solution Center' and is developing technologies for next-generation semiconductor packaging processes from the perspective of customers (semiconductor manufacturers), combining mounting processes and materials.

[0003] As a technology in such a semiconductor package field, Patent Documents 1 to 3 disclose an example of a hybrid bonding technology used in a Wafer-to-Wafer (W2W) bonding process or a Chip-on-Wafer (CoW) bonding process in 3D mounting of semiconductor devices.

[0004] Japanese Unexamined Patent Application Publication No. 2021-197430, Japanese Unexamined Patent Application Publication No. 2021-197431, Japanese Patent Application Publication No. 2018-528622

[0005] When performing three-dimensional mounting of such semiconductor chips, hybrid bonding technology, which is used in wafer-to-wafer (W2W) bonding, is being considered for fine bonding of wiring between devices. However, when performing three-dimensional mounting of semiconductor chips, unlike W2W, foreign matter, known as debris (cut fragments), is generated during the dicing process when the semiconductor chip is separated into individual pieces. This debris adheres to the bonding interface (each surface of the electrode or insulating layer) of the semiconductor chip. If bonding is performed with the debris still attached to the bonding interface of the semiconductor chip, connection failures may occur in the manufactured semiconductor device.

[0006] The purpose of this disclosure is to provide a method for manufacturing a semiconductor device, a cleaning member, and a cleaning apparatus that can reduce connection failures of semiconductor chips when performing three-dimensional mounting of semiconductor chips.

[0007] [1] This disclosure relates in part to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device comprises: a step of polishing a first insulating layer and a plurality of first electrodes located on the surface side of a first semiconductor substrate, wherein the first semiconductor substrate has a first substrate body, a first insulating layer and a plurality of first electrodes provided on the surface of the first substrate body; a step of dicing the first semiconductor substrate to obtain a plurality of semiconductor chips, each having an insulating portion corresponding to the first insulating layer and at least one of the plurality of first electrodes; a step of cleaning the surfaces of the plurality of semiconductor chips using a cleaning member having a porous elastic material after the first semiconductor substrate has been diced; a step of joining the insulating portion of a semiconductor chip to a second insulating layer located on the surface side of a second semiconductor substrate, wherein the second semiconductor substrate has a second substrate body, a second insulating layer and a second electrode provided on the surface of the second substrate body; and a step of joining the first electrode of a semiconductor chip to the second electrode of the second semiconductor substrate.

[0008] In the semiconductor device manufacturing method described in [1] above, after the first semiconductor substrate is diced, the surfaces of multiple semiconductor chips are cleaned using a cleaning member having a porous elastic material. In this case, debris generated by dicing during dicing can be directly removed by the cleaning member having a porous elastic material. As a result, semiconductor devices can be manufactured using semiconductor chips from which debris generated by dicing has been reliably removed, and connection failures of semiconductor chips can be reduced when performing three-dimensional mounting of semiconductor chips.

[0009] [2] In the semiconductor device manufacturing method described in [1] above, the porosity of the porous elastic material is preferably 80% or more and 95% or less. A porosity of 80% or more of the porous elastic material ensures sufficient flexibility when the porous elastic material is wetted, preventing damage to the semiconductor chip being cleaned. Furthermore, a porosity of 95% or less of the porous elastic material ensures the strength of the cleaning member, enabling reliable cleaning.

[0010] [3] In the semiconductor device manufacturing method described in [1] or [2] above, the average pore size of the porous elastic material is preferably 50 μm or more and 200 μm or less. By having an average pore size of 50 μm or more for the porous elastic material, sufficient elastic force can be ensured when the porous elastic material is wetted, and a sufficient brushing effect can be obtained. Furthermore, by having an average pore size of 200 μm or less for the porous elastic material, precise cleaning of the semiconductor chip surface can be reliably performed.

[0011] [4] In any of the semiconductor device manufacturing methods described in [1] to [3] above, the porous elastic body may be a polyvinyl alcohol-based or polyvinyl acetal-based porous elastic body. By using an elastic body formed from such a material, a cleaning member that hardens in a dry state but softens in a wet state can be easily obtained. Furthermore, the cleaning member will have excellent water absorption and water retention properties when a cleaning solution is used, and will have suitable flexibility and appropriate rebound elasticity when wet. In addition, the wear resistance of the cleaning member can be improved, which can increase the manufacturing efficiency of semiconductor devices.

[0012] [5] In any of the semiconductor device manufacturing methods described in [1] to [4] above, in the step of separating the first semiconductor substrate into individual pieces, it is preferable to attach a dicing tape to the back surface of the first semiconductor substrate opposite to the front surface before dicing, and in the cleaning step, it is preferable to clean with a cleaning member while a plurality of semiconductor chips are fixed on the dicing tape or carrier. In this case, the surfaces of the plurality of semiconductor chips can be cleaned together by the cleaning member. For example, a glass carrier wafer may be used as the carrier.

[0013] [6] In any of the semiconductor device manufacturing methods described in [1] to [5] above, the cleaning member may be a porous elastic body and have a rotatable roll-shaped cleaning brush, and in the cleaning step, cleaning may be performed by rotating the cleaning brush while supplying cleaning liquid. In this case, debris on the surface of the semiconductor chip can be removed more reliably.

[0014] [7] In the semiconductor device manufacturing method described in [6] above, the cleaning solution may be pure water or ammonia hydrogenated water. When the cleaning solution is pure water, it is not necessary to consider the chemical resistance of the dicing tape used in the manufacturing of the semiconductor device (e.g., the dicing process), and a suitable dicing tape can be used. When the cleaning solution is ammonia hydrogenated water, it is possible to prevent the re-adhesion of debris that has been removed.

[0015] [8] In the method for manufacturing a semiconductor device according to any of [1] to [7] above, it is preferable that at least one of the first insulating layer and the second insulating layer is an organic insulating layer. In this case, even if debris that could not be removed by cleaning with a cleaning member remains on the surface of the semiconductor chip, the organic insulating layer can contain the debris and ensure that the insulating layers are properly bonded together.

[0016] [9] The disclosure relates in another aspect to a cleaning member. This cleaning member is used in any of the semiconductor device manufacturing methods described in [1] to [8] above, and has a porous elastic body. By using such a cleaning member, the surface of the diced semiconductor chip can be reliably cleaned, thereby ensuring reliable bonding of the semiconductor chip in hybrid bonding.

[0017]

[10] In the cleaning member described in [9] above, the porosity of the porous elastic body is preferably 80% or more and 95% or less, the average pore diameter of the porous elastic body is preferably 50 μm or more and 200 μm or less, and the porous elastic body is preferably a polyvinyl alcohol-based or polyvinyl acetal-based porous elastic body. In this case, as described above, the surface of the semiconductor chip can be reliably cleaned with the cleaning member.

[0018]

[11] The disclosure further relates to a cleaning apparatus. This cleaning apparatus comprises a cleaning member used in any of the semiconductor device manufacturing methods described in [1] to [8] above, a support unit for supporting a plurality of semiconductor chips to be cleaned, and a supply unit for supplying a cleaning solution to the plurality of semiconductor chips. By using such a cleaning apparatus, the surface of the diced semiconductor chips can be reliably cleaned, thereby ensuring reliable bonding of the semiconductor chips in hybrid bonding.

[0019]

[12] In the cleaning apparatus described in

[11] above, it is preferable that the supply unit supplies pure water or ammonia hydrogenated water as the cleaning solution to multiple semiconductor chips. When the cleaning solution is pure water, it becomes unnecessary to consider the chemical resistance of the dicing tape used in the manufacturing of semiconductor devices (e.g., the dicing process), and a suitable dicing tape can be used. When the cleaning solution is ammonia hydrogenated water, it is possible to prevent the re-adhesion of debris that has been removed.

[0020] According to this disclosure, connection failures of semiconductor chips can be reduced when performing three-dimensional mounting of semiconductor chips.

[0021] Figure 1 is a schematic cross-sectional view showing an example of a semiconductor device (C2W) manufactured by a semiconductor device manufacturing method according to one embodiment. Figures 2(a) to 2(d) are diagrams sequentially showing a method for manufacturing the semiconductor device shown in Figure 1. Figure 3 is a schematic diagram illustrating a process for cleaning multiple semiconductor chips. Figure 4(a) shows the case where the surface of the individual semiconductor chips is cleaned using a cleaning brush, and Figure 4(b) shows the case where the surface of the individual semiconductor chips is cleaned using only pure water.

[0022] Embodiments of this disclosure will be described in detail below, with reference to the drawings as necessary. In the following description, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. When terms such as "left," "right," "front," "back," "up," "down," "above," and "below" are used in this specification and claims, they are for illustrative purposes only and do not necessarily mean that the relative positions are permanent. Moreover, the dimensional ratios in the drawings are not limited to those shown.

[0023] In this specification, the term "layer" includes not only structures that are formed across the entire surface when observed in a plan view, but also structures that are formed in only a part of the surface. In this specification, the term "process" includes not only independent processes, but also processes that are not clearly distinguishable from other processes, as long as the intended function of the process is achieved. Numerical ranges indicated using "~" indicate a range that includes the numbers written before and after "~" as the minimum and maximum values, respectively.

[0024] (Configuration of Semiconductor Device) Figure 1 is a schematic cross-sectional view showing an example of a semiconductor device manufactured by the method according to this embodiment. As shown in Figure 1, the semiconductor device 1 is, for example, an example of a semiconductor package, and comprises a plurality of semiconductor chips 10 and a semiconductor substrate 20, and has a chip-on-wafer (CoW) structure. The plurality of semiconductor chips 10 are manufactured by dicing a semiconductor substrate 100, which will be described later. The plurality of semiconductor chips 10 are mounted on the semiconductor substrate 20 to form a three-dimensional mounting structure. The semiconductor substrate 20 may be, for example, a substrate on which a plurality of semiconductor chips, such as an LSI (Large scale Integrated Circuit) chip or a CMOS (Complementary Metal Oxide Semiconductor) sensor, are formed at locations corresponding to each semiconductor chip 10. Each semiconductor chip 10 may be, for example, an LSI or a memory chip. The plurality of semiconductor chips 10 and the semiconductor substrate 20 are finely bonded together by hybrid bonding, which will be described later, so that their respective terminal electrodes and the insulating layers around them are firmly and precisely bonded to each other without misalignment. The semiconductor device 1 may be further fragmented into individual semiconductor devices, comprising at least one semiconductor chip 10 further fragmented from the configuration shown in Figure 1, and a substrate portion which is a part of a semiconductor substrate 20 corresponding to the fragmented semiconductor chip 10. Furthermore, the manufacturing method according to this embodiment may be applied to a C2C bonding process, in which case semiconductor chips are bonded together.

[0025] (Method of Manufacturing a Semiconductor Device) Next, the method of manufacturing the semiconductor device 1 will be explained with reference to Figures 2 and 3. Figures 2(a) to 2(d) are diagrams that sequentially show the method for manufacturing the semiconductor device shown in Figure 1. Figure 3 is a schematic diagram that explains the process of cleaning multiple semiconductor chips.

[0026] The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (i): (a) A step of preparing a semiconductor substrate 100 corresponding to a plurality of semiconductor chips 10, having a substrate body 101, an insulating layer 102 and a plurality of electrodes 103. (b) A step of preparing a semiconductor substrate 200 having a substrate body 201, an insulating layer 202 and a plurality of electrodes 203. (c) A step of polishing the insulating layer 102 of the semiconductor substrate 100 together with the electrodes 103. (d) A step of polishing the insulating layer 202 of the semiconductor substrate 200 together with the electrodes 203. (e) A step of separating the semiconductor substrate 100 into individual pieces and obtaining a plurality of semiconductor chips 110, each having a substrate portion 101A corresponding to the substrate body 101, an insulating portion 102A corresponding to the insulating layer 102, and at least one electrode 103. (f) After separating the semiconductor substrate 100 into individual pieces, a step of cleaning the surfaces 111 of the multiple semiconductor chips 110 using a cleaning member 160 having a porous elastic material. (g) A step of aligning the electrodes 103 of each of the multiple semiconductor chips 110 with respect to the electrodes 203 of the semiconductor substrate 200. (h) A step of bonding each insulating portion 102A of the multiple semiconductor chips 110 to the insulating layer 202 of the semiconductor substrate 200. (i) A step of bonding the electrodes 103 of each of the multiple semiconductor chips 110 to the electrodes 203 of the semiconductor substrate 200.

[0027] [Steps (a) and (b)] Step (a) is a step of preparing a semiconductor substrate 100 (first semiconductor substrate), which is a silicon substrate on which an integrated circuit consisting of semiconductor elements and wiring connecting them is formed, corresponding to a plurality of semiconductor chips 10. In step (a), as shown in Figure 2(a), a plurality of electrodes 103 (a plurality of first electrodes) made of copper or aluminum are provided at predetermined intervals on the surface 101a of a substrate body 101 (first substrate body) made of silicon or the like, and an insulating layer 102 (first insulating layer) made of an organic or inorganic material is provided. The electrodes 103 are terminal electrodes for exposing the integrated circuit etc. formed on the semiconductor substrate 100 to the outside by penetrating the insulating layer 102. The insulating layer 102 may be provided on the surface 101a of the substrate body 101 and then the plurality of electrodes 103 may be provided, or the plurality of electrodes 103 may be provided on the surface 101a of the substrate body 101 and then the insulating layer 102 may be provided. Multiple electrodes 103 can be fabricated, for example, using a semi-additive method, but may also be fabricated using other known methods.

[0028] Step (b) is a step of preparing a semiconductor substrate 200 (second semiconductor substrate), which is a silicon substrate on which an integrated circuit consisting of semiconductor elements and wiring connecting them is formed. In step (b), as shown in Figure 2(a), a plurality of electrodes 203 (a plurality of second electrodes) made of copper or aluminum are provided at predetermined intervals on the surface 201a of a substrate body 201 (second substrate body) made of silicon or the like, and an insulating layer 202 (second insulating layer) made of an organic or inorganic material is provided. The electrodes 203 are terminal electrodes for exposing the integrated circuit etc. formed on the semiconductor substrate 200 to the outside by penetrating the insulating layer 202. The insulating layer 202 may be provided on the surface 201a of the substrate body 201 and then the plurality of electrodes 203 may be provided, or the plurality of electrodes 203 may be provided on the surface 201a of the substrate body 201 and then the insulating layer 202 may be provided. The plurality of electrodes 203 can be manufactured using, for example, a semi-additive method, but may also be manufactured using other known methods.

[0029] The insulating layer 102 and insulating layer 202 used in steps (a) and (b) are formed to include an organic material. The organic material used in these insulating layers may be, for example, polyimide, polyimide precursor (e.g., polyimiamic ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or PBO precursor. These organic materials may be, for example, silicon oxide (SiO₂ ２ Compared to inorganic materials such as ), it has a lower modulus of elasticity and is a soft material. By using such an organic material, when bonding the insulating layers together in step (h) described later, even if there is fine foreign matter such as debris (cutting fragments) on the insulating layer, it is absorbed into the insulating layer, preventing bonding failure due to debris and ensuring reliable bonding of the insulating layers. The modulus of elasticity of the organic material constituting insulating layer 102 and insulating layer 202 may be, for example, 7.0 GPa or less, 5.0 GPa or less, 3.5 GPa or less, 3.0 GPa or less, or 2.5 GPa or less. The modulus of elasticity referred to here means Young's modulus.

[0030] Since the organic material used in the insulating layer is liquid or soluble in a solvent, the insulating layers 102 and 202 can be easily formed as thin films by spin coating or the like. Furthermore, since these organic materials have heat resistance, they can withstand the temperature (for example, high temperatures of 300°C or higher) when joining electrodes 103 and 203 in step (i) described later, and the bonding between the insulating layers does not deteriorate due to high temperatures. The organic material constituting insulating layer 102 and insulating layer 202 may be a resin composition containing a photosensitive resin or a thermosetting resin. The organic material constituting insulating layer 102 and insulating layer 202 may be a thermosetting non-conductive film (NCF). Note that insulating layer 102 and insulating layer 202 may be insulating layers containing both inorganic and organic materials, one insulating layer may be formed from an inorganic material and the other insulating layer may be formed from an organic material, or both insulating layers may be formed from inorganic materials. The inorganic material used in the insulating layer may be, for example, silicon oxide (SiO2). ２ ) etc.

[0031] The thickness of the insulating layer 102 may be 20 μm or less. By making the thickness of the insulating layer 102 sufficiently thin, the wiring and other components formed from the electrodes 103 can be made finer. For example, the minimum size (electrode width) of the electrodes 103 formed within the insulating layer 102 is determined by the thickness of the insulating layer 102 and the aspect ratio of the photosensitive material used. If the aspect ratio of the photosensitive material is, for example, 1:1 (aperture width:depth), the electrode width of the electrodes 103 can be made 20 μm or less by making the thickness of the insulating layer 102 20 μm or less. The thickness of the insulating layer 102 may be greater than 20 μm. In this case, when bonding the insulating layers together in step (h) described later, more debris can be embedded in the resin insulating layer 102, and the insulating layers can be joined together more reliably. It is also possible to improve the adhesion between the insulating layers by relieving the stress when joining the insulating layers with one of the resin insulating layers.

[0032] The thickness of the insulating layer 102 may be 1 μm or more. In this case, by embedding minute debris within the resin insulating layer, good connection between the insulating layer 102 and the insulating layer 202 can be ensured even if minute debris remains after cleaning in step (f). For example, the size of the debris that can be embedded in the insulating layer 102 is defined by the thickness of the resin insulating layer 102. If the thickness of the insulating layer 102 is, for example, 1 μm, debris with a diameter or width of 1 μm can be embedded within the insulating layer 102. That is, according to this manufacturing method, even if there is debris smaller than the thickness of the insulating layer 102, good connection between the insulating layer 102 and the insulating layer 202 can be ensured by embedding the debris in the resin insulating layer. The thickness of the insulating layer 202 may be 20 μm or less, thicker than 20 μm, or 1 μm or more, similar to the insulating layer 102. The insulating layer 202 may also have debris embedded in it as described above.

[0033] [Steps (c) and (d)] Step (c) is a step of polishing the semiconductor substrate 100. In step (c), the surface of the insulating layer 102 on which a plurality of electrodes 103 are provided is polished using the CMP (Chemical Mechanical Polishing) method. This polishing makes the average roughness of the surface of the insulating layer 102 and the tip surface of each electrode 103 2.0 nm or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less, enabling the hybrid bonding described later. Debris on the surface of the semiconductor substrate 100 may be removed by this polishing. In this polishing step, a part of the step between the surface 102a of the insulating layer 102 and the tip surface of the electrode 103 may be formed.

[0034] Step (d) is a step of polishing the semiconductor substrate 200. In step (d), the surface of the insulating layer 202 on which a plurality of electrodes 203 are provided is polished using the CMP method. This polishing makes the average roughness of the surface of the insulating layer 202 and the tip surface of each electrode 203 2.0 nm or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less, enabling the hybrid bonding described later. Debris on the surface of the semiconductor substrate 200 may be removed by this polishing. In this polishing step, a part of the step between the surface 202a of the insulating layer 202 and the tip surface of the electrode 203 may be formed.

[0035] In steps (c) and (d), the insulating layer 102 may be polished so that its thickness is the same as the insulating layer 202, or it may be polished so that its thickness is greater than that of the insulating layer 202. Alternatively, the insulating layer 102 may be polished so that its thickness is less than that of the insulating layer 202. When the insulating layer 102 is thicker than the insulating layer 202 and is made of an organic material, much of the debris adhering to the bonding interface during individualization or chip mounting onto the semiconductor chip 10 can be contained by the insulating layer 102, thereby reducing bonding defects. On the other hand, when the insulating layer 102 is thinner than the insulating layer 202, the height of the mounted semiconductor chip 10, i.e., the semiconductor device 1, can be reduced.

[0036] [Step (e)] Step (e) is a step of separating the semiconductor substrate 100 into individual pieces and obtaining a plurality of semiconductor chips 110. The semiconductor chip 110 referred to here corresponds to the semiconductor chip 10 in Figure 1. When the polishing of the semiconductor substrate 100 is completed, in step (e), as shown in Figure 2(b), the polished semiconductor substrate 100 is separated into individual pieces and a plurality of semiconductor chips 110 are obtained, each having a substrate portion 101A corresponding to the substrate body 101, an insulating portion 102A corresponding to the insulating layer 102, and at least one electrode 103. In step (e), the semiconductor substrate 100 is placed on a dicing tape 105 and separated into a plurality of semiconductor chips 110 by cutting means such as a dicer 150, from the insulating layer 102 toward the substrate body 101. The dicing tape 105 is attached to the back surface 101b of the substrate body 101 (the back surface of the semiconductor substrate 100). In step (e), the insulating layer 102 of the semiconductor substrate 100 is divided into insulating portions 102A corresponding to each semiconductor chip 110, as shown in Figure 2(b). Similarly, the substrate body 101 is divided into corresponding substrate portions 101A. As a dicing method for separating the semiconductor substrate 100 into individual pieces, for example, plasma dicing, stealth dicing, or laser dicing can be used. Note that this separation (dicing) generates debris D, which may adhere to the electrodes 103 of the semiconductor chip 110 or the surfaces of the insulating portions 102A.

[0037] [Step (f)] Step (f) is a step in which, after the semiconductor substrate 100 has been separated into individual pieces, the surfaces 111 of the multiple semiconductor chips 110 are cleaned using a cleaning member 160 having a porous elastic material. Once the semiconductor substrate 100 has been separated into individual pieces and multiple semiconductor chips 110 have been obtained, a cleaning device 190 having a cleaning member 160, a supply unit 165, a roller member 170 and a squeezing roller 180 is prepared as shown in Figure 2(c) and Figure 3. Then, the multiple semiconductor chips 110 are placed in predetermined locations on the cleaning device 190, and the surfaces 111 of the semiconductor chips 110 are cleaned with the cleaning member 160 while supplying cleaning liquid L from the supply unit 165 to the cleaning member 160.

[0038] The cleaning member 160 has a shaft portion 161 and a sponge roller portion 162. The sponge roller portion 162 is a rotatable roll-shaped cleaning brush, and is provided on the outer circumference of the shaft portion 161 and integrated with it. By rotating the shaft portion 161, the sponge roller portion 162 also rotates. The sponge roller portion 162 is, for example, a porous elastic body made of polyvinyl alcohol (PVA) or polyvinyl acetal (PVAT) material. By using a sponge roller portion 162 made of PVA or PVAT material, a cleaning member 160 that is hard in a dry state but softens in a wet state can be easily obtained. Furthermore, the cleaning member 160 has excellent water absorption and water retention properties when using a cleaning liquid L, and can have suitable flexibility and appropriate rebound elasticity when wet. In addition, the wear resistance of the cleaning member 160 can be improved, which can increase the manufacturing efficiency of semiconductor devices. The sponge roller portion 162, formed from a PVAt-based material, is obtained by, for example, mixing one or more types of polyvinyl alcohol (raw material) with an average degree of polymerization of 50 to 3000 and a degree of saponification of 80% or more to make an aqueous solution, adding aldehydes as a crosslinking agent, mineral acids as a catalyst, and starch as a pore-forming agent to this aqueous solution, pouring the mixture into a predetermined mold, reacting it at 40 to 80°C, removing it from the mold, and then washing it with water to remove the pore-forming agent and the like.

[0039] The porosity of the sponge roller portion 162 is not particularly limited, but for example, it is preferable that the porosity is 80% or more and 95% or less. A porosity of 80% or more in the sponge roller portion 162 ensures sufficient flexibility when the sponge roller portion 162 is wet, preventing damage to the semiconductor chip 110 being cleaned. Furthermore, a porosity of 95% or less in the sponge roller portion 162 ensures the strength of the sponge roller portion 162, enabling reliable cleaning. Here, "porosity" refers to a value calculated by measuring the apparent volume and true volume of a porous body formed from a rectangular parallelepiped made of PVA-based or PVAt-based material in a dry state after being thoroughly dried in a dryer, using a dry automatic puncture clock, and using the following formula (1): Porosity (%) = {(Apparent Volume - True Volume) / Apparent Volume} × 100 … (1)

[0040] The average pore diameter of the sponge roller portion 162 is not particularly limited, but is preferably, for example, 50 μm or more and 200 μm or less. An average pore diameter of 50 μm or more ensures sufficient elasticity when the sponge roller portion 162 is wet, thereby providing a sufficient brushing effect. Furthermore, an average pore diameter of 200 μm or less ensures reliable precision cleaning of the surface 111 of the semiconductor chip 110. Here, "average pore diameter" refers to the average value of the diameters of multiple pores present in the internal structure of the sponge roller portion 162. In this embodiment, the average pore diameter is defined as the average of the major axes (distance in the longitudinal direction of each pore) of a predetermined number of pores extracted from multiple pores according to predetermined criteria, and can be determined, for example, by the following measurement method: The sponge roller portion 162 is cut at a predetermined position, and the internal structure exposed on the cut surface is photographed with an electron microscope. Next, a predetermined measurement range is set on the photograph, and 20 stomata with the largest major diameters are extracted from among the multiple stomata within that measurement range. Then, the major diameter of each of the extracted 20 stomata is measured. Finally, the average of the 20 largest measurements from the 1st to the 20th is calculated as the average stomatal diameter.

[0041] Furthermore, the apparent density of the sponge roller section 162 is 0.06 g / cm³. ３ The apparent density may be greater than or equal to 600%, and may also be greater than or equal to 600%. The apparent density is obtained by measuring the dry weight and external dimensions of a PVA-based or PVA-at porous material of a predetermined shape (e.g., rectangular) in a dry state, calculating the wet volume from the external dimensions, and dividing the dry weight by the wet volume. The water retention rate is calculated by measuring the dry weight and the wet weight of a PVA-based or PVA-at porous material in a sufficiently moistened state, and using the following formula (2): Water retention rate (%) = {(wet weight - dry weight) / dry weight} × 100 … (2)

[0042] Although the outer peripheral surface of the sponge roller portion 162 is flat in FIG. 3, it is not limited to this. That is, the sponge roller portion 162 may be provided with a number of protrusions protruding radially outward from the outer peripheral surface. In this case, the brushing effect can be enhanced.

[0043] Above the cleaning member 160, a supply unit 165 for supplying the cleaning liquid L to the cleaning member 160 is provided. The supply unit 165 supplies the cleaning liquid L to the sponge roller portion 162 in a shower shape, for example. The supply unit 165 may directly supply the cleaning liquid L to the surface 111 of the semiconductor chip 110. As the cleaning liquid L, for example, pure water or ammonia peroxide water can be used. Ammonia peroxide water is a cleaning liquid used in so-called APM cleaning, which is a cleaning liquid in which ammonia water, hydrogen peroxide water, and pure water are blended in a predetermined ratio. When ammonia peroxide water is used, it is preferably prevented that the debris D once removed reattaches to the surface 111 of the semiconductor chip 110 or the like. When pure water is used as the cleaning liquid L, it is not necessary to consider the chemical resistance of the dicing tape used in the manufacture of the semiconductor device (for example, the dicing process), and a suitable dicing tape can be used.

[0044] Below the cleaning member 160, a roller member 170 (support part) having the same configuration as the cleaning member 160 is provided. The roller member 170 supports the plurality of semiconductor chips 110 to be cleaned, which are fixed to the dicing tape 105, from below. The plurality of semiconductor chips 110 may be cleaned while being supported and fixed by other support means, such as a glass carrier wafer. The cleaning member 160 and the roller member 170 transport the plurality of semiconductor chips 110 fixed to the dicing tape 105 while sandwiching them. The cleaning member 160 and the roller member 170 rotate in the direction shown in the figure. Due to this transport and the rotation of the sponge roller part 162, a large amount of debris D adhering to the surface of the plurality of semiconductor chips 110 (for example, the surface of the electrodes) is removed by the cleaning member 160. Since the sponge roller part 162 of the cleaning member 160 is made of a porous material, the debris D is absorbed into the sponge roller part 162 and does not damage the surface 111 of the semiconductor chips 110. In other words, the semiconductor chip 110 can be cleaned without worsening the surface roughness of the surface 111. A squeezing roller 180 is provided below the roller member 170. The squeezing roller 180 squeezes out and discharges excess cleaning liquid, etc.

[0045] [Step (g)] Step (g) is a step in which the electrodes 103 of each of the multiple semiconductor chips 110 are aligned with respect to the electrodes 203 of the semiconductor substrate 200, as shown in Figure 2(d). In step (g), each semiconductor chip 110 is aligned so that each electrode 103 of each semiconductor chip 110 faces the corresponding electrode 203 of the semiconductor substrate 200.

[0046] [Step (h)] Step (h) is a step of joining each insulating portion 102A of the plurality of semiconductor chips 110 to the insulating layer 202 of the semiconductor substrate 200. In step (h), after removing debris D such as organic substances or metal oxides adhering to the surfaces of each semiconductor chip 110 and the semiconductor substrate 200, alignment of the semiconductor chip 110 with respect to the semiconductor substrate 200 is performed. When the alignment is completed, as shown in (d) of FIG. 2, each insulating portion 102A of the plurality of semiconductor chips 110 is joined to the insulating layer 202 of the semiconductor substrate 200 as hybrid bonding. At this time, the insulating portions 102A of the plurality of semiconductor chips 110 and the insulating layer 202 of the semiconductor substrate 200 may be heated uniformly and then joined. The temperature difference between the semiconductor chip 110 and the semiconductor substrate 200 during joining is preferably, for example, 10° C. or less. By heating and joining at a uniform temperature, an insulating joint portion where the insulating portion 102A and the insulating layer 202 are joined is formed, and the plurality of semiconductor chips 110 are mechanically and firmly attached to the semiconductor substrate 200. Further, since it is heating and joining at a uniform temperature, misalignment or the like at the joining portion is unlikely to occur, and high-precision joining can be performed. At this stage of attachment, the electrode 103 of the semiconductor chip 110 and the electrode 203 of the semiconductor substrate 200 are separated from each other and not connected (however, alignment is performed).

[0047] [Step (i)] Step (i) is a step in which the electrodes 103 of each of the multiple semiconductor chips 110 and the electrodes 203 of the semiconductor substrate 200 are joined. In step (i), as shown in Figure 2(d), once the bonding in step (h) is completed, a predetermined amount of heat, or pressure, or both, is applied to join the electrodes 103 of the multiple semiconductor chips 110 and the electrodes 203 of the semiconductor substrate 200 as a hybrid bond. When the electrodes 103 and 203 are made of copper, the annealing temperature in step (i) is preferably 150°C to 400°C, and more preferably 150°C to 200°C. Through this joining process, the electrodes 103 and their corresponding electrodes 203 are joined to form an electrode joint, and the electrodes 103 and 203 are firmly joined mechanically and electrically. The electrode joining in step (i) is performed after the joining in step (h), but may be performed simultaneously with the joining in step (h). Subsequently, all semiconductor chips 110 are bonded to the semiconductor substrate 200 to obtain the semiconductor device 1 shown in Figure 1.

[0048] As described above, a semiconductor device 1 can be obtained in which a plurality of semiconductor chips 110 are electrically and mechanically and precisely positioned on a semiconductor substrate 200. Subsequently, the semiconductor device (CoW) with the configuration shown in Figure 1 may be further fragmented to individually form each semiconductor device, which consists of at least one semiconductor chip 10 (110) and a portion of the semiconductor substrate 200 corresponding to the fragmented semiconductor chip 10.

[0049] As described above, according to the semiconductor device manufacturing method of this embodiment, after the semiconductor substrate 100 is divided into individual pieces, the surfaces of multiple semiconductor chips 110 are cleaned using a cleaning member 160 having a sponge roller portion 162 which is a porous elastic material. Therefore, debris D generated by dicing during piece division can be directly removed by the cleaning member 160 having the sponge roller portion 162. As a result, the semiconductor device 1 can be manufactured using semiconductor chips 110 from which debris D generated by dicing has been reliably removed, and connection failures of semiconductor chips can be reduced when performing three-dimensional mounting of the semiconductor chips 110.

[0050] In the semiconductor device manufacturing method according to this embodiment, a dicing tape 105 is attached to the back surface (back surface 101b of the substrate body 101) of the semiconductor substrate 100, opposite to the front surface, and then dicing is performed to create individual pieces. After individualization, the multiple semiconductor chips 110 are fixed on the dicing tape 105 or carrier and then cleaned with a cleaning member 160. This allows the surfaces 111 of the multiple semiconductor chips 110 to be cleaned together by the cleaning member 160.

[0051] In the semiconductor device manufacturing method according to this embodiment, it is preferable that at least one of the insulating layer 102 and insulating layer 202 is an organic insulating layer. In this case, even if debris D that could not be removed by cleaning with the cleaning member 160 remains on the surface 111 of the semiconductor chip 110, the organic insulating layer can confine the debris D, ensuring reliable bonding between the insulating layers 102 and 202.

[0052] Although embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments and can be applied to various embodiments. For example, in the above description, a semiconductor device manufacturing method was explained using a CoW bonding process as an example of hybrid bonding, but the semiconductor device manufacturing method according to this embodiment may also be applied to a chip-to-chip bonding process.

[0053] The present invention will be described more specifically below with reference to examples, but the present invention is not limited to these examples.

[0054] In the following experimental examples, the amount of debris D (foreign matter) remaining on the surface of a semiconductor chip was evaluated when the surface of the semiconductor chip was cleaned with pure water only after dicing (Comparative Example 1) and when the surface of the semiconductor chip was cleaned with pure water and a cleaning brush after dicing (Example 1).

[0055] The cleaning brush used in Example 1 was a brush roller (product name manufactured by AION Corporation) made of a roll-shaped sponge (porous material) and consisting of a PVA-based brush (or PVAt-based brush). The porosity and average pore diameter of the cleaning brush were 90% and 150 μm, respectively. The cleaning time (or semiconductor chip transport speed) was 60 seconds.

[0056] As shown in Figure 4(a), in Example 1, the debris D on the copper electrode was removed and reduced by cleaning with the cleaning brush and pure water described above. On the other hand, as shown in Figure 4(b), in Comparative Example 1, the debris D on the copper electrode could not be removed to much extent by pure water alone and remained. In both Experimental Example 1 and Comparative Example 1, pure water was used as the cleaning solution, so the roughness of the tip surface of the copper electrode did not change significantly from the state after CMP polishing in step (c). Note that the vertical and horizontal axes shown in Figures 4(a) and (b) represent the scale (μm).

[0057] As shown in the above experimental example, it was confirmed that cleaning with a PVA-based brush (or PVAt-based brush) removes more of the debris D on the copper electrode than cleaning with pure water alone. In the above experimental example, pure water was used as the cleaning solution, but it is conceivable that even more debris D on the electrode could be removed by using ammonia hydrogenated water. This is because ammonia hydrogenated water itself has a stronger debris removal capacity than pure water, and for example, it prevents the debris D that has been removed from reattaching to the surface of the semiconductor chip. Therefore, it is conceivable that the surface of the semiconductor chip can be further cleaned by supplying ammonia hydrogenated water as the cleaning solution while cleaning with a PVA brush (or PVAt-based brush).

[0058] 1...Semiconductor device, 100...Semiconductor substrate (first semiconductor substrate), 101...Substrate body (first substrate body), 101a...Front surface, 101b...Back surface, 102...Insulating layer (first insulating layer), 102A...Insulating portion, 103...Electrode (first electrode), 105...Dicing tape, 110...Semiconductor chip, 111...Front surface, 200...Semiconductor substrate (second semiconductor substrate), 201...Substrate body (second substrate body), 201a...Front surface, 202...Insulating layer (first insulating layer), 203...Electrode (second electrode), 150...Dicer, 160...Cleaning member, 162...Sponge roller part, 165...Supply part, 170...Roller member (support part).

Claims

1. A method for manufacturing a semiconductor device, comprising:

1. A step of polishing a first insulating layer and a plurality of first electrodes located on the surface side of a first semiconductor substrate, wherein the first semiconductor substrate comprises a first substrate body, the first insulating layer and the plurality of first electrodes provided on the surface of the first substrate body; 2. A step of dicing the first semiconductor substrate to obtain a plurality of semiconductor chips, each having an insulating portion corresponding to the first insulating layer and at least one of the plurality of first electrodes; 3. After dicing the first semiconductor substrate, a step of cleaning the surfaces of the plurality of semiconductor chips using a cleaning member having a porous elastic material; 4. A step of joining the insulating portion of the semiconductor chip to a second insulating layer located on the surface side of a second semiconductor substrate, wherein the second semiconductor substrate comprises a second substrate body, the second insulating layer and second electrodes provided on the surface of the second substrate body; and 5. A step of joining the first electrode of the semiconductor chip to the second electrode of the second semiconductor substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the porosity of the porous elastic material is 80% or more and 95% or less.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the average pore size of the porous elastic material is 50 μm or more and 200 μm or less.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the porous elastic body is a porous elastic body based on polyvinyl alcohol or polyvinyl acetal.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein in the step of separating the first semiconductor substrate into individual pieces, a dicing tape is attached to the back surface of the first semiconductor substrate opposite to the front surface before dicing, and in the cleaning step, the cleaning is performed with the cleaning member while the plurality of semiconductor chips are fixed on the dicing tape or carrier.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the cleaning member has a rotatable roll-shaped cleaning brush as the porous elastic body, and in the cleaning step, cleaning is performed by rotating the cleaning brush while supplying a cleaning liquid.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the cleaning solution is pure water or ammonia hydrochloride.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein at least one of the first insulating layer and the second insulating layer is an organic insulating layer.

9. A cleaning member used in a method for manufacturing a semiconductor device according to any one of claims 1 to 8, the cleaning member having a porous elastic body.

10. The cleaning member according to claim 9, wherein the porosity of the porous elastic material is 80% or more and 95% or less, the average pore diameter of the porous elastic material is 50 μm or more and 200 μm or less, and the porous elastic material is a polyvinyl alcohol-based or polyvinyl acetal-based porous elastic material.

11. A cleaning device comprising: a cleaning member used in a method for manufacturing a semiconductor device according to any one of claims 1 to 8; a support portion for supporting the plurality of semiconductor chips to be cleaned; and a supply portion for supplying cleaning liquid to the plurality of semiconductor chips.

12. The cleaning apparatus according to claim 11, wherein the supply unit supplies pure water or ammonia hydrochloride as the cleaning solution to the plurality of semiconductor chips.

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