Photodetection device and electronic equipment

Abstract

A photodetection device according to an embodiment of the present disclosure comprises: a pixel array in which photoelectric conversion units that output pulses in accordance with the incidence of photons are arranged in an array; and a signal processing unit which is arranged in the pixel array and which processes output signals from the photoelectric conversion units. The signal processing unit performs signal processing including thinning processing.

Description

Optical Detection Device and Electronic Device

[0001] The present disclosure relates to an optical detection device and an electronic device.

[0002] An optoelectronic conversion device including a photon detection element and a signal processing circuit that performs weighted addition processing on a detection signal based on an output signal of the photon detection element has been proposed (Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-44636

[0004] In a device for detecting light, it is desirable to be able to read signals efficiently.

[0005] It is desired to provide an optical detection device advantageous for signal reading.

[0006] The optical detection device according to an embodiment of the present disclosure includes a pixel array in which optoelectronic conversion units that output pulses in response to the incidence of photons are arranged in an array, and a signal processing unit that is arranged in the pixel array and processes output signals from the optoelectronic conversion units. The signal processing unit performs signal processing including decimation processing. The electronic device according to an embodiment of the present disclosure includes an optical detection device having a pixel array in which optoelectronic conversion units that output pulses in response to the incidence of photons are arranged in an array, and a signal processing unit that is arranged in the pixel array and processes output signals from the optoelectronic conversion units. The signal processing unit performs signal processing including decimation processing.

[0007] Figure 1 is a block diagram showing an example of the schematic configuration of a photodetector according to an embodiment of the present disclosure. Figure 2 is a diagram illustrating an example of the pixel configuration of a photodetector according to an embodiment of the present disclosure. Figure 3 is a timing chart showing an example of operation of a photodetector according to an embodiment of the present disclosure. Figure 4 is a diagram illustrating an example of operation of a photodetector according to an embodiment of the present disclosure. Figure 5 is a diagram illustrating an example of the pixel configuration of a photodetector according to an embodiment of the present disclosure. Figure 6 is a timing chart showing an example of operation of a photodetector according to an embodiment of the present disclosure. Figure 7 is a timing chart showing an example of operation of a photodetector according to an embodiment of the present disclosure. Figure 8 is a diagram illustrating an example of the configuration of a signal processing circuit of a photodetector according to an embodiment of the present disclosure. Figure 9 is a timing chart showing an example of operation of a photodetector according to an embodiment of the present disclosure. Figure 10 is a diagram illustrating an example of the configuration of a signal processing circuit of a photodetector according to an embodiment of the present disclosure. Figure 11 is a timing chart showing an example of operation of a photodetector according to an embodiment of the present disclosure. Figure 12 is a timing chart showing an example of operation of a photodetector according to an embodiment of the present disclosure. Figure 13 is a diagram showing an example of the schematic configuration of an electronic device according to an embodiment of the present disclosure. Figure 14 is a diagram illustrating an example of the configuration of a photodetector according to Modification 1 of the present disclosure. Figure 15 is a timing chart showing an example of operation of a photodetector according to Modification 1 of the present disclosure. Figure 16 is a timing chart showing an example of operation of a photodetector according to Modification 1 of the present disclosure. Figure 17 is a diagram illustrating an example of the configuration of a photodetector according to Modification 2 of the present disclosure. Figure 18 is a timing chart showing an example of operation of a photodetector according to Modification 2 of the present disclosure. Figure 19 is a diagram illustrating an example of the configuration of a photodetector according to Modification 3 of the present disclosure. Figure 20 is a timing chart showing an example of operation of a photodetector according to Modification 3 of the present disclosure. Figure 21 is a diagram illustrating an example of the configuration of a photodetector according to Modification 4 of the present disclosure. Figure 22 is a timing chart showing an example of operation of a photodetector according to Modification 4 of the present disclosure. Figure 23 is a diagram illustrating another example of the configuration of a photodetector according to Modification 4 of the present disclosure. Figure 24 is a timing chart showing another example of operation of a photodetector according to Modification 4 of the present disclosure.Figure 25 is a diagram illustrating an example configuration of a photodetector according to Modification 5 of the present disclosure. Figure 26 is a timing chart showing an example of operation of the photodetector according to Modification 5 of the present disclosure. Figure 27 is a diagram illustrating another example configuration of the photodetector according to Modification 5 of the present disclosure. Figure 28 is a timing chart showing another example of operation of the photodetector according to Modification 5 of the present disclosure. Figure 29 is a block diagram showing an example of a schematic configuration of a vehicle control system. Figure 30 is an explanatory diagram showing an example of the installation positions of the external information detection unit and the imaging unit.

[0008] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. Embodiments 2. Modifications 3. Examples of Use 4. Application Examples

[0009] <1. Embodiments> Figure 1 is a block diagram showing an example of a schematic configuration of a light detection device according to an embodiment of the present disclosure. The light detection device is a device capable of detecting incident light, and is configured, for example, as an imaging device. The light detection device 1 has a plurality of pixels P including light-receiving elements, and is configured to receive incident light and generate a signal.

[0010] The light detection device 1 is constructed using, for example, a substrate (such as a silicon (Si) substrate or a silicon on insulator (SOI) substrate) on which the light-receiving elements of each pixel P are provided. The light detection device 1 receives light transmitted through an optical system (not shown) and generates a signal. The light detection device 1 may also have a structure (i.e., a laminated structure) composed of multiple substrates (or semiconductor layers) stacked on top of each other.

[0011] The photodetector 1 has a region (pixel array 100) where multiple pixels P are provided, as shown in the example in Figure 1. Multiple pixels P are arranged in an array-like manner in the pixel array 100. As an example, the photodetector 1 has a pixel array 100 in which multiple pixels P are arranged in a matrix-like two-dimensional arrangement as the imaging area. Each pixel P includes, for example, an avalanche diode as a light-receiving element and is configured to generate a signal in response to the reception of photons.

[0012] The light detection device 1 captures incident light (image light) from the subject to be measured, for example, through an optical system including an optical lens and an aperture (aperture diaphragm). The light detection device 1 (imaging device) captures the image of the subject formed by the optical system. The light detection device 1 receives the light that has passed through the optical system and generates a pixel signal.

[0013] Each pixel P may be composed of a SPAD (single-photon avalanche diode). The photodetector of pixel P receives light from the object to be measured (e.g., visible light, infrared light, etc.), generates an electric charge through photoelectric conversion, and produces a photocurrent. The photodetector 1 is a device that can receive light and generate a signal, and can also be called a light receiving device.

[0014] The light detection device 1 is configured as an image sensor, a distance measuring sensor, etc. The light detection device 1 can be used in various electronic devices such as digital still cameras, video cameras, and mobile phones.

[0015] The light detection device 1 can also be applied to sensors capable of detecting events, such as event-driven sensors (also known as EVS (Event Vision Sensor), EDS (Event Driven Sensor), DVS (Dynamic Vision Sensor), etc.). The light detection device according to this disclosure is applicable to various electronic devices.

[0016] As an example, the light detection device 1 includes a pixel array 100, a pixel control unit 111, a processing unit 112, and a control unit 113, as shown in Figure 1. The number and arrangement of pixels P in the pixel array 100 can be changed as appropriate. The pixel control unit 111 is configured to control each pixel P in the pixel array 100.

[0017] The pixel control unit 111 is a control circuit (pixel control circuit) and is composed of multiple circuits, such as a buffer, a shift register, and an address decoder. The pixel control unit 111 generates signals for controlling pixels P and outputs them to each pixel P of the pixel array 100. The pixel control unit 111 is controlled by the control unit 113 and controls the pixels P of the pixel array 100.

[0018] The pixel control unit 111 generates signals for controlling pixels P, such as signals for controlling the photoelectric conversion unit 10 of pixel P, and supplies them to each pixel P. The pixel control unit 111 can perform control to read out pixel signals from each pixel P. The pixel control unit 111 can also be described as a pixel drive unit (pixel drive circuit) configured to drive each pixel P.

[0019] The control unit 113 is configured to control each part of the light detection device 1. The control unit 113 receives data such as a clock and operating mode commands from an external source, and can output data such as internal information of the light detection device 1. The control unit 113 is a control circuit and, for example, has a timing generator configured to generate various timing signals.

[0020] The control unit 113 controls the operation of the pixel control unit 111 and the processing unit 112, etc., based on various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. The control unit 113 may include circuits such as a PLL (Phase Locked Loop) and a DAC (Digital to Analog Converter).

[0021] The processing unit 112 is configured to acquire signals from each pixel P and perform signal processing. The processing unit 112 is a processing circuit and consists of circuits that perform various signal processing on the input pixel signals. The processing unit 112 (processing circuit) includes an arithmetic circuit, a memory circuit, and the like.

[0022] The processing unit 112 can perform various signal processing operations, such as filtering, noise reduction, and interpolation of pixel signals. For example, the processing unit 112 performs signal processing on the pixel signals output from each pixel P and outputs the processed pixel signals. The processing unit 112 may include a processor and memory.

[0023] The processing unit 112 performs various signal processing on the signal of each pixel P and can generate and output image data showing the subject image, image data relating to the distance to the measurement target (distance image data), etc. Note that some or all of the pixel control unit 111, processing unit 112, and control unit 113 may be configured as an integral unit.

[0024] The pixel array 100, pixel control unit 111, processing unit 112, control unit 113, etc. described above may be provided on a single substrate or divided and provided on multiple substrates. The pixel control unit 111, processing unit 112, control unit 113, etc. may be provided, for example, as peripheral circuits in the peripheral region of the pixel array 100. The light detection device 1 may have a laminated structure formed by stacking multiple substrates.

[0025] Figure 2 is a diagram illustrating an example of the pixel configuration of a photodetector according to an embodiment. The pixel P of the photodetector 1 includes a photoelectric conversion unit 10 containing an avalanche diode 20 as a light-receiving element, a signal processing unit 50, and a column readout circuit 105. The signal processing unit 50 is a signal processing circuit and is provided, for example, for each photoelectric conversion unit 10. Note that the signal processing unit 50 may be provided for multiple photoelectric conversion units 10. The photodetector 1 also has an arithmetic circuit 120.

[0026] Furthermore, Figure 3 is a timing chart showing an example of operation of the light detection device according to the embodiment. The timing chart shown in Figure 3 has time on the horizontal axis and illustrates the signals VK and PLS generated at pixel P, the signal PIX_OUT output from pixel P, and the signal OUT generated in the arithmetic circuit 120.

[0027] The photoelectric conversion unit 10 is configured, for example, to output a pulse in response to the incidence of a photon. The photoelectric conversion unit 10 includes an avalanche diode 20, a current supply circuit 30, and a detection circuit 40. The photoelectric conversion units 10 are arranged in an array in the pixel array 100. Note that the configuration of the photoelectric conversion unit 10 is not limited to the illustrated example and can be changed as appropriate. The photoelectric conversion unit 10 can also be called a photoelectric conversion circuit.

[0028] The avalanche diode 20 is configured to receive light and generate a signal. The avalanche diode 20 is, for example, a SPAD (Single Photon Avalanche Diode) and has a multiplication region (multiplication section) capable of avalanche multiplication. The avalanche diode 20 can convert incident photons into electric charge and output an electrical signal (signal VK in the example shown in Figure 2, etc.) corresponding to the incident photons.

[0029] The avalanche diode 20 is electrically connected, for example, to the current supply circuit 30 and the detection circuit 40. In the example shown in Figure 2, the cathode, one electrode of the avalanche diode 20, is electrically connected to node N1, which is connected to the current supply circuit 30 and the detection circuit 40. The anode, the other electrode of the avalanche diode 20, is electrically connected, for example, to wiring, electrodes, etc., to which a relatively low voltage is supplied.

[0030] In the example shown in Figure 2, the anode of the avalanche diode 20 is electrically connected to the potential line L2, which serves as the power line. A voltage VSP is supplied to the anode of the avalanche diode 20 via the potential line L2, for example, from a power supply unit (i.e., a voltage source) capable of supplying voltage. The voltage VSP is, for example, a negative voltage.

[0031] The current supply circuit 30 is configured to supply current to the avalanche diode 20. The current supply circuit 30 (supply unit) is electrically connected to the potential line L1 and can supply current and voltage to the avalanche diode 20. The potential line L1 is a wire to which a predetermined potential (voltage) is supplied. In the example shown in Figure 2, the potential line L1 is a power line to which the power supply voltage VDD is supplied.

[0032] The current supply circuit 30 is, for example, composed of a transistor M1. Transistor M1 is, for example, a MOS transistor (MOSFET) having gate, source, and drain terminals. In the example shown in Figure 2, transistor M1 is a P-type transistor (for example, a PMOS transistor).

[0033] One of the source and drain of transistor M1 is electrically connected to a potential line L1 to which the power supply voltage VDD is supplied, and the other of the source and drain of transistor M1 is electrically connected to an avalanche diode 20. The current supply circuit 30 is configured, for example, as a current source capable of supplying current to the avalanche diode 20. The current supply circuit 30 can also be called a recharge circuit (recharge section).

[0034] The transistor M1 of the current supply circuit 30 can, for example, generate a current corresponding to the signal level of the signal input to its gate and supply the generated current to the avalanche diode 20. The current supply circuit 30 (supply unit) may be configured using a resistive element. The current supply circuit 30 may also be configured with a switch that electrically connects or disconnects the potential line L1 and the avalanche diode 20.

[0035] A voltage greater than the breakdown voltage of the avalanche diode 20 can be applied between the cathode and anode of the avalanche diode 20 by the voltage supplied via the current supply circuit 30 and the voltage VSP supplied by the potential line L2. In other words, the potential difference across the avalanche diode 20 can be set to a potential difference greater than the breakdown voltage.

[0036] The avalanche diode 20 becomes operational in Geiger mode when a reverse bias voltage greater than the breakdown voltage is applied. In Geiger mode, the avalanche diode 20 can generate an avalanche multiplication phenomenon in response to the incidence of photons, producing a pulsed current. At pixel P, a signal VK corresponding to the photocurrent flowing through the avalanche diode 20 due to the incidence of photons is output to the detection circuit 40.

[0037] The current supply circuit 30 supplies current to the avalanche diode 20, for example, when avalanche multiplication occurs and the potential difference between the electrodes of the avalanche diode 20 is small. The current supply circuit 30 (i.e., the recharge circuit) recharges the avalanche diode 20, making it possible to operate the avalanche diode 20 again in Geiger mode. The current supply circuit 30 can recharge the avalanche diode 20 and recharge the voltage of the avalanche diode 20.

[0038] The detection circuit 40 is configured to generate a signal PLS based on the signal VK generated by the avalanche diode 20. The detection circuit 40 can output a signal PLS which is a voltage signal based on the current of the avalanche diode 20. The detection circuit 40 is an output circuit and is configured to output a signal PLS.

[0039] The detection circuit 40 is configured to output a pulse based on the voltage of the avalanche diode 20, for example. The detection circuit 40 detects the output voltage of the avalanche diode 20 and outputs it as a pulse. The detection circuit 40 is configured, for example, using an inverter (INV). The detection circuit 40 has, for example, an input section 41 and an output section 42, and can output an inverted signal of the input signal.

[0040] In the example shown in Figure 2, the detection circuit 40 is composed of an INV circuit. The INV circuit is composed of, for example, a PMOS transistor and an NMOS transistor connected in series between the potential line L1 and the reference potential line. As an example, the reference potential line is a wire to which a voltage VSS (e.g., 0V) is applied, i.e., a ground line (earth wire).

[0041] The input section 41 of the detection circuit 40 is electrically connected, for example, to the cathode of the avalanche diode 20 and the current supply circuit 30. In the example shown in Figure 2, the input section 41 of the detection circuit 40 (i.e., the inverter circuit) is electrically connected to node N1 which connects the avalanche diode 20 and the current supply circuit 30.

[0042] The detection circuit 40 receives a signal VK from the avalanche diode 20. The signal level of signal VK, i.e., the voltage (potential) of signal VK, changes according to the current flowing through the avalanche diode 20. The detection circuit 40 (i.e., the output circuit) outputs a low-level signal PLS, for example, when the voltage of signal VK is higher than a threshold. Also, the detection circuit 40 outputs a high-level signal PLS when the voltage of signal VK is lower than a threshold.

[0043] In the example shown in FIG. 2, the INV circuit, which is the detection circuit 40, causes the voltage of the signal PLS to transition from a low level to a high level when the voltage of the signal VK becomes lower than the threshold voltage of the INV circuit due to the reception of photons in the avalanche diode 20. Further, when the voltage of the signal VK becomes higher than the threshold voltage of the INV circuit as the avalanche diode 20 is recharged by the current supply circuit 30, the detection circuit 40 causes the voltage of the signal PLS to transition from a high level to a low level.

[0044] The detection circuit 40 can output a signal PLS, which is a pulse signal based on the voltage of the signal VK, to the signal processing unit 50. Note that the configuration of the detection circuit 40 is not limited to the example described above and can be changed as appropriate. The detection circuit 40 may be configured by a buffer circuit, an AND circuit, a NAND circuit, an OR circuit, a NOR circuit, or the like. The detection circuit 40 may have a level conversion circuit (level shifter).

[0045] The signal processing unit 50 is configured to be able to acquire the pixel signal from the photoelectric conversion unit 10 and perform a thinning process. For example, the signal processing unit 50 performs a thinning process on the signal PLS input from the detection circuit 40 of the photoelectric conversion unit 10 and is configured to generate a signal PIX_OUT by the thinning process of the signal PLS. The signal processing unit 50 may be provided for each photoelectric conversion unit 10 within the pixel array 100. The signal processing unit 50 may be provided for a plurality of photoelectric conversion units 10. For example, one signal processing unit 50 is arranged for a plurality of photoelectric conversion units 10.

[0046] In the example shown in FIG. 2, a signal PLS, which is a pulse signal, is input to the signal processing unit 50 from the detection circuit 40. The signal processing unit 50 (signal processing circuit) generates and outputs a signal PIX_OUT having a number of pulses less than the number of pulses of the signal PLS, for example, by performing a thinning process on the signal PLS.

[0047] The signal processing unit 50 has, for example, a decimation filter. The signal processing unit 50 can be configured as a decimation filter that performs decimation of the signal PLS. The signal processing unit 50 generates, for example, a signal PIX_OUT having a data rate lower than the data rate of the signal PLS by means of thinning processing (i.e., decimation processing) on the signal PLS.

[0048] The signal processing unit 50 outputs the signal PIX_OUT obtained by the thinning process. In the photodetection device 1, for example, the signal PIX_OUT is output as a pixel signal of the pixel P to the arithmetic circuit 120 by the column readout circuit 105. The column readout circuit 105 is configured using, for example, switches.

[0049] The column readout circuit 105 is configured to be able to read out the pixel signal generated by the signal processing unit 50 outside the pixel array 100. The column readout circuit 105 is connected, for example, between the signal processing unit 50 and the arithmetic circuit 120 and is configured to output the signal PIX_OUT from the signal processing unit 50 to the arithmetic circuit 120. The arithmetic circuit 120 is provided outside the pixel array 100 (pixel array) including, for example, a plurality of pixels P.

[0050] The arithmetic circuit 120 is configured to be able to acquire pixel signals and execute arithmetic processing. The arithmetic circuit 120 is configured to perform, for example, integration processing (or low-pass filter processing). The arithmetic circuit 120 is provided for each pixel P or for every plurality of pixels P outside the pixel array 100. For example, the processing unit 112 (see also FIG. 1) of the photodetection device 1 includes the arithmetic circuit 120.

[0051] The arithmetic circuit 120 is configured to acquire the signal PIX_OUT and generate a signal OUT based on the signal PIX_OUT. The arithmetic circuit 120 can generate, for example, a signal OUT (i.e., a signal OUT corresponding to the amount of incident light) corresponding to the light reception frequency in the avalanche diode 20 by performing a process of integrating the signal PIX_OUT.

[0052] The arithmetic circuit 120 is configured to generate a signal OUT based on the number of pulses of the signal PIX_OUT, for example. The arithmetic circuit 120 is configured using a counter (counter circuit) as an example. The arithmetic circuit 120 counts the pulses of the signal PIX_OUT and generates a signal OUT corresponding to the number of pulses of the signal PIX_OUT.

[0053] The arithmetic circuit 120 may be configured using a moving average circuit. The arithmetic circuit 120 generates the signal OUT by, for example, performing a moving average operation on the signal PIX_OUT. The arithmetic circuit 120 may also include an FIR (Finite Impulse Response) filter, an IIR (Infinite Impulse Response) filter, and the like.

[0054] Furthermore, the arithmetic circuit 120 may be configured to generate a signal OUT based on the pulse interval of the signal PIX_OUT. The arithmetic circuit 120 includes a pulse interval detection circuit, for example, a counter (i.e., a time counter) configured to count the interval between pulses. The arithmetic circuit 120 can count the pulse interval of the signal PIX_OUT and generate a signal OUT corresponding to the pulse interval of the signal PIX_OUT.

[0055] Figure 4 is a diagram illustrating an example of operation of the light detection device according to the embodiment. In Figure 4, the signal PLS, the signal PIX_OUT, and the signal OUT are shown on the same time axis. As shown in the example in Figure 4, the signal processing unit 50 generates the signal PIX_OUT by decimation processing of the signal PLS and outputs the signal PIX_OUT to the arithmetic circuit 120.

[0056] The arithmetic circuit 120 generates the signal OUT by performing arithmetic processing (e.g., integration processing) on ​​the signal PIX_OUT, as schematically shown in Figure 4. For example, in the processing unit 112 having the arithmetic circuit 120, a signal OUT is generated for each pixel P, and image data including the signal OUT for each pixel P is generated.

[0057] In the light detection device 1 according to this embodiment, as described above, each pixel P has a signal processing unit 50 capable of performing decimation. Therefore, pixel signal decimation can be performed at pixel P, and the pixel signal after decimation can be read out from pixel P. This makes it possible to perform efficient signal readout.

[0058] In the optical detection device 1, as shown in the example in Figure 4, for example, the signal PIX_OUT, which has a reduced data amount (or data rate) due to decimation, can be read out as a pixel signal from pixel P, enabling efficient pixel signal readout. This makes it possible to improve functionality while suppressing an increase in circuit area.

[0059] Figure 5 is a diagram illustrating an example of the pixel configuration of a light detection device according to an embodiment. Figures 6 and 7 are timing charts showing an example of operation of the light detection device according to an embodiment. The signal processing unit 50 may be configured to change the decimation period. The signal processing unit 50 is configured to change the decimation period in response to a control signal input from an external source, for example.

[0060] In the example shown in Figure 5, the signal processing unit 50 is supplied with a control signal, Sc, from an external circuit (for example, a pixel control unit 111). The signal processing unit 50 switches the pulse decimation period of the signal PLS according to the signal Sc. The signal processing unit 50 can generate the signal PIX_OUT by performing a decimation process on the signal PLS with a period set by the signal Sc.

[0061] The photodetector 1, for example, has a first mode and a second mode as operating modes. For example, when the first mode is set by the signal Sc, the signal processing unit 50 performs a relatively long period of decimation processing, as shown in the example in Figure 6. In the example of the first mode shown in Figure 6, the signal processing unit 50 generates and outputs a signal PIX_OUT, which has one pulse for every four pulses of the signal PLS.

[0062] Furthermore, when the second mode is set by the control signal Sc, the signal processing unit 50 performs a relatively short period of decimation processing, as shown in the example in Figure 7. In the example of the second mode shown in Figure 7, the signal processing unit 50 generates and outputs a signal PIX_OUT, which has one pulse for every two pulses of the signal PLS.

[0063] Figure 8 is a diagram illustrating an example of the configuration of the signal processing unit of the photodetector according to the embodiment. Figure 9 is a timing chart showing an example of the operation of the photodetector according to the embodiment. The signal processing unit 50 includes, for example, a counter 60 and a detection circuit 70, as shown in the example in Figure 8. In Figure 9, the signal PLS, signals S1 and S2 output from the counter 60, and the signal PIX_OUT are shown on the same time axis.

[0064] The counter 60 includes, for example, multiple stages of flip-flops (flip-flops C1 and C2 in Figure 8) and is configured to count the signal PLS. For example, flip-flop C1 holds the first bit of the count value and outputs a signal S1 indicating the first bit of the count value. Flip-flop C2 holds the second bit of the count value and outputs a signal S2 indicating the second bit of the count value.

[0065] The detection circuit 70 is configured to generate and output a signal PIX_OUT as a pixel signal based on the output signal of the counter 60. The detection circuit 70 can be described as an overflow detection circuit. The detection circuit 70 is constructed using logic circuits such as AND circuits, NAND circuits, and OR circuits. In the example shown in Figure 8, the detection circuit 70 has an AND circuit 71 and an AND circuit 72.

[0066] The AND circuit 71 receives the signal S1 from flip-flop C1 (i.e., the count value of the first bit) and the signal S2 from flip-flop C2 (i.e., the count value of the second bit). The AND circuit 72 receives the output signal from AND circuit 71 and the signal PLS from detection circuit 40.

[0067] As shown in the example in Figure 9, the detection circuit 70 outputs a signal PIX_OUT corresponding to the signal PLS when both signals S1 and S2 are at a high level. The detection circuit 70 (i.e., the overflow detection circuit) can generate and output a signal PIX_OUT having one pulse for every four pulses of the signal PLS. Note that the configuration of the counter 60 and the detection circuit 70 is not limited to the illustrated example and can be changed as appropriate.

[0068] Figure 10 is a diagram illustrating an example of the configuration of the signal processing unit of the photodetector according to the embodiment. Figures 11 and 12 are timing charts showing an example of operation of the photodetector according to the embodiment. The signal processing unit 50 may be configured to change the decimation period. The detection circuit 70 of the signal processing unit 50 is configured to include, for example, an OR circuit 73.

[0069] The OR circuit 73 receives a signal Sc from an external circuit (for example, the pixel control unit 111) and a signal S2 from the flip-flop C2. The AND circuit 71 receives the output signal from the OR circuit 73 and a signal S1 from the flip-flop C1. The signal processing unit 50 sets the decimation period according to the control signal Sc.

[0070] The signal processing unit 50 has multiple operating modes (e.g., a first mode, a second mode). For example, when the signal Sc is at a low level, i.e., in the first mode, the signal processing unit 50 performs a relatively long period of decimation processing, as shown in the example in Figure 11. In the example shown in Figure 11, the signal processing unit 50 generates and outputs a signal PIX_OUT, which has one pulse for every four pulses of the signal PLS.

[0071] When the signal Sc is at a high level, i.e., in the second mode, the signal processing unit 50 performs a relatively short period of decimation, as shown in the example in Figure 12. In the example shown in Figure 12, the signal processing unit 50 generates and outputs a signal PIX_OUT, which has one pulse for every two pulses of the signal PLS.

[0072] Figure 13 shows an example of a schematic configuration of an electronic device according to an embodiment. The electronic device 200 includes, for example, a light detection device 1, an optical system 201, a control unit 202, and a processing unit 203. The optical system 201 includes one or more lenses and guides light from the object to be measured to the light detection device 1. The optical system 201 is configured, for example, as an imaging optical system and can form an image of the object to be measured on the light detection device 1.

[0073] The photodetector 1, for example, captures an image of a subject formed by the optical system 201. The photodetector 1 generates a pixel signal by photoelectric conversion of the received light (visible light, infrared light, etc.). The control unit 202 is configured to control the photodetector 1. The control unit 202 supplies a signal to the photodetector 1 to control its operation.

[0074] The processing unit 203 is configured to perform signal processing on signals output from the light detection device 1 (for example, pixel signals of each pixel). The processing unit 203 (i.e., the signal processing unit) includes, for example, a processor and memory (ROM, RAM, etc.), and is configured to perform various signal processing (information processing). The electronic device 200 can be applied to various electronic devices.

[0075] [Function and Effects] The photodetector according to this embodiment comprises a pixel array (pixel array 100) in which photoelectric conversion units (photoelectric conversion units 10) that output pulses in response to the incidence of photons are arranged in an array, and a signal processing unit (signal processing unit 50) arranged within the pixel array that processes the output signals from the photoelectric conversion units. The signal processing unit performs signal processing, including decimation.

[0076] The photodetector 1 according to this embodiment comprises a pixel array 100 having a plurality of photoelectric conversion units 10, and a signal processing unit 50 that processes output signals from the photoelectric conversion units 10. The signal processing unit 50 is configured to perform decimation. This makes it possible to realize a photodetector that is advantageous for signal readout.

[0077] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0078] <2. Modified Examples> (2-1. Modified Example 1) Figure 14 is a diagram illustrating an example of the configuration of a photodetector according to Modified Example 1 of the present disclosure. Figures 15 and 16 are timing charts showing an example of operation of the photodetector according to Modified Example 1. The signal processing unit 50 of pixel P has an integration circuit 74 and a detection circuit 70 including a comparison circuit 75. The signal processing unit 50 is configured to generate and output the signal PIX_OUT based on the comparison result between the signal CNT corresponding to the number of pulses of the signal PLS and the reference signal REF.

[0079] The integrating circuit 74 of the signal processing unit 50 includes, for example, a current source 61, a switch 62, and a capacitive element Ca. The integrating circuit 74 is configured to generate a signal CNT having a voltage value (signal value) corresponding to the number of pulses of the signal PLS. The integrating circuit 74 maintains the voltage of the signal CNT corresponding to the number of pulses of the signal PLS. The integrating circuit 74 is configured as an analog counter circuit and can also be called an analog counter.

[0080] Switch 62 is electrically connected between the capacitive element Ca and the current source 61. Switch 62 is composed of, for example, a transistor M10. In the example shown in Figure 14, transistor M10 is an NMOS transistor. Switch 62 is controlled on and off by the signal PLS input from the detection circuit 40.

[0081] The capacitive element Ca has a predetermined capacitance value and is configured to hold a voltage. The capacitive element Ca is electrically connected to the transistor M10, which acts as a switch 62. The capacitive element Ca is composed of, for example, a MOS capacitor, an MIM (Metal-Insulator-Metal) capacitor, etc. The switch 62 electrically connects or disconnects the capacitive element Ca and the current source 61.

[0082] In the integrating circuit 74, for example, the switch 62 turns on in response to a pulse of the signal PLS, and the voltage of the capacitive element Ca, i.e., the signal voltage of the signal CNT, decreases in response to the current of the current source 61. The voltage of the capacitive element Ca decreases with each pulse of the signal PLS (i.e., for example, each period during which the signal PLS is at a high level), and a signal CNT is generated with a voltage that changes according to the number of pulses of the signal PLS.

[0083] The comparison circuit 75 is configured, for example, by a comparator circuit, and is configured to compare the signal CNT and the reference signal REF. The comparison circuit 75 compares the voltage of the signal CNT, which is the output voltage of the integrating circuit 74, with the reference voltage, which is the voltage of the reference signal REF, and outputs the signal PIX_OUT, which is the output signal as a result of the comparison. The signal PIX_OUT is a signal that indicates the magnitude relationship between the voltage of the signal CNT and the voltage of the reference signal REF.

[0084] Furthermore, the signal processing unit 50 has a reset circuit 76. The reset circuit 76 includes, for example, transistors M11 to M13 and is configured to reset the voltage held by the capacitive element Ca, i.e., the voltage of the signal CNT. The reset circuit 76 is configured, for example, as part of the detection circuit 70 or the integration circuit 74.

[0085] Transistor M11 of the reset circuit 76 is a P-type transistor (PMOS transistor in Figure 14). Transistors M12 and M13 are N-type transistors (NMOS transistors in Figure 14), respectively. The reset circuit 76 may also include transistor M14 (PMOS transistor in Figure 14).

[0086] The reset circuit 76 resets the charge stored in the capacitive element Ca and resets the voltage of the capacitive element Ca in accordance with the signal PIX_OUT, which is the output signal of the comparison circuit 75. In the example shown in Figure 14, when the signal PIX_OUT is at a high level and the signal PLS is at a low level, a low-level signal RESET is generated. When the signal RESET becomes low, the transistor M14 turns on, and the voltage of the capacitive element Ca is reset.

[0087] The signal processing unit 50 is configured to generate a pulse for signal PIX_OUT, i.e., perform a decimation operation, when the voltage of signal CNT, based on the number of pulses of signal PLS, reaches the voltage of reference signal REF (reference voltage). The decimation interval (i.e., decimation frequency) can be controlled by adjusting the value (level) of the reference signal REF.

[0088] In the first mode shown in Figure 15, the signal processing unit 50 performs decimation with a long period (i.e., low frequency). For example, the signal processing unit 50 generates a signal PIX_OUT having one pulse for every four pulses of the signal PLS. In the second mode shown in Figure 16, the signal processing unit 50 performs decimation with a short period (i.e., high frequency). For example, the signal processing unit 50 may generate a signal PIX_OUT having one pulse for every two pulses of the signal PLS.

[0089] (2-2. Modification 2) Figure 17 is a diagram illustrating an example of the configuration of the photodetector according to Modification 2. Figure 18 is a timing chart showing an example of the operation of the photodetector according to Modification 2. The signal processing unit 50 has a filter 80 and a sampling circuit 90. The filter 80 (filter circuit) is connected, for example, between the detection circuit 40 and the sampling circuit 90.

[0090] Figure 18 shows the signal PLS, the signal S_LPF output by the filter 80, and the signal PIX_OUT on the same time axis. Figure 18 also shows the transition (rising or falling) timing of the signal Sampling input to the sampling circuit 90 with a dashed line. The signal Sampling is, for example, a sampling timing signal (clock signal or pulse signal) supplied by the pixel control unit 111.

[0091] As shown in the example in Figure 17, the filter 80 has, for example, a resistive element R and a capacitive element Cb, and is configured as a low-pass filter (LPF). The filter 80 (low-pass filter) generates and outputs a signal S_LPF having a voltage corresponding to the number of pulses of the signal PLS input from the detection circuit 40.

[0092] The sampling circuit 90 (i.e., sample-and-hold circuit) is configured to, for example, sample the signal S_LPF in response to an external signal, the signal Sampling, and output the signal PIX_OUT based on the signal S_LPF. The sampling circuit 90 can capture and hold the signal S_LPF in synchronization with the signal Sampling, and generate and output the signal PIX_OUT corresponding to the signal S_LPF.

[0093] (2-3. Modification 3) Figure 19 is a diagram illustrating an example of the configuration of the photodetector according to Modification 3. Figure 20 is a timing chart showing an example of the operation of the photodetector according to Modification 3. The current supply circuit 30 is configured, for example, using a transistor M1 as a switch. The current supply circuit 30 can also be called a recharge circuit or a connection circuit.

[0094] In the timing chart shown in Figure 20, the signal VK, the detection period control signal which is input to the current supply circuit 30, the detection timing control signal which is input to the detection circuit 40, the signal PLS, the signals S1 and S2 output from the counter 60, and the signal PIX_OUT are all shown on the same time axis.

[0095] The current supply circuit 30 is controlled by a signal input from a control circuit (such as the pixel control unit 111 or control unit 113) that controls the photoelectric conversion unit 10. The current supply circuit 30 (connection circuit) is controlled, for example, to a low resistance state (i.e., a low impedance state) or a high resistance state (i.e., a high impedance state) according to the signal voltage input from the control circuit.

[0096] One of the source and drain of transistor M1 is electrically connected to a potential line L1 to which, for example, the power supply voltage VDD is supplied. The other of the source and drain of transistor M1 is electrically connected to an avalanche diode 20. The current supply circuit 30 is controlled to be ON (conducting) or OFF (non-conducting) by, for example, a pixel control unit 111.

[0097] In the example shown in Figure 19, the current supply circuit 30 is configured to electrically connect or disconnect the potential line L1 and the avalanche diode 20 based on the detection period control signal. The current supply circuit 30 is controlled by the detection period control signal, which is a pulse signal, and is configured to be rechargeable for the avalanche diode 20. The photoelectric conversion unit 10 is reset by the detection period control signal.

[0098] In the light detection device 1, for example, as shown in Figure 20, a detection period control signal, which is a pulse signal, is repeatedly input to the current supply circuit 30, and the current supply circuit 30 is intermittently turned on. As an example, the pixel control unit 111 outputs the detection period control signal to the current supply circuit 30 to control the timing of recharging the avalanche diode 20.

[0099] The pixel control unit 111 performs intermittent recharging of the avalanche diode 20, for example, by controlling the current supply circuit 30. The current supply circuit 30 is turned on at predetermined cycles (time intervals) according to the detection period control signal, and can perform periodic recharging of the avalanche diode 20.

[0100] The detection circuit 40 is configured, for example, using transistors M2, M3, and M4. Transistors M2 to M4 are connected in series between a potential line L11 and a reference potential line (for example, a ground line). The potential line L11 is a wire to which a predetermined potential (voltage) is applied.

[0101] Transistors M2 and M3 are P-type transistors (PMOS transistors in Figure 19), respectively. Transistor M4 is an N-type transistor (NMOS transistor in Figure 19). The gates of transistors M2 and M4 are electrically connected to each other.

[0102] A detection timing control signal is input to the gates of transistors M2 and M4 by a control circuit that controls the photoelectric conversion unit 10, such as the pixel control unit 111. The pixel control unit 111 outputs the detection timing control signal, which is a pulse signal, to transistors M2 and M4, and controls the generation and output timing of the signal PLS. The timing of pulse generation is controlled in synchronization with the detection timing control signal.

[0103] The detection circuit 40 is configured to generate a signal PLS based on the current of the avalanche diode 20 in response to the detection timing control signal. The detection circuit 40 generates and outputs the signal PLS in synchronization with the detection timing control signal. As an example, the detection circuit 40 generates and outputs a signal PLS corresponding to the voltage of signal VK during the period when the detection timing control signal is at a low level. The detection circuit 40 can output a signal PLS, which is controlled by the detection timing control signal and is a pulse signal, to the signal processing unit 50.

[0104] In the example shown in Figure 19, the signal processing unit 50 includes a counter 60 and a detection circuit 70 (overflow detection circuit). Based on the signal PLS input from the detection circuit 40, the signal processing unit 50 generates and outputs the signal PIX_OUT as a pixel signal, as shown in the example in Figure 20. The same effects as those of the above-described embodiment can be obtained in the optical detection device 1 according to this modified example.

[0105] (2-4. Modification 4) In the embodiments and modifications described above, examples of the configuration of the light detection device 1 have been explained, but the configuration of the light detection device 1 (imaging device) is not limited to the examples described above. For example, the configuration of the pixel P and the signal processing unit 50 is not limited to the illustrated example and can be changed as appropriate.

[0106] Figure 21 is a diagram illustrating an example configuration of the photodetector according to Modification 4. Figure 22 is a timing chart showing an example of operation of the photodetector according to Modification 4. The signal processing unit 50 includes, for example, a holding circuit 95, a filter 80, and a sampling circuit 90. The filter 80 may include at least one of the sampling circuit 90 and the holding circuit 95.

[0107] In the timing chart shown in Figure 22, the signals VK, detection period control signal, detection timing control signal, Sampling signal, PLS signal, S_LATCH signal, F1 to F3 signals, FIR_OUT signal, and PIX_OUT signal are all shown on the same time axis.

[0108] The filter 80 includes, for example, a plurality of delay circuits 81 (in the example shown in Figure 21, delay circuits 81a, 81b, and 81c) and a plurality of adder circuits 82 (in the example shown in Figure 21, adder circuits 82a, 82b, and 82c), and is configured as an FIR filter. The delay circuits 81 (delay section) are configured, for example, using a plurality of inverters or buffers. The adder circuits 82 (adder section) are configured to perform addition processing of input signals.

[0109] The holding circuit 95 is configured, for example, by a latch (latch circuit). The holding circuit 95 is configured to sample the signal PLS and output the signal S_LATCH based on the signal PLS. As an example, the holding circuit 95 may acquire and hold the signal PLS in synchronization with the detection timing control signal, and generate and output the signal S_LATCH corresponding to the signal PLS.

[0110] The filter 80 (i.e., the FIR filter) is configured to generate signals F1, F2, and F3 by delaying the signal S_LATCH using delay circuits 81a, 81b, and 81c, as shown in the example in Figure 22. The filter 80 can also generate the signal FIR_OUT by adding signals F1, F2, and F3 using adder circuits 82a, 82b, and 82c, and output the signal FIR_OUT.

[0111] The sampling circuit 90 is configured to sample the signal FIR_OUT in response to the signal Sampling and output the signal PIX_OUT based on the signal FIR_OUT. The sampling circuit 90 can capture and hold the signal FIR_OUT in synchronization with the signal Sampling, and generate and output the signal PIX_OUT corresponding to the signal FIR_OUT.

[0112] Figure 23 is a diagram illustrating another configuration example of the photodetector according to Modification 4. Figure 24 is a timing chart showing another operation example of the photodetector according to Modification 4. The signal processing unit 50 includes, for example, a holding circuit 95, a plurality of integrating circuits 85 (integrating circuit 85a, integrating circuit 85b in Figure 23), and a sampling circuit 90.

[0113] The timing chart shown in Figure 24 illustrates the signal VK, the detection period control signal, the detection timing control signal, the signal Sampling, the signal PLS, the signal S_LATCH, the signals INTEG1 and INTEG2 generated by the integrating circuits 85a and 85b, and the signal PIX_OUT.

[0114] The integrating circuits 85a and 85b each include, for example, a delay circuit 86 and an adder circuit 87. The delay circuit 86 (delay section) is composed of, for example, multiple stages of inverters or buffers. The adder circuit 87 (adder section) is configured to perform addition processing of input signals.

[0115] The signal processing unit 50 is configured to generate signals INTEG1, INTEG2, and FIR_OUT using integration circuits 85a and 85b, as shown in the example in Figure 23. The sampling circuit 90, for example, samples the signal FIR_OUT output by the integration circuit 85b and outputs a signal PIX_OUT based on the signal FIR_OUT. In this modified example, the same effects as in the above-described embodiment can be obtained.

[0116] (2-5. Modification 5) Figure 25 is a diagram illustrating an example of the configuration of the photodetector according to Modification 5. Figure 26 is a timing chart showing an example of the operation of the photodetector according to Modification 5. In the example shown in Figure 25, the signal processing unit 50 has a counter 60 and a sampling circuit 90. The signal processing unit 50 may be configured to output a signal PIX_OUT based on the value of the upper bit (e.g., the most significant bit) of the count value from the counter 60.

[0117] In the timing chart shown in Figure 26, the signal VK, the detection period control signal, the detection timing control signal, the signal Sampling, the signal PLS, the signals S1 and S2 output by the counter 60, the signal PIX_OUT, and the signal OUTA generated by the calculation circuit 120 are all shown on the same time axis.

[0118] The sampling circuit 90 is configured to sample the most significant bit of the count value from the counter 60, for example, the signal S2 that represents the most significant bit, and to output the signal PIX_OUT based on the signal S2. For example, the sampling circuit 90 captures and holds the signal S2 in synchronization with the signal Sampling, and generates the signal PIX_OUT corresponding to the signal S2. The sampling circuit 90 can also output the signal PIX_OUT to the arithmetic circuit 120.

[0119] The arithmetic circuit 120 generates a signal OUTA having pulses corresponding to the transition timing (e.g., falling edge) of the signal PIX_OUT output by the signal processing unit 50, for example, as shown in the example in Figure 26. Based on the signal OUTA obtained by the decimation process, the arithmetic circuit 120 can generate a signal OUT corresponding to the light reception frequency in the avalanche diode 20.

[0120] Figure 27 is a diagram illustrating another configuration example of the photodetector according to Modification 5. Figure 28 is a timing chart showing another operation example of the photodetector according to Modification 5. The signal processing unit 50 has, for example, a holding circuit 96. The holding circuit 96 is connected between the counter 60 and the sampling circuit 90. The holding circuit 96 is configured, for example, using a latch circuit.

[0121] In the timing chart shown in Figure 28, the signal VK, the detection period control signal, the detection timing control signal, the signal Sampling, the signal PLS, the signals S1 and S2, the signal OF_LATCH, the signal PIX_OUT, and the signal OUTA generated by the arithmetic circuit 120 are all shown on the same time axis.

[0122] The holding circuit 96 is configured to generate and output the signal OF_LATCH according to the transition timing of the signal (e.g., signal S2) that indicates the value of the most significant bit of the count value from the counter 60. The holding circuit 96 can generate and output the signal OF_LATCH, which has a signal value that changes according to the falling edge of signal S2 and the signal Sampling, for example, as shown in the example in Figure 28.

[0123] As shown in the example in Figure 28, the arithmetic circuit 120 generates a signal OUTA having pulses corresponding to the signal value (e.g., high level) of the signal PIX_OUT at predetermined intervals (e.g., timing synchronized with the signal Sampling). Based on the signal OUTA, the arithmetic circuit 120 can generate a signal OUT corresponding to the light reception frequency of the avalanche diode 20. In this modified example, the same effects as in the above-described embodiment can be obtained.

[0124] <3. Examples of Use> The above-described light detection device 1 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in televisions and home appliances such as refrigerators and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of the skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0125] <4. Application Examples> (Application Examples to Mobile Devices) The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0126] Figure 29 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0127] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 29, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0128] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0129] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0130] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0131] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0132] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0133] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0134] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0135] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0136] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 29, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0137] Figure 30 shows an example of the installation position of the imaging unit 12031.

[0138] In Figure 30, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0139] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by imaging units 12101 and 12105 are mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0140] Figure 30 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0141] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0142] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0143] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0144] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0145] The above describes an example of a mobile control system to which the technology described herein can be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the light detection device 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, the functionality can be enhanced, and high-precision control using captured images can be performed in the mobile control system.

[0146] Although the present disclosure has been described above with reference to embodiments, modifications, usage examples, and application examples, the present technology is not limited to the above embodiments, and various modifications are possible. For example, although the above-described modifications were described as modifications of the above embodiments, the configurations of each modification can be combined as appropriate.

[0147] One embodiment of the photodetector in this disclosure comprises a pixel array in which photoelectric conversion units that output pulses in response to the incidence of photons are arranged in an array, and a signal processing unit disposed within the pixel array that processes the output signals from the photoelectric conversion units. The signal processing unit performs signal processing including decimation. This makes it possible to realize a photodetector that is advantageous for signal readout.

[0148] The effects described herein are merely examples and are not limited to those described herein; other effects may also exist. Furthermore, this disclosure may also take the following configurations: (1) A photodetector comprising: a pixel array in which photoelectric conversion units that output pulses in response to the incidence of photons are arranged in an array; and a signal processing unit arranged in the pixel array and processing the output signals from the photoelectric conversion units, wherein the signal processing unit performs signal processing including decimation. (2) The photodetector according to (1), further comprising a column readout circuit connected to the output of the signal processing unit, wherein the signal processing unit generates a first signal by signal processing including decimation, and the column readout circuit reads the first signal outside the pixel array. (3) The photodetector according to (1) or (2), wherein the signal processing unit is arranged in an array for each of the photoelectric conversion units. (4) The photodetector according to any one of (1) to (3), wherein one signal processing unit is arranged for a plurality of photoelectric conversion units. (5) The photodetector according to any one of (1) to (4), wherein the signal processing unit has a decimation filter that performs decimation processing. (6) The photodetector according to any one of (1) to (5), wherein the period of the decimation processing of the signal processing unit is variable. (7) The photodetector according to any one of (1) to (6), wherein the signal processing unit has a counter that counts the number of pulses, and the signal processing unit outputs a part of the count signal as a first signal. (8) The photodetector according to any one of (1) to (6), wherein the signal processing unit has a counter that counts the number of pulses, and the signal processing unit detects an overflow of the counter and outputs it as a first signal. (9) The photodetector according to any one of (1) to (6), wherein the signal processing unit has a counter that counts the number of pulses, and the signal processing unit selectively detects an overflow of any bit of the counter by an external control signal and outputs it as a first signal. (10) The light detection device according to any one of (1) to (9), wherein the signal processing unit further outputs a count value as a second signal.(11) The photodetector according to any one of (1) to (10), wherein the signal processing unit has an integrating circuit that holds a voltage corresponding to the number of pulses and a comparison circuit that compares the output voltage of the integrating circuit with a reference voltage and outputs the comparison result, and the signal processing unit outputs the comparison result as a first signal. (12) The photodetector according to any one of (1) to (11), wherein the signal processing unit has a low-pass filter and a sampling circuit that holds a signal at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal. (13) The photodetector according to any one of (1) to (12), wherein the photoelectric conversion unit receives a detection timing control signal and a detection period control signal, the pulse generation timing is controlled in synchronization with the detection timing control signal, and the photoelectric conversion unit is reset by the detection period control signal. (14) The photodetector according to (13), wherein the signal processing unit comprises a FIR (Finite Impulse Response) filter and a sampling circuit that holds a signal at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal. (15) The photodetector according to (13), wherein the signal processing unit comprises a plurality of integrating circuits and a sampling circuit that holds a signal at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal. (16) The photodetector according to (13), wherein the signal processing unit comprises a counter that counts the number of pulses and a sampling circuit that holds the output of the counter at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal. (17) The photodetector according to any one of (1) to (16), wherein the signal processing unit comprises a counter for counting the number of pulses, an overflow detection circuit for detecting an overflow of the counter, and a sampling circuit for holding the output of the overflow detection circuit at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal.(18) The photodetector according to any one of (1) to (17), further comprising: a column readout circuit connected to the output of the signal processing unit; and an arithmetic circuit located outside the pixel array and connected to the column readout circuit, wherein the signal processing unit generates a first signal by signal processing including decimation; the column readout circuit reads the first signal outside the pixel array; and the arithmetic circuit generates a third signal. (19) The photodetector according to (18), wherein the arithmetic circuit comprises at least one of: a counter; a moving average circuit; an FIR (Finite Impulse Response) filter; and an IIR (Infinite Impulse Response) filter. (20) The photodetector according to (19), wherein the arithmetic circuit generates the third signal based on the interval of the signals output from the column readout circuit. (21) The photodetector according to any one of (1) to (20), wherein the photoelectric conversion unit comprises an avalanche diode, a current supply circuit that supplies current to the avalanche diode, and a detection circuit that detects the output voltage of the avalanche diode and outputs it as a pulse. (22) An electronic device comprising a pixel array in which photoelectric conversion units that output pulses in response to the incidence of photons are arranged in an array, and a signal processing unit arranged in the pixel array that processes the output signals from the photoelectric conversion units, wherein the signal processing unit performs signal processing including decimation.

[0149] This application claims priority based on Japanese Patent Application No. 2025-024764, filed with the Japan Patent Office on 19 February 2025, and all contents of that application are incorporated herein by reference.

[0150] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A photodetector comprising: a pixel array in which photoelectric conversion units that output pulses in response to the incidence of photons are arranged in an array; and a signal processing unit arranged within the pixel array and processing the output signals from the photoelectric conversion units, wherein the signal processing unit performs signal processing including decimation.

2. The photodetector according to claim 1, further comprising a column readout circuit connected to the output of the signal processing unit, wherein the signal processing unit generates a first signal by signal processing including decimation, and the column readout circuit reads the first signal outside the pixel array.

3. The photodetector according to claim 1, wherein the signal processing unit is arranged in an array for each of the photoelectric conversion units.

4. The photodetector according to claim 1, wherein one signal processing unit is arranged for each of the multiple photoelectric conversion units.

5. The photodetector according to claim 1, wherein the signal processing unit has a decimation filter that performs decimation processing.

6. The photodetector according to claim 1, wherein the period of the signal processing unit's decimation process is variable.

7. The photodetector according to claim 1, wherein the signal processing unit has a counter for counting the number of pulses, and the signal processing unit outputs a part of the count signal as a first signal.

8. The photodetector according to claim 1, wherein the signal processing unit has a counter for counting the number of pulses, and the signal processing unit detects an overflow of the counter and outputs it as a first signal.

9. The optical detection device according to claim 1, wherein the signal processing unit has a counter for counting the number of pulses, and the signal processing unit selectively detects an overflow of any bit of the counter by means of an external control signal and outputs it as a first signal.

10. The photodetector according to claim 7, wherein the signal processing unit further outputs a count value as a second signal.

11. The photodetector according to claim 1, wherein the signal processing unit includes an integrating circuit that holds a voltage corresponding to the number of pulses and a comparison circuit that compares the output voltage of the integrating circuit with a reference voltage and outputs the comparison result, and the signal processing unit outputs the comparison result as a first signal.

12. The photodetector according to claim 1, wherein the signal processing unit comprises a low-pass filter and a sampling circuit that holds a signal at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal.

13. The photodetector according to claim 1, wherein the photoelectric conversion unit receives a detection timing control signal and a detection period control signal, the pulse generation timing is controlled in synchronization with the detection timing control signal, and the photoelectric conversion unit is reset by the detection period control signal.

14. The photodetector according to claim 13, wherein the signal processing unit comprises a FIR (Finite Impulse Response) filter and a sampling circuit that holds a signal at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal.

15. The photodetector according to claim 13, wherein the signal processing unit comprises a plurality of integration circuits and a sampling circuit that holds a signal at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal.

16. The photodetector according to claim 13, wherein the signal processing unit comprises a counter for counting the number of pulses and a sampling circuit for holding the output of the counter at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal.

17. The photodetector according to claim 1, wherein the signal processing unit comprises a counter for counting the number of pulses, an overflow detection circuit for detecting an overflow of the counter, and a sampling circuit for holding the output of the overflow detection circuit at a timing determined by an external signal, and the signal processing unit outputs the sampled signal as a first signal.

18. The photodetector according to claim 1, further comprising: a column readout circuit connected to the output of the signal processing unit; and an arithmetic circuit disposed outside the pixel array and connected to the column readout circuit, wherein the signal processing unit generates a first signal by signal processing including decimation; the column readout circuit reads the first signal outside the pixel array; and the arithmetic circuit generates a third signal.

19. The photodetector according to claim 18, wherein the calculation circuit comprises at least one of a counter, a moving average circuit, an FIR (Finite Impulse Response) filter, and an IIR (Infinite Impulse Response) filter.

20. The optical detection device according to claim 19, wherein the calculation circuit generates the third signal based on the interval of the signals output from the column reading circuit.

21. The photodetector according to claim 1, wherein the photoelectric conversion unit comprises an avalanche diode, a current supply circuit that supplies current to the avalanche diode, and a detection circuit that detects the output voltage of the avalanche diode and outputs it as a pulse.

22. An electronic device comprising a pixel array in which photoelectric conversion units that output pulses in response to the incidence of photons are arranged in an array, and a signal processing unit arranged within the pixel array that processes the output signals from the photoelectric conversion units, wherein the signal processing unit performs signal processing including decimation.

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