Semiconductor device
Patent Information
- Application Number
- PCT/JP2026/005491
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-21
- Filing Date
- 2026-02-16
- Publication Date
- 2026-08-27
Smart Images
Figure JP2026005491_27082026_PF_FP_ABST
Abstract
Description
Semiconductor device
[0001] The present disclosure relates to a semiconductor device including a vertical MOS (Metal Oxide Semiconductor) transistor.
[0002] Conventionally, a semiconductor device including a vertical MOS transistor having a plurality of gate trenches protruding from a body region to a drain region is known (see, for example, Patent Document 1).
[0003] Japanese Patent No. 3999225
[0004] In the semiconductor device including the vertical MOS transistor, it is desired to be able to relatively easily control the breakdown voltage of the vertical MOS transistor.
[0005] Therefore, an object of the present disclosure is to provide a semiconductor device including a vertical MOS transistor capable of relatively easily controlling the breakdown voltage.
[0006] A semiconductor device according to one aspect of this disclosure is a vertical MOS (Metal Oxide) A semiconductor device comprising a semiconductor transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; a low-concentration impurity layer of the first conductivity type containing an impurity of a second concentration lower than the first concentration, formed in contact with the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, containing an impurity of a third concentration, formed in the low-concentration impurity layer including the upper surface of the low-concentration impurity layer; a plurality of gate trenches extending in a first direction parallel to the upper surface of the semiconductor substrate and in a second direction perpendicular to the first direction, formed at equal intervals in the second direction parallel to the upper surface of the semiconductor substrate, extending from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and to a part of the low-concentration impurity layer; a plurality of gate conductors formed inside each of the plurality of gate trenches; and a plurality of source regions and a plurality of body contact regions alternately formed in the first direction at a predetermined period in each of a plurality of specific mesa portions, which are at least a part of a plurality of mesa portions sandwiched between the plurality of gate trenches in the second direction. The semiconductor device comprises a plurality of source regions of a first conductivity type formed in the specific mesa portion including the upper surface of the specific mesa portion, and a plurality of body contact regions of a second conductivity type formed in the specific mesa portion including the upper surface of the specific mesa portion, containing an impurity of a fourth concentration higher than the third concentration, wherein the plurality of specific mesa portions is a mesa portion comprising the plurality of source regions and the plurality of body contact regions formed alternately in the first direction at a predetermined period, the body region is a central region whose depth from the upper surface of the low-concentration impurity layer is constant at a first depth, and consists of a central region that does not include the outer periphery of the body region in a plan view of the semiconductor device, and a peripheral region which is a region other than the central region, the peripheral region having a shallow bottom region whose depth from the upper surface of the low-concentration impurity layer is shallower than the first depth, and each of the plurality of central region mesa portions, at least a part of which is included in the central region, is one of the plurality of specific mesa portions, and the plurality of gate trenches are from the upper surface of the low-concentration impurity layer,It includes a plurality of central region gate trenches formed to a depth extending through at least a portion of the central region to a depth up to a portion of the low-concentration impurity layer, and a plurality of shallow-bottom region gate trenches formed from the upper surface of the low-concentration impurity layer to a depth extending through the shallow-bottom region to a depth up to a portion of the low-concentration impurity layer, the plurality of shallow-bottom region gate trenches that do not include portions that penetrate the central region.
[0007] According to one aspect of the present disclosure, a semiconductor device is provided that includes a vertical MOS transistor capable of controlling the breakdown voltage relatively easily.
[0008] Figure 1 is a schematic plan view showing an example of the structure of a semiconductor device according to the embodiment. Figure 2 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to the embodiment. Figure 3 is a circuit diagram of the semiconductor device according to the embodiment. Figure 4 is a schematic plan view showing an example of the structure of a semiconductor device according to the embodiment. Figure 5 is a schematic enlarged cross-sectional perspective view showing an example of the structure around the first gate trench according to the embodiment in the first central region according to the embodiment. Figure 6 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment in the first central region according to the embodiment. Figure 7 is a schematic enlarged plan view showing an example of the structure around the first gate trench according to the embodiment in the first central region according to the embodiment. Figure 8 is a schematic enlarged cross-sectional view showing an example of the structure near the outer periphery of the first body region according to the embodiment. Figure 9 is a schematic enlarged cross-sectional view showing an example of the structure near the outer periphery of the first body region according to the embodiment. Figure 10 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment in a state where the protective oxide film formation process according to the embodiment has been carried out. Figure 11 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the trench formation process according to the embodiment has been carried out. Figure 12 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the gate insulating film formation process according to the embodiment has been carried out. Figure 13 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the polysilicon formation process according to the embodiment has been carried out. Figure 14 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the polysilicon dry etch process according to the embodiment has been carried out. Figure 15 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the planar oxide film formation process according to the embodiment has been carried out. Figure 16 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the first planar oxide film etch-back process according to the embodiment has been carried out.Figure 17 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the second planarization oxide film etch-back process according to the embodiment has been carried out. Figure 18 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the body region formation process according to the embodiment has been carried out. Figure 19 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the source region formation process according to the embodiment has been carried out. Figure 20 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the oxide film formation process according to the embodiment has been carried out. Figure 21 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the contact opening process according to the embodiment has been carried out. Figure 22 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench according to the embodiment when the electrode and protective film formation process according to the embodiment has been carried out.
[0009] (Background to obtaining one aspect of this disclosure) In general, in a vertical MOS transistor having multiple gate trenches that protrude from the body region to the drain region, it is known that the part with the highest electric field strength is the tip of the multiple gate trenches.
[0010] This is because the electric field strength within the depletion layer at the PN junction between the body region and the drain region increases as you move away from the PN junction towards the drain region.
[0011] Therefore, in the vertical MOS transistor with the above structure, the first place where breakdown occurs is the tip of one of the gate trenches.
[0012] However, in conventional vertical MOS transistors, where the amount of protrusion from the body region to the drain region of multiple gate trenches is constant, it is difficult to determine which of the multiple gate trenches will cause breakdown to occur first until the vertical MOS transistor is actually manufactured.
[0013] This is because, in the conventional vertical MOS transistor described above, manufacturing variations occur in the quality of individual gate trenches during the manufacturing process for producing multiple gate trenches. For example, the depth of the gate trenches may vary slightly, or the thickness of the gate insulating film may be thinner. Therefore, it is impossible to know which gate trench tip will be the first to break down until the vertical MOS transistor is actually manufactured.
[0014] In response, the inventors, through experiments and studies, found that by intentionally including a gate trench among several gate trenches in which the amount of protrusion from the body region to the drain region is significantly larger than that of other gate trenches, exceeding the range of manufacturing variations, the location where the first breakdown occurs can be limited to the tip of that gate trench.
[0015] The inventors also found that if the location where the initial breakdown occurs can be limited during the design phase, the breakdown voltage can be controlled relatively easily.
[0016] Based on these findings, the inventors conducted further experiments and studies, leading them to conceive of the semiconductor device described in this disclosure.
[0017] A semiconductor device according to one aspect of this disclosure is a vertical MOS (Metal Oxide) A semiconductor device comprising a semiconductor transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; a low-concentration impurity layer of the first conductivity type containing an impurity of a second concentration lower than the first concentration, formed in contact with the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type, containing an impurity of a third concentration, formed in the low-concentration impurity layer including the upper surface of the low-concentration impurity layer; a plurality of gate trenches extending in a first direction parallel to the upper surface of the semiconductor substrate and in a second direction perpendicular to the first direction, formed at equal intervals in the second direction parallel to the upper surface of the semiconductor substrate, extending from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and to a part of the low-concentration impurity layer; a plurality of gate conductors formed inside each of the plurality of gate trenches; and a plurality of source regions and a plurality of body contact regions alternately formed in the first direction at a predetermined period in each of a plurality of specific mesa portions, which are at least a part of a plurality of mesa portions sandwiched between the plurality of gate trenches in the second direction. The semiconductor device comprises a plurality of source regions of a first conductivity type formed in the specific mesa portion including the upper surface of the specific mesa portion, and a plurality of body contact regions of a second conductivity type formed in the specific mesa portion including the upper surface of the specific mesa portion, containing an impurity of a fourth concentration higher than the third concentration, wherein the plurality of specific mesa portions is a mesa portion comprising the plurality of source regions and the plurality of body contact regions formed alternately in the first direction at a predetermined period, the body region is a central region whose depth from the upper surface of the low-concentration impurity layer is constant at a first depth, and consists of a central region that does not include the outer periphery of the body region in a plan view of the semiconductor device, and a peripheral region which is a region other than the central region, the peripheral region having a shallow bottom region whose depth from the upper surface of the low-concentration impurity layer is shallower than the first depth, and each of the plurality of central region mesa portions, at least a part of which is included in the central region, is one of the plurality of specific mesa portions, and the plurality of gate trenches are from the upper surface of the low-concentration impurity layer,It includes a plurality of central region gate trenches formed to a depth extending through at least a portion of the central region to a depth up to a portion of the low-concentration impurity layer, and a plurality of shallow-bottom region gate trenches formed from the upper surface of the low-concentration impurity layer to a depth extending through the shallow-bottom region to a depth up to a portion of the low-concentration impurity layer, the plurality of shallow-bottom region gate trenches that do not include portions that penetrate the central region.
[0018] According to the semiconductor device with the above configuration, multiple shallow-bottom gate trenches can be included within the multiple central-region gate trenches, where the amount of protrusion from the body region to the low-concentration impurity layer functioning as a drain region is significantly larger than that of the multiple central-region gate trenches, exceeding the range of manufacturing variations.
[0019] Therefore, with the semiconductor device configured as described above, the area where the first breakdown occurs can be limited to one of the leading edges of multiple shallow-bottom gate trenches during the design phase before manufacturing the semiconductor device.
[0020] Therefore, the semiconductor device with the above configuration provides a semiconductor device equipped with a vertical MOS transistor that can control the breakdown voltage relatively easily.
[0021] Furthermore, among the maximum depths from the upper surface of the low-concentration impurity layer in the body region at the position through which each of the plurality of shallow-bottom gate trenches penetrates, the maximum depth from the upper surface of the low-concentration impurity layer in the body region at the position through which the furthest shallow-bottom gate trench penetrates, which is the furthest shallow-bottom gate trench with the greatest distance from the central region in the second direction, may be the smallest.
[0022] As a result, among the multiple shallow-bottom gate trenches, the amount of protrusion from the body region to the low-concentration impurity layer that functions as a drain region is greatest in the furthest shallow-bottom gate trench.
[0023] Therefore, with the semiconductor device configured as described above, the location where the first breakdown occurs can be the tip of the furthest shallow-bottom gate trench, which is relatively far from the central region.
[0024] Furthermore, the shallow bottom region contains a monotonically decreasing region in which the depth from the top surface of the low-concentration impurity layer decreases monotonically depending on the distance from the central region in the second direction, and among the plurality of source regions, a plurality of monotonically decreasing source regions formed in a plan view at a position contained within the monotonically decreasing region have a monotonically decreasing depth from the top surface of the low-concentration impurity layer in which they decrease monotonically depending on the distance from the central region in the second direction, and the gradient of the depth from the top surface of the low-concentration impurity layer in the monotonically decreasing region in the second direction and the plurality of monotonically decreasing The gradient of the depth of the source region from the upper surface of the low-concentration impurity layer in the second direction is equal to the plurality of shallow-bottom region gate trenches, which are a plurality of first monotonically decreasing region gate trenches sandwiched in the second direction between any one of the plurality of specific mesa portions and any other specific mesa portion, and which include a plurality of first monotonically decreasing region gate trenches formed to a depth from the upper surface of the low-concentration impurity layer, penetrating at least a portion of the monotonically decreasing region to a portion of the low-concentration impurity layer.
[0025] This makes it possible to make the channel length of channels formed adjacent to multiple first monotonically decreasing region gate trenches equal to the channel length of channels formed adjacent to multiple central region gate trenches.
[0026] Therefore, the threshold voltage of the vertical MOS transistor can be stabilized.
[0027] Furthermore, the plurality of shallow-bottom gate trenches further include a plurality of second monotonically decreasing region gate trenches that are not sandwiched between any one of the plurality of specific mesa portions and any other specific mesa portion in the second direction, and which are formed to a depth from the upper surface of the low-concentration impurity layer, penetrating at least a part of the monotonically decreasing region, to a part of the low-concentration impurity layer, and the distance of the plurality of second monotonically decreasing region gate trenches from the central region in the second direction may be greater than any of the distances of the plurality of first monotonically decreasing region gate trenches from the central region in the second direction.
[0028] As a result, the amount of protrusion from the body region of the multiple second monotonically decreasing region gate trenches to the low-concentration impurity layer that functions as a drain region is greater than the amount of protrusion from the body region of the multiple first monotonically decreasing region gate trenches to the low-concentration impurity layer that functions as a drain region.
[0029] Therefore, with the semiconductor device configured above, the location where the initial breakdown occurs can be limited to one of the leading edges of a plurality of second monotonically decreasing region gate trenches, relatively far from the central region.
[0030] Furthermore, the vertical MOS transistor may be further equipped with a gate electrode, wherein each of the plurality of first monotonically decreasing region gate conductors formed inside the plurality of first monotonically decreasing region gate trenches is electrically connected to the gate electrode, and at least one of the plurality of second monotonically decreasing region gate conductors formed inside the plurality of second monotonically decreasing region gate trenches is not electrically connected to the gate electrode.
[0031] This makes it possible to suppress the adverse effects of a breakdown occurring at one of the leading edges of multiple second monotonically decreasing region gate trenches, which can cause physical damage to the gate insulating film surrounding the monotonically decreasing region gate conductor formed inside the second monotonically decreasing region gate trench where the breakdown occurred, resulting in a short circuit at the damaged location and causing all gate conductors in the semiconductor device to cease functioning.
[0032] Furthermore, the vertical MOS transistor comprises a gate electrode and gate wiring that, in a plan view, surrounds the entire body region and is electrically connected to the gate electrode and the plurality of gate conductors, and is formed above the upper surface of the low-concentration impurity layer, wherein the length of the shallow bottom region in the second direction may be longer than the shortest distance between the furthest shallow bottom region gate trench and the gate wiring in the second direction.
[0033] This allows for a relatively large area of the active region of the vertical MOS transistor in a planar view of the semiconductor device.
[0034] Furthermore, the minimum protrusion length of the furthest shallow-bottom gate trench from the shallow-bottom region may be 100 nm or more longer than the maximum protrusion length of the plurality of central-region gate trenches from the central region.
[0035] Hereinafter, a specific example of a semiconductor device according to one aspect of this disclosure will be described with reference to the drawings. The embodiments shown here are all examples of this disclosure. Therefore, the numerical values, shapes, components, arrangement and connection configurations of components, as well as the steps (processes) and the order of steps shown in the following embodiments are examples and are not intended to limit this disclosure. Furthermore, each figure is a schematic diagram and is not necessarily a strict illustration. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified.
[0036] (Embodiment) The following describes a semiconductor device equipped with a vertical MOS transistor according to an embodiment.
[0037] Here, we will explain using the example of a semiconductor device according to the embodiment that has two vertical MOS transistors. However, the number of vertical MOS transistors in the semiconductor device according to the embodiment is not necessarily limited to two; it may be one, or it may be three or more.
[0038] Furthermore, in this description, the semiconductor device according to the embodiment is described as a face-down mountable chip-size package (CSP) type semiconductor device. However, the semiconductor device according to the embodiment is not necessarily limited to a face-down mountable semiconductor device, nor is it necessarily limited to a chip-size package type semiconductor device.
[0039] [1. Structure of Semiconductor Device] Figure 1 is a schematic plan view showing an example of the structure of a semiconductor device 1 according to Embodiment 1.
[0040] In Figure 1, the first source electrode 11 (described later), the second source electrode 21 (described later), the first gate electrode 19 (described later), and the second gate electrode 29 (described later) are shown with dashed lines as if they were directly visible from outside the semiconductor device 1. However, in reality, these cannot be directly visible from outside the semiconductor device 1.
[0041] Figure 2 is a schematic cross-sectional view showing an example of the structure of the semiconductor device 1. Figure 2 shows the cross-section along line I-I in Figure 1.
[0042] Figure 3 is a circuit diagram of semiconductor device 1.
[0043] As shown in Figures 1 to 3, the semiconductor device 1 comprises a semiconductor layer 40, a metal layer 30, an oxide film 34, a protective film 35, a first source electrode 11, a second source electrode 21, a first gate electrode 19, a second gate electrode 29, a first vertical MOS transistor 10 formed in a first region A1 of the semiconductor layer 40, and a second vertical MOS transistor 20 formed in a second region A2 of the semiconductor layer 40 adjacent to the first region A1 in a plan view of the semiconductor device 1.
[0044] Here, the first region A1 and the second region A2 are the one and the other that bisect the semiconductor layer 40 by area in a plan view of the semiconductor device 1.
[0045] Further, the semiconductor device 1 includes one or more first source pads 111 (the first source pads 111a to the first source pads 111d in FIGS. 1 and 2 correspond; hereinafter, when it is not necessary to explicitly distinguish each individual from each other, the first source pads 111a to the first source pads 111d are also simply referred to as "the first source pads 111"), which are source pads of the first vertical MOS transistor 10, and a first gate pad 119, which is a gate pad of the first vertical MOS transistor 10, at a position included in the first region A1 in a plan view of the semiconductor device 1, and one or more second source pads 121 (the second source pads 121a to the second source pads 121d in FIGS. 1 and 2 correspond; hereinafter, when it is not necessary to explicitly distinguish each individual from each other, the second source pads 121a to the second source pads 121d are also simply referred to as "the second source pads 121"), which are source pads of the second vertical MOS transistor 20, and a second gate pad 129, which is a gate pad of the second vertical MOS transistor 20, at a position included in the second region A2 in a plan view of the semiconductor device 1.
[0046] The semiconductor layer 40 is formed by laminating a semiconductor substrate 32 and a low-concentration impurity layer 33.
[0047] The semiconductor substrate 32 is made of silicon of the first conductivity type containing impurities of the first concentration.
[0048] The low-concentration impurity layer 33 is formed on the semiconductor substrate 32 in contact with the semiconductor substrate 32 and is made of silicon of the first conductivity type containing impurities of a second concentration lower than the first concentration.
[0049] The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.
[0050] Generally, semiconductors have two types of conductivity: P-type and N-type. The first conductivity type may be either P-type or N-type. For the sake of explanation, we will assume that the first conductivity type is N-type and the second conductivity type (described later) is P-type. However, it is also acceptable for the first conductivity type to be P-type and the second conductivity type to be N-type.
[0051] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40, and may be a multilayer structure including, for example, a layer mainly composed of silver or copper.
[0052] The oxide film 34 is formed on the low-concentration impurity layer 33, in contact with the low-concentration impurity layer 33.
[0053] The protective film 35 is a protective film that covers the oxide film 34, the first source electrode 11, the second source electrode 21, the first gate electrode 19, and the upper surface of the second gate electrode 29.
[0054] The protective film 35 includes one or more (in this case, four) openings that expose one or more (in this case, four) portions of the upper surface of the first source electrode 11 to the outside of the protective film 35, one or more (in this case, four) openings that expose one or more (in this case, four) portions of the upper surface of the second source electrode 21 to the outside of the protective film 35, an opening that exposes a portion of the upper surface of the first gate electrode 19 to the outside of the protective film 35, and an opening that exposes a portion of the upper surface of the second gate electrode 29 to the outside of the protective film 35.
[0055] The first source electrode 11 is the source electrode of the first vertical MOS transistor 10, formed in a position enclosed within the first region A1 in a plan view of the semiconductor device 1, and is made of metal.
[0056] The upper surface of the first source electrode 11 is exposed to the outside of the protective film 35 through one or more (four in this case) openings in the protective film 35. Each of the upper surfaces of the first source electrode 11 that is exposed to the outside of the protective film 35 through one or more (four in this case) openings in the protective film 35 forms one or more (four in this case) first source pads 111.
[0057] In other words, the first source pad 111 is the portion of the upper surface of the first source electrode 11 that is exposed to the outside of the protective film 35 at the opening of the protective film 35.
[0058] The second source electrode 21 is a source electrode of a second vertical MOS transistor 20, formed in a position enclosed within the second region A2 in a plan view of the semiconductor device 1, and is made of metal.
[0059] The upper surface of the second source electrode 21 is exposed to the outside of the protective film 35 through one or more (four in this case) openings in the protective film 35. Each of the upper surfaces of the second source electrode 21 that is exposed to the outside of the protective film 35 through one or more (four in this case) openings in the protective film 35 forms one or more (four in this case) second source pads 121.
[0060] In other words, the second source pad 121 is the portion of the upper surface of the second source electrode 21 that is exposed to the outside of the protective film 35 at the opening of the protective film 35.
[0061] The first gate electrode 19 is the gate electrode of the first vertical MOS transistor 10, formed in a position enclosed within the first region A1 in a plan view of the semiconductor device 1, and is made of metal.
[0062] The upper surface of the first gate electrode 19 is exposed to the outside of the protective film 35 at the opening of the protective film 35. The upper surface of the first gate electrode 19 that is exposed to the outside of the protective film 35 at the opening of the protective film 35 is the first gate pad 119.
[0063] In other words, the first gate pad 119 is the portion of the upper surface of the first gate electrode 19 that is exposed to the outside of the protective film 35 at the opening of the protective film 35.
[0064] The second gate electrode 29 is the gate electrode of the second vertical MOS transistor 20, formed in a position enclosed within the second region A2 in a plan view of the semiconductor device 1, and is made of metal.
[0065] The upper surface of the second gate electrode 29 is exposed to the outside of the protective film 35 at the opening in the protective film 35. The upper surface of the second gate electrode 29 that is exposed to the outside of the protective film 35 at the opening in the protective film 35 forms the second gate pad 129.
[0066] In other words, the second gate pad 129 is the portion of the upper surface of the second gate electrode 29 that is exposed to the outside of the protective film 35 at the opening of the protective film 35.
[0067] Furthermore, in the first source pad 111, the second source pad 121, the first gate pad 119, and the second gate pad 129, metal rewiring may be formed in the corresponding openings of the protective film 35.
[0068] In the first region A1 of the low-concentration impurity layer 33, a first body region 18 of a second conductivity type different from the first conductivity type, containing impurities of a third concentration, is formed in the low-concentration impurity layer 33, including the upper surface of the low-concentration impurity layer 33.
[0069] Furthermore, in the first region A1 of the low-concentration impurity layer 33, a plurality of first gate trenches 17 are formed in the low-concentration impurity layer 33, extending in a first direction parallel to the upper surface of the semiconductor substrate 32 (the Y-axis direction in Figures 1 and 2), and at equal intervals in a second direction perpendicular to the first direction (the X-axis direction in Figures 1 and 2), extending from the upper surface of the low-concentration impurity layer 33, through the first body region 18, and to a depth of a part of the low-concentration impurity layer 33.
[0070] Then, a first gate conductor 15 is formed inside each of the multiple first gate trenches 17, surrounded by a first gate insulating film 16.
[0071] In other words, the semiconductor device 1 further comprises a first body region 18, a plurality of first gate trenches 17, a plurality of first gate conductors 15, and a plurality of first gate insulating films 16 in the first region A1.
[0072] Furthermore, in the second region A2 of the low-concentration impurity layer 33, a plurality of second gate trenches 27 are formed in the low-concentration impurity layer 33, extending in a first direction and spaced equally in a second direction, from the upper surface of the low-concentration impurity layer 33, through the second body region 28, to a depth of a part of the low-concentration impurity layer 33.
[0073] Furthermore, a second gate conductor 25 is formed inside each of the multiple second gate trenches 27, surrounded by a second gate insulating film 26.
[0074] In other words, the semiconductor device 1 further comprises a second body region 28, a plurality of second gate trenches 27, a plurality of second gate conductors 25, and a plurality of second gate insulating films 26 in the second region A2.
[0075] Figure 4 is a schematic plan view showing an example of the structure of the semiconductor device 1.
[0076] In Figure 4, the protective film 35, oxide film 34, first source electrode 11, first gate electrode 19, second source electrode 21, and second gate electrode 29 are depicted as if they were transparent. However, in reality, they are not transparent, and structures beyond them cannot be directly seen by passing through them.
[0077] As shown in Figure 4, the semiconductor device 1 further includes a first gate wiring 41 that surrounds the entire first body region 18 at a position contained within the first region A1 in a plan view of the semiconductor device 1, and is formed above the upper surface of the low-concentration impurity layer 33, and a second gate wiring 42 that surrounds the entire second body region 28 at a position contained within the second region A2 in a plan view of the semiconductor device 1, and is formed above the upper surface of the low-concentration impurity layer 33.
[0078] The first gate wiring 41 is made of polysilicon and is electrically connected to the first gate electrode 19 and the plurality of first gate conductors 15. As a result, the plurality of first gate conductors 15 are electrically connected to the first gate electrode 19.
[0079] The second gate wiring 42 is made of polysilicon and is electrically connected to the second gate electrode 29 and the plurality of second gate conductors 25. As a result, the plurality of second gate conductors 25 are electrically connected to the second gate electrode 29.
[0080] Furthermore, as shown in Figure 4, the first body region 18 is a first central region 51 whose depth from the upper surface of the low-concentration impurity layer 33 is constant at a first depth, and consists of a first central region 51 that does not include the outer periphery of the first body region 18 in a plan view of the semiconductor device 1, and a first peripheral region 52 which is the region other than the first central region 51. The second body region 28 is a second central region 61 whose depth from the upper surface of the low-concentration impurity layer 33 is constant at a first depth, and consists of a second central region 61 that does not include the outer periphery of the second body region 28 in a plan view of the semiconductor device 1, and a second peripheral region 62 which is the region other than the second central region 61.
[0081] As shown in Figure 4, the first peripheral region 52 is a region that includes the outer periphery of the first body region 18 and surrounds the entire first central region 51 in a plan view of the semiconductor device 1. The second peripheral region 62 is a region that includes the outer periphery of the second body region 28 and surrounds the entire second central region 61 in a plan view of the semiconductor device 1.
[0082] In this embodiment, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are identical. Therefore, in the following description, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 will be treated as identical, and the first vertical MOS transistor 10 will be used as the basis for the explanation.
[0083] Figure 5 is a schematic enlarged cross-sectional perspective view showing an example of the structure around the first gate trench 17 in the first central region 51 of the semiconductor device 1.
[0084] In Figure 5, the first source electrode 11 is depicted as if it were transparent, but in reality, the first source electrode 11 is not transparent, and structures on the other side of the first source electrode 11 cannot be directly seen by passing through the first source electrode 11.
[0085] Figure 6 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 in the first central region 51 of the semiconductor device 1. Figure 6 shows the cross-section along line II-II in Figure 5.
[0086] Figure 7 is a schematic enlarged plan view showing an example of the structure around the first gate trench 17 in the first central region 51 of the semiconductor device 1.
[0087] In Figure 7, the first source electrode 11 is omitted from the description, as if it were not present. However, in reality, the first source electrode 11 is located above the Z-axis direction in Figure 7.
[0088] Here, if we refer to each of the multiple regions sandwiched between the multiple first gate trenches 17 in the second direction (the X-axis direction in Figures 5 to 7) in the low-concentration impurity layer 33 of the first region A1 as the first mesa portion 70, then as shown in Figures 5 to 7, in the low-concentration impurity layer 33 of the first central region 51, in each of the multiple specific mesa portions 70A, which are at least a part of the multiple first mesa portions 70, there are multiple first source regions 14 and multiple first body contact regions 13 that are alternately formed in the first direction (the Y-axis direction in Figures 5 to 7) at a predetermined period, and there are multiple first source regions 14 of a first conductivity type formed in the specific mesa portion 70A including the upper surface of the specific mesa portion 70A, and multiple first body contact regions 13 of a second conductivity type that are formed in the specific mesa portion 70A including the upper surface of the specific mesa portion 70A and contain an impurity of a fourth concentration higher than the third concentration.
[0089] Here, the specific mesa portion 70A refers to the first mesa portion 70 that comprises a plurality of first source regions 14 and a plurality of first body contact regions 13 that are alternately formed in a predetermined period in a first direction.
[0090] Thus, the semiconductor device 1 further comprises a plurality of first source regions 14 and a plurality of first body contact regions 13.
[0091] It is also possible to consider the first body contact region 13 as a part of the first body region 18. For this reason, in this embodiment, the first body contact region 13 may be illustrated as if it were a part of the first body region 18.
[0092] Here, as shown in Figures 5 and 6, all of the upper surfaces and parts of the sides of the multiple first source regions 14 are in contact with the first source electrode 11, and all of the upper surfaces and parts of the sides of the multiple first body contact regions 13 are in contact with the first source electrode 11.
[0093] In this manner, the first source electrode 11 is in contact with a plurality of first source regions 14 and a plurality of first body contact regions 13.
[0094] Figures 8 and 9 are schematic enlarged cross-sectional views showing an example of the structure near the outer periphery of the first body region 18 of the semiconductor device 1. Figure 8 shows the cross-section at III-III in Figure 4, and Figure 9 shows the cross-section at IV-IV in Figure 4.
[0095] The cross-section at IV-IV in Figure 4 is the cross-section at the position where the first gate conductor 15 is cut. Therefore, the first body region 18 does not actually appear in the cross-section at IV-IV in Figure 4. However, in order to deepen the understanding of the structure of the semiconductor device 1 near the outer periphery of the first body region 18, Figure 9 shows the shape of the first body region 18 in the cross-section parallel to the cross-section at IV-IV in Figure 4, where the first mesa portion 70 is cut, with a dashed line.
[0096] As shown in Figure 8, a first peripheral region 52 is formed near the outer periphery of the first body region 18, which includes the outer periphery of the first body region 18, and in a plan view of the semiconductor device 1, the first peripheral region 52 surrounds the entire first central region 51.
[0097] Furthermore, as shown in Figure 8, the first peripheral region 52 has a shallow bottom region 53 that is shallower than the first depth from the upper surface of the low-concentration impurity layer 33.
[0098] Figure 8 shows an example of a configuration in which the entire first peripheral region 52 is a shallow-bottom region 53. However, as long as a shallow-bottom region 53 exists in the first peripheral region 52, it is not necessarily limited to a configuration in which the entire first peripheral region 52 is a shallow-bottom region 53.
[0099] For example, in the first peripheral region 52, there may be a region that is deeper than the first depth from the upper surface of the low-concentration impurity layer 33, on the outer periphery side of the shallow bottom region 53 in a plan view of the semiconductor device 1.
[0100] Furthermore, as shown in Figure 8, each of the multiple central region mesa portions 70B, in which at least a portion of the multiple first mesa portions 70 is included in the first central region 51, is one of the multiple specific mesa portions 70A.
[0101] Furthermore, as shown in Figure 8, the plurality of first gate trenches 17 include a plurality of central region gate trenches 17A formed to a depth from the upper surface of the low-concentration impurity layer 33, penetrating at least a portion of the first central region 51, to a portion of the low-concentration impurity layer 33, and a plurality of shallow-bottom region gate trenches 17B formed to a depth from the upper surface of the low-concentration impurity layer 33, penetrating the shallow-bottom region 53, to a portion of the low-concentration impurity layer 33, and not including portions penetrating the first central region 51.
[0102] According to the semiconductor device 1 with the above configuration, the plurality of shallow-bottom gate trenches 17B can be included in the plurality of first gate trenches 17, where the amount of protrusion from the first body region 18 to the low-concentration impurity layer 33, which functions as a drain region, is significantly larger than that of the plurality of central region gate trenches 17A, exceeding the range of manufacturing variations.
[0103] Therefore, within the scope of the above configuration, at the design stage before manufacturing the semiconductor device 1, the portion where the first breakdown occurs in the first vertical MOS transistor 10 can be limited to one of the tip portions of the multiple shallow-bottom gate trenches 17B.
[0104] Therefore, the semiconductor device 1 with the above configuration provides a semiconductor device 1 equipped with a first vertical MOS transistor 10 that can control the breakdown voltage relatively easily.
[0105] Furthermore, as shown in Figure 8, among the maximum depths from the upper surface of the low-concentration impurity layer 33 in the first body region 18 at the position through which each of the multiple shallow-bottom gate trenches 17B penetrates, the maximum depth from the upper surface of the low-concentration impurity layer 33 in the furthest shallow-bottom gate trench 17C, which has the greatest distance from the first central region 51 in the second direction (X-axis direction in Figure 8), may be the smallest.
[0106] As a result, among the multiple shallow-bottom gate trenches 17B, the amount of protrusion from the first body region 18 to the low-concentration impurity layer 33, which functions as a drain region, is largest for the furthest shallow-bottom gate trench 17C.
[0107] Therefore, with the semiconductor device 1 configured as described above, the location where the first breakdown occurs in the first vertical MOS transistor 10 can be the tip of the furthest shallow gate trench 17C, which is relatively far from the first central region 51.
[0108] Furthermore, as shown in Figure 8, in the shallow bottom region 53, there is a monotonically decreasing region 55 in which the depth from the upper surface of the low-concentration impurity layer 33 decreases monotonically depending on the distance from the first central region 51 in the second direction. Among the plurality of first source regions 14, the plurality of monotonically decreasing source regions 14A formed in positions that are contained within the monotonically decreasing region 55 in a plan view of the semiconductor device 1 also decrease monotonically in depth from the upper surface of the low-concentration impurity layer 33 depending on the distance from the first central region 51 in the second direction. The gradient of the depth from the upper surface of the low-concentration impurity layer 33 in the monotonically decreasing region 55 in the second direction and the gradient of the depth from the upper surface of the low-concentration impurity layer 33 in the plurality of monotonically decreasing source regions 14A in the second direction may be considered equal.
[0109] In this specification, "monotonically decreasing" means a function that is monotonically decreasing in the broad sense. That is, a monotonically decreasing function in the broad sense is a function f(x) such that f(x1) ≥ f(x2) when x1 < x2.
[0110] In Figure 8, an example of a configuration in which the entire shallow bottom region 53 is a monotonically decreasing region 55 is shown. However, as long as a monotonically decreasing region 55 exists in the shallow bottom region 53, it is not necessarily limited to a configuration in which the entire shallow bottom region 53 is a monotonically decreasing region 55.
[0111] For example, in the shallow region 53, there may be a region on the outer periphery of the monotonically decreasing region 55 in a plan view of the semiconductor device 1 where the depth from the top surface of the low-concentration impurity layer 33 does not decrease monotonically.
[0112] Furthermore, as shown in Figure 8, the plurality of shallow-bottom gate trenches 17B may include a plurality of first monotonically decreasing region gate trenches 17BA sandwiched between one of the plurality of specific mesa portions 70A and one of the other specific mesa portions 70A in the second direction, and may include a plurality of first monotonically decreasing region gate trenches 17BA formed to a depth from the upper surface of the low-concentration impurity layer 33, penetrating at least a part of the monotonically decreasing region 55, to a part of the low-concentration impurity layer 33.
[0113] This makes it possible to make the channel length of the channels formed near the multiple first monotonically decreasing region gate trenches 17BA equal to the channel length of the channels formed near the multiple central region gate trenches 17A.
[0114] Therefore, the threshold voltage of the first vertical MOS transistor 10 can be stabilized.
[0115] Furthermore, as shown in Figure 8, the plurality of shallow-bottom gate trenches 17B may further include a plurality of second monotonically decreasing region gate trenches 17BB that are not sandwiched between any one of the plurality of specific mesa portions 70A and any other specific mesa portion 70A in the second direction, and which are formed to a depth from the upper surface of the low-concentration impurity layer 33, penetrating at least a part of the monotonically decreasing region 55, to a part of the low-concentration impurity layer 33.
[0116] In this case, as shown in Figure 8, the distance of the plurality of second monotonically decreasing region gate trenches 17BB from the first central region 51 in the second direction may be greater than any of the distances of the plurality of first monotonically decreasing region gate trenches 17BA from the first central region 51 in the second direction.
[0117] As a result, the amount of protrusion of the multiple second monotonically decreasing region gate trenches 17BB from the first body region 18 to the low-concentration impurity layer 33 which functions as a drain region is greater than the amount of protrusion of the multiple first monotonically decreasing region gate trenches 17BA from the first body region 18 to the low-concentration impurity layer 33 which functions as a drain region.
[0118] Therefore, with the semiconductor device 1 configured as described above, the location where the first breakdown occurs in the first vertical MOS transistor 10 can be limited to one of the leading edges of the multiple second monotonically decreasing region gate trenches 17BB, which are relatively far from the first central region 51.
[0119] Here, of the plurality of first gate conductors 15, each of the plurality of first monotonically decreasing region gate conductors 15A formed inside the plurality of first monotonically decreasing region gate trenches 17BA is electrically connected to the first gate electrode 19, and of the plurality of first gate conductors 15, at least one of the plurality of second monotonically decreasing region gate conductors 15B formed inside the plurality of second monotonically decreasing region gate trenches 17BB is not electrically connected to the first gate electrode 19.
[0120] This makes it possible to suppress the adverse effects of a breakdown occurring at one of the leading edges of the multiple second monotonically decreasing region gate trenches 17BB, which can cause physical damage to the first gate insulating film 16 surrounding the first monotonically decreasing region gate conductor 15A formed inside the second monotonically decreasing region gate trench 17BB where the breakdown occurred, resulting in a short circuit at the damaged location and causing all of the first monotonically decreasing region gate conductors 15A in the semiconductor device 1 to cease functioning.
[0121] Furthermore, as shown in Figure 8, the length W1 of the shallow bottom region 53 in the second direction may be longer than the shortest distance W2 between the furthest shallow bottom region gate trench 17C and the first gate wiring 41 in the second direction.
[0122] This makes it possible to relatively increase the area of the active region of the first vertical MOS transistor 10 in a plan view of the semiconductor device 1.
[0123] Furthermore, as shown in Figure 8, the minimum protrusion length L2 of the furthest shallow-bottom gate trench 17C from the shallow-bottom region 53 may be 100 nm or more longer than the maximum protrusion length L1 of the multiple central-region gate trenches 17A from the first central region 51.
[0124] [2. Method for Manufacturing a Semiconductor Device] The method for manufacturing the semiconductor device 1 with the above configuration will be described below with reference to the drawings.
[0125] In this embodiment, the method for manufacturing the first vertical MOS transistor 10 in the semiconductor device 1 and the method for manufacturing the second vertical MOS transistor 20 in the semiconductor device 1 are the same. Therefore, in the following description, the method for manufacturing the semiconductor device 1 will be explained using the first vertical MOS transistor 10 as a representative example of the first vertical MOS transistor 10 and the second vertical MOS transistor 20.
[0126] The semiconductor device 1 is manufactured by performing, for example, the following steps in this order: (1) protective oxide film formation step, (2) trench formation step, (3) gate insulating film formation step, (4) polysilicon formation step, (5) polysilicon dry etching step, (6) planarization oxide film formation step, (7) first planarization oxide film etching back step, (8) second planarization oxide film etching back step, (9) body region formation step, (10) source region formation step, (11) oxide film formation step, (12) contact opening step, and (13) electrode and protective film formation step.
[0127] Figure 10 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the protective oxide film formation process has been performed. Figure 10 shows a cross-sectional view similar to that of Figure 8. As will be described later, the first gate trench 17 will be formed in the trench formation process that follows this protective oxide film formation process, and therefore it has not yet been formed in this protective oxide film formation process. For this reason, the first gate trench 17 is not shown in Figure 10.
[0128] As shown in Figure 10, the protective oxide film formation step involves forming a low-concentration impurity layer 33 on the semiconductor substrate 32, and then forming a protective oxide film 101 on the low-concentration impurity layer 33, which will ultimately become part of the oxide film 34.
[0129] Figure 11 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the trench formation process has been carried out. Figure 11 shows a cross-sectional view similar to that of Figure 8.
[0130] As shown in Figure 11, the trench formation step is the step of forming a plurality of first gate trenches 17.
[0131] Figure 12 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the gate insulating film formation process has been performed. Figure 12 shows a cross-sectional view similar to that of Figure 8.
[0132] As shown in Figure 12, the gate insulating film formation step is a step of forming a protective oxide film 101 on the wall surface of each of the multiple first gate trenches 17, which will ultimately become the side and bottom portions of the first gate insulating film 16.
[0133] Figure 13 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the polysilicon formation process has been carried out. Figure 13 shows a cross-sectional view similar to that of Figure 8.
[0134] As shown in Figure 13, the polysilicon formation step is a step in which polysilicon 102, which will ultimately become a plurality of first gate conductors 15 and a first gate wiring 41, is formed inside the plurality of first gate trenches 17 and on the upper surface of the protective oxide film 101 formed in the protective oxide film formation step.
[0135] Figure 14 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the polysilicon dry etching process has been performed. Figure 14 shows a cross-sectional view similar to that of Figure 8.
[0136] As shown in Figure 14, the polysilicon dry etching process is a process in which dry etching is performed on the polysilicon 102 formed in the polysilicon formation process to form a plurality of first gate conductors 15 and first gate wiring 41.
[0137] Figure 15 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the planarization oxide film formation process has been performed. Figure 15 shows a cross-sectional view similar to that of Figure 8.
[0138] As shown in Figure 15, the planar oxide film formation step is a step of forming a planar oxide film 103, which will ultimately become a part of the oxide film 34 and a part of the first gate insulating film 16 (the upper surface portion of the first gate insulating film 16), on the entire upper surface of the plurality of first gate trenches 17, the protective oxide film 101, the plurality of first gate conductors 15, and the first gate wiring 41.
[0139] The planarization oxide film formation step involves forming, for example, BPSG (Boron Phosphorus Silicon Glass). However, the planarization oxide film formation step is not limited to BPSG; it may also involve forming TEOS and SOG (Spin On Glass), and the planarization oxide film formed may consist of multiple laminated films.
[0140] As shown in Figures 14 and 15, the upper surface of the first gate wiring 41 is higher than the upper surface of the protective oxide film 101 formed in the protective oxide film formation process. Therefore, as shown in Figure 15, a region is formed on the upper surface of the planarized oxide film 103 in which the height monotonically decreases from the upper part of the first gate wiring 41 toward the positive X-axis in Figure 15.
[0141] Figure 16 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the first planarization oxide film etch-back process has been performed. Figure 16 shows a cross-sectional view similar to that of Figure 8.
[0142] As shown in Figure 16, the first planar oxide film etch-back step is a step of half-etching the planar oxide film 103 formed in the planar oxide film formation step.
[0143] The first planarization oxide film etch-back process is performed, for example, by CMP (Chemical Mechanical Polishing). However, the first planarization oxide film etch-back process is not limited to CMP; it may also be performed by dry etching or wet etching.
[0144] As shown in Figure 16, on the upper surface of the planar oxide film 103 after the first planar oxide film etch-back process, a region is maintained in which the height monotonically decreases in the positive direction of the X-axis in Figure 16, starting from the portion above the first gate wiring 41 that was formed after the planar oxide film formation process.
[0145] Figure 17 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the second planarization oxide film etch-back process has been performed. Figure 17 shows a cross-sectional view similar to that of Figure 8.
[0146] As shown in Figure 17, the second planar oxide film etch-back process is a process of etching back a portion of the planar oxide film 103 that was half-etched in the first planar oxide film formation process and a portion of the protective oxide film 101 that was formed in the protective oxide film formation process until the upper surface of the first gate wiring 41 is exposed.
[0147] As shown in Figure 17, on the upper surfaces of the planar oxide film 103 and protective oxide film 101 after the second planar oxide film etch-back process, a portion of the region maintained after the first planar oxide film etch-back process, where the height monotonically decreases in the positive X-axis direction in Figure 15, is further maintained from the portion above the first gate wiring 41. That is, as shown in Figure 17, on the upper surfaces of the planar oxide film 103 and protective oxide film 101 after the second planar oxide film etch-back process, there is a region where the height monotonically decreases in the positive X-axis direction in Figure 17, from the side of the first gate wiring 41.
[0148] Thus, the second planar oxide etch-back process is a process of etching back the planar oxide 103 and the protective oxide 101 onto the upper surfaces of the planar oxide 103 and the protective oxide 101, so as to maintain a portion of the region that was maintained after the first planar oxide etch-back process, where the height monotonically decreases in the positive direction of the X-axis in Figure 15, starting from the portion above the first gate wiring 41.
[0149] Figure 18 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the body region formation process has been performed. Figure 18 shows a cross-sectional view similar to that of Figure 8.
[0150] As shown in Figure 18, the body region formation step is a step in which a second conductivity type impurity is injected from the upper surface of the semiconductor device 1 after the second planarization oxide film etch-back step to form the first body region 18.
[0151] Here, the impurity of the second conductivity type is, for example, boron, when the second conductivity type is P-type.
[0152] As described above, on the upper surfaces of the planar oxide film 103 and protective oxide film 101 after the second planar oxide film etch-back process, there is a region where the height monotonically decreases from above the side surface of the first gate wiring 41 toward the positive X-axis in Figure 17. For this reason, as shown in Figure 18, a monotonically decreasing region 55 is formed in the first body region 18, in which the depth from the upper surface of the low-concentration impurity layer 33 monotonically decreases depending on the distance from the first central region 51 in the second direction.
[0153] Figure 19 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 in the state after the source region formation process has been performed. Figure 19 shows a cross-sectional view similar to that of Figure 8.
[0154] As shown in Figure 19, the source region formation step is a step in which a first conductivity type impurity is injected from the upper surface of the semiconductor device 1 after the body region formation step to form a plurality of first source regions 14.
[0155] Here, the impurity of the first conductivity type is, for example, phosphorus, when the first conductivity type is N-type.
[0156] As described above, on the upper surfaces of the planar oxide film 103 and protective oxide film 101 after the second planar oxide film etch-back process, there is a region where the height is monotonically decreasing from above the side surface of the first gate wiring 41 toward the second direction (the positive direction of the X-axis in Figure 17). For this reason, the multiple first source regions 14 include multiple monotonically decreasing source regions 14A, as shown in Figure 19, whose depth from the upper surface of the low-concentration impurity layer 33 is monotonically decreasing depending on the distance from the first central region 51 in the second direction.
[0157] Figure 20 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the oxide film formation process has been carried out. Figure 20 shows a cross-sectional view similar to that of Figure 8.
[0158] As shown in Figure 20, the oxide film formation step is a step of forming an oxide film 104, which will ultimately become part of the oxide film 34, on the entire upper surface of the semiconductor device 1.
[0159] In Figure 20, the planarization oxide film 103, the protective oxide film 101, and the oxide film 104 are not explicitly distinguished, but are simply referred to as oxide film 104.
[0160] Figure 21 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 when the contact opening process has been performed. Figure 21 shows a cross-sectional view similar to that of Figure 8.
[0161] As shown in Figure 21, the contact opening process is a process of removing a portion of the oxide film 104 to form contact openings for forming the first source electrode 11 and the first gate electrode 19. Although Figure 21 only shows the formation of the contact opening for forming the first source electrode 11, contact openings for forming the first gate electrode 19 are also formed outside the area shown in Figure 21.
[0162] Of the oxide film 104, the portion remaining inside the first gate trench 17 becomes the first gate insulating film 16, and the remaining portion becomes the oxide film 34. For this reason, in Figure 21 and Figure 22 described later, the portion of the oxide film 104 remaining inside the first gate trench 17 is described as the first gate insulating film 16, and the remaining portion is described as the oxide film 34.
[0163] Figure 22 is a schematic enlarged cross-sectional view showing an example of the structure around the first gate trench 17 after the electrode and protective film formation process has been carried out. Figure 22 shows a cross-sectional view similar to that of Figure 8.
[0164] As shown in Figure 22, the electrode and protective film formation process involves forming a first source electrode 11 and a first gate electrode 19 in each of the contact openings formed in the contact opening process, and then forming a protective film 35 on the upper surface of the semiconductor device 1. Although only the formation of the first source electrode 11 is shown in Figure 22, the first gate electrode 19 is also formed outside the area shown in Figure 22.
[0165] (Supplement) The above description of a semiconductor device according to one aspect of the present disclosure was based on an embodiment, but the present disclosure is not limited to this embodiment. As long as it does not depart from the spirit of the present disclosure, various modifications that a person skilled in the art can conceive of may be included within the scope of one or more aspects of the present disclosure.
[0166] This disclosure is widely applicable to semiconductor devices and the like that equipped with vertical MOS transistors.
[0167] 1 Semiconductor device 10 First vertical MOS transistor 11 First source electrode 13 First body contact region 14 First source region 14A Monotonically decreasing source region 15 First gate conductor 15A First monotonically decreasing region gate conductor 15B Second monotonically decreasing region gate conductor 16 First gate insulating film 17 First gate trench 17A Central region gate trench 17B Shallow bottom region gate trench 17BA First monotonically decreasing region gate trench 17BB Second monotonically decreasing region gate trench 17C Farthest shallow bottom region gate trench 18 First body region 19 First gate electrode 20 Second vertical MOS transistor 21 Second source electrode 24 Second source region 25 Second gate conductor 26 Second gate insulating film 27 Second gate trench 28 Second body region 29 Second gate electrode 30 Metal layer 32 Semiconductor substrate 33 Low-concentration impurity layer 34, 104 Oxide film 35 Protective film 40 Semiconductor layer 41 First gate wiring 42 Second gate wiring 51 First central region 52 First peripheral region 53 Shallow bottom region 55 Monotonically decreasing region 61 Second central region 62 Second peripheral region 70 Mesa region 70A Specific mesa region 70B Central region mesa region 101 Protective oxide film 102 Polysilicon 103 Planarizing oxide film 111, 111a, 111b, 111c, 111d First source pad 119 First gate pad 121, 121a, 121b, 121c, 121d Second source pad 129 Second gate pad A1 First region A2 Second region
Claims
1. A semiconductor device comprising a vertical MOS (Metal Oxide Semiconductor) transistor, comprising: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; a low-concentration impurity layer of the first conductivity type, formed in contact with the semiconductor substrate and containing an impurity of a second concentration lower than the first concentration; a body region of a second conductivity type different from the first conductivity type, formed in the low-concentration impurity layer including the upper surface of the low-concentration impurity layer and containing an impurity of a third concentration; a plurality of gate trenches extending in a first direction parallel to the upper surface of the semiconductor substrate and in a second direction perpendicular to the first direction, formed at equal intervals in the second direction parallel to the upper surface of the semiconductor substrate, extending from the upper surface of the low-concentration impurity layer to a depth penetrating the body region and reaching a part of the low-concentration impurity layer; and a plurality of gate conductors formed inside each of the plurality of gate trenches. Each of a plurality of specific mesa portions, which is at least a part of a plurality of mesa portions sandwiched between the plurality of gate trenches in the second direction, comprises a plurality of source regions and a plurality of body contact regions formed alternately in the first direction at a predetermined period, wherein the plurality of source regions of a first conductivity type formed in the specific mesa portion including the upper surface of the specific mesa portion, and the plurality of body contact regions of a second conductivity type formed in the specific mesa portion including the upper surface of the specific mesa portion, and containing a fourth concentration of impurities higher than the third concentration, wherein the plurality of specific mesa portions is a mesa portion comprising the plurality of source regions and the plurality of body contact regions formed alternately in the first direction at a predetermined period, the body region is a central region whose depth from the upper surface of the low-concentration impurity layer is constant at a first depth, and comprises the central region which does not include the outer periphery of the body region in a plan view of the semiconductor device, and a peripheral region which is a region other than the central region, the peripheral region includes a shallow-bottom region whose depth from the upper surface of the low-concentration impurity layer is shallower than the first depth, Each of the multiple central region mesa portions, of which at least a portion is included in the central region, is one of the multiple specific mesa portions, and the multiple gate trenches areA semiconductor device comprising: a plurality of central region gate trenches formed from the upper surface of the low-concentration impurity layer to a depth that penetrates at least a portion of the central region and reaches a portion of the low-concentration impurity layer; and a plurality of shallow-bottom region gate trenches formed from the upper surface of the low-concentration impurity layer to a depth that penetrates the shallow-bottom region and reaches a portion of the low-concentration impurity layer, wherein the plurality of shallow-bottom region gate trenches do not include portions that penetrate the central region.
2. In each of the plurality of shallow region gate trenches, among the maximum depths from the upper surface of the low-concentration impurity layer of the body region at the position through which the shallow region gate trench penetrates, the maximum depth from the upper surface of the low-concentration impurity layer of the furthest shallow region gate trench, which is the furthest shallow region gate trench with the greatest distance from the central region in the second direction, is the smallest.
3. In the shallow bottom region, there exists a monotonically decreasing region in which the depth from the top surface of the low-concentration impurity layer decreases monotonically depending on the distance from the central region in the second direction, and among the plurality of source regions, a plurality of monotonically decreasing source regions formed in a plan view at a position contained within the monotonically decreasing region have a depth from the top surface of the low-concentration impurity layer that decreases monotonically depending on the distance from the central region in the second direction, and the gradient of the depth from the top surface of the low-concentration impurity layer in the monotonically decreasing region in the second direction is equal to the gradient of the depth from the top surface of the low-concentration impurity layer in the plurality of monotonically decreasing source regions in the second direction, The semiconductor device according to claim 2, wherein the plurality of shallow region gate trenches are a plurality of first monotonically decreasing region gate trenches sandwiched in the second direction between any one of the plurality of specific mesa portions and any other specific mesa portion, and the plurality of first monotonically decreasing region gate trenches are formed to a depth from the upper surface of the low-concentration impurity layer, penetrating at least a portion of the monotonically decreasing region, to a portion of the low-concentration impurity layer.
4. The semiconductor device according to claim 3, wherein the plurality of shallow region gate trenches further include a plurality of second monotonically decreasing region gate trenches that are not sandwiched between any one of the plurality of specific mesa portions and any other specific mesa portion in the second direction, and which are formed to a depth from the upper surface of the low-concentration impurity layer, penetrating at least a portion of the monotonically decreasing region, to a portion of the low-concentration impurity layer, and the distance of the plurality of second monotonically decreasing region gate trenches from the central region in the second direction is greater than any of the distances of the plurality of first monotonically decreasing region gate trenches from the central region in the second direction.
5. The semiconductor device according to claim 4, further comprising a gate electrode of the vertical MOS transistor, wherein each of the plurality of first monotonically decreasing region gate conductors formed inside the plurality of first monotonically decreasing region gate trenches is electrically connected to the gate electrode, and at least one of the plurality of second monotonically decreasing region gate conductors formed inside the plurality of second monotonically decreasing region gate trenches is not electrically connected to the gate electrode.
6. The semiconductor device according to claim 2, further comprising: a gate electrode of the vertical MOS transistor; and gate wiring that, in a plan view, surrounds the entire body region and is electrically connected to the gate electrode and the plurality of gate conductors, and is formed above the upper surface of the low-concentration impurity layer, wherein the length of the shallow bottom region in the second direction is longer than the shortest distance between the furthest shallow bottom region gate trench and the gate wiring in the second direction.
7. The semiconductor device according to claim 6, wherein the minimum protrusion length of the furthest shallow-bottom region gate trench from the shallow-bottom region is 100 nm or more longer than the maximum protrusion length of the plurality of central region gate trenches from the central region.