Clock divider for guaranteeing low clock output during power mode transition and control method thereof

Abstract

A clock divider according to an embodiment of the present invention comprises: a counter configured to count clocks of an input clock and generate a counter output used to divide the input clock; an output clock generator configured to generate a clock edge according to the counter output and generate an output clock by dividing the input clock; a state machine configured to control an operation of the counter by updating a counter expiration value of the counter according to a divider value; and a divider value control unit configured to control the divider value according to a clock-low request from a power management unit and output the divider value to the state machine. The divider value control unit outputs a bypass divider value to the state machine in response to the clock-low request, the bypass divider value causing the input clock to be bypassed and output as the output clock.

Description

Clock divider that guarantees low clock output during power mode switching and method for controlling the same

[0001] The present invention relates to a clock divider, and more specifically, to a clock divider that guarantees a low clock output during power mode switching, such as power up / down, and a method for controlling the same.

[0002] A System on Chip (SoC) refers to the technology of integrating various function blocks—such as a CPU (Central Processing Unit), memory, interfaces, digital signal processing circuits, and analog signal processing circuits—into a single semiconductor integrated circuit to implement computer systems or other electronic systems, or the single Integrated Circuit (IC) integrated according to this technology. SoCs are evolving into more complex systems that include various function blocks, such as processors, multimedia, graphics, interfaces, and security. Clock design is critical for SoCs.

[0003] A clock divider is provided to generate the clock required by the SoC. The clock divider generates an output clock by dividing the input clock. In clock design, the clock divider used in the clock tree operates an internal counter based on the division ratio and divides the clock by creating a clock output edge whenever the counter count expires.

[0004] FIG. 1 is an example diagram showing a case where a clock divider divides the input clock by 8 to generate an output clock. FIG. 2 is an example diagram showing a case where the output clock produced by the clock divider is in a low-level state at the moment the input clock is gated. FIG. 3 is an example diagram showing a case where the output clock produced by the clock divider is in a high-level state at the moment the input clock is gated.

[0005] When it is necessary to retain a power domain within a semiconductor system, there is a constraint that the clock input to the flip-flop must be at a low level during the retention signal transition period. A retention flip-flop equipped with a retention function can preserve stored data even when the power is turned off, which is particularly useful in applications where power saving is critical. Retention flip-flops reduce the overall system's power consumption by retaining data when the power is turned off or enters a low-power mode, and ensure data integrity by recovering data when the power is turned back on.

[0006] As shown in Figure 2, during the process of performing clock division by 8, if the counter value for clock division is 4, 5, 6, or 7 at the moment (GT) when the input clock is gated, the output clock becomes a low level state. If the condition is simply to stop the clock toggle, clock gating can be performed by ICG (Integrated Clock Gating), but if clock gating is performed in a clock divider equipped with a counter, the output clock may stop at a high level rather than a low level depending on the counter's count state in that cycle.

[0007] For example, as shown in FIG. 3, when the counter for clock division is operating during the interval where the output clock is at a high level, that is, the interval where the counter's count value is 0, 1, 2, or 3 at the moment the input clock is gated, the output clock stops at a high level. In this way, even if the input clock is gated, the output clock may stop at a high level rather than a low level depending on the counter's count state.

[0008] If there are flip-flops that operate by receiving the output clock from a clock divider, and these flip-flops are required to be retained, the clock of the corresponding flip-flops must be at a low level during the retention signal transition period; however, if it is not guaranteed that the output clock of the clock divider is in a low level state, proper retention cannot be performed for the flip-flops. This problem can be a factor that restricts the degrees of freedom in clock design.

[0009] As a technology to solve these problems, Patent Application No. 10-2024-0096475 (filed July 22, 2024) discloses a clock divider that ensures the output clock is in a low-level state during the retention signal switching interval so that the retention operation can be performed smoothly. FIG. 4 is a configuration diagram showing a clock divider that ensures the output clock is in a low-level state during the retention signal switching interval.

[0010] The clock divider (10) illustrated in FIG. 4 checks whether the output clock of the output clock generator (12) has stopped in a low-level state after the counter (11) expires when the state machine (13) receives a clock low request from the power management unit (20), and then stops the counter operation so that the clock output stops. In this case, it can be guaranteed that the output clock input to the retention flip-flop (30) is in a low-level state during the retention transition period for power down.

[0011] However, the clock divider (10) illustrated in FIG. 4 may not guarantee normal operation of the subsequent clock divider in a cascade structure clock divider in which two or more clock dividers (10a, 10b) are connected in series. FIG. 5 is a configuration diagram showing a cascade structure clock divider. As shown in FIG. 5, when multiple clock dividers (10a, 10b) are combined in a cascade structure, each clock divider (10a, 10b) receives a clock low request, checks whether each counter expires and the clock output has stopped at a low level, and stops the counter operation so that the clock output stops.

[0012] At this time, it is not known which clock divider output clock among the front clock divider (10a) and the rear clock divider (10b) will stop first, and it may vary depending on the divider ratio of each clock divider (10a, 10b). If the output clock of the front clock divider (10a) stops at a low level first, a problem may occur in which the rear clock divider (10b) cannot operate the counter and the state machine.

[0013] The present invention is intended to provide a clock divider and a control method thereof that ensure a low clock output during the retention signal switching interval when switching power modes, such as power up / down, so that the retention operation can be performed smoothly.

[0014] In addition, the present invention is intended to provide a clock divider and a control method thereof that can ensure an output clock for retention at a low level while maintaining the operation of a cascade structure clock divider.

[0015] In addition, the present invention is intended to provide a clock divider and a control method thereof that ensures a low-level state of the output clock by bypassing the input clock and generating the output clock when a clock low request is made by a power management unit.

[0016] In addition, the present invention is intended to provide a clock divider and a control method thereof, wherein a plurality of clock dividers combined in a cascade structure are simultaneously switched to a low level by gating the input clock.

[0017] The technical problems to be solved by the embodiments of the present invention are not limited to those described above, and other technical problems can be inferred from the following embodiments.

[0018] A clock divider according to an embodiment of the present invention comprises: a counter that counts the clock of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a clock edge according to the counter output and generates an output clock divided from the input clock; a state machine that controls the operation of the counter by updating the counter expiration value of the counter according to the division value; and a division value control unit that controls the division value according to a clock row request from a power management unit and outputs it to the state machine. The division value control unit outputs a bypass division value to the state machine such that the input clock is bypassed to the output clock and output according to the clock row request.

[0019] The above-described division value control unit may include a division value controller that outputs a clock division value stored in a register to the state machine; and a clock row request controller that generates a bypass division value according to the clock row request and outputs it to the division value controller. The division value controller may override the bypass division value and output it to the state machine.

[0020] The above counter may operate or stop counting operation based on a counter expiration value corresponding to the above bypass division value. The above output clock generator may generate and output an output clock identical to the input clock based on the above bypass division value or the cessation of the counting operation of the above counter.

[0021] The state machine above can update the counter expiration value according to the bypass division value so that the output clock stops at a low level according to the gating of the input clock performed after the clock low request.

[0022] The state machine above can update the counter expiration value according to the bypass division value and control the counter so that the output clock becomes a low level during the retention signal switching period.

[0023] The above state machine can update the counter expiration value according to the bypass division value after the count expiration of the counter expiration value according to the clock division value.

[0024] The above output clock is input to a flip-flop, and the flip-flop can be retained when it is guaranteed that the output clock is in a low level state.

[0025] A semiconductor system according to an embodiment of the present invention comprises: the clock divider; one or more flip-flops that receive an output clock, which is divided from an input clock and output by the clock divider within a power domain, and operate by the output clock; and a power management unit that outputs a clock row request to a division value control unit of the clock divider for retention.

[0026] The power management unit can output a retention signal to the flip-flop when it is guaranteed that the output clock is in a low level state in response to the clock low request.

[0027] According to an embodiment of the present invention, a computer-readable non-transient recording medium is provided on which a computer program is recorded for executing a clock divider control method for controlling the operation of a clock divider comprising a counter, an output clock generator, a state machine, and a division value control unit.

[0028] The above clock divider control method comprises: a step of counting the clock of an input clock by the counter to generate a counter output for dividing the input clock; a step of generating a clock edge according to the counter output by the output clock generator to generate an output clock divided from the input clock; a step of controlling the operation of the counter by updating the counter expiration value of the counter according to the division value by the state machine; and a step of controlling the division value to be output to the state machine according to a clock row request of a power management unit by the division value control unit.

[0029] The step of controlling the division value may include the step of outputting a bypass division value to the state machine such that, in accordance with the clock row request, the input clock is bypassed to the output clock and output.

[0030] The step of controlling the division value may include: outputting the clock division value stored in the register to the state machine by means of the division value controller of the division value control unit; generating the bypass division value according to the clock row request by means of the clock row request controller of the division value control unit and outputting it to the division value controller; and overriding the bypass division value and outputting it to the state machine by means of the division value controller.

[0031] The above clock divider control method may further include: a step in which the counter operates by a counter expiration value corresponding to the bypass divider value or stops the counting operation according to the bypass divider value; and a step in which the output clock generator generates and outputs an output clock identical to the input clock according to the bypass divider value or according to the cessation of the counter's counting operation according to the bypass divider value.

[0032] The above clock divider control method may further include the step of the state machine updating the counter expiration value according to the bypass divider value, so that the output clock is stopped at a low level according to the gating of the input clock performed after the clock low request.

[0033] The above clock divider control method may further include the step of the state machine updating the counter expiration value according to the bypass divider value so that the output clock becomes a low level during the retention signal switching interval.

[0034] The above clock divider control method may further include the step of the state machine updating the counter expiration value according to the bypass divider value after the counting expiration of the counter expiration value according to the clock divider value.

[0035] The above clock divider control method may further include the step of inputting the output clock into a flip-flop, and the flip-flop being retained when it is guaranteed that the output clock is in a low-level state.

[0036] According to an embodiment of the present invention, a clock divider and a control method thereof are provided, which ensure a low clock output in the retention signal switching interval during power mode switching, such as power up / down, so that the retention operation can be performed smoothly.

[0037] In addition, according to an embodiment of the present invention, a clock divider and a control method thereof are provided, which can ensure an output clock for retention at a low level while maintaining the operation of a cascade structure clock divider.

[0038] In addition, according to an embodiment of the present invention, when a clock low request is made by the power management unit, the input clock is bypassed and an output clock is generated, thereby ensuring a low level state of the output clock.

[0039] In addition, according to an embodiment of the present invention, a plurality of clock dividers combined in a cascade structure can be switched to a low level simultaneously by gating the input clock.

[0040] The effects that the present invention aims to achieve are not limited to those mentioned above, and other unmentioned effects can be clearly understood by those skilled in the art from the description below.

[0041] Figure 1 is an example diagram showing a case where a clock divider divides the input clock by 8 to generate an output clock.

[0042] Figure 2 is an example diagram showing the case where the output clock output by the clock divider is in a low-level state at the moment the input clock is gated.

[0043] Figure 3 is an example diagram showing the case where the output clock output by the clock divider is in a high level state at the moment the input clock is gated.

[0044] Figure 4 is a configuration diagram showing a clock divider that ensures the output clock is in a low-level state during the retention signal switching interval.

[0045] Figure 5 is a configuration diagram showing a cascade structure clock divider.

[0046] FIG. 6 is a configuration diagram showing a clock divider according to an embodiment of the present invention.

[0047] FIG. 7 is an illustrative diagram for explaining the operation of a clock divider according to an embodiment of the present invention.

[0048] FIG. 8a is a configuration diagram showing a cascade structure clock divider according to an embodiment of the present invention.

[0049] FIG. 8b is an example diagram illustrating the operation of a cascade structure clock divider shown in FIG. 8a.

[0050] FIG. 9 is a conceptual diagram showing a computing device for executing a clock divider control method according to an embodiment of the present invention.

[0051] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding well-known functions or configurations will be omitted if there is a risk that the essence of the present invention may be unnecessarily obscured. In the attached drawings, identical or corresponding components are assigned the same reference numerals whenever possible. In the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0052] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to fully inform a person skilled in the art of the scope of the invention.

[0053] The terms used in this specification will be briefly explained, and the disclosed embodiments will be described in detail. The terms used in this specification have been selected to be as widely used as possible, taking into account their functions in the present invention; however, these terms may vary depending on the intent of those skilled in the relevant field, case law, or the emergence of new technologies. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall content of the present invention.

[0054] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. In the present invention, terms such as 'include' and 'include' may indicate the presence of features, steps, actions, elements, and / or components, and such terms do not exclude the addition of one or more other functions, steps, actions, elements, components, and / or combinations thereof.

[0055] In the present invention, where a specific component is described as being 'combined,' 'combined,' 'connected,' 'associated,' or 'reacting' with any other component, the specific component may be directly combined, combined, connected, and / or associated with, or react with the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Additionally, in the present invention, "and / or" may include each of the one or more listed items or a combination of at least some of the one or more items. In the present invention, terms such as "first," "second," etc., are used to distinguish a specific component from another component, and the components described above are not limited by these terms. For example, the "first" component may be used to refer to an element of the same or similar form as the "second" component.

[0056] A clock divider according to an embodiment of the present invention includes a state machine that controls the operation of a counter by updating the counter expiration value of the counter according to the division value, and a division value control unit that controls the division value according to a clock low request from a power management unit and outputs it to the state machine. The division value control unit can output a bypass division value to the state machine such that the input clock is bypassed to the output clock and output according to the clock low request from the power management unit. Accordingly, after the counting expiration of the counter, the input clock is bypassed in an undivided state by the bypass division value, and an output clock identical to the input clock is output from the output clock generator. At this time, if the input clock is made to a low level at the top of the clock tree, all clock dividers output the low-level input clock as is. Therefore, it can be ensured that the output clock stops at a low level through gating of the input clock during the retention signal switching section when switching power modes such as power up and / or power down.

[0057] The retention signal transition interval may be the interval during which the device transitions from normal mode to retention mode. Retention mode may be a mode in which data stored within a flip-flop is retained when the power is off or in a low-power state. In this specification, power mode transition may refer to a state in which the power is turned off or reduced (low-power state), or a state in which the power is turned on or increased (high-power state), such as power up and / or power down. For example, when the device transitions to normal mode after retention mode to turn the power back on or to normal power mode (a power mode higher than low-power mode), the flip-flop may retain the data stored at the time of transition to retention mode.

[0058] FIG. 6 is a configuration diagram showing a clock divider according to an embodiment of the present invention. Referring to FIG. 6, a clock divider (100) according to an embodiment of the present invention may include a counter (110), an output clock generator (120), a state machine (130), and a division value control unit (140). A clock divider (100) according to an embodiment of the present invention may include a state machine (130) and a division value control unit (140) within the clock divider (100) that control the counter (110) so that the output clock of the clock divider (100) becomes a low level during a retention signal switching section when power is down, in accordance with a Clock Low Request of a power management unit (200).

[0059] The counter (110) can generate a counter output based on the count of a counter expire value corresponding to the divide value of the clock by counting the input clock. The counter (110) can generate a counter output by comparing the counter expire value corresponding to the divide value with the count value of the counter (110) for the input clock. For example, when the divide value is N (N is an integer greater than or equal to 2), the counter (110) can output a counter output to an output clock generator (120) whenever the N / 2 value is counted.

[0060] For example, when the division value is 8, the counter (110) can generate a first counter output and output it to the output clock generator (120) at the moment when four input clocks from the first clock to the fourth clock are counted, and then generate a second counter output and output it to the output clock generator (120) at the moment when four input clocks from the fifth clock to the eighth clock are counted.

[0061] As another example, when the prescaler value is 4, the counter (110) can generate a first counter output and output it to the output clock generator (120) at the moment when two input clocks from the first clock to the second clock are counted, and then generate a second counter output and output it to the output clock generator (120) at the moment when two input clocks from the third clock to the fourth clock are counted.

[0062] When the prescaler value is 8, the counter expiration value set for the counter (110) is 8, and when the prescaler value is 4, the counter expiration value set for the counter (110) can be 4. When the prescaler value is N, the counter expiration value set for the counter (110) can be N. That is, when the prescaler value is N, the counter expiration value set for the counter (110) can be input to the output clock generator (120) when the input clock reaches the Nth count (or the (N-1)th count in the case of counting from 0), based on starting the count from 1.

[0063] When the division value is N, the counter (110) can generate a first counter output and output it to the output clock generator (120) at the moment when N / 2 of the input clocks are counted, and then generate a second counter output and output it to the output clock generator (120) at the moment when N / 2 of the input clocks are counted again. The output clock generator (120) can generate an output clock divided from the input clock according to the counter outputs (first counter output, second counter output) of the counter (110).

[0064] The first counter output of the counter (110) is a signal that causes the output clock generator (120) to generate a falling edge (or rising edge) of the output clock, and the second counter output of the counter (110) may be a signal that causes the output clock generator (120) to generate a rising edge (or falling edge) of the output clock. The output clock generator (120) can generate a rising edge and a falling edge repeatedly according to the counter output from the counter (110) whenever it counts a value corresponding to half of the divided value, thereby generating and outputting an output clock divided from the input clock.

[0065] When the prescaler value is 8, the clock period of the output clock can be 8 times the reference clock period of the input clock. In this case, the frequency of the output clock becomes 1 / 8 of the input clock. As another example, when the prescaler value is 4, the clock period of the output clock can be 4 times the reference clock period of the input clock. In this case, the frequency of the output clock becomes 1 / 4 of the input clock. When the prescaler value is N (N is an integer greater than or equal to 2), the clock period of the output clock becomes N times the reference clock period of the input clock, and the frequency of the output clock becomes 1 / N of the input clock.

[0066] When the division value changes, the counter (110) may generate a counter output based on the coefficient of the first counter expiration value corresponding to the division value before the change, and generate a counter output based on the coefficient of the second counter expiration value corresponding to the division value after the change. For example, when the division value changes from 8 divisions to 4 divisions, the division value before the change may be 8, and the division value after the change may be 4. As another example, when the division value changes from 4 divisions to 8 divisions, the division value before the change may be 4, and the division value after the change may be 8. The division value may preferably be a multiple of 2, but is not necessarily limited thereto. In addition, various division values ​​other than the 4 divisions and 8 divisions exemplified may be applied.

[0067] To prevent unintended duty cycle changes caused by a change in the division value, the state machine (130) can control the update of the counter expiration value based on the count value of the counter (110) and the counter expiration value corresponding to the division value before the change. When the division value is changed, the state machine (130) can update the counter to a second counter expiration value corresponding to the changed division value depending on whether the first counter expiration value has expired. The first counter expiration value may be the counter expiration value corresponding to the first division value before the change, and the second counter expiration value may be the counter expiration value corresponding to the second division value after the change. For example, if the division value is changed from 8 division to 4 division, the first counter expiration value may be 8 and the second counter expiration value may be 4.

[0068] The state machine (130) receives a clock division value (clock division value) stored in a CMU register (210) provided in a Clock Management Unit (CMU), and can set the counter expiration value of the counter (110) according to the clock division value of the CMU register (210). The CMU is a module that plays the role of generating, distributing, and adjusting clocks in a semiconductor system, and can perform functions such as clock source selection (selection of internal or external clocks (PLL, XTAL, RC OSC, etc.), clock distribution (supplying appropriate clocks to each subsystem such as cores, memory, and peripherals), clock gating (blocking clocks that are not needed for low-power mode), and clock scaling (dynamically adjusting clock speeds for power efficiency).

[0069] The CMU register (210) can store various setting values ​​to control the system clock. The CMU register (210) can store setting information for selecting a clock source to be used by the system, PLL setting (Phase-Locked Loop Configuration) information (frequency control information, etc.), setting information for clock gating, clock divider setting (Clock Divider Configuration) information, low power clock control related clock setting information, etc.

[0070] In one embodiment, when the division value is changed, the state machine (130) can determine whether the count of the first counter expiration value has expired by comparing the first counter expiration value (the existing counter expiration value before the division value change) corresponding to the division value before the change with the count value of the counter. If the count value of the counter (110) has not reached the first counter expiration value, the state machine (130) may wait without updating the second counter expiration value (new counter expiration value) corresponding to the changed division value. The state machine (130) may update the counter expiration value of the counter (110) to the second counter expiration value the moment the count value of the counter (110) reaches the first counter expiration value.

[0071] In this way, when the division value is changed, the state machine (130) waits without updating the counter expiration value corresponding to the changed division value until the counter expiration value corresponding to the division value before the change is counted, and then at the moment when the counting of the counter (110) corresponding to the division value before the change is completed (the moment when the first counter expiration value expires), it can update the counter expiration value (second counter expiration value) corresponding to the changed division value for the counter (110).

[0072] That is, the state machine (130) can withhold the update of the counter expiration value corresponding to the change in the division value until the clock duty ratio at the division value before the change and the clock duty ratio at the division value after the change become equal. In other words, the state machine (130) can wait for the update of the counter expiration value for a number of clocks corresponding to the difference between the first counter expiration value before the change in the division value of the counter (110) and the count value of the counter at the time when the division value is changed.

[0073] For example, when the counter (110) counts the 5th clock of the input clock and the prescaler value changes from 8 to 4, the first counter expiration value becomes 8 and the current count value of the counter (110) becomes 5. Therefore, the state machine (130) waits until the counter (110) counts an additional 3 clocks (8 clocks - 5 clocks) of the input clock, and then counts the remaining 3 clocks in the counter (110) until the counter expiration state is reached, at which time the counter expiration value can be updated from the existing 8 to the changed 4. If the changed prescaler value is N (N is an integer greater than or equal to 2), the state machine (130) can set the counter expiration value of the counter (110) to a count value N corresponding to the number of N clocks.

[0074] The power management unit (200) can control the power supplied to the IP blocks. For example, when the system-on-chip enters standby mode, the power management unit (200) can cut off the power supply provided to each IP block to reduce the power consumption of the system-on-chip. At this time, the power management unit (200) can output a clock low request to the state machine (130) of the clock divider (110) for retention.

[0075] The division value control unit (140) can control the division value according to the clock row request of the power management unit (200) and output it to the state machine. The division value control unit (140) outputs a bypass division value to the state machine such that the input clock is bypassed to the output clock according to the clock row request of the power management unit (200). The bypass division value may be, for example, a division value corresponding to '0' or '1'.

[0076] For example, the frequency of the input clock (F in ) and the frequency of the output clock (F out ) is F out = F in The relationship / (DIVRATIO+1) can hold. In this case, the bypass prescaler value (DIVRATIO) can be '0'. Or, F out = F in When defining a prescaler value to establish a / DIVRATIO relationship, the bypass prescaler (DIVRATIO) may be set to '1', or, according to another definition, may be a value other than '0' or '1'. In either case, the bypass prescaler refers to a prescaler value that causes the output clock to be output at the same frequency as the input clock.

[0077] The division value control unit (140) may include a clock row request controller (141) and a division value controller (142). The clock row request controller (141) may generate a bypass division value (e.g., 'Divide Value = 0') in response to a clock row request from the power management unit (200) and output it to the division value controller (142). The clock row request controller (141) may be implemented as an override control block within the clock divider (100) and may play a role in overriding the division value to 0 as the bypass division value when a clock row request is received.

[0078] The clock division controller (142) can output the clock division value stored in the register (CMU register) to the state machine (130). When a bypass division value is input from the clock row request controller (141), the clock division controller (142) can override the bypass division value and output it to the state machine (130). That is, the clock division controller (142) can ignore the clock division value input from the CMU register (210) and prioritize the bypass division value input from the clock row request controller (141) to output it to the state machine (130).

[0079] The state machine (130) can control the counter (110) so that the output clock becomes low level during the retention signal switching period. The state machine (130) determines whether the count value of the counter (110) has reached a counter expiration value corresponding to the clock division value of the CMU register (210) (counter expiration status), and can wait until the count value of the counter (110) reaches a counter expiration value corresponding to the clock division value.

[0080] When the state machine (130) receives a bypass division value from the division value controller (142), it can update the counter expiration value of the counter (110) according to the bypass division value, thereby controlling the counter (110) so that the output clock of the clock divider (100) becomes a low level during the retention signal switching period. When the count value of the counter (110) reaches the counter expiration value corresponding to the clock division value of the CMU register (210), the state machine (130) can set the counter expiration value corresponding to the bypass division value in the counter (110). The counter (110) can operate based on the counter expiration value corresponding to the bypass division value. Accordingly, the input clock can be bypassed as is without being divided and output as the output clock.

[0081] FIG. 7 is an illustrative diagram for explaining the operation of a clock divider according to an embodiment of the present invention. Referring to FIG. 6 and FIG. 7, when a power management unit (200) sends a Clock Low Request to a clock divider (100) as it proceeds with a power up / down sequence, the Clock Low Request controller (141) can convert this into a command to override with "DIVRATIO = 0" (bypass divider value) and send it to a divider value controller (142).

[0082] The clock divider controller (142) outputs the clock divider value provided from the CMU register (210) to the state machine (130) to control the clock divider (100) to operate according to the clock divider value. During this process, if a bypass divider value corresponding to the clock row request of the power management unit (200) is provided from the clock row request controller (141), the divider value can be overridden with the bypass divider value and output to the state machine (130).

[0083] The state machine (130) can update the counter expiration value of the counter (110) to a bypass counter expiration value corresponding to the bypass division value after the clock division value counting interval (T1) from the clock row request time (CLR) to the counter expiration time (CE) when the counter expiration value of the counter currently being counted (110) is completed. In the subsequent bypass division value counting interval (T2), the count output of the counter (110) can be generated according to the bypass counter expiration value.

[0084] Accordingly, the output clock generator (120) generates an output clock by generating a rising edge of the output clock according to the rising edge of the input clock and a falling edge of the output clock according to the falling edge of the input clock, and as a result, the input clock can be bypassed and output as the output clock. In this state, if the input clock is gated at the gating point (GT), it can be guaranteed that the output clock of all clock dividers (100) is in a low level state. Gating of the input clock means a state in which the input clock is maintained in a low level state during the gating period, and at this time, the input clock becomes off.

[0085] When the counting expiration value of the counter (110) is set to a bypass division value (e.g., a state where 'DIVRATIO = 0'), the output clock is bypassed with a clock waveform identical to the input clock, and since the counter (110) inside the clock divider (100) does not operate, when the input clock is gated, the output clock of the clock divider (100) does not stop at a high level but must stop at a low level. Meanwhile, if the counting operation of the counter (110) is stopped by the state machine (130) according to the bypass division value, the counter (110) may be prevented from operating so that the input clock is bypassed to the output clock without being divided.

[0086] FIG. 8a is a configuration diagram showing a cascade structure clock divider according to an embodiment of the present invention. FIG. 8b is an example diagram for explaining the operation of the cascade structure clock divider illustrated in FIG. 8a. Referring to FIG. 8a and FIG. 8b, the cascade structure clock divider may be provided as a cascade structure in which a plurality of clock dividers (100a, 100b) are connected in series. That is, the cascade structure clock divider is a structure in which the first output clock of the first clock divider (front-end clock divider (100a)) is input as the input clock of the second clock divider (rear-end clock divider) (100b).

[0087] When the first clock divider (100a) receives a clock row request from the power management unit (200) at the clock row request time (CLR), it can override the first divider value with a bypass divider value to update the counter expiration value of the first counter (110a) to a bypass counter expiration value. Similarly, when the second clock divider (100b) receives a clock row request from the power management unit (200) at the clock row request time (CLR), it can override the second divider value with a bypass divider value to update the counter expiration value of the second counter (110b) to a bypass counter expiration value.

[0088] The first division value of the first clock divider (100a) and the second division value of the second clock divider (100a) may be the same division value or different division values. The first clock divider (100a) and the second clock divider (100b) bypass the input clock according to the bypass division value from the counter expiration time (CE) when the count values ​​of the counters (110a, 110b) reach the counter expiration value corresponding to the first division value and the second division value, respectively.

[0089] Accordingly, the first output clock of the first clock divider (100a) is generated and output by bypassing the input clock, and the first output clock thus output becomes the input clock of the second clock divider (100b). Since the second clock divider (100b) outputs a second output clock identical to the first output clock corresponding to the input clock according to the bypass divider value, the output clocks of the first clock divider (100a) and the second clock divider (100b) all become identical to the input clock.

[0090] Accordingly, at the gating point (GT), the output clocks of the first clock divider (100a) and the second clock divider (100b) can be stopped at a low level simultaneously by gating the input clock. In this way, even when multiple clock dividers (100a, 100b) are cascaded, the retention signal movement is guaranteed in a state where the output clock is always at a low level, so the retention of the flip-flops (300) can be performed normally.

[0091] As described above, according to the clock divider of the embodiment of the present invention, particularly in a cascade structure clock divider, it is possible to prevent the output clock of the preceding clock divider from stopping at a low level before the output clock of the following clock divider stops at a low level.

[0092] If the output clock of the front clock divider becomes low level first and stops while the rear clock divider is operating, the rear clock divider(s) cannot perform normal clock operation and the degree of freedom of clock design is limited; however, according to an embodiment of the present invention, when switching power modes, the front clock divider and the rear clock divider can be made to stop at a low level simultaneously by gating the input clock.

[0093] Accordingly, even in the case of a cascade structure clock divider, it is guaranteed that the output clocks of all clock dividers will become low levels without issue during retention, so the output clocks of the clock dividers can be used directly in the retention logic, and this can improve the freedom of clock design.

[0094] As described above, according to an embodiment of the present invention, when switching power modes such as power up / down, the output clock of the clock divider is guaranteed to be a low clock output during the retention signal switching interval, so that the retention operation of the flip-flops can be performed smoothly and correctly. In addition, the output clock for retention can be guaranteed to be at a low level while maintaining the operation of a cascade structure clock divider (especially a subsequent clock divider).

[0095] In addition, according to an embodiment of the present invention, when a clock low request is made by a power management unit, the input clock is bypassed to generate an output clock, thereby ensuring a low-level state of the output clock. Furthermore, multiple clock dividers combined in a cascade structure can be simultaneously switched to a low level by gating the input clock. Additionally, when performing retention, the output clock of the clock divider can be guaranteed to be at a low level, allowing the output clock of the clock divider to be used directly in the retention logic, which increases the freedom of clock design in the semiconductor system.

[0096] FIG. 9 is a conceptual diagram illustrating a computing device for executing a clock divider control method according to an embodiment of the present invention. An exemplary computing device (900) for performing the above-described method and / or embodiment is described. According to one embodiment, the computing device (900) may be implemented using hardware and / or software configured to interact with a user. Here, the computing device (900) may include, but is not limited to, a laptop, a desktop, a workstation, a personal digital assistant, a server, a blade server, a main frame, etc. The components of the above-described computing device (1300), their connection relationships, and their functions are intended to be exemplary and are not intended to limit the embodiments of the present invention described and / or claimed herein.

[0097] The computing device (900) includes a processor (910), memory (920), storage device (930), communication device (940), a high-speed interface (950) connected to the memory (920) and a high-speed expansion port, and a low-speed interface (960) connected to a low-speed bus and storage device. Each of the components (910, 920, 930, 940, 950 and 960) may be interconnected using various buses and may be mounted on the same main board or connected in other suitable ways. The processor (910) may be configured to process instructions of a computer program by performing basic arithmetic, logic, and input / output operations. For example, the processor (910) may process instructions stored in memory (920), storage device (930), etc., and / or instructions executed within the computing device (900) to display graphic information on an external input / output device (970), such as a display device coupled to the high-speed interface (950).

[0098] The communication device (940) may provide a configuration or function for the input / output device (970) and the computing device (900) to communicate with each other via a network, and may provide a configuration or function to support the input / output device (970) and / or the computing device (900) communicating with other external devices, etc. For example, a request or data generated by the processor of an external device according to any program code may be transmitted to the computing device (900) via a network under the control of the communication device (940). Conversely, a control signal or command provided under the control of the processor (910) of the computing device (900) may be transmitted to another external device via the communication device (940) and the network.

[0099] In the illustration, the computing device (900) is described as including one processor (910), one memory (920), etc., but is not limited thereto, and the computing device (900) may be implemented using multiple memories, multiple processors and / or multiple buses, etc. Additionally, in the illustration, it is described as having one computing device (900), but is not limited thereto, and multiple computing devices may interact and perform operations necessary to execute the method described above.

[0100] Memory (920) can store information within a computing device (900). According to one embodiment, memory (920) may be composed of a volatile memory unit or a plurality of memory units. Additionally or alternatively, memory (920) may be composed of a non-volatile memory unit or a plurality of memory units. Furthermore, memory (920) may be composed of other forms of computer-readable media, such as a magnetic disk or an optical disk. Additionally, memory (920) may store an operating system and at least one program code and / or instruction.

[0101] The storage device (930) may be one or more mass storage devices for storing data for the computing device (900). For example, the storage device (930) may be a computer-readable medium including a magnetic disc such as a hard disk or removable disk, an optical disc, a semiconductor memory device such as an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable PROM), or a flash memory device, or may be configured to include such a computer-readable medium. Additionally, a computer program may be tangibly implemented on such a computer-readable medium.

[0102] The high-speed interface (950) and the low-speed interface (960) may be means for interaction with an input / output device (970). For example, the input device may include a device such as a camera including an audio sensor and / or an image sensor, a keyboard, a microphone, a mouse, etc., and the output device may include a device such as a display, a speaker, a haptic feedback device, etc. In another example, the high-speed interface (950) and the low-speed interface (960) may be means for interfacing with a device in which the configuration or function for performing input and output is integrated into one, such as a touchscreen, etc.

[0103] According to one embodiment, the high-speed interface (950) manages bandwidth-intensive operations for the computing device (900), while the low-speed interface (960) may manage less bandwidth-intensive operations than the high-speed interface (950), but such function assignments are merely exemplary. According to one embodiment, the high-speed interface (950) may be coupled to high-speed expansion ports capable of accommodating memory (920), an input / output device (970), and various expansion cards (not shown). Additionally, the low-speed interface (960) may be coupled to a storage device (930) and a low-speed expansion port. Furthermore, the low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), may be coupled to one or more input / output devices (970), such as a keyboard, a pointing device, or a scanner, or to a networking device such as a router or a switch via a network adapter.

[0104] The computing device (900) may be implemented in a number of different forms. For example, the computing device (900) may be implemented as a standard server or as a group of such standard servers. Additionally or alternatively, the computing device (900) may be implemented as part of a rack server system or as a personal computer such as a laptop computer. In this case, components from the computing device (900) may be combined with other components within any mobile device (not shown). The computing device (900) may include one or more other computing devices or be configured to communicate with one or more other computing devices.

[0105] In the drawing, the input / output device (970) is depicted as not being included in the computing device (900), but is not limited thereto and may be configured as a single device with the computing device (900). Additionally, the high-speed interface (950) and / or low-speed interface (960) are depicted as elements configured separately from the processor (910), but are not limited thereto and the high-speed interface (950) and / or low-speed interface (960) may be configured to be included in the processor (910).

[0106] The methods and / or various embodiments described above may be realized in digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present invention may be executed by a data processing device, for example, one or more programmable processors and / or one or more computing devices, or implemented as a computer program stored on a computer-readable medium and / or on a computer-readable medium. The computer program described above may be written in any form of programming language, including a compiled language or an interpreted language, and may be distributed in any form, such as a standalone program, a module, or a subroutine. The computer program may be distributed through a single computing device, a plurality of computing devices connected through the same network, and / or a plurality of computing devices distributed to be connected through a plurality of different networks.

[0107] The above-described methods and / or various embodiments may be performed by one or more processors configured to execute one or more computer programs that process, store, and / or manage any functions, functions, etc. by operating based on input data or generating output data. For example, the methods and / or various embodiments of the present invention may be performed by special-purpose logic circuits such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and an apparatus and / or system for performing the methods and / or embodiments of the present invention may be implemented as a special-purpose logic circuit such as an FPGA or an ASIC.

[0108] One or more processors executing a computer program may include one or more processors of a general-purpose or special-purpose microprocessor and / or any type of digital computing device. The processor may receive instructions and / or data from each of read-only memory and random access memory, or receive instructions and / or data from read-only memory and random access memory. In the present invention, components of a computing device performing the methods and / or embodiments may include one or more processors for executing instructions and one or more memories for storing instructions and / or data.

[0109] According to one embodiment, a computing device may exchange data with one or more mass storage devices for storing data. For example, the computing device may receive and / or receive data from a magnetic disc or an optical disc, and may transfer data to a magnetic disc or an optical disc. A computer-readable medium suitable for storing instructions and / or data associated with a computer program may include, but is not limited to, any form of non-volatile memory including semiconductor memory devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable PROM), and flash memory devices. For example, the computer-readable medium may include magnetic discs such as internal hard disks or removable disks, photomagnetic discs, CD-ROMs, and DVD-ROMs.

[0110] To provide interaction with a user, the computing device may include, but is not limited to, a display device for providing or displaying information to the user (e.g., CRT (Cathode Ray Tube), LCD (Liquid Crystal Display), etc.) and a pointing device (e.g., keyboard, mouse, trackball, etc.) on which the user can provide input and / or commands, etc. on the computing device. That is, the computing device may further include any other type of device for providing interaction with the user. For example, the computing device may provide any form of sensory feedback to the user for interaction with the user, including visual feedback, auditory feedback and / or tactile feedback. In this regard, the user may provide input to the computing device through various gestures such as visual, vocal, and motion.

[0111] In the present invention, various embodiments may be implemented in a computing device comprising back-end components (e.g., data servers), middleware components (e.g., application servers), and / or front-end components. In this case, the components may be interconnected by any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network may be composed of a wired network such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication, a mobile communication network, a Wireless LAN (WLAN), a wireless network such as Wi-Fi, Bluetooth, and ZigBee, or a combination thereof. For example, the communication network may include a Local Area Network (LAN), a Wide Area Network (WAN), etc.

[0112] A computing device based on the exemplary embodiments described herein may be implemented using hardware and / or software configured to interact with a user, including a user device, a user interface (UI) device, a user terminal, or a client device. For example, the computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, the computing device may include, but is not limited to, Personal Digital Assistants (PDAs), tablet PCs, game consoles, wearable devices, Internet of Things (IoT) devices, Virtual Reality (VR) devices, Augmented Reality (AR) devices, etc. The computing device may further include other types of devices configured to interact with a user. Additionally, the computing device may include a portable communication device suitable for wireless communication over a network such as a mobile communication network (e.g., a mobile phone, a smartphone, a wireless cellular phone, etc.). A computing device may be configured to communicate wirelessly with a network server using wireless communication technologies and / or protocols such as radio frequency (RF), microwave frequency (MWF) and / or infrared frequency (IRF).

[0113] Various embodiments of the present invention, including specific structural and functional details, are exemplary. Accordingly, the embodiments of the present invention are not limited to those described above and may be implemented in various other forms. Furthermore, the terms used in the present invention are intended to describe some embodiments and are not to be interpreted as limiting the embodiments. For example, singular words and the above may be interpreted to include plural forms unless the context clearly indicates otherwise.

[0114] In this invention, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which such concepts belong. Furthermore, commonly used terms, such as those defined in advance, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology.

[0115] Although the present invention has been described in relation to some embodiments, various modifications and changes may be made without departing from the scope of the invention as understood by a person skilled in the art to which the invention pertains. Furthermore, such modifications and changes should be considered to fall within the scope of the claims appended to this specification.

Claims

1. A counter that counts the clock of an input clock and generates a counter output for dividing the input clock; An output clock generator that generates a clock edge according to the above counter output to generate an output clock divided from the input clock; A state machine that controls the operation of the counter by updating the counter expiration value of the counter according to the division value; and A division value control unit that controls the division value according to a clock row request of a power management unit and outputs it to the state machine; The above division value control unit Outputting a bypass divider value to the state machine in accordance with the above clock row request, such that the input clock is bypassed to the output clock and output. Clock divider.

2. In Claim 1, The above division value control unit A clock division controller that outputs a clock division value stored in a register to the state machine; and A clock row request controller that generates the bypass division value according to the clock row request and outputs it to the division value controller; The above division value controller Override the above bypass division value and output it to the state machine Clock divider.

3. In Claim 2, The above counter operates based on the counter expiration value corresponding to the above bypass division value, and The output clock generator above generates and outputs an output clock identical to the input clock according to the bypass division value. Clock divider.

4. In Claim 3, The above state machine is Updating the counter expiration value according to the above bypass division value so that the output clock stops at a low level according to the gating of the input clock performed after the above clock low request. Clock divider.

5. In Claim 3, The above state machine is Updating the counter expiration value according to the above bypass division value, thereby controlling the counter so that the output clock becomes a low level during the retention signal switching period. Clock divider.

6. In Claim 2, The above state machine is After the count expiration of the counter expiration value according to the clock division value above, the counter expiration value is updated according to the bypass division value above. Clock divider.

7. In Claim 1, The above output clock is input to a flip-flop, and the flip-flop is retained when it is guaranteed that the output clock is in a low-level state. Clock divider.

8. Clock divider of Claim 1; In the power domain, one or more flip-flops that receive an output clock, which is divided from the input clock by the clock divider and output, and operate according to the output clock; and A power management unit that outputs a clock row request to a division value control unit of the clock divider for retention; A semiconductor system including 9. In Claim 8, The above power management unit is Outputting a retention signal to the flip-flop when the output clock is guaranteed to be in a low level state in response to the above clock low request. Semiconductor system.

10. A computer-readable, non-transient recording medium having a computer program recorded thereon for executing a clock divider control method that controls the operation of a clock divider comprising a counter, an output clock generator, a state machine, and a divider value control unit, The above clock divider control method A step of counting the clock of the input clock by the above counter and generating a counter output for dividing the input clock; A step of generating a clock edge according to the counter output by the output clock generator to generate an output clock divided from the input clock; A step of controlling the operation of the counter by updating the counter expiration value of the counter according to the division value by the state machine above; and The method includes the step of controlling the division value to be output to the state machine according to a clock row request of the power management unit by the division value control unit; The step of controlling the above division value A step of outputting a bypass division value to the state machine such that, in accordance with the above clock row request, the input clock is bypassed to the output clock and output; A non-transient recording medium including 11. In Claim 10, The step of controlling the above division value A step of outputting the clock division value stored in the register to the state machine by the division value controller of the division value control unit; A step of generating the bypass division value according to the clock row request by the clock row request controller of the division value control unit and outputting it to the division value controller; and A step of overriding the bypass division value by the division value controller and outputting it to the state machine; A non-transient recording medium including 12. In Claim 11, The above clock divider control method A step in which the above counter operates by a counter expiration value corresponding to the bypass division value; and A step in which the output clock generator generates and outputs an output clock identical to the input clock according to the bypass division value; A non-transient recording medium that further includes 13. In Claim 12, The above clock divider control method A step in which the state machine updates the counter expiration value according to the bypass division value, and the output clock stops at a low level according to the gating of the input clock performed after the clock low request; A non-transient recording medium that further includes 14. In Claim 12, The above clock divider control method A step in which the state machine updates the counter expiration value according to the bypass division value, thereby controlling the counter such that the output clock becomes a low level during the retention signal switching interval; A non-transient recording medium that further includes 15. In Claim 11, The above clock divider control method A step in which the state machine updates the counter expiration value according to the bypass division value after the counting expiration of the counter expiration value according to the clock division value; A non-transient recording medium that further includes 16. In Claim 10, The above clock divider control method A step in which the output clock is input to a flip-flop, and the flip-flop is retained when it is guaranteed that the output clock is in a low-level state; A non-transient recording medium that further includes

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