Display device and electronic device

Abstract

This display device comprises: a substrate; pixel electrodes and a common electrode disposed on the substrate; and a light-emitting element disposed on the pixel electrodes and the common electrode, wherein the light-emitting element includes: a semiconductor stack having a structure in which light-emitting units emitting light of different colors are stacked; a protective film disposed on a side surface of the semiconductor stack; and at least one side electrode disposed on a side surface of the protective film and electrically connected to the semiconductor stack on the side surface of the semiconductor stack.

Description

Display devices and electronic devices

[0001] Embodiments of the present invention relate to display devices and electronic devices, and in particular to display devices and electronic devices including light-emitting elements.

[0002] As the information society develops, the demand for display devices and electronic devices capable of displaying images is increasing in various forms. Accordingly, various types of display devices and electronic devices containing pixels for displaying images are being developed. Display devices may be provided independently or integrated into electronic devices to be used as the display screen of the electronic device.

[0003] The problem that the present invention aims to solve is to provide a display device and an electronic device including a light-emitting element with improved light-emitting efficiency.

[0004] The problems of the present invention are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0005] A display device according to one embodiment may include a substrate; pixel electrodes and a common electrode disposed on the substrate; and a light-emitting element disposed on the pixel electrodes and the common electrode. The light-emitting element may include a semiconductor stack having a structure in which light-emitting units emitting light of different colors are stacked; a protective film disposed on a side of the semiconductor stack; and at least one side electrode disposed on a side of the protective film and electrically connected to the semiconductor stack on a side of the semiconductor stack.

[0006] In one embodiment, the light-emitting element may further include at least one bottom electrode disposed on the bottom surface of the semiconductor stack and electrically connected to the semiconductor stack.

[0007] In one embodiment, each of the light-emitting units comprises an active layer and a first conductivity semiconductor layer and a second conductivity semiconductor layer disposed on different sides of the active layer, and the at least one lower electrode may comprise a first electrode disposed on a portion of the lower surface of the semiconductor stack and electrically connected to the second conductivity semiconductor layers of the light-emitting units by penetrating a portion of the semiconductor stack.

[0008] In one embodiment, the first electrode may be bonded to the common electrode.

[0009] In one embodiment, the at least one lower electrode may further include a second electrode disposed on another part of the lower surface of the semiconductor stack and electrically connected to a first conductive semiconductor layer included in one of the light-emitting units.

[0010] In one embodiment, the second electrode may be bonded to one of the pixel electrodes.

[0011] In one embodiment, each of the light-emitting units comprises an active layer and a first conductivity semiconductor layer and a second conductivity semiconductor layer disposed on different sides of the active layer, and the at least one side electrode may include a third electrode disposed on a side portion of the semiconductor stack and penetrating the protective film to contact the side of the first conductivity semiconductor layer included in one of the light-emitting units.

[0012] In one embodiment, the third electrode may be placed on one of the pixel electrodes.

[0013] In one embodiment, the display device may further include a connecting electrode disposed on the third electrode and the one pixel electrode and electrically connecting the third electrode and the one pixel electrode.

[0014] In one embodiment, the at least one side electrode may include a transparent conductive material.

[0015] In one embodiment, the light-emitting units may include: a first light-emitting unit comprising a first active layer emitting light of a first color, and a first semiconductor layer and a second semiconductor layer disposed on different sides of the first active layer; a second light-emitting unit comprising a second active layer emitting light of a second color, and a third semiconductor layer and a fourth semiconductor layer disposed on different sides of the second active layer; and a third light-emitting unit comprising a third active layer emitting light of a third color, and a fifth semiconductor layer and a sixth semiconductor layer disposed on different sides of the third active layer.

[0016] In one embodiment, the pixel electrodes include a first pixel electrode electrically connected to the first light-emitting unit, a second pixel electrode electrically connected to the second light-emitting unit, and a third pixel electrode electrically connected to the third light-emitting unit, and the light-emitting element may include a first electrode electrically connected to the common electrode, a second electrode electrically connected to the first pixel electrode, a third electrode electrically connected to the second pixel electrode, and a fourth electrode electrically connected to the third pixel electrode.

[0017] In one embodiment, the at least one side electrode comprises the third electrode and the fourth electrode, wherein the third electrode is disposed on one side of the protective film that overlaps with the second pixel electrode and penetrates the protective film to contact the side of the third semiconductor layer, and the fourth electrode is disposed on one side of the protective film that overlaps with the third pixel electrode and penetrates the protective film to contact the side of the fifth semiconductor layer.

[0018] In one embodiment, the display device may further include: a first connecting electrode disposed on the third electrode and the second pixel electrode and electrically connecting the third electrode and the second pixel electrode; and a second connecting electrode disposed on the fourth electrode and the third pixel electrode and electrically connecting the fourth electrode and the third pixel electrode.

[0019] In one embodiment, the at least one side electrode further includes at least one of the first electrode and the second electrode, and the display device may further include at least one of a third connecting electrode electrically connecting the first electrode and the common electrode, and a fourth connecting electrode electrically connecting the second electrode and the first pixel electrode.

[0020] In one embodiment, the first electrode is disposed on one side of the protective film that overlaps with the common electrode and penetrates the protective film to contact the sides of the second semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer, respectively, and the second electrode is disposed on one side of the protective film that overlaps with the first pixel electrode and penetrates the protective film to contact the sides of the first semiconductor layer.

[0021] In one embodiment, the light-emitting element further includes at least one lower electrode disposed on the lower surface of the semiconductor stack, and the at least one lower electrode may include at least one of the first electrode and the second electrode.

[0022] In one embodiment, the first electrode is disposed on a portion of the lower surface of the semiconductor stack and on the upper surface of the common electrode and is bonded to the common electrode, and is electrically connected to the second semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer by penetrating a portion of the semiconductor stack, and the second electrode is disposed on another portion of the lower surface of the semiconductor stack and on the upper surface of the first pixel electrode and is bonded to the first pixel electrode and can be electrically connected to the first semiconductor layer.

[0023] An electronic device according to one embodiment may include a display module including a display panel; and a processor that transmits an image data signal to the display module. The display panel may include: a substrate; pixel electrodes and a common electrode disposed on the substrate; a light-emitting element comprising a semiconductor stack having a structure in which light-emitting units emitting different colors of light are stacked and disposed on the pixel electrodes and the common electrode, a protective film disposed on the side of the semiconductor stack, and a side electrode disposed on the side of the protective film and electrically connected to the semiconductor stack on the side of the semiconductor stack; and a connecting electrode disposed on one of the pixel electrodes and the common electrode and the side electrode, and electrically connecting the pixel electrodes, one of the common electrode and the side electrode.

[0024] In one embodiment, the light-emitting element further includes a bottom electrode disposed on the bottom surface of the semiconductor stack and electrically connected to the semiconductor stack, and the bottom electrode may be bonded to the other one of the pixel electrodes and the common electrode.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] The display device and electronic device according to the embodiments may include a light-emitting element. The light-emitting element according to the embodiments may include a semiconductor stack comprising light-emitting units that emit light of different colors, a protective film disposed on the side of the semiconductor stack, and a side electrode disposed on the side of the protective film and electrically connected to the semiconductor stack on the side of the semiconductor stack.

[0027] According to the embodiments, the loss of light-emitting area caused by electrodes connected to a semiconductor stack can be reduced or minimized, and the light-emitting efficiency of the light-emitting element can be improved. Accordingly, the light efficiency of a display device and an electronic device including a light-emitting element can be improved. In addition, according to the embodiments, as the light-emitting elements of the subpixels forming the pixel are integrated into a single light-emitting element, the size of the pixel can be easily reduced. Accordingly, high-resolution display devices and electronic devices can be easily manufactured.

[0028] In some embodiments, the light-emitting element may further include a bottom electrode disposed on the bottom surface of a semiconductor stack. According to the display device and electronic device including the light-emitting element according to the embodiments, the light-emitting element can be disposed more stably on the pixel electrode layer of the display device and electronic device. Accordingly, the reliability of the display device and electronic device can be improved.

[0029] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0030] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0031] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0032] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0033] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0034] FIG. 5 is a plan view showing the display area of ​​a display panel according to one embodiment.

[0035] FIGS. 6 to 10 are plan views showing a light-emitting element according to one embodiment.

[0036] FIG. 11 is a cross-sectional view showing the display area of ​​a display panel according to one embodiment.

[0037] FIG. 12 is a cross-sectional view showing the display area of ​​a display panel according to one embodiment.

[0038] Figure 13 is a cross-sectional view showing the A1 region of Figure 11 in detail.

[0039] FIG. 14 is a cross-sectional view showing the display area of ​​a display panel according to one embodiment.

[0040] FIG. 15 is a cross-sectional view showing the display area of ​​a display panel according to one embodiment.

[0041] FIG. 16 is a plan view showing the display area of ​​a display panel according to one embodiment.

[0042] FIG. 17 is a plan view showing the display area of ​​a display panel according to one embodiment.

[0043] FIGS. 18 to 21 are plan views showing a light-emitting element according to one embodiment.

[0044] FIG. 22 is a cross-sectional view showing the display area of ​​a display panel according to one embodiment.

[0045] FIG. 23 is a block diagram of an electronic device according to one embodiment.

[0046] FIG. 24 is a schematic diagram of an electronic device according to various embodiments.

[0047] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0048] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0049] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0050] Specific embodiments will be described below with reference to the attached drawings.

[0051] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0052] Referring to FIG. 1, the display device (1) may be a device capable of providing images such as video or still images. For example, the display device (1) may be a device capable of displaying images by including a display module including a display panel (100). As an example, the display device (1) may refer to any electronic device that provides a display screen on which an image can be displayed or includes a display module for displaying an image.

[0053] The display device (1) may be provided independently or may be included in an electronic device that provides a display screen to form the display screen of said electronic device. For example, the display device (1) may be included in various electronic devices such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs), and used as a display screen. Additionally, the display device (1) may be included in other electronic devices such as virtual reality (VR) devices or augmented reality (AR) devices and used to display images on said electronic devices. In one embodiment, the electronic device including the display device (1) may further include a display device housing in which the display device (1) is housed, and / or a case or cover for protecting said display device (1).

[0054] FIG. 1 illustrates a display module, which is a major component of a display device (1). In one embodiment, the display device (1) (or an electronic device including a display module) may include additional components. For example, the display device (1) may further include a housing or case, etc., for housing the display module of FIG. 1.

[0055] In one embodiment, the display device (1) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro light-emitting diode (for example, a micro LED or a nano LED). Hereinafter, as an example of a display device (1) to which the embodiments may be applied, a micro light-emitting display device including a micro light-emitting diode is disclosed. However, the embodiments are not limited thereto. For example, the type of light-emitting element included in the display device (1) is not limited to a micro light-emitting diode, and the display device (1) may include a light-emitting element of a different type and / or size.

[0056] The display device (1) may include a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply unit (500) (also referred to as a “power supply circuit”).

[0057] The display panel (100) may be formed as a rectangular plane having sides in a first direction (DR1) and sides in a second direction (DR2) that intersect the first direction (DR1). The corners where the sides in the first direction (DR1) and the sides in the second direction (DR2) meet may be formed in a rounded or angular shape. The plane shape of the display panel (100) is not limited to a rectangle and may be formed in other polygons, circles, or ellipses. The display panel (100) may be formed substantially flat, but is not limited thereto. The display panel (100) may be formed rigidly as a whole, or may be formed flexibly so that it can be bent, curved, folded, or rolled up in at least a part.

[0058] The display panel (100) may include a main area (MA) and a sub area (SBA).

[0059] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include pixels that display an image. Each pixel may include a plurality of subpixels. For example, each pixel may include a first subpixel emitting light of a first color, a second subpixel emitting light of a second color, and a third subpixel emitting light of a third color, but the embodiments of the present specification are not limited thereto.

[0060] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0061] The display driving circuit (250) can generate signals and voltages to drive the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0062] The circuit board (300) may be attached to one end of the sub-region (SBA). If the sub-region (SBA) is omitted, the circuit board (300) may be attached to one end of the main area (MA) (for example, one end of the non-display area (NDA)). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0063] The power supply unit (500) can generate multiple panel driving voltages according to the power voltage supplied from the outside. The power supply unit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner.

[0064] FIG. 2 is a layout diagram showing a display device according to one embodiment. FIG. 2 illustrates a sub-region (SBA) that is unfolded without being bent.

[0065] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0066] The main area (MA) may include a display area (DA) that displays images and a non-display area (NDA) that is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0067] A display area (DA) includes pixels (PX) for displaying an image, and each pixel (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a group of subpixels of the smallest unit capable of expressing a white gradation.

[0068] The non-display area (NDA) may be placed adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0069] The first scan driver (SDC1) and the second scan driver (SDC2) may be placed in a non-display area (NDA). The first scan driver (SDC1) may be placed on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be placed on the other side (e.g., the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driving circuit (250) through scan fan-out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driving circuit (250), generate scan signals according to the scan control signal, and output them to the scan lines.

[0070] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and may be positioned at the bottom of the display panel (100). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0071] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0072] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0073] The pad area (PA) is an area where pads (PDs) and a display driving circuit (250) are placed. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with the bending area (BA).

[0074] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) may be positioned below the connecting area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connecting area (CA) and the pad area (PA). One side of the bending area (BA) is in contact with the connecting area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0075] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0076] Referring to FIG. 3 in addition to FIG. 1 and 2, the display area (DA) may include pixels (PX), scan lines (SL), light emission control lines (EL), and data lines (DL).

[0077] Pixels (PX) may be arranged in a matrix form, etc. For example, pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2), but are not limited thereto. Scan lines (SL) and light emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1). In one embodiment, scan lines (SL) may include write scan lines (GWL), initialization scan lines (GIL), and bias scan lines (GBL).

[0078] Each of the plurality of subpixels (SPX) included in each of the pixels (PX) may be connected to any one of the write scan lines (GWL), any one of the initial scan lines (GIL), any one of the bias scan lines (GBL), any one of the light emission control lines (EL), and any one of the data lines (DL). In describing the embodiments, the term "connection" may include direct connection or indirect connection, and may include the meaning of electrical and / or physical connection. Each of the plurality of subpixels (SPX) may receive a data voltage of the data line (DL) according to the write scan signal of the write scan line (GWL), and may emit light from the light-emitting element according to the data voltage.

[0079] The non-display area (NDA) includes a first scan drive unit (SDC1), a second scan drive unit (SDC2), and a display drive circuit (250).

[0080] Each of the first scan drive unit (SDC1) and the second scan drive unit (SDC2) may include a write scan signal output unit (611), an initial scan signal output unit (612), a bias scan signal output unit (613), and a light emission control signal output unit (614). Each of the write scan signal output unit (611), the initial scan signal output unit (612), the bias scan signal output unit (613), and the light emission control signal output unit (614) may receive a scan timing control signal (SCS) from a timing control unit (251) (also referred to as a "timing control circuit").

[0081] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control unit (251) and output them sequentially to the write scan lines (GWL).

[0082] The initialization scan signal output unit (612) can generate initialization scan signals according to the scan timing control signal (SCS) and output them sequentially to the initialization scan lines (GIL).

[0083] The bias scan signal output unit (613) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (GBL).

[0084] The light emission control signal output unit (614) can generate light emission control signals according to the scan timing control signal (SCS) and output them sequentially to the light emission control lines (EL).

[0085] The display driving circuit (250) includes a timing control unit (251) and a data driving unit (252) (also referred to as the "data driving circuit").

[0086] The data driver (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control unit (251). The data driver (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SPX) are selected by the write scan signals of the first scan driver (SDC1) and the second scan driver (SDC2), and data voltages can be supplied to the selected subpixels (SPX).

[0087] The timing control unit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control unit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control unit (251) can output the digital video data (DATA) and the data timing control signal (DCS) to the data driving unit (252).

[0088] The power supply unit (500) can generate a plurality of panel driving voltages according to the power voltage supplied from the outside. For example, the power supply unit (500) can generate a first driving voltage (VDD), a second driving voltage (VSS), a third driving voltage (VINT), and a fourth driving voltage (VAINT) and supply them to the display panel (100).

[0089] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0090] Referring to FIG. 4 in addition to FIG. 3, a subpixel (SPX) according to one embodiment may be connected to scan lines (SL in FIG. 3), a light emission control line (EL), and a data line (DL). For example, the subpixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), a light emission control line (EL), and a data line (DL).

[0091] A subpixel (SPX) according to one embodiment may include a light-emitting element (LE) and a pixel circuit (PXC) electrically connected to the light-emitting element (LE). The pixel circuit (PXC) may include circuit elements for driving the light-emitting element (LE). In one embodiment, each pixel (PX) includes a first subpixel, a second subpixel, and a third subpixel, and the first subpixel, the second subpixel, and the third subpixel may each include a pixel circuit (PXC). In one embodiment, the equivalent circuit diagrams of the first subpixel, the second subpixel, and the third subpixel may be identical.

[0092] The pixel circuit (PXC) may include a driving transistor (DT), switching elements, and a capacitor (C1). In one embodiment, the switching elements may include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0093] The driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls a driving current (Ids) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0094] The light-emitting element (LE) is electrically connected to the driving transistor (DT) and can emit light with a brightness corresponding to the driving current (Ids). In one embodiment, the anode electrode of the light-emitting element (LE) is connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode of the light-emitting element (LE) can be connected to a second power line (VSL) to which a second driving voltage (VSS in FIG. 3) is applied. In one embodiment, the light-emitting element (LE) may be a micro light-emitting diode.

[0095] A capacitor (C1) is formed between the gate electrode of a driving transistor (DT) and a first power line (VDL) to which a first driving voltage (VDD in FIG. 3) is applied. The first driving voltage (VDD) may be a voltage level higher than the second driving voltage (VSS). One electrode of the capacitor (C1) may be connected to the gate electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0096] In one embodiment, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as p-type MOSFETs as shown in FIG. 4. The active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed of polysilicon.

[0097] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to the write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to the initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to the bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed as p-type MOSFETs, they may be turned on when a scan signal of gate low voltage and a light emission control signal are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the light emission line (EL), respectively. One electrode of the third transistor (ST3) may be connected to a first initialization voltage line (VIL) to which a third driving voltage (VINT in FIG. 3) is applied, and one electrode of the fourth transistor (ST4) may be connected to a second initialization voltage line (VAIL) to which a fourth driving voltage (VAINT in FIG. 3) is applied. The third driving voltage (VINT) and the fourth driving voltage (VAINT) may be different voltages. Additionally, the third driving voltage (VINT) and the fourth driving voltage (VAINT) may be voltages at a lower level than the first driving voltage (VDD) and voltages at a higher level than the second driving voltage (VSS).

[0098] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. In this case, the active layer of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductor. Additionally, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) may be turned on when a gate high voltage scan signal is applied, and the third transistor (ST3) may be turned on when an initialization scan signal of a gate high voltage is applied. In contrast, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, so they can be turned on when a scan signal of the gate low voltage and a light emission control signal are applied.

[0099] Alternatively, if the fourth transistor (ST4) is formed as an n-type MOSFET and the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) are formed as p-type MOSFETs, the active layer of the fourth transistor (ST4) may be formed as an oxide semiconductor, and the active layer of each of the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be formed as polysilicon. In addition, the fourth transistor (ST4) may be turned on when a scan signal of gate high voltage is applied, whereas the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be turned on when a scan signal of gate low voltage and a light emission control signal are applied.

[0100] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) is formed of an oxide semiconductor and can be turned on when a scan signal of gate high voltage and a light emission control signal are applied.

[0101] FIG. 5 is a plan view showing a display area of ​​a display panel according to one embodiment. For example, FIG. 5 shows a part of a display area (DA) including two pixels (PX) arranged sequentially in a second direction (DR2). FIG. 5 shows an embodiment of a layout structure of a light-emitting element layer including light-emitting elements (LE) of pixels (PX) among the elements included in a display panel (100 of FIG. 1 to 3). The display panel (100) may further include a backplane layer (for example, a thin-film transistor layer (TFTL) of FIG. 11 and 12) including circuit elements (for example, transistors and capacitor (C1) of FIG. 4) electrically connected to the light-emitting elements (LE) of pixels (PX).

[0102] Referring to FIG. 5, each pixel (PX) may include a plurality of pixel electrodes (PXE), at least one common electrode (CE), and at least one light-emitting element (LE). For example, each pixel (PX) may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), a third pixel electrode (PXE3), a common electrode (CE), and a light-emitting element (LE).

[0103] The first pixel electrode (PXE1) may be the pixel electrode (PXE) of the first subpixel (SPX1). The second pixel electrode (PXE2) may be the pixel electrode (PXE) of the second subpixel (SPX2). The third pixel electrode (PXE3) may be the pixel electrode (PXE) of the third subpixel (SPX3).

[0104] In one embodiment, a pixel (PX) may include a single common electrode (CE) shared by subpixels (SPX). For example, the common electrode (CE) may extend in a first direction (DR1) in each pixel row (or horizontal line) of a display area (DA), and the subpixels (SPX) of the pixels (PX) placed in that pixel row may share a single common electrode (CE). However, the embodiments are not limited thereto. For example, a pixel (PX) may include a plurality of common electrodes (CE) separated into individual patterns and placed in each subpixel (SPX).

[0105] Pixel electrodes (PXE) and a common electrode (CE) may be spaced apart from each other in each pixel area. For example, pixel electrodes (PXE) may be spaced apart from each other in a first direction (DR1), and a common electrode (CE) may be spaced apart from the pixel electrodes (PXE) in a second direction (DR2). The arrangement, location, and / or number of pixel electrodes (PXE) and a common electrode (CE) may vary depending on the embodiments.

[0106] In one embodiment, the first pixel electrode (PXE1) may be positioned between the second pixel electrode (PXE2) and the third pixel electrode (PXE3), but the arrangement order or position of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may vary. The first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may face different parts of the common electrode (CE) in the second direction (DR2).

[0107] The first pixel electrode (PXE1) can be electrically connected to a circuit element included in the first subpixel (SPX1). For example, the first pixel electrode (PXE1) can be electrically connected to at least one circuit element (for example, the fourth transistor (ST4) and the sixth transistor (ST6) of FIG. 4) included in the pixel circuit of the first subpixel (SPX1) (for example, the pixel circuit (PXC) of FIG. 4) through the first contact hole (CT1).

[0108] Additionally, the first pixel electrode (PXE1) may be electrically connected to a part of the light-emitting element (LE). For example, the first pixel electrode (PXE1) may be electrically connected to a first conductive semiconductor layer (for example, a p-type semiconductor layer of the first light-emitting unit (EMU1)) included in the first light-emitting unit (EMU1) of the light-emitting element (LE).

[0109] The second pixel electrode (PXE2) can be electrically connected to a circuit element included in the second subpixel (SPX2). For example, the second pixel electrode (PXE2) can be electrically connected to at least one circuit element included in the pixel circuit of the second subpixel (SPX2) (for example, the pixel circuit (PXC) of FIG. 4) through the second contact hole (CT2).

[0110] Additionally, the second pixel electrode (PXE2) may be electrically connected to a part of the light-emitting element (LE). For example, the second pixel electrode (PXE2) may be electrically connected to a first conductive semiconductor layer (for example, a p-type semiconductor layer of the second light-emitting unit (EMU2)) included in the second light-emitting unit (EMU2) of the light-emitting element (LE).

[0111] The third pixel electrode (PXE3) can be electrically connected to a circuit element included in the third subpixel (SPX3). For example, the third pixel electrode (PXE3) can be electrically connected to at least one circuit element included in the pixel circuit of the third subpixel (SPX3) (for example, the pixel circuit (PXC) of FIG. 4) through the third contact hole (CT3).

[0112] Additionally, the third pixel electrode (PXE3) may be electrically connected to a part of the light-emitting element (LE). For example, the third pixel electrode (PXE3) may be electrically connected to a first conductive semiconductor layer (for example, a p-type semiconductor layer of the third light-emitting unit (EMU3)) included in the third light-emitting unit (EMU3) of the light-emitting element (LE).

[0113] The common electrode (CE) may be electrically connected to a second power line (VSL in FIG. 4) to which a second driving voltage (VSS in FIG. 3) is applied, within the display area (DA) and / or in the non-display area (NDA in FIG. 1 to 3). For example, the common electrode (CE) may be electrically connected to a second power line (VSL) disposed within a thin-film transistor layer of the display panel (100) through a fourth contact hole (CT4). In one embodiment, the common electrode (CE) extends into a non-display area (NDA) and may also be electrically connected to the second power line (VSL) (for example, a part of the second power line (VSL) formed in the form of a power bus line in the non-display area (NDA)). In another embodiment, the fourth contact hole (CT4) may not be formed in the display area (DA). In this case, the common electrode (CE) can be electrically connected to the second power line (VSL) only in the non-display area (NDA).

[0114] Additionally, the common electrode (CE) may be electrically connected to a part of the light-emitting element (LE). For example, the common electrode (CE) may be electrically connected to second conductivity type semiconductor layers included in the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) of the light-emitting element (LE) (for example, the n-type semiconductor layer of each of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3)).

[0115] A light-emitting element (LE) may be placed on the pixel electrodes (PXE) and the common electrode (CE) of each pixel (PX). For example, the light-emitting element (LE) may be placed on a portion of each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), the third pixel electrode (PXE3), and the common electrode (CE). The light-emitting element (LE) may be electrically connected between each pixel electrode (PXE) and the common electrode (CE).

[0116] In one embodiment, the light-emitting element (LE) may comprise a plurality of light-emitting units (EMUs) that emit light of different colors and constitute the light-emitting element (LE) of each subpixel (SPX). For example, the light-emitting element (LE) of the first subpixel (SPX1), the light-emitting element (LE) of the second subpixel (SPX2), and the light-emitting element (LE) of the third subpixel (SPX3) may be integrated into a single light-emitting element (LE). In this case, the light-emitting element (LE) may include a first light-emitting unit (EMU1) that emits light of a first color (e.g., light in a red wavelength band) corresponding to the emission wavelength of a first subpixel (SPX1), a second light-emitting unit (EMU2) that emits light of a second color (e.g., light in a green wavelength band) corresponding to the emission wavelength of a second subpixel (SPX2), and a third light-emitting unit (EMU3) that emits light of a third color (e.g., light in a blue wavelength band) corresponding to the emission wavelength of a third subpixel (SPX3). For example, the light-emitting element (LE) may be a micro LED with a 1-chip structure in which a red light-emitting element emitting red light, a green light-emitting element emitting green light, and a blue light-emitting element emitting blue light are integrated into a single chip (e.g., an RGB 1-Chip Micro LED or a Single Chip RGB Micro LED).

[0117] The first light-emitting unit (EMU1) can be electrically connected between the first pixel electrode (PXE1) and the common electrode (CE). The first light-emitting unit (EMU1) can form a first color light-emitting element included in the first subpixel (SPX1), for example, a red light-emitting element.

[0118] The second light-emitting unit (EMU2) can be electrically connected between the second pixel electrode (PXE2) and the common electrode (CE). The second light-emitting unit (EMU2) can form a second color light-emitting element included in the second subpixel (SPX2), for example, a green light-emitting element.

[0119] The third light-emitting unit (EMU3) can be electrically connected between the third pixel electrode (PXE3) and the common electrode (CE). The third light-emitting unit (EMU3) can form a third color light-emitting element included in the third subpixel (SPX3), for example, a blue light-emitting element.

[0120] The first subpixel (SPX1) may include a first pixel electrode (PXE1), a light-emitting element (LE) (for example, a first color light-emitting element including a first light-emitting unit (EMU1)), and a light-emitting part including a common electrode (CE). In one embodiment, the first subpixel (SPX1) may further include a driving part electrically connected to the light-emitting part (for example, a pixel circuit (PXC) electrically connected to the first pixel electrode (PXE1)). By doing so, the timing of light emission or brightness of the first light-emitting unit (EMU1) can be controlled independently.

[0121] The second subpixel (SPX2) may include a light-emitting unit comprising a second pixel electrode (PXE2), a light-emitting element (LE) (for example, a second color light-emitting element including a second light-emitting unit (EMU2)), and a common electrode (CE). In one embodiment, the second subpixel (SPX2) may further include a driving unit electrically connected to the light-emitting unit (for example, a pixel circuit (PXC) electrically connected to the second pixel electrode (PXE2)). By doing so, the timing of light emission or brightness of the second light-emitting unit (EMU2) can be controlled independently.

[0122] The third subpixel (SPX3) may include a light-emitting part comprising a third pixel electrode (PXE3), a light-emitting element (LE) (for example, a third color light-emitting element including a third light-emitting unit (EMU3)), and a common electrode (CE). In one embodiment, the third subpixel (SPX3) may further include a driving part electrically connected to the light-emitting part (for example, a pixel circuit (PXC) electrically connected to the third pixel electrode (PXE3)). By doing so, the timing of light emission or brightness of the third light-emitting unit (EMU3) can be controlled independently.

[0123] The display area (DA) may include pixel columns, each containing pixels (PX) arranged in a second direction (DR2). In one embodiment, the first pixel electrodes (PXE1) of the pixels (PX) included in each pixel column may be arranged in the second direction (DR2). Additionally, the second pixel electrodes (PXE2) of the pixels (PX) included in each pixel column may be arranged in the second direction (DR2), and the third pixel electrodes (PXE3) of the pixels (PX) included in each pixel column may be arranged in the second direction (DR2). However, the arrangement of the pixel electrodes (PXE) may be varied according to the embodiments.

[0124] FIGS. 6 to 10 are plan views showing a light-emitting element according to one embodiment. For example, FIGS. 6 to 10 each show different sides of the light-emitting element (LE) shown in FIG. 5. For example, FIGS. 6 to 10 each show a bottom surface (BS), a top surface (TS), a first side surface (SS1), a second side surface (SS2), a third side surface (SS3), and a fourth side surface (SS4) of the light-emitting element (LE). FIGS. 5 to 10 show an embodiment in which the light-emitting element (LE) has a roughly rectangular shape, but the shape of the light-emitting element (LE) is not limited thereto.

[0125] Referring to FIG. 6 to FIG. 10 in addition to FIG. 5, a light-emitting element (LE) according to one embodiment may include a semiconductor stack (STC), a protective film (PVX) covering at least a portion of the semiconductor stack (STC), and electrodes electrically connected to the semiconductor stack (STC).

[0126] A semiconductor stack (STC) may include a plurality of light-emitting units (EMUs of FIG. 5) included in a light-emitting element (LE). Each light-emitting unit (EMU) may include an active layer and a first conductivity semiconductor layer and a second conductivity semiconductor layer disposed on different sides of the active layer. A detailed description of the detailed structure of the semiconductor stack (STC) will be provided later.

[0127] A protective film (PVX) may be placed on the side of a semiconductor stack (STC). The protective film (PVX) may cover the side of the light-emitting units (EMU) included in the semiconductor stack (STC). The protective film (PVX) may be further placed on a portion of the bottom surface of the semiconductor stack (STC). The protective film (PVX) may be exposed on the bottom surface (BS), the first side (SS1), the second side (SS2), the third side (SS3), and the fourth side (SS4) of the light-emitting element (LE). In one embodiment, an end of the protective film (PVX) may also be exposed on the top surface (TS) of the light-emitting element (LE). Although FIG. 7 illustrates an embodiment in which the protective film (PVX) does not cover the top surface of the semiconductor stack (STC) and the semiconductor stack (STC) is exposed on the top surface (TS) of the light-emitting element (LE), the embodiments are not limited thereto. For example, the protective layer (PVX) may cover the top surface of the semiconductor stack (STC).

[0128] A light-emitting element (LE) may include a plurality of electrodes electrically connected to a plurality of light-emitting units (EMU). For example, the light-emitting element (LE) may include a plurality of electrodes for driving a plurality of light-emitting units (EMU) independently and / or individually. As an example, the light-emitting element (LE) may include a second electrode (ET2), a third electrode (ET3), and a fourth electrode (ET4) for individually connecting the first conductivity type semiconductors of a first light-emitting unit (EMU1 in FIG. 5), a second light-emitting unit (EMU2 in FIG. 5), and a third light-emitting unit (EMU3 in FIG. 5) to a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3), respectively. Additionally, the light-emitting element (LE) may further include at least one first electrode (ET1) for electrically connecting the second conductivity type semiconductors of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) to a common electrode (CE). In the case of a display panel (100) with a common-cathode structure (for example, as in the embodiment of FIG. 4, the anode electrode of the light-emitting element (LE) is connected to a pixel circuit (PXC) and the cathode electrode of the light-emitting element (LE) is connected to a second power line (VSL) and the display panel (100) includes a sub-pixel (SPX)), the first conductivity type semiconductor layers of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may be p-type semiconductor layers, and the second conductivity type semiconductor layers of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may be n-type semiconductor layers. Conversely, in the case of a common-anode structure display panel (100), the first conductivity type semiconductor layers of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) are n-type semiconductor layers, and the second conductivity type semiconductor layers of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may be p-type semiconductor layers.

[0129] Accordingly, the light-emitting element (LE) may include more than the number of light-emitting units (EMU). For example, the light-emitting element (LE) including the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may include at least four electrodes. In one embodiment, when the second semiconductor layers of at least two of the light-emitting units (EMU) among the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) are electrically connected to a common electrode (CE) through different electrodes, the light-emitting element (LE) may include at least five electrodes. For example, when the second semiconductor layers of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) are electrically connected to a common electrode (CE) through different electrodes, the light-emitting element (LE) may include six electrodes.

[0130] In the embodiments of FIGS. 6 to 10, the light-emitting element (LE) may include a first electrode (ET1) that is commonly connected to the second semiconductor layers of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3), and a second electrode (ET2), a third electrode (ET3), and a fourth electrode (ET4) that are individually connected to the first semiconductor layers of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3). Accordingly, the number of electrodes included in the light-emitting element (LE) can be reduced or minimized, and the efficiency and reliability of the bonding process for placing the light-emitting element (LE) inside the display panel (100) can be increased.

[0131] In one embodiment, at least one electrode among the first electrode (ET1), second electrode (ET2), third electrode (ET3), and fourth electrode (ET4) of the light-emitting element (LE) may be formed as a side electrode (SIE). At least one other electrode among the first electrode (ET1), second electrode (ET2), third electrode (ET3), and fourth electrode (ET4) of the light-emitting element (LE) may be formed as a bottom electrode (BTE).

[0132] The bottom electrode (BTE) may be placed on the bottom surface (BS) of the light-emitting element (LE). For example, the bottom electrode (BTE) may be placed on the bottom surface of a semiconductor stack (STC) and / or a protective film (PVX). In one embodiment, the bottom electrode (BTE) may include a first electrode (ET1) and a second electrode (ET2) separated from each other.

[0133] The first electrode (ET1) is disposed on the common electrode (CE) and can be electrically connected to the common electrode (CE). In one embodiment, the first electrode (ET1) can be bonded to the upper surface of the common electrode (CE) through a bonding process or the like.

[0134] The first electrode (ET1) can be electrically connected to at least one semiconductor layer included in the semiconductor stack (STC). For example, the first electrode (ET1) may be placed on a portion of the lower surface of the semiconductor stack (STC) and penetrate at least a portion of the semiconductor stack (STC) to be electrically connected to the second conductivity type semiconductor layers of the light-emitting units (EMU) included in the semiconductor stack (STC).

[0135] The second electrode (ET2) is disposed on the first pixel electrode (PXE1) and can be electrically connected to the first pixel electrode (PXE1). In one embodiment, the second electrode (ET2) can be bonded to the upper surface of the first pixel electrode (PXE1) through a bonding process or the like.

[0136] The second electrode (ET2) may be electrically connected to at least one semiconductor layer included in the semiconductor stack (STC). For example, the second electrode (ET2) may be placed on a portion of the lower surface of the semiconductor stack (STC) and may be electrically connected to the first conductive semiconductor layer of the first light-emitting unit (EMU1) included in the semiconductor stack (STC). In one embodiment, the second electrode (ET2) may penetrate at least a portion of the semiconductor stack (STC) and be electrically connected to the first conductive semiconductor layer of the first light-emitting unit (EMU1). In another embodiment, when the first conductive semiconductor layer of the first light-emitting unit (EMU1) is placed at the bottom of the semiconductor stack (STC), the second electrode (ET2) may contact the lower surface of the first conductive semiconductor layer of the first light-emitting unit (EMU1) without penetrating the semiconductor stack (STC).

[0137] A side electrode (SIE) may be disposed on the side of a light-emitting element (LE). For example, the side electrode (SIE) may be disposed on the side of a protective film (PVX). In one embodiment, the side electrode (SIE) may include a third electrode (ET3) disposed on a third side (SS3) of the light-emitting element (LE), and a fourth electrode (ET4) disposed on a fourth side (SS4) of the light-emitting element (LE).

[0138] The third electrode (ET3) may be disposed on the second pixel electrode (PXE2) and electrically connected to the second pixel electrode (PXE2). The third electrode (ET3) may be electrically connected to at least one semiconductor layer included in the semiconductor stack (STC). For example, the third electrode (ET3) may be disposed on a portion of the side of the protective film (PVX) at the third side (SS3) of the light-emitting element (LE) and electrically connected to the first conductive semiconductor layer of the second light-emitting unit (EMU2) included in the semiconductor stack (STC). In one embodiment, the third electrode (ET3) may be electrically connected to the semiconductor stack (STC) on the side of the semiconductor stack (STC). For example, the third electrode (ET3) may penetrate the protective film (PVX) on the side of the semiconductor stack (STC) and come into contact with the side of the first conductive semiconductor layer of the second light-emitting unit (EMU2).

[0139] In one embodiment, the third electrode (ET3) may be placed only on a portion of the third side (SS3) of the light-emitting element (LE). For example, the third electrode (ET3) may be placed on a portion of the side of the protective film (PVX) that overlaps with the second pixel electrode (PXE2). Accordingly, the third electrode (ET3) may be placed only on a portion of the third side (SS3) of the light-emitting element (LE) at a position corresponding to the second pixel electrode (PXE2). For example, the third electrode (ET3) may be placed only on a portion of the third side (SS3) of the light-emitting element (LE) that is placed on the second pixel electrode (PXE2), and may not be placed on another portion of the third side (SS3) of the light-emitting element (LE) that is placed on the common electrode (CE). Additionally, the third electrode (ET3) may not be placed on the first side (SS1) and the second side (SS2) of the light-emitting element (LE). Accordingly, electrical stability between the other pixel electrodes (PXE) excluding the second pixel electrode (PXE2), the common electrode (CE), and the third electrode (ET3), and electrical stability between different electrodes of the light-emitting element (LE) can be secured. For example, by sufficiently securing the separation distance between the first pixel electrode (PXE1) and the third electrode (ET3), the separation distance between the common electrode (CE) and the third electrode (ET3), and the separation distance between the first, second, third, and fourth electrodes (ET1, ET2, ET3, ET4) of the light-emitting element (LE), short circuit defects can be effectively prevented.

[0140] The fourth electrode (ET4) may be disposed on the third pixel electrode (PXE3) and electrically connected to the third pixel electrode (PXE3). The fourth electrode (ET4) may be electrically connected to at least one semiconductor layer included in the semiconductor stack (STC). For example, the fourth electrode (ET4) may be disposed on a portion of the side of the protective film (PVX) at the fourth side (SS4) of the light-emitting element (LE) and electrically connected to the first conductivity type semiconductor layer of the third light-emitting unit (EMU3) included in the semiconductor stack (STC). In one embodiment, the fourth electrode (ET4) may be electrically connected to the semiconductor stack (STC) on the side of the semiconductor stack (STC). For example, the fourth electrode (ET4) may penetrate the protective film (PVX) on the side of the semiconductor stack (STC) and come into contact with the side of the first conductivity type semiconductor layer of the third light-emitting unit (EMU3).

[0141] In one embodiment, the fourth electrode (ET4) may be placed only on a portion of the fourth side (SS4) of the light-emitting element (LE). For example, the fourth electrode (ET4) may be placed on a portion of the side of the protective film (PVX) that overlaps with the third pixel electrode (PXE3). Accordingly, the fourth electrode (ET4) may be placed only on a portion of the fourth side (SS4) of the light-emitting element (LE) at a position corresponding to the third pixel electrode (PXE3). For example, the fourth electrode (ET4) may be placed only on a portion of the fourth side (SS4) of the light-emitting element (LE) that is placed on the third pixel electrode (PXE3), and may not be placed on another portion of the fourth side (SS4) of the light-emitting element (LE) that is placed on the common electrode (CE). Additionally, the fourth electrode (ET4) may not be placed on the first side (SS1) and the second side (SS2) of the light-emitting element (LE). Accordingly, electrical stability between the other pixel electrodes (PXE) excluding the third pixel electrode (PXE3), the common electrode (CE), and the fourth electrode (ET4), and electrical stability between different electrodes of the light-emitting element (LE) can be secured. For example, by sufficiently securing the separation distance between the first pixel electrode (PXE1) and the fourth electrode (ET4), the separation distance between the common electrode (CE) and the fourth electrode (ET4), and the separation distance between the first, second, third, and fourth electrodes (ET1, ET2, ET3, ET4) of the light-emitting element (LE), short circuit defects can be effectively prevented.

[0142] FIG. 11 is a cross-sectional view showing a display area of ​​a display panel according to one embodiment. FIG. 12 is a cross-sectional view showing a display area of ​​a display panel according to one embodiment. For example, FIG. 11 and FIG. 12 each show an example of a cross-section of a pixel (PX) corresponding to the X1-X1' line and the X2-X2' line of FIG. 5.

[0143] FIG. 13 is a cross-sectional view showing region A1 of FIG. 11 in detail. For example, FIG. 13 shows a cross-section of a light-emitting element (LE) according to one embodiment in detail.

[0144] Referring to FIGS. 11 to 13 in addition to FIGS. 5 to 10, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. When the substrate (SUB) is made of a polymer resin, it may be a stretchable flexible substrate. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0145] A barrier layer (BR) may be disposed on a substrate (SUB). The barrier layer (BR) is a film intended to protect the transistors of the thin-film transistor layer (TFTL) and the light-emitting elements (LE) disposed on the thin-film transistor layer (TFTL) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. The barrier layer (BR) may be composed of a plurality of alternately stacked inorganic films.

[0146] A thin-film transistor (TFT1) may be disposed on the barrier layer (BR). In one embodiment, the thin-film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) shown in FIG. 4. The thin-film transistor (TFT1) may include an active layer (ACT1) and a gate electrode (G1).

[0147] FIGS. 11 and 12 illustrate a schematic cross-section of a thin-film transistor (TFT1) included in each subpixel (SPX). In FIGS. 11 and 12, the thin-film transistor (TFT1) placed at a position corresponding to each subpixel (SPX) (for example, the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) of FIG. 5) may be one of the transistors included in each subpixel (SPX) (for example, the driving transistor (DT) of FIG. 3 and one of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6)).

[0148] An active layer (ACT1) of a thin-film transistor (TFT1) may be disposed on a barrier layer (BR). The active layer (ACT1) of the thin-film transistor (TFT1) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the active layer (ACT1) of the thin-film transistor (TFT1) may include an oxide semiconductor (for example, indium-gallium-zinc oxide (IGZO), indium-gallium-zinc-tin oxide (IGZTO), or indium-gallium-tin oxide (IGTO)).

[0149] The active layer (ACT1) may include a channel region (CHA1), a source region (S1), and a drain region (D1). The channel region (CHA1) may overlap with the gate electrode (G1) in the third direction (DR3). The source region (S1) may be positioned on one side of the channel region (CHA1), and the drain region (D1) may be positioned on the other side of the channel region (CHA1). At least a portion of the source region (S1) and the drain region (D1) may not overlap with the gate electrode (G1) in the third direction (DR3). The conductivity (e.g., carrier concentration) of the source region (S1) and the drain region (D1) may be higher than the conductivity of the channel region (CHA1).

[0150] A first gate insulating layer (131) can be disposed on the active layer (ACT1) of a thin-film transistor (TFT1).

[0151] A first gate metal layer may be disposed on the first gate insulating layer (131). The first gate metal layer may include a gate electrode (G1) of a thin-film transistor (TFT1) and a first capacitor electrode (CAE1). The gate electrode (G1) of the thin-film transistor (TFT1) may overlap with the active layer (ACT1) of the thin-film transistor (TFT1) in a third direction (DR3).

[0152] A second gate insulating layer (132) may be disposed on the gate electrode (G1) of the thin-film transistor (TFT1) and the first capacitor electrode (CAE1).

[0153] A second gate metal layer may be disposed on the second gate insulating layer (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap with the first capacitor electrode (CAE1) in the third direction (DR3). A capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating layer (132).

[0154] An interlayer insulating layer (141) may be disposed on the second capacitor electrode (CAE2).

[0155] A first data metal layer may be disposed on the interlayer insulating layer (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to the drain region (D1) of the active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating layer (131), the second gate insulating layer (132), and the interlayer insulating layer (141).

[0156] A first flattening layer (160) for flattening the step difference caused by the thin-film transistor (TFT1) may be disposed on the first source connection electrode (PCE1).

[0157] A second data metal layer may be disposed on the first flattening layer (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second source contact hole (PCT2) that penetrates the first flattening layer (160).

[0158] A second flattening layer (180) may be placed on the second source connection electrode (PCE2).

[0159] The barrier layer (BR), the first gate insulating layer (131), the second gate insulating layer (132), and the interlayer insulating layer (141) are made of an inorganic insulating material (for example, silicon nitride (SiN)). x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂ x ), or aluminum oxide (AlO x It can be formed with at least one inorganic insulating layer including (etc.). Each of the barrier layer (BR), the first gate insulating layer (131), the second gate insulating layer (132), and the interlayer insulating layer (141) can be formed in a single layer or multilayer structure.

[0160] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may include a conductive material (for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof). Each of the first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or a multilayer structure.

[0161] The first flattening layer (160) and the second flattening layer (180) may include at least one organic insulating layer comprising an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin). Each of the first flattening layer (160) and the second flattening layer (180) may be formed as a single layer or a multilayer structure.

[0162] A light-emitting element layer may be disposed on the second planarization layer (180). The light-emitting element layer may include pixel electrodes (PXE), a common electrode (CE), and a light-emitting element (LE) of each pixel (PX). The light-emitting element layer may further include a first organic layer (210), a barrier (BWL), a capping layer (CAP), and a third planarization layer (220) (or a second organic layer) disposed around the light-emitting element (LE). The light-emitting element layer may further include first and second connecting electrodes (BE1, BE2).

[0163] A pixel electrode layer and a partition (BWL), etc., may be disposed on the second planarization layer (180). A light-emitting element (LE) and first and second connecting electrodes (BE1, BE2) may be disposed on the pixel electrode layer. A first organic layer (210) may be disposed in the space between the light-emitting element (LE) and the partition (BWL). The first organic layer (210) and the partition (BWL) may surround the pixel electrode layer, the light-emitting element (LE), and the first and second connecting electrodes (BE1, BE2).

[0164] The pixel electrode layer may include pixel electrodes (PXE) for each of the pixels (PX) (for example, a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3)) and a common electrode (CE).

[0165] Each pixel electrode (PXE) may be electrically connected to a second source connection electrode (PCE2) of each subpixel (SPX) through a contact hole (e.g., a first contact hole (CT1), a second contact hole (CT2), or a third contact hole (CT3) of FIG. 5) penetrating the second planarization layer (180). Each pixel electrode (PXE) may be electrically connected to a thin film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2).

[0166] The pixel electrode layer may include a conductive material (for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof) and may be formed as a single layer or a multilayer. For example, each of the pixel electrodes (PXE) and the common electrode (CE) may be formed as a single layer or a multilayer conductive pattern including at least one conductive material. The pixel electrodes (PXE) and the common electrode (CE) may be formed simultaneously and, accordingly, may have the same conductive material and cross-sectional structure.

[0167] In one embodiment, each of the pixel electrodes (PXE) and the common electrode (CE) of the pixel electrode layer may include a reflective layer containing a metal with high reflectivity. Accordingly, the brightness and light efficiency of the pixel (PX) can be improved by reflecting downward light from the light-emitting element (LE).

[0168] A light-emitting element (LE) may be disposed on pixel electrodes (PXE) and a common electrode (CE). In one embodiment, the light-emitting element (LE) may include an inorganic material such as gallium nitride (GaN). In one embodiment, the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of the light-emitting element (LE) may each be several to several hundred μm. For example, the length of the first direction (DR1), the length of the second direction (DR2), and the length of the third direction (DR3) of the light-emitting element (LE) may each be 100 μm or less.

[0169] Light-emitting elements (LEs) can be formed by growing on a semiconductor substrate, such as a silicon substrate or a sapphire substrate. Light-emitting elements (LEs) can be transferred directly from the semiconductor substrate onto pixel electrodes (PXEs) and a common electrode (CE). Alternatively, light-emitting elements (LEs) can be transferred onto pixel electrodes (PXEs) and a common electrode (CE) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material, such as PDMS or silicon, as a transfer substrate.

[0170] The light-emitting element (LE) may include a semiconductor stack (STC), a protective film (PVX), a first electrode (ET1), a second electrode (ET2), a third electrode (ET3), and a fourth electrode (ET4). In one embodiment, the light-emitting element (LE) may further include a third insulating layer (INS3) and a fourth insulating layer (INS4) disposed on a portion of the first electrode (ET1). The fourth insulating layer (INS4) may be omitted.

[0171] A semiconductor stack (STC) may include a plurality of light-emitting units (EMUs) as illustrated in FIG. 13. For example, the semiconductor stack (STC) may include a first light-emitting unit (EMU1), a second light-emitting unit (EMU2), and a third light-emitting unit (EMU3). The first light-emitting unit (EMU1) may also be referred to as the "first stack" or "first light-emitting element." The second light-emitting unit (EMU2) may also be referred to as the "second stack" or "second light-emitting element." The third light-emitting unit (EMU3) may also be referred to as the "third stack" or "third light-emitting element."

[0172] The semiconductor stack (STC) may have a structure in which a first light-emitting unit (EMU1), a second light-emitting unit (EMU2), and a third light-emitting unit (EMU3) are stacked. For example, the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may overlap each other in a third direction (DR3).

[0173] In one embodiment, the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may be arranged sequentially in the third direction (DR3). However, the stacking order of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may vary depending on the embodiments.

[0174] Each of the plurality of light-emitting units (EMU) may include a first conductivity semiconductor layer (SEMA), an active layer (MQW) (also referred to as the "light-emitting layer"), and a second conductivity semiconductor layer (SEMB). The active layer (MQW) may be disposed between the first conductivity semiconductor layer (SEMA) and the second conductivity semiconductor layer (SEMB). In one embodiment, the thickness of the second conductivity semiconductor layer (SEMB) may be greater than the thickness of the first conductivity semiconductor layer (SEMA).

[0175] The first light-emitting unit (EMU1) may include a first semiconductor layer (SEM1A), a first active layer (MQW1) (also referred to as the "first light-emitting layer"), and a second semiconductor layer (SEM1B). The first semiconductor layer (SEM1A) may be a first conductivity type semiconductor layer (SEMA) (e.g., a p-type semiconductor layer), and the second semiconductor layer (SEM1B) may be a second conductivity type semiconductor layer (SEMB) (e.g., an n-type semiconductor layer). The first semiconductor layer (SEM1A) and the second semiconductor layer (SEM1B) may be disposed on different surfaces of the first active layer (MQW1). For example, the first semiconductor layer (SEM1A) may be disposed on the upper surface of the first active layer (MQW1), and the second semiconductor layer (SEM1B) may be disposed on the lower surface of the first active layer (MQW1).

[0176] The second light-emitting unit (EMU2) may include a third semiconductor layer (SEM2A), a second active layer (MQW2) (also referred to as the "second light-emitting layer"), and a fourth semiconductor layer (SEM2B). The third semiconductor layer (SEM2A) may be a first conductivity type semiconductor layer (SEMA) (e.g., a p-type semiconductor layer), and the fourth semiconductor layer (SEM2B) may be a second conductivity type semiconductor layer (SEMB) (e.g., an n-type semiconductor layer). The third semiconductor layer (SEM2A) and the fourth semiconductor layer (SEM2B) may be disposed on different sides of the second active layer (MQW2). For example, the third semiconductor layer (SEM2A) may be disposed on the upper surface of the second active layer (MQW2), and the fourth semiconductor layer (SEM2B) may be disposed on the lower surface of the second active layer (MQW2).

[0177] The third light-emitting unit (EMU3) may include a fifth semiconductor layer (SEM3A), a third active layer (MQW3) (also referred to as the "third light-emitting layer"), and a sixth semiconductor layer (SEM3B). The fifth semiconductor layer (SEM3A) may be a first conductivity type semiconductor layer (SEMA) (e.g., a p-type semiconductor layer), and the sixth semiconductor layer (SEM3B) may be a second conductivity type semiconductor layer (SEMB) (e.g., an n-type semiconductor layer). The fifth semiconductor layer (SEM3A) and the sixth semiconductor layer (SEM3B) may be disposed on different sides of the third active layer (MQW3). For example, the fifth semiconductor layer (SEM3A) may be disposed on the upper surface of the third active layer (MQW3), and the sixth semiconductor layer (SEM3B) may be disposed on the lower surface of the third active layer (MQW3).

[0178] Each of the first conductivity type semiconductor layers (SEMA) (e.g., the first semiconductor layer (SEM1A), the third semiconductor layer (SEM2A), and the fifth semiconductor layer (SEM3A)) may comprise a semiconductor material doped with the first conductivity type dopant. For example, each of the first conductivity type semiconductor layers (SEMA) may be a p-type semiconductor layer comprising gallium nitride (GaN) doped with a p-type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. In another embodiment, in the case of a common-anode structured display panel (100), each of the first conductivity type semiconductor layers (SEMA) may be an n-type semiconductor layer comprising gallium nitride (GaN) doped with an n-type dopant such as silicon (Si), germanium (Ge), tin (Sn), etc.

[0179] Each of the second conductivity semiconductor layers (SEMB) (e.g., the second semiconductor layer (SEM1B), the fourth semiconductor layer (SEM2B), and the sixth semiconductor layer (SEM3B)) may comprise a semiconductor material doped with a second conductivity dopant. For example, each of the second conductivity semiconductor layers (SEMB) may be an n-type semiconductor layer comprising gallium nitride (GaN) doped with an n-type dopant. In another embodiment, in the case of a common-anode structured display panel (100), each of the second conductivity semiconductor layers (SEMB) may be a p-type semiconductor layer comprising gallium nitride (GaN) doped with a p-type dopant.

[0180] Each of the active layers (MQW) (e.g., a first active layer (MQW1), a second active layer (MQW2), and a third active layer (MQW3)) may include the same semiconductor material as each of the first conductivity semiconductor layer (SEMA) and each of the second conductivity semiconductor layer (SEMB). For example, if the first conductivity semiconductor layers (SEMA) and the second conductivity semiconductor layers (SEMB) include gallium nitride (GaN), each of the active layers (MQW) may include gallium nitride (GaN). For example, the active layers (MQW) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The active layer (MQW) included in each light-emitting unit (EMU) can emit light by the recombination of electron-hole pairs that occurs according to an electric signal applied through each first conductivity type semiconductor layer (SEMA) and second conductivity type semiconductor layer (SEMB).

[0181] Each active layer (MQW) may be formed as a single or multiple quantum well structure. When each active layer (MQW) is formed as a multiple quantum well structure, the active layer (MQW) may include well layers and barrier layers that are alternately stacked. In one embodiment, each well layer may be formed of InGaN, and each barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, each active layer (MQW) may have a structure in which semiconductor materials with a large band gap energy and semiconductor materials with a small band gap energy are alternately stacked, or may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0182] The first active layer (MQW1), the second active layer (MQW2), and the third active layer (MQW3) can each emit light of a first color, light of a second color, and light of a third color, respectively. In one embodiment, when each active layer (MQW) includes indium gallium nitride (InGaN), the color of the light emitted from each light-emitting unit (EMU) may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer (MQW) shifts toward the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer shifts toward the blue wavelength band. For example, when the first active layer (MQW1), the second active layer (MQW2), and the third active layer (MQW3) each emit light in a red wavelength range (for example, red light with a central wavelength range of 610 nm to 650 nm), light in a green wavelength range (for example, green light with a central wavelength range of 510 nm to 550 nm), and light in a blue wavelength range (for example, blue light with a central wavelength range of 450 nm to 495 nm), the indium (In) content of the second active layer (MQW2) may be lower than the indium (In) content of the first active layer (MQW1) and higher than the indium (In) content of the third active layer (MQW3). For example, the indium (In) content of the first active layer (MQW1) may be approximately 30% to 45%, the indium (In) content of the second active layer (MQW2) may be approximately 20% to 30%, and the indium (In) content of the third active layer (MQW3) may be approximately 10% to 20%.

[0183] In one embodiment, the semiconductor stack (STC) may further include at least one intermediate layer disposed between light-emitting units (EMU). For example, the semiconductor stack (STC) may further include a first intermediate layer (IML1) disposed between a first light-emitting unit (EMU1) and a second light-emitting unit (EMU2), and a second intermediate layer (IML2) disposed between a second light-emitting unit (EMU2) and a third light-emitting unit (EMU3).

[0184] The first intermediate layer (IML1) and the second intermediate layer (IML2) may include functional layers for enhancing or improving the function (e.g., luminous efficiency) or electrical characteristics (e.g., reliability) of each of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3). For example, each of the first intermediate layer (IML1) and the second intermediate layer (IML2) may include at least one of a tunnel functional layer (or charge generation layer) for appropriately supplying or moving electrons and holes to adjacent light-emitting units (EMU), and a barrier layer (or insulating layer) for stable individual driving of adjacent light-emitting units (EMU).

[0185] In addition, the semiconductor stack (STC) may further include additional functional layers. For example, the semiconductor stack (STC) may further include an electron blocking layer, etc. For example, the semiconductor stack (STC) includes a plurality of active layers (MQW), and first conductivity semiconductor layers (SEMA) and second conductivity semiconductor layers (SEMB) disposed on different sides of each of the active layers (MQW), and may optionally further include at least one intermediate layer and / or functional layer.

[0186] A protective film (PVX) may be placed on the side of a semiconductor stack (STC). For example, the protective film (PVX) may wrap the sides of a first light-emitting unit (EMU1), a second light-emitting unit (EMU2), and a third light-emitting unit (EMU3). The protective film (PVX) may further wrap the sides of a first intermediate layer (IML1) and a second intermediate layer (IML2).

[0187] The protective film (PVX) may also be placed on a portion of the lower surface of the semiconductor stack (STC). For example, the protective film (PVX) may partially or entirely cover the lower surface of the second semiconductor layer (SEM1B) included in the first light-emitting unit (EMU1).

[0188] In one embodiment, the protective film (PVX) may also be disposed on a portion of the second electrode (ET2). For example, the protective film (PVX) may be disposed on the side of the second electrode (ET2) that penetrates the semiconductor stack (STC) to prevent the second semiconductor layer (SEM1B) and the first active layer (MQW1) included in the first light-emitting unit (EMU1) from coming into contact with the second electrode (ET2).

[0189] The protective layer (PVX) may include a material suitable for protecting the semiconductor stack (STC). For example, the protective layer (PVX) may be silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂ x ), or aluminum oxide (AlO x It can be formed into an inorganic film containing inorganic insulating materials such as ).

[0190] The first electrode (ET1) of the light-emitting element (LE) can be placed on the common electrode (CE). The second electrode (ET2), the third electrode (ET3), and the fourth electrode (ET4) of the light-emitting element (LE) can be placed on the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3), respectively.

[0191] In one embodiment, the first electrode (ET1) and the second electrode (ET2) of the light-emitting element (LE) may be bottom electrodes (BTE) disposed on the bottom surface (BS) of the light-emitting element (LE). The third electrode (ET3) and the fourth electrode (ET4) of the light-emitting element (LE) may be side electrodes (SIE) disposed on the sides of the light-emitting element (LE) (for example, the third side (SS3) and the fourth side (SS4)).

[0192] The first electrode (ET1) may be disposed on the common electrode (CE) and electrically connected to the common electrode (CE). For example, the lower surface of the first electrode (ET1) may come into contact with the upper surface of the common electrode (CE). However, the embodiments are not limited thereto. For example, an additional conductive layer (such as a conductive layer including a conductive ball or a bonding layer) may be disposed between the first electrode (ET1) and the common electrode (CE).

[0193] Additionally, the first electrode (ET1) can penetrate at least a portion of the semiconductor stack (STC) and be electrically connected to the second conductivity type semiconductor layers (SEMB) of the semiconductor stack (STC). For example, the first electrode (ET1) penetrates the first and second light-emitting units (EMU1, EMU2) and the first and second intermediate layers (IML1, IML2) of the semiconductor stack (STC), and can further penetrate the sixth semiconductor layer (SEM3B) of the third light-emitting unit (EMU3) by a certain thickness.

[0194] The first electrode (ET1) may contact the second conductive semiconductor layers (SEMB) included in the first and second light-emitting units (EMU1, EMU2), for example, the second semiconductor layer (SEM1B) and the fourth semiconductor layer (SEM2B), in the portion penetrating the first and second light-emitting units (EMU1, EMU2). Accordingly, the first electrode (ET1) may be electrically connected to the second semiconductor layer (SEM1B) and the fourth semiconductor layer (SEM2B).

[0195] A third insulating layer (INS3) may be disposed between the first conductive semiconductor layers (SEMA) and active layers (MQW) included in the first and second light-emitting units (EMU1, EMU2), for example, the first semiconductor layer (SEM1A), the first active layer (MQW1), the third semiconductor layer (SEM2A), and the second active layer (MQW2), and the first electrode (ET1). For example, in the portion where the first electrode (ET1) penetrates the semiconductor stack (STC), the third insulating layer (INS3) may cover the side of the first conductive semiconductor layers (SEMA) included in the first and second light-emitting units (EMU1, EMU2) and may further cover the side of the active layers (MQW) included in the first and second light-emitting units (EMU1, EMU2). Accordingly, the first electrode (ET1) may be insulated from the first semiconductor layer (SEM1A), the first active layer (MQW1), the third semiconductor layer (SEM2A), and the second active layer (MQW2). In one embodiment, a third insulating layer (INS3) may also be disposed between the first and second intermediate layers (IML1, IML2) and the first electrode (ET1), but is not limited thereto. The third insulating layer (INS3) may include an insulating material, for example, an inorganic insulating material. The third insulating layer (INS3) may include the same material as the protective film (PVX), but is not limited thereto.

[0196] The first electrode (ET1) may come into contact with the sixth semiconductor layer (SEM3B) at a portion that penetrates the sixth semiconductor layer (SEM3B) of the third light-emitting unit (EMU3). Accordingly, the first electrode (ET1) may be electrically connected to the sixth semiconductor layer (SEM3B). In one embodiment, the first electrode (ET1) may not penetrate the fifth semiconductor layer (SEM3A) and the third active layer (MQW3) of the third light-emitting unit (EMU3). For example, the upper surface of the first electrode (ET1) may be spaced apart from the third active layer (MQW3) and positioned below the third active layer (MQW3).

[0197] In one embodiment, a fourth insulating layer (INS4) may be disposed on the upper surface of the first electrode (ET1) surrounded by the third light-emitting unit (EMU3). Accordingly, the first electrode (ET1) and the third active layer (MQW3) can be more stably insulated. The fourth insulating layer (INS4) may include an insulating material, for example, an inorganic insulating material. The fourth insulating layer (INS4) may include the same material as the protective film (PVX), but is not limited thereto. The fourth insulating layer (INS4) may be omitted.

[0198] The second electrode (ET2) may be disposed on the first pixel electrode (PXE1) and electrically connected to the first pixel electrode (PXE1). For example, the lower surface of the second electrode (ET2) may come into contact with the upper surface of the first pixel electrode (PXE1). However, the embodiments are not limited thereto. For example, an additional conductive layer (such as a conductive layer including a conductive ball or a bonding layer) may be disposed between the second electrode (ET2) and the first pixel electrode (PXE1).

[0199] Additionally, the second electrode (ET2) may penetrate at least a portion of the first light-emitting unit (EMU1) and be electrically connected to the first semiconductor layer (SEM1A) included in the first light-emitting unit (EMU1). For example, the second electrode (ET2) may penetrate a portion of the first light-emitting unit (EMU1) and come into contact with the first semiconductor layer (SEM1A). A protective film (PVX) may be disposed between the first active layer (MQW1) and the second semiconductor layer (SEM1B) included in the first light-emitting unit (EMU1) and the second electrode (ET2). Accordingly, the second electrode (ET2) may be insulated from the first active layer (MQW1) and the second semiconductor layer (SEM1B).

[0200] The first electrode (ET1) and the second electrode (ET2) may be bonded to the common electrode (CE) and the first pixel electrode (PXE1), respectively, by a bonding method using heat and / or pressure (e.g., eutectic bonding) or a bonding method using a medium layer containing a conductive material (e.g., an anisotropic conductive film containing conductive balls). However, the bonding method or the bonding structure for connecting the first and second electrodes (ET1, ET2) and the light-emitting element (LE) may vary depending on the embodiments. The first electrode (ET1) and the second electrode (ET2) may include a conductive material suitable for each bonding method. For example, the first electrode (ET1) and the second electrode (ET2) may include a metal suitable for eutectic bonding, but are not limited thereto.

[0201] The third electrode (ET3) can be placed on the second pixel electrode (PXE2) and electrically connected to the second pixel electrode (PXE2). For example, the third electrode (ET3) can be electrically connected to the second pixel electrode (PXE2) through the first connecting electrode (BE1).

[0202] Additionally, the third electrode (ET3) can be electrically connected to the third semiconductor layer (SEM2A) included in the second light-emitting unit (EMU2) from the side of the semiconductor stack (STC). For example, the third electrode (ET3) can penetrate the protective film (PVX) at a position corresponding to the third semiconductor layer (SEM2A) and come into contact with the side of the third semiconductor layer (SEM2A).

[0203] The fourth electrode (ET4) can be placed on the third pixel electrode (PXE3) and electrically connected to the third pixel electrode (PXE3). For example, the fourth electrode (ET4) can be electrically connected to the third pixel electrode (PXE3) through the second connecting electrode (BE2).

[0204] Additionally, the fourth electrode (ET4) may be electrically connected to the fifth semiconductor layer (SEM3A) included in the third light-emitting unit (EMU3) from the side of the semiconductor stack (STC). For example, the fourth electrode (ET4) may penetrate the protective film (PVX) at a position corresponding to the fifth semiconductor layer (SEM3A) and contact the side of the fifth semiconductor layer (SEM3A). Alternatively, the fourth electrode (ET4) may be positioned on the upper edge of the protective film (PVX) and contact the side of the fifth semiconductor layer (SEM3A).

[0205] In one embodiment, the third electrode (ET3) and the fourth electrode (ET4) may include a transparent conductive material. For example, the third electrode (ET3) and the fourth electrode (ET4) may include a transparent conductive material that combines conductivity and light transparency. As an example, each of the third electrode (ET3) and the fourth electrode (ET4) may include a transparent conductive oxide (TCO) with excellent conductivity and transparency, such as indium tin oxide (ITO) or indium zinc oxide (IZO). When the third electrode (ET3) and the fourth electrode (ET4) are formed simultaneously, the third electrode (ET3) and the fourth electrode (ET4) may include the same transparent conductive material.

[0206] As the third electrode (ET3) and the fourth electrode (ET4) are each formed as transparent electrodes, the amount of light passing through the third electrode (ET3) and the fourth electrode (ET4) to reach the reflective film (RF) of the barrier (BWL) can be increased. Accordingly, the reflected light by the reflective film (RF) can be increased, thereby increasing the light emission rate of the pixel (PX). Accordingly, the brightness and light efficiency of the pixel (PX) can be improved.

[0207] The first connecting electrode (BE1) can be placed on the second pixel electrode (PXE2) and the third electrode (ET3) to electrically connect the second pixel electrode (PXE2) and the third electrode (ET3). For example, the first connecting electrode (BE1) can be electrically connected to the second pixel electrode (PXE2) and the third electrode (ET3) by being placed directly on a part of the second pixel electrode (PXE2) and the third electrode (ET3) and making contact with the second pixel electrode (PXE2) and the third electrode (ET3).

[0208] The second connecting electrode (BE2) can be placed on the third pixel electrode (PXE3) and the fourth electrode (ET4) to electrically connect the third pixel electrode (PXE3) and the fourth electrode (ET4). For example, the second connecting electrode (BE2) can be electrically connected to the third pixel electrode (PXE3) and the fourth electrode (ET4) by being placed directly on a part of the third pixel electrode (PXE3) and the fourth electrode (ET4) and making contact with the third pixel electrode (PXE3) and the fourth electrode (ET4).

[0209] Each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may include a conductive material. For example, each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0210] In one embodiment, the first connecting electrode (BE1) and the second connecting electrode (BE2) may include a transparent conductive material. In this case, the amount of light passing through the first connecting electrode (BE1) and the second connecting electrode (BE2) to reach the reflective film (RF) of the barrier (BWL) may be increased. Accordingly, the light reflected by the reflective film (RF) may be increased, thereby increasing the light emission rate of the pixel (PX).

[0211] In another embodiment, the first connecting electrode (BE1) and the second connecting electrode (BE2) may comprise a metal with high reflectivity (e.g., aluminum (Al)). Accordingly, light emitted from the light-emitting element (LE) that reaches the first connecting electrode (BE1) and the second connecting electrode (BE2) of the light-emitting element (LE) can be reflected from the first connecting electrode (BE1) and the second connecting electrode (BE2) and proceed toward the upper direction of the light-emitting element (LE). Accordingly, the amount of light emitted toward the upper side of the light-emitting element (LE) can be increased.

[0212] A barrier (BWL) may surround a light-emitting element (LE) at a position spaced apart from the light-emitting element (LE). The barrier (BWL) may define a light-transmitting area through which light emitted from the light-emitting element (LE) can pass, for example, a light-emitting area of ​​a pixel (PX). For example, the barrier (BWL) may be placed in a non-light-emitting area surrounding a light-emitting area to surround each light-emitting area, including the area where the light-emitting element (LE) is placed and its surroundings, and may be opened in correspondence with the light-emitting area.

[0213] In one embodiment, the barrier (BWL) may be formed to a height less than or equal to the height of the light-emitting element (LE). In this case, the light-emitting element (LE) can be more easily placed on the pixel electrodes (PXE) and the common electrode (CE). For example, there is an advantage that the light-emitting element (LE) is easy to transfer during the transfer process.

[0214] The bulkhead (BWL) may include a bank (BNK) defining the shape of the bulkhead (BWL) and a first insulating layer (INS1) covering the bank (BNK). In one embodiment, the bulkhead (BWL) may further include a reflective film (RF) disposed on the first insulating layer (INS1) and a second insulating layer (INS2) covering the reflective film (RF).

[0215] The bank (BNK) may include organic materials. For example, the bank (BNK) may be formed from an organic film containing organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0216] The first insulating layer (INS1) may include an inorganic material. For example, the first insulating layer (INS1) is silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂ x ), or aluminum oxide (AlO x It can be formed from inorganic materials such as ) etc.

[0217] A reflective film (RF) may be placed on the side of the bank (BNK). In one embodiment, the reflective film (RF) may also be placed on the top surface of the bank (BNK). For example, the reflective film (RF) may cover the entire bank (BNK).

[0218] The reflective film (RF) may face the side of the light-emitting element (LE). The fact that the reflective film (RF) faces the side of the light-emitting element (LE) includes cases where the reflective film (RF) faces horizontally at the same height as at least one part of the side of the light-emitting element (LE), as well as cases where the reflective film (RF) is positioned at a location and / or height where light emitted from the light-emitting element (LE) in a lateral direction can reach.

[0219] The reflective film (RF) may include a material with high light reflectivity, for example, a metal such as aluminum (Al). Alternatively, the reflective film (RF) may consist of inorganic films having different refractive indices arranged alternately (for example, silicon nitride (SiN). x), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂ x ), or aluminum oxide (AlO x It may also be formed as a dispersed Bragg reflector including )). By reflecting light traveling in the lateral direction of the light-emitting element (LE) by the reflective film (RF), the light emission rate of the pixel (PX) can be increased.

[0220] The second insulating layer (INS2) may include an inorganic material. As an example, the second insulating layer (INS2) may be, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂ x ), or aluminum oxide (AlO x It can be formed from inorganic materials such as ) etc.

[0221] The first organic layer (210) can be filled between the light-emitting element (LE) and the partition (BWL). For example, the first organic layer (210) can cover the side of the light-emitting element (LE) entirely or partially. In one embodiment, the first organic layer (210) is formed to a height that can cover the first connecting electrode (BE1) and the second connecting electrode (BE2), and may be formed to a height less than or equal to the height of the light-emitting element (LE), but is not limited thereto.

[0222] The first organic layer (210) may include an organic material. For example, the first organic layer (210) may be formed as an organic film including an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first organic layer (210) can mitigate the step difference caused by the light-emitting element (LE).

[0223] A capping layer (CAP) may be disposed on light-emitting elements (LE), a barrier (BWL), and a first organic layer (210). The capping layer (CAP) may comprise a material suitable for protecting the light-emitting elements (LE). For example, the capping layer (CAP) may be silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO₂ x ), or aluminum oxide (AlO x It can be formed from inorganic materials such as ) etc.

[0224] The third flattening layer (220) may be disposed on the capping layer (CAP). The third flattening layer (220) is intended to flatten the upper surface of the display panel (100) (or the upper surface of the light-emitting element layer included in the display panel (100)), and the upper surface of the third flattening layer (220) may be substantially flat. In one embodiment, the third flattening layer (220) is formed of an organic film containing an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, and thus may have a substantially flat surface. In another embodiment, the third flattening layer (220) may contain an inorganic material and may be formed of an inorganic film of sufficient thickness to have a substantially flat surface, or may be flattened through a flattening process such as a polishing process or an etching process.

[0225] FIG. 14 is a cross-sectional view showing a display area of ​​a display panel according to one embodiment. FIG. 15 is a cross-sectional view showing a display area of ​​a display panel according to one embodiment. For example, FIG. 14 and FIG. 15 each show an example of a cross-section of a pixel (PX) corresponding to the X1-X1' line and the X2-X2' line of FIG. 5.

[0226] Compared to FIGS. 11 and 12, FIGS. 14 and 15 show different embodiments of the internal structure of a light-emitting element (LE). In describing the embodiments of this specification, the same reference numerals are used for elements similar or identical to at least one embodiment described above, and redundant descriptions are omitted.

[0227] Referring to FIGS. 14 and 15 in addition to FIGS. 11 to 13, the light-emitting element (LE) may include a plurality of light-emitting units (EMU) each comprising first conductivity semiconductor layers (SEMA), each active layer (MQW), and each second conductivity semiconductor layer (SEMB), as in the embodiment of FIG. 13. However, in each light-emitting unit (EMU), the stacking order of the first conductivity semiconductor layer (SEMA) and the second conductivity semiconductor layer (SEMB) may differ. For example, unlike the embodiments of FIGS. 11 to 13, in the embodiments of FIGS. 14 and 15, a second conductivity semiconductor layer (SEMB) having a thickness greater than that of the first conductivity semiconductor layer (SEMA) may be disposed below each active layer (MQW), and the first conductivity semiconductor layer (SEMA) may be disposed above each active layer (MQW).

[0228] In the embodiments of FIGS. 14 and 15, a first conductivity type semiconductor layer (SEMA) of a first light-emitting unit (EMU1) (for example, the first semiconductor layer (SEM1A) of FIG. 3) is disposed at the bottom of the semiconductor stack (STC), and a second electrode (ET2) of a light-emitting element (LE) can directly contact the lower surface of the first conductivity type semiconductor layer (SEMA) of the first light-emitting unit (EMU1). In one embodiment, the second electrode (ET2) may not penetrate the semiconductor stack (STC). The third electrode (ET3) and the fourth electrode (ET4) of the light-emitting element (LE) can contact the side of the semiconductor stack (STC) at a position corresponding to the first conductivity type semiconductor layer (SEMA) of the second light-emitting unit (EMU2) and the third light-emitting unit (EMU3), respectively (for example, the third semiconductor layer (SEM2A) and the fifth semiconductor layer (SEM3A) of FIG. 3).

[0229] FIGS. 11 to 13 and FIGS. 14 and 15 disclose embodiments in which the stacking order of the first conductivity semiconductor layer (SEMA), the active layer (MQW), and the second conductivity semiconductor layer (SEMB) in each of the light-emitting units (EMU) is the same, but the embodiments are not limited thereto. The stacking order of the first conductivity semiconductor layer (SEMA), the active layer (MQW), and the second conductivity semiconductor layer (SEMB) included in the first light-emitting unit (EMU1) may differ from the stacking order of the first conductivity semiconductor layer (SEMA), the active layer (MQW), and the second conductivity semiconductor layer (SEMB) included in the second light-emitting unit (EMU2), and / or the stacking order of the first conductivity semiconductor layer (SEMA), the active layer (MQW), and the second conductivity semiconductor layer (SEMB) included in the third light-emitting unit (EMU3). In this case as well, the third electrode (ET3) and the fourth electrode (ET4) can contact the side of the semiconductor stack (STC) at a position corresponding to the first conductivity type semiconductor layer (SEMA) of the second light-emitting unit (EMU2) and the third light-emitting unit (EMU3), respectively.

[0230] FIG. 16 is a plan view showing a display area of ​​a display panel according to one embodiment. FIG. 17 is a plan view showing a display area of ​​a display panel according to one embodiment. For example, FIG. 16 and FIG. 17 show a portion of a display area (DA) including two pixels (PX) sequentially arranged in a second direction (DR2), and show embodiments different from the embodiment of FIG. 5 with respect to a light-emitting element (LE).

[0231] Referring to FIGS. 16 and 17, the light-emitting element (LE) may include side electrodes (SIE) disposed separately from each other on the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3). For example, the second electrode (ET2) of the light-emitting element (LE) may be formed as a side electrode (SIE) disposed on one side of the light-emitting element (LE) disposed on the first pixel electrode (PXE1).

[0232] The light-emitting element (LE) may include a bottom electrode (BTE) according to the embodiments of FIGS. 5 to 15, or may not include a bottom electrode (BTE).

[0233] In one embodiment, the light-emitting element (LE) includes side electrodes (SIE) disposed on each pixel electrode (PXE) as shown in FIG. 16, and may further include a first electrode (ET1) disclosed in the embodiments described above. For example, the light-emitting element (LE) may further include a first electrode (ET1) disposed on a portion of the lower surface (BS) of the light-emitting element (LE) and bonded between common electrodes (CE).

[0234] In one embodiment, the light-emitting element (LE) may further include a side electrode (SIE) disposed on a common electrode (CE). For example, as shown in FIG. 17, the first electrode (ET1) of the light-emitting element (LE) may be formed as a side electrode (SIE) disposed on one side of the light-emitting element (LE) disposed on the common electrode (CE). As an example, the light-emitting element (LE) may include a first electrode (ET1), a second electrode (ET2), a third electrode (ET3), and a fourth electrode (ET4) disposed on different sides and each electrically connected to a pixel electrode (PXE) or a common electrode (CE).

[0235] FIGS. 18 to 21 are plan views showing a light-emitting element according to one embodiment. For example, FIGS. 18 to 21 each show different sides of the light-emitting element (LE) shown in FIG. 17. For example, FIGS. 18 to 21 each show a bottom surface (BS), a top surface (TS), a first side surface (SS1), and a second side surface (SS2) of the light-emitting element (LE). The third side surface (SS3) and the fourth side surface (SS4) of the light-emitting element (LE) may be identical to the third side surface (SS3) and the fourth side surface (SS4) of the light-emitting element (LE) shown in FIGS. 9 and 10.

[0236] Compared to FIGS. 5 to 10, FIGS. 18 to 21 show an embodiment in which the first electrode (ET1), second electrode (ET2), third electrode (ET3), and fourth electrode (ET4) of the light-emitting element (LE) are all formed as side electrodes (SIE).

[0237] FIG. 22 is a cross-sectional view showing a display area of ​​a display panel according to one embodiment. For example, FIG. 22 shows one embodiment of a cross-section of a pixel (PX) corresponding to the X3-X3' line of FIG. 17.

[0238] Referring to FIG. 18 through FIG. 22 in addition to FIG. 17, a light-emitting element (LE) according to one embodiment may include a first electrode (ET1) disposed on a first side (SS1), a second electrode (ET2) disposed on a second side (SS2), a third electrode (ET3) disposed on a third side (SS3), and a fourth electrode (ET4) disposed on a fourth side (SS4). For example, the first electrode (ET1), the second electrode (ET2), the third electrode (ET3), and the fourth electrode (ET4) of the light-emitting element (LE) may be formed as side electrodes (SIE) disposed separately from each other on different sides of the light-emitting element (LE).

[0239] As in the embodiments described above, the light-emitting element (LE) may include a semiconductor stack (STC) comprising a first light-emitting unit (EMU1), a second light-emitting unit (EMU2), and a third light-emitting unit (EMU3). Each of the first light-emitting unit (EMU1), the second light-emitting unit (EMU2), and the third light-emitting unit (EMU3) may include a first conductivity semiconductor layer (SEMA), an active layer (MQW), and a second conductivity semiconductor layer (SEMB).

[0240] A display panel (100) according to one embodiment may further include a third connecting electrode (BE3) and a fourth connecting electrode (BE4) that electrically connect the first electrode (ET1) and the second electrode (ET2) of the light-emitting element (LE) to the common electrode (CE) and the first pixel electrode (PXE1), respectively. The third electrode (ET3) and the fourth electrode (ET4) of the light-emitting element (LE) may be electrically connected to the second pixel electrode (PXE2) and the third pixel electrode (PXE3), respectively, by the first connecting electrode (BE1) and the second connecting electrode (BE2), as in the embodiments of FIGS. 5 to 15.

[0241] A first electrode (ET1) of a light-emitting element (LE) is disposed on one side of a protective film (PVX) that overlaps with a common electrode (CE) and can be electrically connected to at least one semiconductor layer included in the semiconductor stack (STC) on the side of the semiconductor stack (STC). For example, the first electrode (ET1) of the light-emitting element (LE) can penetrate the protective film (PVX) and contact each side of a second conductive semiconductor layer (SEMB) included in the light-emitting units (EMU) of the semiconductor stack (STC).

[0242] The second electrode (ET2) of the light-emitting element (LE) is disposed on one side of a protective film (PVX) that overlaps with the first pixel electrode (PXE1) and can be electrically connected to at least one semiconductor layer included in the semiconductor stack (STC) on the side of the semiconductor stack (STC). For example, the second electrode (ET2) of the light-emitting element (LE) can penetrate the protective film (PVX) and contact the side of a first conductive semiconductor layer (SEMA) included in the first light-emitting unit (EMU1) of the semiconductor stack (STC).

[0243] The third connecting electrode (BE3) can be placed on the common electrode (CE) and the first electrode (ET1) to electrically connect the common electrode (CE) and the first electrode (ET1). For example, the third connecting electrode (BE3) can be electrically connected to the common electrode (CE) and the first electrode (ET1) by being placed directly on a part of the common electrode (CE) and the first electrode (ET1) and coming into contact with the common electrode (CE) and the first electrode (ET1).

[0244] The fourth connecting electrode (BE4) can be placed on the first pixel electrode (PXE1) and the second electrode (ET2) to electrically connect the first pixel electrode (PXE1) and the second electrode (ET2). For example, the fourth connecting electrode (BE4) can be electrically connected to the first pixel electrode (PXE1) and the second electrode (ET2) by being placed directly on a part of the first pixel electrode (PXE1) and the second electrode (ET2) and coming into contact with the first pixel electrode (PXE1) and the second electrode (ET2).

[0245] Each of the third connecting electrode (BE3) and the fourth connecting electrode (BE4) may include a conductive material. For example, each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0246] In one embodiment, the third connecting electrode (BE3) and the fourth connecting electrode (BE4) may include a transparent conductive material, which was previously exemplified as the material of the first connecting electrode (BE1) and the second connecting electrode (BE2), or a metal with high reflectivity. For example, the first connecting electrode (BE1), the second connecting electrode (BE2), the third connecting electrode (BE3), and the fourth connecting electrode (BE4) may be formed simultaneously using the same conductive material.

[0247] A display panel (100) according to one embodiment may further include an adhesive layer (230) disposed below a light-emitting element (LE). The adhesive layer (230) is disposed between the pixel electrode layer and the light-emitting element (LE) and may cover a portion of each of the pixel electrodes (PXE) and the common electrode (CE). The adhesive layer (230) may not cover another portion of each of the pixel electrodes (PXE) and the common electrode (CE).

[0248] The adhesive layer (230) serves to temporarily fix or adhere the light-emitting element (LE) to prevent the light-emitting element (LE) from tilting or falling over during the process of transferring the light-emitting element (LE) to the display panel (100). For example, the adhesive layer (230) may be a film for temporarily adhering the light-emitting element (LE) onto pixel electrodes (PXE) and a common electrode (CE). To facilitate temporary adhesion, the thickness of the adhesive layer (230) may be greater than the thickness of each of the pixel electrodes (PXE) and the common electrode (CE).

[0249] Although FIG. 22 illustrates a structure in which the adhesive layer (230) is placed only in a part of each pixel area, the embodiments are not limited thereto. For example, according to another embodiment, the adhesive layer (230) is formed over the entire display area (DA), but may be locally removed in a portion corresponding to the connection holes for connecting the first connecting electrode (BE1), the second connecting electrode (BE2), the third connecting electrode (BE3), and the fourth connecting electrode (BE4) to the second pixel electrode (PXE2), the third pixel electrode (PXE3), the common electrode (CE), and the first pixel electrode (PXE1), respectively.

[0250] The adhesive layer (230) may include an organic insulating material. For example, the adhesive layer (230) may be formed of a photosensitive organic film including a photoresist. Alternatively, the adhesive layer (230) may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. A light-emitting element (LE) may be placed on the adhesive layer (230).

[0251] FIGS. 17 to 22 disclose an embodiment in which the light-emitting element (LE) does not include the bottom electrode (BTE) described in the embodiments of FIGS. 5 to 15, but the embodiments are not limited thereto. Additionally, each of the embodiments described in FIGS. 5 to 22 may be carried out alone or combined with at least one other embodiment.

[0252] For example, as in the embodiments of FIGS. 17 to 22, each of the first conductivity semiconductor layers (SEMA) and the second conductivity semiconductor layers (SEMB) included in the semiconductor stack (STC) of the light-emitting element (LE) may be electrically connected to each pixel electrode (PXE) or common electrode (CE) through a side electrode (SIE) that is electrically connected to the semiconductor stack (STC) from the side of the semiconductor stack (STC). In addition, at least one of the first conductivity semiconductor layers (SEMA) and the second conductivity semiconductor layers (SEMB) included in the semiconductor stack (STC) of the light-emitting element (LE) may also be electrically connected to each pixel electrode (PXE) or common electrode (CE) through a bottom electrode (BTE) disposed on the bottom surface of the semiconductor stack (STC), as in the embodiments of FIGS. 5 to 15. For example, the first electrode (ET1) of the light-emitting element (LE) may be formed as a multi-electrode including a bottom electrode (BTE) disposed on the bottom surface of the light-emitting element (LE) and penetrating the semiconductor stack (STC), and a side electrode (SIE) disposed on the side of the light-emitting element (LE) and penetrating the protective film (PVX) to contact the side of the semiconductor stack (STC).

[0253] As described above, the light-emitting element (LE) according to the embodiments may include a semiconductor stack (STC) comprising a plurality of light-emitting units (EMU) that emit light of different colors, a protective film (PVX) disposed on the side of the semiconductor stack (STC), and at least one side electrode (SIE) disposed on the side of the protective film (PVX) and electrically connected to a part of the semiconductor stack (STC) on the side of the semiconductor stack (STC). According to the embodiments, in a light-emitting element (LE) with a one-chip structure, the number of electrodes penetrating the semiconductor stack (STC) can be reduced or minimized, and the loss of the light-emitting area of ​​the semiconductor stack (STC) (or the volume loss of at least one active layer (MQW) included in the semiconductor stack (STC)) can be reduced or prevented. Accordingly, the light-emitting efficiency of the light-emitting element (LE) can be improved.

[0254] Additionally, the light-emitting element (LE) according to the embodiments may include a reduced or minimized number of electrodes. According to the embodiments, the light-emitting element (LE) can be more easily placed and / or bonded inside the display device (1) or electronic device (10) (for example, on the thin-film transistor layer (TFTL) and / or pixel electrode layer of the display panel (100). Accordingly, the efficiency of the bonding process for placing the light-emitting element (LE) in each pixel (PX) can be increased. In addition, a repair process can be more easily performed even if a bonding defect occurs in the light-emitting element (LE).

[0255] A display device (1) according to the embodiments may include the light-emitting element (LE). According to the embodiments, the size of the pixel (PX) can be easily reduced by integrating the light-emitting elements (LE) of the subpixels (SPX) into a single light-emitting element (LE), and the light-emitting efficiency of the pixel (PX) can also be improved by improving the light-emitting efficiency of the light-emitting element (LE). Accordingly, a high-resolution display device (1) can be easily manufactured, and the light efficiency of the display device can be improved.

[0256] In some embodiments, the light-emitting element (LE) may further include a bottom electrode (BTE) disposed on the bottom surface (BS) of the semiconductor stack (STC) and electrically connected to the bottom surface (BS) of the semiconductor stack (STC) and / or another part of the semiconductor stack (STC) internally. According to the light-emitting element (LE) and the display device (1) including the same, the light-emitting element (LE) can be disposed more stably on the pixel electrode layer of the display device (1). Accordingly, the reliability of the display device (1) can be improved.

[0257] A display device (1) according to at least one of the embodiments described above may be applied to various electronic devices. An electronic device according to one embodiment may include the display device (1) described above (or a display module including a display panel (100) according to at least one embodiment), and may further include a module or device having additional functions other than the display device (1).

[0258] FIG. 23 is a block diagram of an electronic device according to one embodiment. Referring to FIG. 23, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0259] The electronic device (10) can output various information in the form of an image through the display module (11). For example, when the processor (12) executes an application stored in memory (13), the image information provided by the application can be provided to the user through the display module (11).

[0260] The display module (11) may include a display panel (100) for displaying an image. For example, the display module (11) may include a display panel (100) according to at least one of the embodiments described above.

[0261] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0262] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). For example, the memory (13) may store image data signals and / or input control signals.

[0263] The processor (12) can control the display module (11) using information stored in the memory (13). The processor (12) can transmit video data signals and / or input control signals stored in the memory (13) to the display module (11). For example, when the processor (12) executes an application stored in the memory (13), video data signals and / or input control signals are transmitted to the display module (11), and the display module (11) can process the received signals and output video information through a display screen.

[0264] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0265] At least one of each component of the electronic device (10) described above may be included in the display device (1) according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device (1), while others may be provided separately from the display device (1). For example, the display device (1) may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device (1).

[0266] FIG. 24 is a schematic diagram of an electronic device according to various embodiments.

[0267] Referring to FIG. 24, various electronic devices (10 of FIG. 23) to which a display device (1) according to embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0268] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

1. Substrate; Pixel electrodes and a common electrode disposed on the substrate; and It includes a light-emitting element disposed on the pixel electrodes and the common electrode, The above light-emitting element is, A semiconductor stack having a structure in which light-emitting units emitting light of different colors are stacked; A protective film disposed on the side of the semiconductor stack; and A display device comprising at least one side electrode disposed on the side of the protective film and electrically connected to the semiconductor stack on the side of the semiconductor stack.

2. In Paragraph 1, A display device comprising at least one lower electrode disposed on the lower surface of the semiconductor stack and electrically connected to the semiconductor stack.

3. In Paragraph 2, Each of the above-mentioned light-emitting units comprises an active layer and a first conductivity type semiconductor layer and a second conductivity type semiconductor layer disposed on different sides of the active layer, and A display device comprising at least one lower electrode, wherein the lower electrode comprises a first electrode disposed on a portion of the lower surface of the semiconductor stack and electrically connected to the second conductivity type semiconductor layers of the light-emitting units by penetrating a portion of the semiconductor stack.

4. In Paragraph 3, The first electrode is a display device that is bonded to the common electrode.

5. In Paragraph 3, A display device comprising at least one lower electrode, further comprising a second electrode disposed on another part of the lower surface of the semiconductor stack and electrically connected to a first conductive semiconductor layer included in one of the light-emitting units.

6. In Paragraph 5, A display device in which the second electrode is bonded to one of the pixel electrodes.

7. In Paragraph 1, Each of the above-mentioned light-emitting units comprises an active layer and a first conductivity type semiconductor layer and a second conductivity type semiconductor layer disposed on different sides of the active layer, and A display device comprising at least one side electrode, wherein the side electrode comprises a third electrode disposed on a side portion of the semiconductor stack and penetrating the protective film to contact the side of a first conductive semiconductor layer included in one of the light-emitting units.

8. In Paragraph 7, The third electrode is a display device disposed on one of the pixel electrodes.

9. In Paragraph 8, A display device further comprising a connecting electrode disposed on the third electrode and the one pixel electrode, and electrically connecting the third electrode and the one pixel electrode.

10. In Paragraph 1, The above-mentioned at least one side electrode comprises a transparent conductive material, a display device.

11. In Paragraph 1, The above-mentioned light-emitting units are, A first light-emitting unit comprising a first active layer emitting light of a first color, and a first semiconductor layer and a second semiconductor layer disposed on different sides of the first active layer; A second light-emitting unit comprising a second active layer emitting light of a second color, and a third semiconductor layer and a fourth semiconductor layer disposed on different sides of the second active layer; and A display device comprising a third light-emitting unit including a third active layer emitting light of a third color, and a fifth semiconductor layer and a sixth semiconductor layer disposed on different sides of the third active layer.

12. In Paragraph 11, The pixel electrodes include a first pixel electrode electrically connected to the first light-emitting unit, a second pixel electrode electrically connected to the second light-emitting unit, and a third pixel electrode electrically connected to the third light-emitting unit. The light-emitting element comprises a first electrode electrically connected to the common electrode, a second electrode electrically connected to the first pixel electrode, a third electrode electrically connected to the second pixel electrode, and a fourth electrode electrically connected to the third pixel electrode, forming a display device.

13. In Paragraph 12, The above at least one side electrode includes the third electrode and the fourth electrode, and The third electrode is disposed on one side of the protective film that overlaps with the second pixel electrode, penetrates the protective film, and contacts the side of the third semiconductor layer. A display device wherein the fourth electrode is disposed on one side of the protective film that overlaps with the third pixel electrode, and penetrates the protective film to contact the side of the fifth semiconductor layer.

14. In Paragraph 13, A first connecting electrode disposed on the third electrode and the second pixel electrode and electrically connecting the third electrode and the second pixel electrode; and A display device further comprising a second connecting electrode disposed on the fourth electrode and the third pixel electrode, and electrically connecting the fourth electrode and the third pixel electrode.

15. In Paragraph 13, The above at least one side electrode further includes at least one of the first electrode and the second electrode, and A display device further comprising at least one of a third connecting electrode electrically connecting the first electrode and the common electrode, and a fourth connecting electrode electrically connecting the second electrode and the first pixel electrode.

16. In Paragraph 15, The first electrode is disposed on one side of the protective film that overlaps with the common electrode, penetrates the protective film, and contacts the sides of the second semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer, respectively. A display device wherein the second electrode is disposed on one side of the protective film that overlaps with the first pixel electrode, and penetrates the protective film to contact the side of the first semiconductor layer.

17. In Paragraph 12, The light-emitting element further comprises at least one lower electrode disposed on the lower surface of the semiconductor stack, and A display device wherein the above-mentioned at least one lower electrode comprises at least one of the first electrode and the second electrode.

18. In Paragraph 17, The first electrode is disposed on a portion of the lower surface of the semiconductor stack and on the upper surface of the common electrode and is bonded to the common electrode, and penetrates a portion of the semiconductor stack and is electrically connected to the second semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer. A display device wherein the second electrode is disposed on the upper surface of the first pixel electrode and on another part of the lower surface of the semiconductor stack and is bonded to the first pixel electrode and is electrically connected to the first semiconductor layer.

19. A display module including a display panel; and It includes a processor that transmits an image data signal to the above-mentioned display module, The above display panel is, Substrate; Pixel electrodes and a common electrode disposed on the above substrate; A light-emitting element comprising: a semiconductor stack having a structure in which light-emitting units emitting different colors of light are stacked and disposed on the pixel electrodes and the common electrode, a protective film disposed on the side of the semiconductor stack, and a side electrode disposed on the side of the protective film and electrically connected to the semiconductor stack from the side of the semiconductor stack; and An electronic device comprising a connecting electrode disposed on the pixel electrodes, one of the common electrodes, and the side electrode, and electrically connecting the pixel electrodes, one of the common electrodes, and the side electrode.

20. In Paragraph 19, The light-emitting element further includes a bottom electrode disposed on the bottom surface of the semiconductor stack and electrically connected to the semiconductor stack, and The above-mentioned lower electrode is an electronic device that is bonded to the pixel electrodes and another of the common electrodes.

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