Wafer cooling module and method of cooling system on wafer using wafer cooling module

Abstract

Various embodiments may relate to a wafer cooling module. The wafer cooling module may include a top layer which may include one or more inlet ports and one or more outlet ports. The wafer cooling module may include a middle layer which may include an interconnection wafer defining a plurality of fluid channels, the plurality of fluid channels being fluidly connected to the inlet ports and the outlet ports. The wafer cooling module may include a bottom layer which may include a plurality of stepped, isolated cooling nodes fluidly connected to the plurality of fluid channels. In an embodiment, each cooling node of the plurality of stepped isolated cooling nodes may have a cooling flow pattern different from cooling flow patterns of other cooling nodes, and wherein each cooling flow pattern is optimized based on predetermined thermal management requirements.

Description

WAFER COOLING MODULE AND METHOD OF COOLING SYSTEM ON WAFER USING WAFER COOLING MODULETECHNICAL FIELD

[0001] Various aspects of this disclosure relate to a wafer cooling module. Various aspects of this disclosure may relate to a method of cooling a system on wafer using a wafer cooling module.BACKGROUND

[0002] With high demanding for heterogenous integration of versatile functions into advanced packages, thermal management has been pushed to the corner, and become imperative critical for reliable system operation. System on wafer (SoW) is expected to play a significant role in future data center, consuming large amounts of power to fulfil tough computation tasks. As semiconductor integration advances, large multi-chiplet systems increasingly transition from system-in-package architectures to system on wafer (SoW) architectures to achieve accelerated computing. Potential performance of large system is constrained by thermal challenge due to high power and complex issue. Multiple components with massive heating power and various thermal request for heterogenous integration, posing critical challenge for thermal management and cooling design. The conventional liquid cooling solutions of bulky size and long thermal path are not able to address the increasingly complex thermal issue for SoW application, especially to both commit compact profile and interactive heating effect. With the heating density becomes higher and higher, each factor along the thermal path becomes critical directly affect whole performance of the device or systems. A SoW may integrate heterogeneous components including processing units, memory stacks, photonic integrated circuits, and power management units.

[0003] Accordingly, there is a need for a wafer-level cooling solution that is compatible with wafer processes, provides localized and heterogeneous cooling, and reduces thermal coupling across the wafer.SUMMARY

[0004] Various embodiments may relate to a wafer cooling module. The wafer cooling module may include a top layer which may include one or more inlet ports and one or more outlet ports. The wafer cooling module may include a middle layer which may include an interconnection wafer defining a plurality of fluid channels, the plurality of fluid channels being fluidly connected to the inlet ports and the outlet ports. The wafer cooling module may include a bottom layer which may include a plurality of stepped, isolated cooling nodes fluidly connected to the plurality of fluid channels. In an embodiment, each cooling node of the plurality of stepped isolated cooling nodes may have a cooling flow pattern different from cooling flow patterns of other cooling nodes, and wherein each cooling flow pattern is optimized based on predetermined thermal management requirements.

[0005] In various embodiments, the plurality of stepped isolated cooling nodes are configured for direct bonding to the system on wafer.

[0006] In various embodiments, the bottom layer is formed of silicon to reduce thermal mismatch with components of the system on wafer.

[0007] In various embodiments, the stepped configuration of the plurality of stepped isolated cooling nodes accommodates components of different heights on the system on wafer.

[0008] In various embodiments, at least one cooling node of the plurality of stepped isolated cooling nodes comprises a lateral laminar cooling flow pattern.

[0009] In various embodiments, at least one cooling node of the plurality of stepped isolated cooling nodes comprises a vertical impingement jet cooling flow pattern.

[0010] In various embodiments, the vertical impingement jet cooling flow pattern includes inlet and outlet paths located on a top side of the at least one cooling node.

[0011] In various embodiments, the plurality of fluid channels includes isolated hot and cold fluid channels to reduce thermal interaction between adjacent cooling nodes of the plurality of stepped, isolated cooling nodes.

[0012] In various embodiments, the inlet ports and outlet ports are arranged to form a crossflow or confluent flow configuration across the interconnection wafer.

[0013] In various embodiments, the wafer cooling module is fabricated and bonded using a wafer-level process compatible with system-on-wafer integration.

[0014] Various embodiments may relate to a method of cooling system on wafer using wafer cooling module. The method may include providing the wafer cooling module which may include a top layer, a middle layer, and a bottom layer which may include a plurality of stepped isolated cooling nodes. The method may include bonding the bottom layer of the wafer cooling module to the system on wafer. The method may include supplying a coolant through one or more inlet ports of the top layer. The method may include directing the coolant through a plurality of fluid channels in the middle layer to the plurality of stepped, isolated cooling nodes. The method may also include removing heat from components on the system on wafer using different cooling flow patterns in different cooling nodes of the plurality of stepped isolated cooling nodes based on predetermined thermal management requirements.

[0015] In various embodiments, the plurality of stepped isolated cooling nodes are configured for direct bonding to the system on wafer.

[0016] In various embodiments, the bottom layer is formed of silicon to reduce thermal mismatch with components of the system on wafer.

[0017] In various embodiments, the stepped configuration of the cooling nodes accommodates components of different heights on the system on wafer.

[0018] In various embodiments, removing heat comprises applying a lateral laminar cooling flow pattern in at least one cooling node of the plurality of stepped isolated cooling nodes.

[0019] In various embodiments, wherein removing heat includes applying a vertical impingement jet cooling flow pattern in at least one cooling node of the plurality of stepped isolated cooling nodes.

[0020] In various embodiments, the vertical impingement jet cooling flow pattern includes delivering and removing coolant through a top side of the at least one cooling node.

[0021] In various embodiments, the method further includes isolating hot and cold coolant flows within the middle layer to reduce thermal interaction between adjacent cooling nodes of the plurality of stepped isolated cooling nodes.

[0022] In various embodiments, the inlet ports and outlet ports are arranged to form a crossflow or confluent flow configuration across the interconnection wafer.

[0023] In various embodiments, the wafer cooling module is fabricated and bonded using a wafer-level process compatible with system-on-wafer integration.BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:FIG. 1 is a schematic image of the wafer cooling module attached on top of SoW according to various embodiments.FIG. 2 is a schematic image of the wafer cooling module with three wafer stacking structure according to various embodiments.FIG. 3 is a schematic showing a cooling wafer with the main flow motion of the inlet ports and outlet ports according to various embodiments.FIG. 4 is a schematic showing zoom-in flow stream inside the cooling wafer according to various embodiments.FIG. 5A is a schematic showing a top view of cooling wafer according to various embodiments. FIG. 5B is a schematic showing a cross-section view along x direction (long bar line) according to various embodiments.FIG. 5C is a schematic of a cross-sectional view along y direction (dotted line) according to various embodiments.FIG. 6 is a schematic showing a top view of flow pattern in cooling nodes according to various embodiments.FIG. 7A shows a results simulation of a conventional liquid cooling solution according to various embodiments.FIG. 7B shows a results simulation of a heterogenous liquid cooling with wafer module according to various embodiments.FIG. 8 shows a flow chart of method of cooling system on wafer using wafer cooling module according to various embodiments.DETAILED DESCRIPTION

[0025] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0026] Embodiments described in the context of one of the methods or wafer cooling module are analogously valid for the other methods or wafer cooling module. Similarly, embodiments described in the context of a method are analogously valid for a wafer cooling module, and vice versa.

[0027] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and / or combinations and / or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0028] In the context of various embodiments, the articles “a”, “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements.

[0029] In the context of various embodiments, the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.

[0030] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0031] FIG. 1 is a schematic image of the wafer cooling module attached on top of SoW according to various embodiments.

[0032] In FIG. 1, a cooling system 100 is shown. The cooling system 100 may include a wafer cooling module 102. The wafer cooling module 102 may be a wafer level solution compatible with wafer process for implementation. The wafer cooling module may be directly bonded with stacks 106 in system on wafer 104. The formed different flow pattern will handle different thermal issues for different components on SoW 104. With stacked structure of wafer cooling module 102,stepped contact configuration can be achieved to enable reduced thermal resistance from cooling nodes to heating sources.

[0033] In various embodiments, the stacked structure of the wafer cooling module 102 may include a top layer which may include inlet and outlet ports, a middle layer which may include an interconnection wafer defining a plurality of fluid channels and a bottom layer which may include a plurality of stepped, isolated cooling nodes fluidly connected to the plurality of fluid channels. The top layer, middle layer and the bottom layer of the wafer cooling module 102 may form a stacked structure.

[0034] In various embodiments, there may have processing units (XPU), memory stacks (HBM), photonics chips (PIC), and power management units on one system on wafer, their power consumption, temperature limit and thermal sensitivity are all different. As such a cooling module to address all those issues, also considering fabrication and implementation is desired.

[0035] FIG. 2 is a schematic image of the wafer cooling module with three wafer (layer) stacking structure according to various embodiments.

[0036] In FIG. 2, a wafer cooling module 200 is shown. The wafer cooling module 200 may include a top layer 202 which may include one or more inlet ports 208a and one or more outlet ports 208b. In various embodiments, the one or more inlet ports 208a may be feeding ducts. In various embodiments, the one or more outlet ports 208b may be draining ducts.

[0037] In various embodiments, a cooling liquid or coolant may be injected in the inlet ports 208a. The “cooling liquid” may generally refer to any fluid, solution, or liquid which may be carried from one part of the module to another part of the module, thus transferring thermal energy. The cooling liquid may for instance be antifreeze, e.g. a solution of ethylene glycol, diethylene glycol, or propylene glycol.

[0038] In various embodiments, the wafer cooling module 200 may include a middle layer 204 which may include an interconnection wafer 210 defining a plurality of fluid channels 212, the plurality of fluid channels 212 being fluidly connected to the inlet ports 208a and the outlet ports 208b. The plurality of fluid channels 212 may be or may include flow configuration structures, channels, and chambers.

[0039] In various embodiments, the wafer cooling module 200 may include a bottom layer 206 which may include a plurality of stepped, isolated cooling nodes 214 fluidly connected to theplurality of fluid channels 212. In an embodiment, each cooling node of the plurality of stepped isolated cooling nodes 214 may have a cooling flow pattern different from cooling flow patterns of other cooling nodes, and wherein each cooling flow pattern is optimized based on predetermined thermal management requirements.

[0040] In various embodiments, the plurality of stepped isolated cooling nodes 214 may be configured for direct bonding to the system on wafer.

[0041] In various embodiments, a bottom surface of cooling nodes 214 may be in direct contact with top surface of components, chips or stacks on SoW. There may be bonding solder or thermal interface material at the contact interfaces.

[0042] In various embodiments, the bottom layer is formed of silicon to reduce thermal mismatch with components of the system on wafer. To enable minimized heat conduction resistance and reduce thermal stress due to coefficient of thermal expansion mismatch, the cooling nodes may be made of Silicon, and may be compatible with Silicon chips or stacks for integration.

[0043] In various embodiments, the stepped configuration of the cooling nodes may accommodate components of different heights on the system on wafer.

[0044] In various embodiments, the wafer cooling module is fabricated and bonded using a wafer-level process compatible with system-on-wafer integration.

[0045] For avoidance of doubt, FIG. 2 seeks to highlight the features of a cooling module 200 according to various embodiments, and is not intended to indicate or limit the arrangement, orientation, shapes, and sizes etc. of the various features.

[0046] FIG. 3 is a schematic showing the wafer cooling module with the main flow motion of the inlet ports and outlet ports according to various embodiments.

[0047] In FIGG the top layer 302 is shown. In various embodiments, the top layer 302 may include one or more inlet ports 308a and one or more outlet ports 308b. In an embodiment, the one or more inlet ports 308a may be two inlet ports. In an embodiment, the one or more outlet ports 308b may be two outlet ports. In an embodiment, any suitable number or arrangement of inlet ports 308a and outlet ports 308b may be used.

[0048] In various embodiments, the one or more inlet ports 308a and one or more outlet ports 308b may form a holistic cross flow stream covering the whole (or substantially whole) of the SoW areas (e.g. be respectively diagonally arranged across the SoW), as is shown in FIG. 3. Inother words, the one or more inlet ports 308a and one or more outlet ports 308b may be arranged across the SoW such that at least a flow stream of one or more inlet ports 308a and one or more outlet ports 308b may be able to cover each component of the SoW.

[0049] FIG. 4 is a schematic showing zoom-in flow stream inside the wafer cooling module according to various embodiments.

[0050] In FIG. 4, a middle layer 404 which may include an interconnection wafer 410 defining a plurality of fluid channels 412, the plurality of fluid channels 412 which may be fluidly connected to the inlet ports 308a and the outlet ports 308b of FIG. 3.

[0051] In some embodiments, the interconnection wafer 410 may define a plurality of flow configuration structures, including channels and chambers.

[0052] In some embodiments, the interconnection wafer 410 may define cold fluid channels configured to deliver coolant to the cooling nodes and hot fluid channels configured to collect heated coolant from the cooling nodes. The cold and hot fluid channels are isolated from one another, thereby forming isolated heat delivery paths for individual cooling nodes and reducing thermal interaction between adjacent zones on the interconnection wafer.

[0053] In some embodiments, the interconnection wafer 410 is formed of a material having relatively low thermal conductivity to further limit lateral heat spreading.

[0054] In various embodiments, the plurality of fluid channels 412 which may be hot and cold channels on the interconnection wafer 410 may be formed as the isolated heat delivery path to main reliable function of each cooling nodes.

[0055] In various embodiments, cold working fluid (i.e. the coolant) comes from the cold channels, then flow into the cooling nodes taking some heat away. The coolant may then approach the confluence from one pattern cooling nodes to another pattern cooling nodes. In various embodiments, after taking heat away the coolant may become or form hot working fluid which may flow out of the outlet ports 308b.

[0056] In various embodiments, from the whole wafer perspective, left side and right side of the interconnection wafer may have different flow stream direction for cold and hot working fluid. In some embodiments, the one or more inlet ports 308a and one or more outlet ports 308b may be disposed respectively on one side of the interconnection wafer, for example, the one or more inlet ports 308a may be disposed on the left side of the interconnection wafer and the one or more outletports 308b may be disposed on the right side of the interconnection wafer. In various embodiments, the cold fluid and the hot fluid may be travelling in different parts of the interconnection wafer which may allow for isolation of hot and cold zones. Advantageously, this type of configuration enables high efficiency heat delivery and good isolation for various zones.

[0057] In various embodiments, the inlet ports and the outlet ports may be arranged to form a holistic cross-flow or confluent flow configuration across the interconnection wafer. The inlet ports are configured to introduce relatively cold coolant, and the outlet ports are configured to remove heated coolant.

[0058] Advantageously, this arrangement enables coolant to flow across substantially the entire area of the system on wafer while maintaining directional separation between cold and hot working fluid streams.

[0059] FIG. 5A is a schematic showing a top view of cooling wafer according to various embodiments.

[0060] FIG. 5B is a schematic showing a cross-section view along x direction (long bar line) according to various embodiments.

[0061] FIG. 5C is a schematic of a cross-sectional view along y direction (dotted line) according to various embodiments.

[0062] In various embodiments, the wafer cooling module may include a bottom layer 506 which may include a plurality of stepped, isolated cooling nodes 514 fluidly connected to the plurality of fluid channels 412.

[0063] In various embodiments, each cooling node of the plurality of stepped isolated cooling nodes 514 may have a cooling flow pattern different from cooling flow patterns of other cooling nodes.

[0064] In various embodiments, each cooling flow pattern is optimized based on predetermined thermal management requirements. In the isolated cooling nodes 514, the flow pattern are different mainly according to thermal management objectives for the bottom heat sources which may be the components on the system on wafer.

[0065] In various embodiments, at least one cooling node comprises a lateral laminar flow pattern.

[0066] In various embodiments, at least one cooling node comprises a vertical impingement jet flow pattern.

[0067] In the embodiment of FIG. 5B, the left and right cooling nodes 514 may form laminar flow from one side to another in lateral direction, while the center nodes may form impingement jet flow in vertical direction which may enable high heat removal capability in these zones. In some embodiments, the laminar flow in the lateral direction may be a smooth, orderly fluid motion where particles move in parallel layers with minimal mixing (i.e, the hot and cold fluid has minimal mixing).

[0068] In the embodiment of FIG.5C, to zoom in, the flow motion inside the nodes with vertical flow, the working flow come from top side of the middle layer, also may leave the nodes from top side, forming vertical parallel flow. The heat in the hot coolant may not cause further thermal interaction to the adjacent zones, which may achieve focusing cooling for specific components and avoid over heating for the nearby temperature sensitive components.

[0069] In various embodiments, the vertical impingement jet flow pattern includes inlet and outlet paths located on a top side of the cooling node. In various embodiments, the impingement jet flow may be a high-efficiency fluid dynamics phenomenon where a fluid jet creates distinct flow regions (separated hot and cold flow regions) that enhance heat transfer of hot components on the SoW.

[0070] In various embodiments, the middle layer defines isolated hot and cold fluid channels to reduce thermal interaction between adjacent cooling nodes.

[0071] In various embodiments, the inlet ports and outlet ports are arranged to form a crossflow or confluent flow configuration across the top layer.

[0072] In some embodiments, each cooling node comprises an internal cooling flow pattern, and the cooling flow pattern of one cooling node differs from that of another cooling node.

[0073] In some embodiments, at least one cooling node comprises a lateral laminar flow pattern, in which coolant flows laterally across the cooling node. Such a flow pattern may be suitable for components with moderate heat flux or high thermal sensitivity.

[0074] In some embodiments, at least one cooling node 514 comprises a vertical impingement jet flow pattern, in which coolant flows in a substantially vertical direction toward the component surface, enabling high heat removal capability.

[0075] In some embodiments, the vertical impingement jet flow pattern includes coolant inlet and outlet paths located on a top side of the cooling node, such that heated coolant exits the cooling node without causing thermal interaction with adjacent cooling nodes.

[0076] By selecting different cooling flow patterns for different cooling nodes, focused cooling may be provided for high-power components while avoiding overheating of nearby temperaturesensitive components.

[0077] In some embodiments, coolant delivered through cold channels enters multiple cooling nodes and subsequently converges into a confluent flow path within the interconnection layer, forming a hot working fluid that is directed toward the outlet ports.

[0078] In some embodiments, cold working fluid and hot working fluid may flow in opposite directions, enabling high-efficiency heat delivery and improved thermal isolation between different regions of the wafer.

[0079] FIG. 6 is a schematic showing a top view of flow pattern in cooling nodes according to various embodiments.

[0080] In various embodiments, the wafer cooling module may include a bottom layer 606 which may include a plurality of stepped, isolated cooling nodes 614.

[0081] In various embodiments, each cooling node of the plurality of stepped isolated cooling nodes 614 may have a cooling flow pattern different from cooling flow patterns of other cooling nodes.

[0082] In some embodiments, the cooling nodes are arranged in a stepped configuration, such that different cooling nodes have different vertical heights. This stepped configuration enables direct thermal contact with components of different heights on the system on wafer and reduces thermal interface resistance.

[0083] In various embodiments, each cooling flow pattern is optimized based on predetermined thermal management requirements. In the isolated cooling nodes 614, the flow pattern is different mainly according to thermal management objectives for the bottom heat sources which may be the components on the system on wafer. Therefore, even in the same layer for bottom SoW cooling, the flow pattern in each cooling nodes may be different, as is shown in FIG. 6.

[0084] In various embodiments, in an exemplary flow pattern shown in FIG. 6, the isolated cooling nodes 614 follows a lateral laminar cooling flow pattern (as shown by arrow 620). Thecoolant enters an inlet port vertically in (as shown by cross 622) and cools the desired component on the SoW. Thereafter, the coolant which turns into hot fluid exits by outlet ports vertically out (as shown by dot 624).

[0085] In various embodiments, the cooling system may additionally include one or more temperature sensors configured to sense temperature parameters of the cooling wafer module and / or components of the SoW. The cooling system may further include a control circuit configured to determine each cooling flow pattern of the each cooling node of the plurality of stepped isolated cooling nodes 614 based on the temperature parameters and / or predetermined thermal management requirements.

[0086] In various embodiments, when the control circuit determines that a component on the SoW is hot (e.g. exceeding a predefined threshold) or requires cooling (or extra cooling), the control circuit may increase the flow pattern of coolant in the affected area.

[0087] In various embodiments, the wafer cooling module may be directly attached to SoW following wafer process, to handle both high power dissipation and internal thermal interaction, to address the complex thermal issues from different types of components of different thermal requests.

[0088] FIG. 7A shows a results simulation of a conventional liquid cooling solution.

[0089] FIG. 7B shows a results simulation of a heterogenous liquid cooling with wafer module according to various embodiments.

[0090] Several simulations have been performed to investigate cooling capability of using the proposed wafer cooling module. To compare the performance with the conventional liquid cooling solution, a large package model including processing units (XPU), memory stacks (HBM) and photonic chips (PIC) has been built.

[0091] As is shown in FIGS. 7A and 7B, the temperature distribution for both cooling solutions are quite different. As shown in FIG. 7A, there is a hot zone 702 and a cold zone 704. Consequently, with conventional cooling solution, there are strong heat interactions 706 on the SoW. In other words, there may be zones which have temperatures in between hot zone and cold zone causing strong heat interactions on the SoW.

[0092] In various embodiments, to maintain all different types of chips under temperature limit, the maximum heating power can be dissipated by conventional cooling is 642W. In this case, thelimitation is from PIC. The XPU doesn’t reach its maximum temperature yet. But if increasing the heating power, there will be high risk of overheating for both PIC and HBM.

[0093] As shown in FIG. 7B, using the disclosed cooling solution, wafer cooling module, the hot zones 712 and cold zones 714 are separated, minimizing heat interaction between adjacent chips. In an embodiment, since each cooling node of the plurality of stepped isolated cooling nodes may have a cooling flow pattern different from cooling flow patterns of other cooling nodes, the hot zones 712 and the cold zones 714 are separated. Consequently, there may be no (or little) heat interactions between the hot zones 712 and cold zones 714 on the SoW. Therefore, different components on the SoW can be maintained at their optimal temperature.

[0094] Advantageously, the chips can reach their full potential. To maintain all chips under temperature limit, the heating power can be dissipated is more than 1.2kW, achieving thermal performance improvement more than 40% for the SoW. Further, due to microfluid application module, the working fluid volume and pumping energy requirement is highly reduced, can be more than half or a third depending on the system loop buildup.

[0095] FIG. 8 shows a flow chart of method of cooling system on wafer using wafer cooling module according to various embodiments.

[0096] In various embodiments, a method 800 of cooling system on wafer using wafer cooling module is shown.

[0097] In various embodiments, the method 800 may include a step 802 of providing the wafer cooling module which may include a top layer, a middle layer, and a bottom layer which may include a plurality of stepped isolated cooling nodes.

[0098] In various embodiments, the method 800 may include a step 804 of bonding the bottom layer of the wafer cooling module to the system on wafer.

[0099] In various embodiments, the method 800 may include a step 806 of supplying a coolant through one or more inlet ports of the top layer.

[0100] In various embodiments, the method 800 may include a step 808 of directing the coolant through a plurality of fluid channels in the middle layer to the plurality of stepped, isolated cooling nodes.

[0101] In various embodiments, the method 800 may include a step 810 of removing heat from components on the system on wafer using different cooling flow patterns in different cooling nodes based on predetermined thermal management requirements.

[0102] For avoidance of doubt, FIG. 8 is not intended to limit the sequence of the steps and may be performed in any suitable order.

[0103] The wafer cooling module and method described herein are suitable for cooling heterogeneous systems on wafer. Technical effects achieved by the disclosed embodiments include reduction of thermal interaction between adjacent components, improved control of wafer-level temperature gradients, increased allowable total power dissipation compared with conventional liquid cooling solutions, reduced coolant volume and pumping energy due to microfluidic implementation and compatibility with wafer-level fabrication and integration processes.

[0104] The disclosed embodiments provide a wafer-level heterogeneous liquid cooling solution for system-on-wafer architectures. By combining a stacked wafer structure, isolated cooling nodes, stepped contact interfaces, and node-specific cooling flow patterns, the invention enables efficient and reliable thermal management of heterogeneous components on a single wafer.

[0105] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

CLAIMS1. A wafer cooling module configured for bonding to a system on wafer, comprising:a top layer comprising one or more inlet ports and one or more outlet ports;a middle layer comprising an interconnection wafer defining a plurality of fluid channels, the plurality of fluid channels being fluidly connected to the inlet ports and the outlet ports; and a bottom layer comprising a plurality of stepped, isolated cooling nodes fluidly connected to the plurality of fluid channels.

2. The wafer cooling module of claim 1, wherein each cooling node of the plurality of stepped isolated cooling nodes comprises a cooling flow pattern different from cooling flow patterns of other cooling nodes, and wherein each cooling flow pattern is optimized based on predetermined thermal management requirements.

3. The wafer cooling module of claim 1, wherein the bottom layer is formed of silicon to reduce thermal mismatch with components of the system on wafer.

4. The wafer cooling module of claim 1, wherein the stepped configuration of the plurality of stepped isolated cooling nodes accommodates components of different heights on the system on wafer.

5. The wafer cooling module of claim 1, wherein at least one cooling node of the plurality of stepped isolated cooling nodes comprises a lateral laminar cooling flow pattern.

6. The wafer cooling module of claim 1, wherein at least one cooling node of the plurality of stepped isolated cooling nodes comprises a vertical impingement jet cooling flow pattern.

7. The wafer cooling module of claim 6, wherein the vertical impingement jet cooling flow pattern includes inlet and outlet paths located on a top side of the at least one cooling node.

8. The wafer cooling module of claim 1, wherein the plurality of fluid channels comprises isolated hot and cold fluid channels to reduce thermal interaction between adjacent cooling nodes of the plurality of stepped, isolated cooling nodes.

9. The wafer cooling module of claim 1, wherein the inlet ports and outlet ports are arranged to form a cross-flow or confluent flow configuration across the interconnection wafer.

10. The wafer cooling module of claim 1, wherein the wafer cooling module is fabricated and bonded using a wafer-level process compatible with system-on-wafer integration.

11. A method of cooling a system on wafer using a wafer cooling module, comprising:providing the wafer cooling module comprising a top layer, a middle layer, and a bottom layer comprising a plurality of stepped isolated cooling nodes;bonding the bottom layer of the wafer cooling module to the system on wafer; supplying a coolant through one or more inlet ports of the top layer;directing the coolant through a plurality of fluid channels in the middle layer to the plurality of stepped, isolated cooling nodes; andremoving heat from components on the system on wafer using different cooling flow patterns in different cooling nodes of the plurality of stepped isolated cooling nodes based on predetermined thermal management requirements.

12. The method of claim 11, wherein bonding the bottom layer to the system on wafer comprises wafer-level bonding.

13. The method of claim 11, wherein removing heat comprises applying a lateral laminar cooling flow pattern in at least one cooling node of the plurality of stepped isolated cooling nodes.

14. The method of claim 11, wherein removing heat comprises applying a vertical impingement jet cooling flow pattern in at least one cooling node of the plurality of stepped isolated cooling nodes.

15. The method of claim 14, wherein the vertical impingement jet cooling flow pattern comprises delivering and removing coolant through a top side of the at least one cooling node.

16. The method of claim 11, further comprising isolating hot and cold coolant flows within the middle layer to reduce thermal interaction between adjacent cooling nodes of the plurality of stepped isolated cooling nodes.

17. The method of claim 11, wherein the stepped configuration of the cooling nodes of the plurality of stepped isolated cooling nodes accommodates components of different heights on the system on wafer.

18. The method of claim 11, further comprising collecting heated coolant through hot fluid channels of the plurality of fluid channels and directing the heated coolant toward one or more outlet ports.

19. The method of claim 11, wherein the coolant is supplied and collected in a cross-flow or confluent flow configuration across the interconnection wafer.

20. The method of claim 11, wherein the wafer cooling module is fabricated and bonded using a wafer-level process compatible with system-on-wafer integration.

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