A hybrid interposer

Abstract

This document describes a hybrid interposer structure for high-power radio-frequency (RF) packaging and heterogeneous integrated circuit (IC) integration. In particular, this application relates to a hybrid interposer structure configured to mitigate heat trapping and enhance thermal dissipation associated with conventional silicon-based interposer structures.

Description

A HYBRID INTERPOSERCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority to Singapore patent application no.10202500435V which was filed on 18 February 2025, the contents of which are hereby incorporated by reference in its entirety for all purposes.TECHNICAL FIELD

[0002] This application relates to a hybrid interposer structure for high-power radiofrequency (RF) packaging and heterogeneous integrated circuit (IC) integration. In particular, this application relates to a hybrid interposer structure configured to mitigate heat trapping and enhance thermal dissipation associated with conventional silicon-based interposer structures.BACKGROUND

[0003] Fifth-generation (5G) communication systems, together with defense and aerospace applications, are accelerating the adoption of silicon interposer technologies for radio-frequency (RF) packaging. Heterogeneous integration of lll-V or silicon-based high-electron-mobility transistor (HEMT) devices onto silicon interposers in 2.5D and 3D configurations offers advantages such as high packaging density and reduced transmission loss. In such systems, RF devices are typically attached to interposers and electrically interconnected using techniques including epoxy die attach and wire bonding, solder attachment, or flip-chip bumping. Despite the various approaches proposed by those skilled in the art such as die-attach and interconnection techniques, thermal management has emerged as one of the most critical challenges in heterogeneous integration. When RF devices operate under high-power conditions to meet increasing demands for high-data-rate transmission, real-time streaming, autonomous vehicle control, and Internet-of-Things (loT) applications, insufficient heat dissipation can lead to performance degradation and long-term reliability issues.

[0004] To address thermal management challenges in high-power RF amplifiers, those skilled in the art have proposed various heat-sinking approaches such as top- or bottommounted finned metal plates, liquid cooling pipes or chambers, phase-change cooling techniques, and liquid metal solutions. However, many of these approaches are bulky, mechanically complex, and susceptible to leakage risks, which limit their suitability for compact, high-density RF packages. As a result, alternative substrate materials have attracted significant interest.

[0005] Silicon carbide (SiC), for example, was found to exhibit a thermal conductivity approximately three times higher than that of silicon and possesses a wide bandgap that supports high-voltage operation, making it attractive for high-power RF applications. Nevertheless, SiC substrates, particularly those of larger wafer sizes, remain costly due to manufacturing complexity and relatively slow ingot growth rates. In RF applications, high-resistivity SiC substrates are typically required to suppress RF signal loss, yet large-diameter high-resistivity SiC wafers are not widely available. This further constrains the adoption of SiC substrates.

[0006] In parallel, those skilled in the art have proposed the use of high-resistivity silicon for RF interposers due to its mature manufacturing ecosystem and availability in large wafer formats. However, silicon’s relatively low thermal conductivity and narrow bandgap limit its suitability for high-power operation. Silicon-on-insulator (SOI) substrates have also been employed to reduce RF losses by decreasing parasitic capacitance through a buried oxide layer. While effective from an RF perspective, the buried oxide layer exhibits extremely low thermal conductivity compared to silicon, acting as a thermal barrier that exacerbates selfheating effects in power amplifiers.

[0007] Hybrid substrate approaches combining silicon and silicon carbide have been explored to balance RF and thermal performance. These approaches typically rely on waferlevel bonding of silicon layers to silicon carbide substrates, followed by high-temperature annealing and thinning of the silicon layer to a target thickness. However, the limited availability of large-area semi-insulating silicon carbide substrates has constrained scalability to wafer sizes of eight inches and beyond. In addition, wafer bonding processes may introduce low-density interfacial layers or air gaps between bonded materials, which can degrade thermal conduction and reduce fabrication yield, particularly in interposer manufacturing processes that require high uniformity and reliability.

[0008] In view of the challenges mentioned above, those skilled in the art are constantly striving to design an interposer structure that simultaneously supports high-power RF operation, efficient thermal dissipation, low RF loss, scalable wafer-level fabrication, and high manufacturing yield, without relying on bulky external cooling structures or costly large-area semi-insulating substrates.SUMMARY

[0009] In one aspect, the present disclosure describes a hybrid interposer that comprises a low-resistivity substrate and a high-resistivity layer formed on the low-resistivity substrate. The interposer also includes one or more transmission lines and at least one active circuit component disposed on the high-resistivity layer. In embodiments of the one aspect, the low-resistivity substrate comprises a cavity selectively formed beneath the one or more transmission lines, the cavity having a length and a width equal to or greater than corresponding dimensions of the one or more transmission lines, and the low-resistivity substrate remains continuous beneath the at least one active component.

[0010] In embodiments of the one aspect, the high-resistivity layer comprises high-resistivity polysilicon and the low-resistivity substrate comprises low-resistivity polycrystalline silicon carbide.

[0011] In embodiments of the one aspect, the high-resistivity layer and the low- resistivity substrate both comprise resistivity polycrystalline silicon carbide, wherein the high-resistivity layer has a higher resistivity than the low-resistivity substrate.

[0012] In embodiments of the one aspect, the cavity has a depth extending partially through the low-resistivity substrate. Additionally, the high-resistivity layer may have a thickness between 2 pm and 30 pm.

[0013] In embodiments of the one aspect, a ratio of a thickness of the high-resistivity layer to a thickness of the low-resistivity substrate is in a range of 1:1 to 1:250. Further, the low-resistivity substrate is configured to conduct heat generated by the at least one active circuit component away from the high-resistivity layer. Still further, the cavity may have a width of at least 100 pm.

[0014] In another aspect, the present disclosure describes method of fabricating a hybrid interposer. The disclosed method comprises the steps of providing a low- resistivity substrate, forming a high-resistivity layer on the low-resistivity substrate, and forming one or more transmission lines and at least one active circuit component on the high-resistivity layer. The method also includes the step of selectively etching a cavity into the low-resistivity substrate beneath the one or more transmission lines, wherein the cavity has a length and a width equal to or greater than corresponding dimensions of the one or more transmission lines, and wherein the low-resistivity substrate remains continuous beneath the at least one active circuit component.

[0015] In embodiments of the another aspect, the forming the high-resistivity layer on the low-resistivity substrate comprises the step of depositing the high-resistivity layer directly on the low-resistivity substrate. Further, the deposition may be performed using chemical vapor deposition (CVD) or epitaxial growth. The forming of the high-resistivity layer may also comprise the step of directly wafer bonding the high-resistivity layer to the low-resistivity substrate and thinning the high-resistivity layer.

[0016] In embodiments of the another aspect, the thinning the high-resistivity wafer may comprise the step of backside grinding and chemical mechanical polishing (CMP) the high-resistivity layer.BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various embodiments of the present disclosure are described below with reference to the following drawings:Figure 1 illustrates a perspective view of the hybrid interposer in accordance with embodiments of the present disclosure;Figure 2 illustrates a cross-sectional view along the y-z axis of the hybrid interposer illustrated in Figure 1;Figure 3 illustrates simulated temperature levels at the top surface of a RF power amplifier versus power density for different interposer substrate configurations;Figure 4 illustrates the maximum power densities of a RF power amplifier when a top-surface temperature of the RF amplifier is maintained at a critical level of 125 °C for different interposer substrate structures when the overall thickness of the interposer is 125 pm;Figure 5 illustrates the maximum power densities of a RF power amplifier when a top-surface temperature of the RF amplifier is maintained at a critical level of 125 °C for different interposer substrate structures when the overall thickness of the interposer is 50 pm; andFigure 6 illustrates a flowchart showing a process for fabricating a hybrid interposer in accordance with embodiments of the disclosure.DETAILED DESCRIPTION

[0018] The following detailed description is made with reference to the accompanying drawings, showing details and embodiments of the present disclosure for the purposes of illustration. Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments, even if not explicitlydescribed in these other embodiments. Additions and / or combinations and / or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0019] In the context of various embodiments, the articles “a,” “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements.

[0020] In the context of various embodiments, the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance as generally understood in the relevant technical field, e.g., within 10% of the specified value.

[0021] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0022] As used herein, “comprising” means including, but not limited to, whatever follows the word “comprising.” Thus, use of the term “comprising” indicates that the listed elements are required or mandatory, but that other elements are optional and may or may not be present.

[0023] As used herein, “consisting of’ means including, and limited to, whatever follows the phrase “consisting of.” Thus, use of the phrase “consisting of” indicates that the listed elements are required or mandatory, and that no other elements may be present.

[0024] In the context of various embodiments, the term “disposed on" relates to the placement or deposition of one material or layer onto the surface of another and may involve one or more types of deposition techniques.

[0025] In the context of various embodiments, the directional terms mentioned herein, such as “above” and “below” or “upper” and “lower” refer to directions as described with reference to the drawings. Therefore, the directional terms are only used for illustration and are not meant to limit the present disclosure.

[0026] Additionally, for the sake of brevity, extensive explanations of conventional techniques of fabricating semiconductor devices and integrated circuits are not described in detail herein. The tasks and processes described herein may also be integrated into a more comprehensive procedure with extra steps of features that are not elaborated upon in thisdocument. Specifically, certain processes of fabricating semiconductor devices are well known to one skilled in the art hence, such processes will be omitted entirely.

[0027] Figure 1 illustrates a perspective view of a hybrid interposer structure in accordance with embodiments of the disclosure. Specifically, hybrid interposer 100 may be configured for radio-frequency (RF) packaging and heterogeneous integration systems. As shown, hybrid interposer 100 includes high-resistivity (HR) layer 104 disposed above a low-resistivity (LR) substrate, which is represented by portions 102a and 102b. One or more transmission lines 108 and active circuit component 106 are arranged on an upper surface of the HR layer 104. It should be noted that the drawing in Figure 1 is not to scale and is intended to emphasize relative placement and functional relationships among the elements rather than exact geometries.

[0028] HR layer 104 functions as a device-support and routing layer for RF signal propagation. Transmission lines 108 may include, but is not limited to, metal interconnects, signal traces, or other conductive routing structures configured to carry high-frequency signals. Active component 106, which may comprise a heat-generating circuit and is mounted on the HR layer 104. It may also be electrically coupled to at least some of the transmission lines 108. In embodiments of the disclosure, active circuit component 106 may comprise any device that consumes electrical power and produces heat during operation. For example, active circuit component 106 may include, but is not limited to, a RF power amplifier, a low-noise amplifier (LNA), a mixer, a driver stage, a power management circuit, a switch, a phase shifter, or other monolithic microwave integrated circuit (MMIC) elements. Active circuit component 106 may be implemented using silicon, lll-V semiconductor technologies such as GaN, GaAs, or InP, or other material systems suitable for high-frequency or high-power operation.

[0029] When in use, heat is typically generated within active circuit component 106 primarily due to power dissipation mechanisms associated with device operation. For example, conduction losses arising from channel resistance, switching losses during high-frequency transitions, leakage currents, and parasitic resistive losses in interconnect structures can convert a portion of supplied electrical energy into thermal energy. In high-power RF applications, where large voltage swings and current densities are present, these mechanisms can produce localized thermal hotspots within the device.

[0030] The generated heat typically propagates away from active circuit component 106 through available thermal paths, including vertically through the underlying substrate and laterally through surrounding materials. If the thermal path is restricted or contains materials with low thermal conductivity, heat accumulation may occur within active circuit component 106, leading to elevated junction temperatures, performance degradation, and potential reliability concerns.

[0031] As illustrated in Figure 1, it is shown that a cavity, i.e., cavity 110, is provided by etching away a portion of the LR substrate beneath the transmission lines 108. In the illustrated embodiment, removal of the LR substrate material creates separated LR regions 102a and 102b with the cavity 110 disposed between these two LR regions. The cavity is selectively positioned so as to underlie transmission lines 108 while not extending beneath active component 106. In embodiments of the disclosure, cavity 110 may comprise an airfilled void or may alternatively be filled with a thermally functional medium such as a phase change material or coolant.

[0032] In some implementations, the lateral dimensions of cavity 110 may be equal to or greater than those of the transmission lines to suppress RF coupling into the low-resistivity material. In an embodiment of the disclosure, the LR substrate may be substantially or completely removed within the region of cavity 110 while in another embodiment, a portion of the LR substrate may remain in the cavity region. Complete removal of the LR substrate within the cavity region may provide maximum electrical isolation for the transmission lines as it may reduce undesirable substrate modes. Specifically, by eliminating lossy substrate material beneath the RF routing structures, substrate coupling, eddy current formation, and parasitic conduction paths can be significantly reduced. In addition, an air-filled or otherwise low-permittivity cavity can reduce effective dielectric loading, which may further benefit signal integrity. In embodiments where the cavity extends only partially through the LR substrate, a residual portion of the substrate material may remain. Although this configuration may provide somewhat less RF isolation compared to full removal, it can offer advantages in terms of mechanical strength, manufacturability, and thermal continuity. Additionally, the depth of the remaining residual portion may be tailored or selected according to impedance requirements of the overlying transmission lines.

[0033] It should be noted that as the LR substrate is not etched beneath active circuit component 106, the substrate remains continuous in that region and provides a direct thermal conduction path for dissipating heat generated during the operation of active circuit component106. This configuration enables RF loss reduction in routing regions while maintaining efficient vertical heat flow from active circuit component 106 into the thermally conductive LR substrate.

[0034] It is useful to note that an orientation indicator including x-, y-, and z-axes is shown in Figure 1. The y-direction generally corresponds to the vertical stacking direction of the layers, while the x- and z-directions extend laterally across the interposer. One skilled in the art will also recognize that although a limited number of transmission lines and a single active component are illustrated, hybrid interposer 100 may include any number of such structures distributed across the HR layer without departing from this disclosure.

[0035] Hybrid interposer 100 may be implemented in different material forms. In particular, a first embodiment and a second embodiment are described herein to illustrate alternative selections for forming the high-resistivity (HR) device layer and the low-resistivity (LR) substrate, i.e. the thermally conductive base substrate, while maintaining the same functional principles, including the selective formation of a cavity beneath transmission line regions and preservation of a continuous thermal path beneath heat-generating circuit components.

[0036] In the first embodiment, the high-resistivity layer (HR-layer-1) may comprise high-resistivity polysilicon (HR poly-Si), while the low-resistivity substrate (LR-substrate-2) may comprise low-resistivity polycrystalline silicon carbide (LR poly-SiC). This arrangement may be beneficial in implementations where compatibility with established silicon processing techniques, fine-pitch patterning capability, or integration with silicon-based circuitry is desired, while still leveraging the superior thermal conductivity of the SiC bulk material for heat removal. In the second embodiment, both HR-layer-1 and LR-substrate-2 may comprise polycrystalline silicon carbide, with the HR layer having a higher resistivity than the base substrate. Such a configuration may reduce material interface discontinuities, enhance thermal continuity, and improve matching of mechanical properties across the interposer.

[0037] As an example, the high-resistivity polycrystalline silicon carbide may exhibit a resistivity of greater than 1 O cm - 100 Q cm, depending on the desired RF isolation while the low-resistivity polycrystalline silicon carbide may have a resistivity lower than 1 Q cm or a range suitable for promoting efficient thermal conduction

[0038] In embodiments of the disclosure, the difference in resistivity between HR-layer-1 and LR-substrate-2 may be achieved through controlled doping, compensation techniques, or growth condition adjustments during formation of the polycrystalline material. Exampledopants may include nitrogen, aluminum, boron, or other species capable of modifying carrier concentration while maintaining compatibility with subsequent device processing.

[0039] In both embodiments, cavity 110 within LR-substrate-2 is created by removal of substrate material as described with reference to Figure 1. The cavity may remain empty or may be filled with a thermally functional medium such as air, a phase change material (PCM), or a coolant.

[0040] Figure 2 illustrates a cross-sectional or frontal view of hybrid interposer 100. Specifically, the cross-sectional view is taken along the z-y plane. In some exemplary implementations, the overall thickness a of the layer / substrate of hybrid interposer 100 may range from approximately 50 pm to 500 pm, while the thickness of the high-resistivity layer b may be in a range of about 2 pm to 50 pm. In certain embodiments, a ratio of the thickness of HR layer 104 to a thickness of the low-resistivity substrate may be in a range of approximately 1:1 to 1:250. These dimensional ranges may be selected to balance RF performance, thermal dissipation capability, mechanical robustness, and manufacturability.

[0041] In embodiments of the disclosure, the two-layer hybrid substrate of hybrid interposer 100 may be fabricated by forming the HR layer directly on the LR substrate. For example, a layer of high-resistivity polysilicon (HR poly-Si) or high-resistivity polycrystalline silicon carbide (HR poly-SiC) may be directly deposited on a low-resistivity polycrystalline silicon carbide (LR poly-SiC) base using techniques such as chemical vapor deposition (CVD) or epitaxial growth. In alternative embodiments, the hybrid structure may be realized through direct wafer bonding between an HR poly-Si or HR poly-SiC wafer and an LR poly-SiC wafer. Following bonding, the thickness of the high-resistivity material may be adjusted to a target value using backside grinding and chemical mechanical polishing (CMP) to obtain the desired device-layer thickness for RF routing and component integration.

[0042] After formation of the layered structure, the cavity beneath the transmission line region may be created by selectively removing material from the LR poly-SiC substrate. In some embodiments, this removal may be achieved using deep silicon-carbide etching in combination with a hard mask to define the cavity geometry. Based on RF simulation and design considerations, the cavity may be formed such that its length and width are equal to or greater than the corresponding dimensions of the transmission lines located above the cavity.

[0043] Figure 3 illustrates simulated top-surface temperatures of a RF power amplifier as a function of applied power density for different interposer substrate configurations. The simulation indicates that hybrid interposer implementations employing a LR poly-SiC base substrate together with either a HR poly-Si layer (i.e., plot 301) or a HR poly-SiC layer (i.e., plot 302) may exhibit reduced temperature rise compared with conventional high-resistivity silicon (i.e., plot 303) and silicon-on-insulator substrates (i.e., plot 304). The improved thermal behavior may be attributed to the superior heat conduction capability of the SiC bulk material, which facilitates efficient removal of heat from the active region while the high-resistivity layer continues to support RF routing.

[0044] Cavity dimensions associated with the transmission line regions may be determined based on electromagnetic simulation. In some simulations, the results suggest that a cavity width greater than approximately 100 pm may assist in maintaining a target characteristic impedance, for instance about 50 ohms, while achieving low insertion loss, such as less than about 2 dB, at frequencies of about 40 GHz. Because the cavities are formed selectively beneath the transmission lines and not beneath the heat-generating circuit components, the localized void regions may provide RF isolation without substantially degrading overall thermal conduction through the interposer.

[0045] Figure 4 illustrates maximum allowable power densities of a RF power amplifier while the device’s top-surface temperature is maintained at a critical level, for example 125 °C, when the RD amplifier is supported by different interposer substrates having a thickness of about 125 pm. The simulation indicates that the hybrid configurations may permit higher power operation relative to conventional silicon and silicon-on-insulator platforms. For example, the hybrid implementation of the first embodiment comprising HR poly-Si / LR poly-SiC (i.e., bar graph 401) may sustain a power density of about 1.32 times that achievable with a silicon interposer and approximately 2.04 times that of a silicon-on-insulator (SOI) substrate. The hybrid implementation of the second embodiment comprising HR poly-SiC / LR poly-SiC (i.e., bar graph 402) may further increase allowable power density to about 1.45 times that of silicon and roughly 2.23 times that of silicon-on-insulator. Such improvements may arise from the enhanced thermal conductivity of the polycrystalline silicon carbide base, which promotes more effective vertical heat spreading from the active region.

[0046] In addition to thermal advantages, poly-SiC may exhibit greater mechanical robustness than silicon-based substrates. The higher material toughness may allow the interposer to be thinned to smaller dimensions while maintaining structural integrity duringfabrication and operation. For example, while silicon or silicon-on-insulator substrates may typically require thicknesses of about 100-150 pm to retain sufficient strength, poly-SiC-based interposers may be reduced to substantially thinner profiles, such as around 50 pm. Reducing substrate thickness may shorten the thermal path between a heat-generating component and an external heat sink, thereby enabling higher permissible power densities.

[0047] Figure 5 illustrates simulated results for a reduced interposer thickness of approximately 50 pm. Under such conditions, the hybrid interposer structures may demonstrate further increases in allowable power density. As shown, the hybrid implementation of the first embodiment comprising HR poly-Si / LR poly-SiC (i.e., bar graph 501) may support approximately 1.16 times the power density of silicon and about 2.6 times that of silicon-on-insulator. The hybrid implementation of the second embodiment comprising HR poly-SiC / LR poly-SiC (i.e., bar graph 502) may achieve approximately 1.41 times the silicon value and roughly 3.17 times the silicon-on-insulator value.

[0048] The hybrid approach described in the previous sections may facilitate realization of large-dimension SiC-based interposer platforms, including formats such as eight inches and potentially twelve inches, suitable for high-power RF applications. In addition, because poly-SiC substrates can leverage established high-volume processing techniques, the resulting interposer solutions may offer cost advantages compared with structures relying on large semi-insulating monocrystalline SiC wafers, particularly when produced at scale.

[0049] A process for fabricating a hybrid interposer in accordance with embodiments of the disclosure is illustrated in Figure 6. Process 600 begins at step 602 by providing a low-resistivity substrate. At step 604, process 600 then forms a high-resistivity layer on the low-resistivity substrate. Process 600 then forms one or more transmission lines and at least one active circuit component on the high-resistivity layer. This occurs at step 606. At step 608, process 600 then selectively etches a cavity into the low-resistivity substrate beneath the one or more transmission lines, wherein the cavity has a length and a width equal to or greater than corresponding dimensions of the one or more transmission lines, and wherein the low-resistivity substrate remains continuous beneath the at least one active circuit component.

[0050] In embodiments of the disclosure the forming the high-resistivity layer on the low-resistivity substrate comprises process 600 depositing the high-resistivity layer directly on the low-resistivity substrate. In embodiments of the disclosure, the deposition of the high-resistivity layer may be performed using chemical vapor deposition (CVD) or epitaxial growth.

[0051] In embodiments of the disclosure, the forming of the high-resistivity layer on the low-resistivity substrate comprises process 600 directly wafer bonding the high-resistivity layer to the low-resistivity substrate and subsequently thinning the high-resistivity layer. In embodiments of the disclosure, the thinning the high-resistivity wafer involves the backside grinding and chemical mechanical polishing (CMP) the high-resistivity layer. In further embodiments, the selective etching of the cavity comprises process 600 deep etching the low-resistivity substrate using a hard mask.

[0052] Numerous other changes, substitutions, variations, and modifications may be ascertained by the skilled in the art and it is intended that the present application encompass all such changes, substitutions, variations, and modifications as falling within the scope of the appended claims.

Claims

CLAIMS:

1. A hybrid interposer comprising:a low-resistivity substrate;a high-resistivity layer formed on the low-resistivity substrate;one or more transmission lines and at least one active circuit component disposed on the high-resistivity layer,wherein the low-resistivity substrate comprises a cavity selectively formed beneath the one or more transmission lines, the cavity having a length and a width equal to or greater than corresponding dimensions of the one or more transmission lines, andwherein the low- resistivity substrate remains continuous beneath the at least one active component.

2. The hybrid interposer according to claim 1, wherein the high-resistivity layer comprises high-resistivity polysilicon and the low-resistivity substrate comprises low-resistivity polycrystalline silicon carbide.

3. The hybrid interposer according to claim 1, wherein the high-resistivity layer and the low- resistivity substrate both comprise polycrystalline silicon carbide, wherein the high- resistivity layer has a higher resistivity than the low-resistivity substrate.

4. The hybrid interposer according to any one of claims 1 to 3, wherein the cavity has a depth extending partially through the low-resistivity substrate.

5. The hybrid interposer according to any one of claims 1 to 4, wherein the high-resistivity layer has a thickness between 2 pm and 30 pm.

6. The hybrid interposer according to any one of claims 1 to 4, wherein a ratio of a thickness of the high-resistivity layer to a thickness of the low-resistivity substrate is in a range of 1 : 1 to 1:250.

7. The hybrid interposer according to claim 1 wherein the low-resistivity substrate is configured to conduct heat generated by the at least one active circuit component away from the high-resistivity layer.

8. The hybrid interposer according to claim 1 wherein the cavity has a width of at least 100 pm.

9. A method of fabricating a hybrid interposer, the method comprising:providing a low-resistivity substrate;forming a high-resistivity layer on the low-resistivity substrate;forming one or more transmission lines and at least one active circuit component on the high-resistivity layer; andselectively etching a cavity into the low-resistivity substrate beneath the one or more transmission lines,wherein the cavity has a length and a width equal to or greater than corresponding dimensions of the one or more transmission lines, andwherein the low- resistivity substrate remains continuous beneath the at least one active circuit component.

10. The method according to claim 9, wherein the high-resistivity layer comprises high- resistivity polysilicon and the low- resistivity substrate comprises low-resistivity polycrystalline silicon carbide.

11. The method according to claim 9, wherein the high-resistivity layer and the low-resistivity substrate both comprise polycrystalline silicon carbide, wherein the high-resistivity layer has a higher resistivity than the low-resistivity substrate.

12. The method according to claim 9, wherein the forming the high-resistivity layer on the low- resistivity substrate comprises the step of:depositing the high-resistivity layer directly on the low-resistivity substrate.

13. The method according to claim 12, wherein the high-resistivity layer is deposited using chemical vapor deposition (CVD) or epitaxial growth.

14. The method according to claim 9, wherein the forming of the high-resistivity layer on the low-resistivity substrate comprises the step of:directly wafer bonding the high-resistivity layer to the low-resistivity substrate; and thinning the high-resistivity layer.

15. The method according to claim 14, wherein the thinning the high-resistivity wafer comprises the steps of:backside grinding and chemical mechanical polishing (CMP) the high-resistivity layer.

16. The method according to claim 9, wherein the selective etching of the cavity comprises the step of:deep etching the low-resistivity substrate using a hard mask.

17. The method according to claim 9, wherein the cavity is formed with a width of at least 100 pm.

18. The method according to claim 9, wherein the step of forming the high-resistivity layer comprises the step of:forming the high-resistivity layer with a thickness between 2 pm and 30 pm.

19. The method according to claim 9, wherein the high-resistivity layer and the low-resistivity substrate are formed such that a ratio of a thickness of the high-resistivity layer to a thickness of the low-resistivity substrate is in a range of 1 : 1 to 1 :250.

Images