Accurate port cross-references for circuit comparisons in electronic design automation (EDA)

Abstract

Systems and methods are presented for accurate port cross-reference determinations in different instances of a cell correspondences in circuit comparisons. A method may include accessing a source circuit design and a layout circuit design and identifying a cell correspondence. The cell correspondence may specify that a given cell in the source circuit design corresponds to a given cell in the layout circuit design. The method may also include performing a circuit comparison between the source circuit design and the layout circuit design, including by detecting a correspondence conflict in which multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design have different port cross-references and creating different port cross-references for the multiple cell correspondence placements. The method may further include adjusting the source circuit design, the layout circuit design, or both, based on the performed circuit comparison.

Description

202418224ACCURATE PORT CROSS-REFERENCES FOR CIRCUIT COMPARISONS IN ELECTRONIC DESIGN AUTOMATION (EDA)BACKGROUND

[0001] Electronic circuits, such as integrated circuits, are used in nearly every facet of modern society, from automobiles to microwaves to personal computers. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to, during, or after fabrication. EDA applications may implement various EDA procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Certain examples are described in the following detailed description and in reference to the drawings.

[0003] Figure 1 shows an example of a computing system that supports accurate port cross-references for circuit comparisons according to the present disclosure.

[0004] Figure 2 shows an example port cross-reference determination in response to a detected correspondence conflict.

[0005] Figure 3 shows an example port cross-reference determination based on a default port cross-reference.

[0006] Figure 4 shows another example port cross-reference determination in response to a detected correspondence conflict.202418224

[0007] Figure 5 shows an example of logic that a system may implement to support accurate port cross-references for circuit comparisons according to the present disclosure.

[0008] Figure 6 shows an example of a computing system that supports accurate port cross-references for circuit comparisons according to the present disclosure.DETAILED DESCRIPTION

[0009] Electronic circuits, such as integrated circuits (ICs), are used in nearly every facet of modern society, from automobiles to microwaves to personal computers. The design, verification, and physical manufacture of circuit devices often involve several steps, sometimes referred to as a "design flow." The particular steps of a design flow are dependent upon various factors, such as the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator (e.g., foundry) that will manufacture the physical circuit. Typically, software and hardware tools can verify the circuit designs at various stages of the design flow, for example through complex rule checks, software-based simulations, hardware-based emulation, and various other techniques supported by modern EDA technology. These steps of a design flow aid in the discovery of errors in circuit designs, and allow design teams and engineers to correct or otherwise improve the designs prior to, during, or after physical manufacture.

[0010] Several steps are common to most design flows of IC design. Initially, the specification for a new circuit can be transformed into or otherwise generated as a logical design. Logical designs are sometimes referred to as a register transfer level (RTL) description of a circuit. With logical designs, a circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high-speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed to confirm that the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as "functional verification."

[0011] After the accuracy of the logical design is confirmed through functional verification, a logical design can be converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist,202418224can describe the specific electronic devices (e.g., transistors, resistors, and capacitors) that form the circuit design, along with the interconnections between these electronic devices. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as "formal verification." Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.

[0012] Once the electronic devices components and their interconnections are established, the design can again be transformed in a design flow. In particular, the next transformation may be to a physical design that describes specific geometric elements that form the circuit design. This type of physical version of a circuit design is often referred to as a "layout" design or “physical layout” (and may simply be referred to as a “layout”). The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to physically manufacture the circuit. Automated place and route tools can be used to define or generate the physical layouts, especially for wires that will be used to interconnect the circuit devices in the physical representation of the circuit design. Each layer of a circuit can have a corresponding layer representation in the layout design, and the geometric shapes described in a layer representation will define the relative locations of the circuit elements that will make up the circuit device (e.g., of transistors, resistors, capacitors, etc.). For example, shapes in the layer representation of a metal layer will define the locations of the metal wires used to connect the circuit devices.

[0013] Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, GDSII contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other layout formats include an open-source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Siemens EDA (formerly Mentor Graphics Corporation), and the Open Artwork System Interchange Standard (OASIS) format proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are202418224used to define the geometrical information in IC layout designs that are employed to manufacture integrated circuits. Once the circuit design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the device using a photolithographic process.

[0014] Typically, a designer will perform a number of verification processes on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. In this process, a layout-versus-schematic (LVS) tool can extract a netlist from the layout design and compare it with the netlist taken from the circuit schematic. LVS can be augmented by formal equivalence checking, which checks whether two circuits perform exactly the same function without demanding isomorphism.

[0015] The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements and minimum linewidths of geometric elements. Such checks may be part of a design rule checking (DRC) process performed on layout design. DRC tools can take, as an input, a physical layout (e.g., in the GDSII or OASIS standard format) as well as a rule deck which specifies the specific rule checks to perform on the layout design. As checks in a DRC process can be specific to a particular circuit fabrication process, rule decks are typically provided by a foundry or circuit manufacturer specifying the particular rules that circuit designs must adhere to for circuit fabrication via the foundry (e.g., at a specified technology node or specific fabrication process parameters). Put another way, foundry-provided rule decks can include a list of rules specific to the semiconductor fabrication process employed by the foundry or otherwise selected for use in circuit manufacture. As such, a set of rules for a particular fabrication process can be referred to as a run-set, rule deck, or just a deck. An example format used for implementation of rule decks is the Standard Verification Rule Format (SVRF) by Siemens EDA (formerly Mentor Graphics Corporation).

[0016] There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive-type epitaxial layer is grown on a silicon substrate through chemical vapor202418224deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.

[0017] Each time that a layer of material is exposed to radiation, a photomask (mask) must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in a physical layout define the relative locations or areas of the circuit wafer that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the design layout, after which the mask can be used in a photolithographic process for fabrication of physical circuits. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. One of these techniques is optical proximity correction (OPC). OPC can be rule-based, model-based, or both. In rule-based OPC, the proximity effects are characterized, and specific solutions are devised for specific geometric configurations. The layout design is then searched using a DRC tool or a geometric-based software engine to find these geometric configurations. Once they are found, the specific solutions are applied. Through various steps of a design flow, the design, manufacture, and fabrication of circuits can be performed and supported through EDA technology.

[0018] While various steps of a design flow are described herein, circuit manufacture processes continue to evolve and may include any additional or alternative flow steps. Moreover, the intricacy of each step in a design flow is immense, especially as circuit designs continue to increase in complexity and as the transistors and other devices that form a circuit are merely a few atoms wide. As such, accurate and effective design202418224flow steps may increase the efficiency of circuit design and improvements at any given step in the design flow can yield significant benefits.

[0019] One aspect of the design flow that can benefit from improved efficiency and effectiveness is the LVS step. In LVS processes, IC design verification can involve comparing two versions of a circuit design to determine whether the compared circuits are equivalent. Often times, LVS involves the comparison of a physical layout with a circuit schematic, digital or logical circuit design (or another design form) in order to verify that the generated physical layout properly effectuates intended design behavior. In some examples, LVS circuit comparison processes can be used to perform layout-to-layout or schematic-to-schematic comparisons. Circuit designs are often represented as a hierarchical structure. In such hierarchical structures, circuit designs can be represented through hierarchical cells (or simply referred to as cells). A hierarchical cell may refer to any circuit design object that can be defined as well as used (e.g., referenced or placed) in the definition of an overall circuit design or in the definition of other cells in the circuit design. As such, the design of a given hierarchical cell may reference or contain instances of other cells, which may in turn reference or contain instances of other different cells, leading to a hierarchy of cells in an overall circuit design. Cells within a circuit design can be referenced any number of times, and each instance, use, or reference to a given cell in a circuit design can be referred to as a placement of the given cell.

[0020] For circuit design equivalence comparisons, one possibility is to compare the “flattened” version or each circuit in which every hierarchical cell instance in each of the compared circuit designs is replaced with the defined contents of the cell. Such a process may be referred to as a “flattening” because hierarchies and cells are replaced with the designed content and the entire circuit design is represented without any cells or hierarchies. However, with the continuously increasing complexities in modern circuit designs that can include billions of circuit elements, often more, the computational latency and resource requirements for such flattening operations to support direct circuit comparisons have become time-prohibitive and cost-prohibitive. Likewise, comparison processes for completely-flattened circuit designs can have incredibly high latencies, rendering LVS and other circuit comparison processes nearimpossible.202418224

[0021] As another possibility for circuit design equivalence comparisons, hierarchybased circuit comparisons have been developed to improved speed and efficiency. In such hierarchy-based circuit comparisons, two different circuit designs are compared on a cell-by-cell basis as specified according to the different hierarchies and cell placements present in the two compared designs. However, with such comparisons, including within an LVS context, the cell hierarchies of the two compared circuit designs typically do not match. This is the case when a one-to-one correspondence does not exist between each hierarchical cell in one compared circuit design to each hierarchical cell in the other compared circuit design. There may be some cell correspondences that exist, but at least some of the cells in one of the compared circuits do not correspond to any cells in the other compared circuit and vice versa. Thus, for any cells in a circuit design without a correspondence to a cell in the other compared circuit design, flattening must be performed in order to properly compare the two circuit designs. Corresponding cells between the layout and source circuit designs need not be flattened, and can be directly equated as equivalent based on specified correspondences. Thus, the greater the degree at which hierarchical cell correspondences are specified between two compared circuits, the less flattening operations need be performed and the greater the efficiency of circuit comparison processes.

[0022] As used herein, a cell correspondence or correspondence relationship between cells of circuit designs may refer to any form of specifying an equivalence relationship between the cells. Thus, a cell correspondence may specify that a given cell in a source circuit design corresponds to a given cell in a layout circuit design. Cell correspondences, also referred to as corresponding hierarchical cells or hierarchical cell correspondences, may be specified through user input, determined through circuit analyses, or configured in any other suitable manner. Correspondence mechanisms may include any format to express an equivalence between cells of two different circuit designs. In some EDA contexts, cell correspondences are referred to as “hcells” and the terms hcell, hcell correspondence, hcell relationship, and the like, are also used herein to refer to cell correspondences. Accordingly, a particular placement of corresponding hierarchical cells may refer to a specific placement of two corresponding cells in compared circuit designs, e.g., a particular placement of a hierarchical cell in a layout circuit design and a placement of a corresponding202418224hierarchical cell in a source circuit design. These placed cells may be deemed equivalent through the cell correspondence and, thus, need not be flattened for circuit comparison processes.

[0023] With the immense complexity of modern circuit designs, cell correspondences offer an efficient mechanism to specify equivalence relationships across entire hierarchical ranges, from low level hierarchical cells to higher level hierarchical cells, and possible top-level cells. For example, a given cell correspondence may be specified between two particular hierarchical cells of two circuit designs, and each of the particular hierarchical cells may be comprised of (e.g., reference, include instances of, etc.) other multiple or different cells of hierarchical level(s). Each of the referenced internal cells, which may be lower hierarchy cells, may include any number of cell ports (such as input ports, output ports, ground or power ports, etc.) A port cross-reference may specify how the ports of various lower hierarchy cells, within one of the particular hierarchical cells in the given cell correspondence, map to the ports of the corresponding lower hierarchy cells, within the other of the particular hierarchical cells in the given cell correspondence. Various illustrative examples of port cross-references are described within.

[0024] One benefit for cell correspondences in modern EDA contexts is that complete equivalence is not always required for cell correspondences to achieve efficiencies in circuit comparisons. That is, two cells in different circuit designs may be specified as equivalent by a cell correspondence even if the two cells are not completely identical. In that regard, cell correspondences may support identification or specification of logical equivalence between two cells even when structural or design differences exist between the two cells. For example, cell correspondences that specify equivalence between cells of different circuit designs may permit swappable placements, symmetric placements, or different port order configurations of lower hierarchical cells referenced (e.g., placed) within the cells of the different circuit designs. However, conventional EDA processes often cannot fully leverage or properly account for the flexibility of such cell correspondences. In particular, many conventional EDA circuit comparison processes assign the same port cross-reference for each placement of a cell correspondence. Such limitations in conventional systems may result in inaccurate port cross-references for LVS and other circuit comparison processes.202418224

[0025] This may be the case as conventional LVS processes may assign the same port cross-reference for each placement of a cell correspondence in compared circuit designs. However, with swappable or symmetric lower-hierarchical cell instances in compared cell correspondence placements, different port configurations can arise, even though such cell correspondence placements represent cells deemed equivalent between the compared circuit designs. Assignment of the same port cross-reference to each cell correspondence placement in circuit comparisons may thus result in inaccuracies, which often times require remedy through manual fixes. Accordingly, conventional circuit comparison processes that result in inaccurate port crossreference determinations may exhibit limited efficiency, increased latency, increased remedy procedures, and increase the time and cost of circuit designs overall.

[0026] The disclosure herein may provide systems, methods, devices, and logic for accurate port cross-references for circuit comparisons. The various technical features presented herein may be collectively referred to as accurate port cross-reference technology, and the disclosure herein may support creation of different port cross-references for different cell correspondence placements of the same cell correspondence. In contrast to conventional methods that solely assign a fixed port cross-reference to each and every cell correspondence placement for a given cell correspondence, the accurate port cross-reference technology described herein may instead create a different port cross-reference responsive to detected correspondence conflicts, as explained herein. The technical flexibility of the accurate port crossreference technology described herein may allow for accurate determination, creation, or assignment of port cross-references to cell correspondence placements on an individual basis. Accordingly, the accurate port cross-reference technology of the present disclosure may increase the efficiency and accuracy of LVS or other circuit comparisons, and thus improve modern EDA systems that support circuit design and manufacture.

[0027] These and other aspects of the accurate port cross-reference technology according to the present disclosure and the technical benefits of such are described in greater detail herein.

[0028] Figure 1 shows an example of a computing system that supports accurate port cross-references for circuit comparisons according to the present disclosure. The computing system 100 may take the form of a single or multiple computing devices202418224such as application servers, compute nodes, desktop or laptop computers, smart phones or other mobile devices, tablet devices, embedded controllers, and more. In some implementations, the computing system 100 hosts, instantiates, executes, supports, or implements an EDA application or EDA system that supports circuit design and analysis, and may accordingly provide or implement any of the accurate port cross-reference technology described herein.

[0029] As an example implementation to support any combination of the accurate port cross-reference technology described herein, the computing system 100 shown in Figure 1 includes a port cross-reference engine 110. The computing system 100 may implement the port cross-reference engine 110 (including components thereof) in various ways, for example as hardware and programming. The programming for the port cross-reference engine 110 may take the form of processor-executable instructions stored on a non-transitory machine-readable storage medium and the hardware for the port cross-reference engine 110 may include a processor to execute those instructions. A processor may take the form of single processor or multiprocessor systems, and in some examples, the computing system 100 implements multiple engines using the same computing system features or hardware components (e.g., a common processor or a common storage medium).

[0030] In operation, the port cross-reference engine 110 may access a source circuit design and a layout circuit design, such as the source circuit design 120 and the layout circuit design 130 shown in Figure 1. As used herein, a source circuit design and layout circuit design may refer to any two different circuit designs that can be compared. As such, the source circuit design 120 and the layout circuit design 130 may be of any format, representation, or produced as part of any step of an EDA design flow. In the LVS context, the source circuit design 120 may take the form of a device schematic or any data representation generated thereof (e.g., an extracted netlist, a graph representation of the cell hierarchy, etc.) and the layout circuit design 130 may take the form of a physical layout or any data representation generated thereof (e.g., an extracted netlist, a graph representation of the cell hierarchy, etc.). The port cross-reference engine 110 may access the source circuit design 120 and the layout circuit design 130 in any suitable manner, e.g., loading the circuit designs from memory, receiving the circuit designs across a communication network, through user-selection or input designs, etc. In modern EDA contexts, the source circuit design202418224120 and the layout circuit design 130 may be represented as multi-tier graphs in support of hierarchical circuit comparisons.

[0031] In operation, the port cross-reference engine 110 may identify a cell correspondence for the source circuit design and the layout circuit design. The cell correspondence may specify that a given cell in the source circuit design corresponds to a given cell in the layout circuit design. In operation, the port cross-reference engine 110 may also perform a circuit comparison between the source circuit design and the layout circuit design, including by detecting a correspondence conflict in which multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design have different port cross-references. A port crossreference may specify which ports of lower hierarchical cells referenced in the given cell in the source circuit design correspond to which ports of lower hierarchical cells referenced in the given cell in the layout circuit design. In performing the circuit comparison, the port cross-reference engine 110 may also create different port cross-references for the multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design. In operation, the port crossreference engine 110 may further adjust the source circuit design, the layout circuit design, or both, based on the performed circuit comparison.

[0032] These and other aspects of the accurate port cross-reference technology of the present disclosure are described in greater detail next.

[0033] Figure 2 shows an example port cross-reference determination in response to a detected correspondence conflict. The example of Figure 2 is described through the port cross-reference engine 110 as an implementation example, and various accurate port cross-reference features of the present disclosure are presented through performance of a circuit comparison between a source circuit design 120 and a layout circuit design 130 (e.g., as part of a LVS comparison or process). Various illustrative examples presented herein are also presented in the context of a cell correspondence 210 as shown in Figure 2. The cell correspondence 210 of Figure 2 specifies that cell SRC of the source circuit design 120 corresponds to cell BLYT in the layout circuit design 130. As noted herein, cell correspondences may provide a mechanism to specify cell equivalences between particular cells in the source and layout circuit designs, increasing the efficiency by which circuit comparisons can be performed (e.g., without flattening). The cell correspondence 210 in Figure 2 is one example of a cell202418224correspondence that the port cross-reference engine 110 may apply in performance of a circuit comparison, and the port cross-reference engine 110 may access and apply any number cell correspondences for the circuit comparison to identify circuit equivalences and reduce overall circuit flattening.

[0034] In performing a circuit comparison, the port cross-reference engine 110 may identify instances of the cell correspondence 210 that occur in the source circuit design 120 and the layout circuit design 130. Each instance of a cell correspondence that occurs in compared circuit designs may be referred to as a cell correspondence placement, and an individual cell correspondence placement may comprise a particular cell placement in the source circuit design 120 and a corresponding cell placement in the layout circuit design 130 (e.g., in one-to-one cell placement equivalences, though one-to-many, many-to-one, and many-to-many cell equivalences can be specified through cell correspondences and are supported by the accurate port-cross reference technology of the present disclosure). In a given circuit comparison, multiple distinct instances of a given cell correspondence may occur, and each distinct instance of the given cell correspondence may be respectively identified by the port cross-reference engine 110 as a different or distinct cell correspondence placement.

[0035] In the example of Figure 2, the port cross-reference engine 110 may identify a placement of the cell correspondence 210 in the compared circuit designs shown as cell correspondence placement 220. Any suitable identification process for cell correspondence placements is contemplated herein. For example, the port crossreference engine 110 may access (or convert) circuit designs in(to) the form of multitier graphs, with graph nodes representing hierarchical cells and different graph tiers representing different hierarchy levels in circuit designs. In such examples, the port cross-reference engine 110 may detect cell correspondence placements through detection of a particular graph node in the source circuit design 120 (represented in graph form) and a corresponding node in the layout circuit design 130 (represented in graph form). The port cross-reference engine 110 may apply or implement any suitable identification process or technology to identify cell correspondence placements in compared circuit designs. The cell correspondence placement 210 identified by the port cross-reference engine 110 in Figure 2 includes a distinct instance of cell ASRC in the source circuit design 120 and a corresponding instance of202418224cell BLYT in the layout circuit design 130. These distinct cell placements are shown in Figure 2 as cell placement 221 (which is also shown as cell Ai in Figure 2) and cell placement 222 (which is also shown as cell Bi in Figure 2).

[0036] Next, the port cross-reference engine 110 may determine a port crossreference for the cell correspondence placement 220. In doing so, the port crossreference engine 110 may compare cell Ai of the source circuit design (also identified in Figure 2 as cell placement 221) with its corresponding cell placement in the layout circuit design, in this case cell Bi (also identified in Figure 2 as cell placement 222). In such a comparison, the port cross-reference engine 110 may determine which ports of internal cell placements within cell Ai correspond to which ports of internal cell placements within cell Bi. Internal cell placements within a given cell placement may include cells of lower hierarchy in the overall circuit design, and the port crossreference engine 110 may identify which specific internal ports correspond between cells Ai and Bi. The port cross-reference engine 110 may do so in any suitable manner, and as supported by any LVS or other circuit comparison processes. In the specific example of Figure 2, cell Ai of the source circuit layout design includes placements of cell Xi and X2, including respective input ports, output ports, and ground ports. Cell Bi in the example of Figure 2 also includes placements of cell Xi and X2, including respective input ports, output ports, and ground ports. Various nets are illustrated in Figure 2, including neti, net2, and nets. The port cross-reference engine 110 may thus map a port configuration between the ports of cells Xi and X2 of cell Ai and the ports of cells Xi and X2 of cell Bi.

[0037] Accordingly, the port cross-reference engine 110 may create a port cross-references for cell correspondence placements identified in a circuit comparison process. As used herein, creating of a port cross-reference may include any process or technique by which a port cross-reference is determined, assigned, or specified. The format, process, or manner by which the port cross-reference engine 110 determines port cross-references between corresponding cells of circuit designs is flexible, and the port cross-reference engine 110 may employ any suitable technique, algorithm, or process to do so. In the example of Figure 2, the port cross-reference engine may determine a port cross-reference for the cell correspondence placement 220, and the port cross-reference may specify which ports of lower hierarchical cells202418224referenced in the cell Ai in the source circuit design 120 correspond to which ports of lower hierarchical cells referenced in cell Bi in the layout circuit design 130.

[0038] In some implementations, the port cross-reference engine 110 may create a default port cross-reference for a cell correspondence. A default port cross-reference may be used by the port cross-reference engine 110 to compare port cross-references determined for cell correspondence placements, as explained further herein. The port cross-reference engine 110 may set an initially-determined port cross-reference for a given cell correspondence as the default port cross-reference for the given cell correspondence. To illustrate, the port cross-reference engine 110 may identify and determine multiple placements of the cell correspondence 210 in a circuit comparison between the source circuit design 120 and the layout circuit design 130. In such an example, the port cross-reference engine 110 may identify the cell correspondence placement 220 as an initial (e.g., first) instance of the cell correspondence 210, and determine a port cross-reference for the cell correspondence placement 220. Then, the port cross-reference engine 110 may create a default port cross-reference for the cell correspondence placement 210 that specifies corresponding ports between the cell placement 221 in the source circuit design 120 and the cell placement 222 in the layout circuit design 130. In other examples, the port cross-reference engine 110 may determine a default port cross-reference for a cell correspondence prior to performing a circuit comparison, e.g., through analysis of the specified cell correspondence, via user input or configuration, or in any other suitable manner.

[0039] As this may be the initial (e.g., first) port cross-reference determined for the cell correspondence 210 in the circuit comparison, the port cross-reference engine 110 may set the port cross-reference determined for the cell correspondence placement 220 as a default port cross-reference for the cell correspondence 210. Such an example is shown in Figure 2 through the default port cross-reference 230 created, determined, set, or assigned by the port cross-reference engine 110. Subsequent port cross-references determined for other placements of a cell correspondence may be compared against a default port cross-reference, e.g., as described in greater detail herein. Note that default port cross references may be cell correspondence-specific. In the example of Figure 2, the port cross-reference engine 110 may set the default port cross-reference as particular (e.g., specifically-applicable) to the cell correspondence 210. Other cell correspondences in the circuit comparison202418224between the source circuit design 120 and the layout circuit design 130 may be characterized by or assigned their own respective default port cross-references, which the port cross-reference engine 110 may determine or set in any consistent manner described herein.

[0040] In performing circuit comparisons, the port cross-reference engine 110 may detect correspondence conflicts. A correspondence conflict may refer to cell correspondence placements of the same cell correspondence that have differing port cross-references. As such, the port cross-reference engine 110 may detect a correspondence conflict in which multiple cell correspondence placements of a cell correspondence in the source circuit design 120 and the layout circuit design 130 have different port cross-references. An example detection of a correspondence conflict for the cell correspondence 210 is illustrated in Figure 2.

[0041] In Figure 2, the port cross-reference engine 110 identifies a second cell correspondence placement, shown in Figure 2 as the cell correspondence placement 240. The cell correspondence placement 240 may differ from the cell correspondence placement 220 in that each represents a different (e.g., distinct) placement of corresponding cells in the source circuit design 120 and the layout circuit design 130. In the example of Figure 2, the cell correspondence placement 240 comprises a second cell placement of a given cell in the source circuit design 120 (shown as cell placement 241 and labeled as cell A2) and a second cell placement of a given cell in the layout circuit design 130 (shown as cell placement 242 and labeled as cell B2). In this example, the port cross-reference engine 110 may detect a correspondence conflict between the cell correspondence placements by determining that a port crossreference between cells A2 and B2 of the cell correspondence placement 240 is different from the default port cross-reference 230 (which, also represents the port cross-reference of cell correspondence placement 220).

[0042] As noted herein, differences in port cross-references for the placements of the same cell correspondence is possible in modern LVS processes and other EDA contexts. One illustration of such a possibility is illustrated through the internal cell X2 of cell placements of the cell correspondence 210. Within cell placements Bi and B2 of the layout circuit design 130, internal cell X2 is placed differently in cell placements Bi and B2 respectively, shown in a mirrored manner in Figure 2. Such a mirrored placement of internal cell placements may be permitted in cell correspondences, for202418224example when a mirrored placements of a same internal cell are functionally or logically equivalent in the context of higher-level cell comparisons. However, such mirrored placements may result in inconsistent port cross-references between the placements of the same cell correspondence, e.g., as shown in Figure 2. Any number of causes, logic, or EDA features may result in inconsistent port cross-references, and the accurate port cross-reference technology of the present disclosure may flexibly address any such scenarios. In contrast to conventional methods that solely assign a fixed port cross-reference to each and every cell correspondence placement for a given cell correspondence, the accurate port cross-reference technology described herein may instead create a different port cross-reference responsive to detected correspondence conflicts.

[0043] In the example of Figure 2, the port cross-reference engine 110 creates different port cross-references for the cell correspondence placement 220 and the cell correspondence 240. The port cross-reference 110 may do so responsive to detection of the correspondence conflict between the determined port cross-reference for the cell correspondence placement 240 and the default port cross-reference 230. In such a scenario, the port cross-reference engine 110 may create a port cross-reference for the second cell correspondence placement (e.g., the cell correspondence placement 240) that specifies corresponding ports between the second cell placement of the given cell in the source circuit design (e.g., A2) and the second cell placement of the given cell in the layout circuit design (e.g., B2). In the example of Figure 2, the port cross-reference engine 110 creates the port cross-reference 250 for the cell correspondence placement 240, which may differ from the port cross-reference assigned to the cell correspondence placement 220 (and also set as the default port cross-reference 230 for the cell correspondence 210).

[0044] In detecting correspondence conflicts for a cell correspondence, the port cross-reference engine 110 need not compare a port cross-reference determined for a given cell correspondence placement with each other previously determined port cross-reference for the cell correspondence 210. Instead, the port cross-reference engine 110 may leverage the default port cross-reference 230 determined for the cell correspondence 210 and may compare any subsequently-determined port cross-references for placements of the cell correspondence 210 with only the default port cross-reference 230. In such examples, the port cross-reference engine 110 may202418224either determine that (i) a subsequently-determined port cross-reference matches the default port cross-reference 230 (in which case, the default port cross-reference 230 can be assigned to the cell correspondence placement) or (ii) a subsequently-determined port cross-reference does not match the default port cross-reference 230 (in which case a correspondence conflict is detected, and a different port crossreference from the default port cross-reference is assigned).

[0045] Through use of the default port cross-reference, increased efficiency and effectiveness of port cross-reference assignments can be achieved by the accurate port-cross reference technology described herein. The relatively-low computing resource requirements and processing latency for a single comparison to the default port cross-reference 230 may allow the port cross-reference engine 110 to speedily detect correspondence conflicts and address the detected conflicts accordingly. For port cross-references that match the default port cross-reference 230, the port crossreference engine 110 need not perform further comparisons to detect correspondence conflicts, and instead assign the default port cross-reference 230 to cell correspondence placements with an identical port cross-reference. For port cross-references that do not match the default port cross-reference 230, the port crossreference engine 110 can detect a conflict correspondence through a single port crossreference comparison, and need not perform further comparisons. Instead, the port cross-reference engine 110 can create a different port cross-reference to address the correspondence conflict (detected through a single port cross-reference comparison). As such, the port cross-reference engine 110 may leverage a default port crossreference to support accurate port cross-references in circuit comparisons with increased efficiency and effectiveness, reduced computational latencies, and while flexibly resolving inconsistent port cross-references for different placements of the same cell correspondence.

[0046] Illustrative examples of such default port cross-reference comparisons are presented next with reference to Figures 3 and 4.

[0047] Figure 3 shows an example port cross-reference determination based on a default port cross-reference. The example of Figure 3 continues the description of Figure 2 in which the port cross-reference engine 110 determines a default port crossreference 230 for the cell correspondence 210. In the example of Figure 3, the port cross-reference engine 110 may continue to perform a circuit comparison between the202418224source circuit design 120 and the layout circuit design 130, and in doing so identify another placement of the cell correspondence 210. In particular, the port crossreference engine 110 may identify the cell correspondence placement 310 of Figure 3 that comprises a cell placement 311 in the source circuit design 120 (also shown in Figure 3 as cell A3) and a cell placement 312 in the layout circuit design 130 (also shown in Figure 3 as cell B3).

[0048] The port cross-reference engine 110 may determine a port cross-reference for the cell correspondence placement 310 and then compare the determined port cross-reference with the default port cross-reference 230 specified or otherwise set for the cell correspondence 210. In this example of Figure 3, the port cross-reference engine 110 may determine that the port cross-reference for the cell correspondence placement 310 is identical to the default port cross-reference 230. This may be the case as the placement of lower hierarchical cells Xi and X2 in each of cells A3 and B3 respectively are identical to that of cell correspondence placement 220, and thus the individual cell ports for lower hierarchical cells Xi and X2 in each of cells A3 and B3 may have identical nets from one another. For this reason, the determined port crossreference for cell correspondence placement 310 may likewise be identical to the default port cross-reference 230. In response to such a determination of matching (e.g., identical) port cross-references, the port cross-reference engine 110 may assign the default port cross reference 230 as the port cross-reference for the cell correspondence placement 230.

[0049] Thus, the example of Figure 3 may provide an example in which the port cross-reference engine 110 may identify a third cell correspondence placement (in this case, the cell correspondence placement 310) that comprises a third cell placement of the given cell in a source circuit design (in this case, cell A3) and a third cell placement of the given cell in a layout circuit design (in this case, cell B3). In this example, the port cross-reference engine 110 may determine that a port crossreference for the third cell correspondence placement (in this case, the cell correspondence placement 310) is identical to the default port cross-reference. In response, the port cross-reference engine 110 may assign the port cross-reference determined for the cell correspondence placement 220 (and set as the default port cross-reference 230) to the third cell correspondence placement (in this case, the cell correspondence placement 310).202418224

[0050] Figure 4 shows another example port cross-reference determination in response to a detected correspondence conflict. The example of Figure 4 continues the description of Figure 2 in which the port cross-reference engine 110 determines a default port cross-reference 230 for the cell correspondence 210. In the example of Figure 4, the port cross-reference engine 110 may continue to perform a circuit comparison between the source circuit design 120 and the layout circuit design 130 (e.g., subsequent to the features and comparison of Figure 3), and in doing so identify another placement of the cell correspondence 210. In particular, the port crossreference engine 110 may identify the cell correspondence placement 410 of Figure 4 that comprises a cell placement 411 in the source circuit design 120 (also shown in Figure 4 as cell A4) and a cell placement 412 in the layout circuit design 130 (also shown in Figure 4 as cell B4).

[0051] The port cross-reference engine 110 may determine a port cross-reference for the cell correspondence placement 410 and then compare the determined port cross-reference with the default port cross-reference 230 set for the cell correspondence 210. In this example of Figure 4, the port cross-reference engine 110 may determine that the port cross-reference for the cell correspondence placement 310 is different from the default port cross-reference 230. This may be the case as the placement of lower hierarchical cells Xi and X2 in each of cells A3 and B3 respectively are different to that of cell correspondence placement 220 (from which the default port cross-reference 230 was set). Accordingly, the port cross-reference engine 110 may detect a correspondence conflict and, in response, create a port cross-reference different from the default port cross-reference 230 to assign to the cell correspondence placement 410. In the example of Figure 4, the port cross-reference engine 110 creates the port cross-reference 420 for the cell correspondence placement 410.

[0052] Thus, the example of Figure 4 may provide an example in which the port cross-reference engine 110 may identify a fourth cell correspondence placement (in this case, the cell correspondence placement 410) that comprises a fourth cell placement of the given cell in a source circuit design (in this case, cell A4) and a fourth cell placement of the given cell in a layout circuit design (in this case, cell B4). In this example, the port cross-reference engine 110 may determine that a port crossreference for the fourth cell correspondence placement (in this case, the cell202418224correspondence placement 410) is different from the default port cross-reference 230. In response, the port cross-reference engine 110 may create a port cross-reference for the fourth cell correspondence placement (in this case, the cell correspondence placement 410) that specifies corresponding ports between the fourth cell placement of the given cell in the source circuit design (in this case, cell A4) and the fourth cell placement of the given cell in the layout circuit design (in this case, cell B4).

[0053] In some implementations, the port cross-reference engine 110 may assign a default port cross-reference to each cell correspondence placement of a given cell correspondence. Such uniform assignment of port cross-references may be similar or consistent with conventional methods in which the same port cross-reference is assigned to every instance of a cell correspondence. However, in contrast to conventional methods and systems, the port cross-reference engine 110 may adaptively create different port cross-references for any cell correspondence placements with a differing port cross-reference from the default port cross-reference. In these examples, in response to detection of a correspondence conflict, the port cross-reference engine 110 may duplicate the port cross-reference data of the cell correspondence (in this case, that includes the default port cross-reference). Then, the port cross-reference engine 110 may set the port cross-reference of the duplicated data to that of the differing port cross-reference, e.g., by changing the default port cross-reference to the differing port cross-reference in the duplicated data. This new data may then be assigned to the specific cell correspondence placement with the differing port cross-references, flexibly allowing creation of different port cross-references. Any of the these described features may be implemented consistently, as part of, or alternatively to any other accurate port cross-reference features described herein.

[0054] In some implementations, the port cross-reference engine 110 may maintain a common graph topology for each placement of a cell correspondence even though different placements of the cell correspondence are assigned different port cross-references. For circuit designs implemented as multi-level graphs, for example, such a feature may reduce memory footprints so that each cell correspondence placement with differing port cross-reference need not consume additional (and possibly duplicative) memory footprints with duplicated graph topologies. As the graph for different cell correspondence placements may remain consistent despite differing port202418224cross-references, the port cross-reference engine 110 need not completely duplicate each cell correspondence node responsive to a detected correspondence conflict. Instead, the port cross-reference engine 110 may have these differing cell correspondence placements (e.g., nodes) point to the same graph topology, while duplicating and updating port cross-reference data to address the differing port cross-references, which may result in more efficient memory footprints, reduced resource requirements, and increased efficiency in LVS or other circuit comparison processes.

[0055] The port cross-reference engine 110 may implement or support any type of reporting features in support of accurate port cross-references. For example, the port cross-reference engine 110 may report the different port cross-references determined for multiple cell correspondence placements of a cell correspondence as part of an output of the circuit comparison performed for the source circuit design 120 and the layout circuit design 130. In some implementations, the port cross-reference may separately report determined port cross-references for each cell correspondence placement of a given cell correspondence. Such reporting features may be configurable (e.g., by user input), and the port cross-reference engine 110 may implement, provide, or otherwise support and custom or configurable reporting features. In some implementations, the port cross-reference engine 110 may report each port cross-reference determined for multiple cell correspondence placements of a cell correspondence, doing so in any suitable format.

[0056] Any number of applications or subsequent processing based on the performed circuit design are contemplated herein. For example, the port crossreference engine 110 may adjust the source circuit design, the layout circuit design, or both, based on the performed circuit comparison (e.g., automatically and / or responsive to user input or based on user-specified modifications). Any suitable adjustments to circuit designs are contemplated herein, including to address issues or other errors detected through the circuit comparison The port cross-reference engine 110 may implement any additional or alternative practical application or technical effect based on the performed circuit comparison, including further circuit analyses, adaptations, or circuit manufacture / fabrication of compared or adjusted circuit designs.

[0057] Figure 5 shows an example of logic 500 that a system may implement to support accurate port cross-references for circuit comparisons according to the present disclosure. For example, the computing system 100 may implement the logic202418224500 as hardware, executable instructions stored on a machine-readable medium, or as a combination of both. The computing system 100 may implement the logic 500 via the port cross-reference engine 110, through which the computing system 100 may perform or execute the logic 500 as a method to support accurate port cross-references in circuit comparisons according to the present disclosure. The following description of the logic 500 is provided using the port cross-reference engine 110 as an example implementation. However, other implementation options by computing systems are possible.

[0058] In implementing the logic 500, the port cross-reference engine 110 may access a source circuit design and a layout circuit design (502) and identify a cell correspondence for the source circuit design and the layout circuit design (504). The cell correspondence may specify that a given cell in the source circuit design corresponds to a given cell in the layout circuit design. In implementing the logic 500, the port cross-reference engine 110 may also perform a circuit comparison between the source circuit design and the layout circuit design (506), including by detecting a correspondence conflict in which multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design have different port cross-references (508) and creating different port cross-references for the multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design (510). In implementing the logic 500, the port cross-reference engine 110 may further adjust the source circuit design, the layout circuit design, or both, based on the performed circuit comparison (512). Any suitable adjustments to circuit designs are contemplated herein, including to address issues or other errors detected through the circuit comparison The port cross-reference engine 110 may implement any additional or alternative practical application or technical effect based on the performed circuit comparison, including further circuit analyses, adaptations, or circuit fabrication for compared circuit designs.

[0059] The logic 500 shown in Figure 5 provides an illustrative example by which a computing system 100 may support or implement various features of the accurate port cross-reference technology described herein. Additional or alternative steps in the logic 500 are contemplated herein, including according to any of the various features described herein for the port cross-reference engine 110.202418224

[0060] Figure 6 shows an example of a computing system 600 that supports accurate port cross-references for circuit comparisons according to the present disclosure. The computing system 600 may include a processor 610, which may take the form of a single or multiple processors. The processor(s) 610 may include a central processing unit (CPU), microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. The computing system 600 may include a machine-readable medium 620. The machine-readable medium 620 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as the port cross-reference instructions 622 shown in Figure 6. As such, the machine-readable medium 620 may be, for example, Random Access Memory (RAM) such as a dynamic RAM (DRAM), flash memory, spin-transfer torque memory, an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disk, and the like.

[0061] The computing system 600 may execute instructions stored on the machine-readable medium 620 through the processor 610. Executing the instructions (e.g., the port cross-reference instructions 622) may cause the computing system 600 to perform or implement any of the accurate port cross-reference technology described herein, including according to any aspect of the port cross-reference engine 110.

[0062] For example, execution of the port cross-reference instructions 622 by the processor 610 may cause the computing system 600 to access a source circuit design and a layout circuit design as well as identify a cell correspondence for the source circuit design and the layout circuit design. Execution of the port cross-reference instructions 622 by the processor 610 may also cause the computing system 600 to perform a circuit comparison between the source circuit design and the layout circuit design, including by detecting a correspondence conflict in which multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design have different port cross-references and creating different port cross-references for the multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design. Execution of the port cross-reference instructions 622 by the processor 610 may further cause the computing system 600 to adjust the source circuit design, the layout circuit design, or both, based on the performed circuit comparison.202418224

[0063] Any combination of the accurate port cross-reference technology as described herein may be implemented via the port cross-reference instructions 622.

[0064] The systems, methods, devices, and logic described above, including the port cross-reference engine 110, may be implemented in many different ways in many different combinations of hardware, logic, circuitry, and executable instructions stored on a machine-readable medium. For example, the port cross-reference engine 110, may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any of the description above, including according to any features of the port cross-reference engine 110.

[0065] The processing capability of the systems, devices, and engines described herein, including the port cross-reference engine 110, may be distributed among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many ways, including data structures such as linked lists, hash tables, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library (e.g., a shared library).

[0066] While various examples and features have been described above, many more implementations are possible.

Claims

202418224CLAIMS1. A method comprising:by a computing system:accessing a source circuit design and a layout circuit design;identifying a cell correspondence for the source circuit design and the layout circuit design, wherein the cell correspondence specifies that a given cell in the source circuit design corresponds to a given cell in the layout circuit design;performing a circuit comparison between the source circuit design and the layout circuit design, including by:detecting a correspondence conflict in which multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design have different port cross-references, wherein a port cross-reference specifies which ports of lower hierarchical cells referenced in the given cell in the source circuit design correspond to which ports of lower hierarchical cells referenced in the given cell in the layout circuit design; andcreating different port cross-references for the multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design; and adjusting the source circuit design, the layout circuit design, or both, based on the performed circuit comparison.

2. The method of claim 1 , wherein detecting the correspondence conflict and creating the different port cross-references comprises:identifying a first cell correspondence placement that comprises a first cell placement of the given cell in the source circuit design and a first cell placement of the given cell in the layout circuit design; andcreating a port cross-reference for the first cell correspondence placement that specifies corresponding ports between the first cell placement of the given cell in the source circuit design and the first cell placement of the given cell in the layout circuit design; and202418224setting the port cross-reference for the first cell correspondence placement as a default port cross-reference.

3. The method of claim 2, wherein detecting the correspondence conflict and creating the different port cross-references further comprises:identifying a second cell correspondence placement that comprises a second cell placement of the given cell in the source circuit design and a second cell placement of the given cell in the layout circuit design;detecting the correspondence conflict by determining that a port crossreference for the second cell placement of the given cell in the source circuit design and the second cell placement of the given cell in the layout circuit design is different from the default port cross-reference; and, in response:creating a port cross-reference for the second cell correspondence placement that specifies corresponding ports between the second cell placement of the given cell in the source circuit design and the second cell placement of the given cell in the layout circuit design.

4. The method of claim 3, further comprising:identifying a third cell correspondence placement that comprises a third cell placement of the given cell in the source circuit design and a third cell placement of the given cell in the layout circuit design;determining that a port cross-reference for the third cell correspondence placement is identical to the default port cross-reference, and in response:assigning the first port cross-reference to the third cell correspondence placement.

5. The method of claim 4, further comprising:identifying a fourth cell correspondence placement that comprises a fourth cell placement of the given cell in the source circuit design and a fourth cell placement of the given cell in the layout circuit design;determining that a port cross-reference for the fourth cell correspondence placement is different from the default port cross-reference, and in response:202418224creating a port cross-reference for the fourth cell correspondence placement that specifies corresponding ports between the fourth cell placement of the given cell in the source circuit design and the fourth cell placement of the given cell in the layout circuit design,wherein the port cross-reference for the fourth cell correspondence placement is identical to the port cross-reference for the second cell correspondence placement.

6. The method of any of claims 1 -5, further comprising maintaining a common graph topology for each placement of the cell correspondence even though different placements of the cell correspondence are assigned different port cross-references.

7. The method of any of claims 1 -6, further comprising reporting the different port cross-references for the multiple cell correspondence placements of the cell correspondence as part of an output of the circuit comparison.

8. A system comprising:a processor; anda non-transitory machine-readable medium comprising instructions that, when executed by the processor, cause a computing system to:access a source circuit design and a layout circuit design; identify a cell correspondence for the source circuit design and the layout circuit design, wherein the cell correspondence specifies that a given cell in the source circuit design corresponds to a given cell in the layout circuit design;perform a circuit comparison between the source circuit design and the layout circuit design, including by:detecting a correspondence conflict in which multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design have different port cross-references, wherein a port cross-reference specifies which ports of lower hierarchical cells referenced in the given cell in the202418224source circuit design correspond to which ports of lower hierarchical cells referenced in the given cell in the layout circuit design; andcreating different port cross-references for the multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design; andadjust the source circuit design, the layout circuit design, or both, based on the performed circuit comparison.

9. The system of claim 8, wherein the instructions cause the computing system to detect the correspondence conflict and creating the different port cross-references by:identifying a first cell correspondence placement that comprises a first cell placement of the given cell in the source circuit design and a first cell placement of the given cell in the layout circuit design; andcreating a port cross-reference for the first cell correspondence placement that specifies corresponding ports between the first cell placement of the given cell in the source circuit design and the first cell placement of the given cell in the layout circuit design; andsetting the port cross-reference for the first cell correspondence placement as a default port cross-reference.

10. The system of claim 9, wherein the instructions cause the computing system to detect the correspondence conflict and creating the different port cross-references further by:identifying a second cell correspondence placement that comprises a second cell placement of the given cell in the source circuit design and a second cell placement of the given cell in the layout circuit design;detecting the correspondence conflict by determining that a port crossreference for the second cell placement of the given cell in the source circuit design and the second cell placement of the given cell in the layout circuit design is different from the default port cross-reference; and, in response:202418224creating a port cross-reference for the second cell correspondence placement that specifies corresponding ports between the second cell placement of the given cell in the source circuit design and the second cell placement of the given cell in the layout circuit design.

11. The system of claim 10, wherein the instructions further cause the computing system to:identify a third cell correspondence placement that comprises a third cell placement of the given cell in the source circuit design and a third cell placement of the given cell in the layout circuit design;determine that a port cross-reference for the third cell correspondence placement is identical to the default port cross-reference, and in response:assign the first port cross-reference to the third cell correspondence placement.

12. The system of claim 11 , wherein the instructions further cause the computing system to:identify a fourth cell correspondence placement that comprises a fourth cell placement of the given cell in the source circuit design and a fourth cell placement of the given cell in the layout circuit design;determine that a port cross-reference for the fourth cell correspondence placement is different from the default port cross-reference, and in response:create a port cross-reference for the fourth cell correspondence placement that specifies corresponding ports between the fourth cell placement of the given cell in the source circuit design and the fourth cell placement of the given cell in the layout circuit designwherein the port cross-reference for the fourth cell correspondence placement is identical to the port cross-reference for the second cell correspondence placement.

13. The system of any of claims 8-12, wherein the instructions further cause the computing system to maintain a common graph topology for each placement of the202418224cell correspondence even though different placements of the cell correspondence are assigned different port cross-references.

14. The system of any of claims 8-13, wherein the instructions further cause the computing system to report the different port cross-references for the multiple cell correspondence placements of the cell correspondence as part of an output of the circuit comparison.

15. A non-transitory machine readable medium comprising instructions that, when executed by a processor, cause a computing system to perform a method according to any of claims 1-7.

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