Structure design for piezoelectric acoustic transistor

Abstract

The present disclosure relates to semiconductor transistor devices, particularly piezoelectric acoustic transistors including lattice-matched nitride semiconductor heterostructures that modulate conductivity in response to applied acoustic pressure. A piezoelectric acoustic transistor includes a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, an active region disposed on the barrier layer including periodic heterostructures, each heterostructure including a first active layer and a second active layer that are lattice matched, a top layer disposed on the active region, and first and second side contact electrodes positioned on opposite sides of the active region, wherein the active region modulates conductivity in response to applied acoustic pressure by forming a two-dimensional electron gas or hole gas at interfaces between the first and second active layers.

Description

STRUCTURE DESIGN FOR PIEZOELECTRIC ACOUSTIC TRANSISTOR CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Application No. 63 / 759,641, titled Structure Design for Piezoelectric Acoustic Transistor, filed 18 February 2025, which is hereby incorporated by reference in its entirety.FIELD OF INVENTION

[0002] The present disclosure relates to semiconductor transistor devices, and more particularly to piezoelectric acoustic transistors comprising lattice-matched nitride semiconductor heterostructures that modulate conductivity in response to applied acoustic pressure.BACKGROUND

[0003] Power semiconductor devices serve as fundamental building blocks in modem electrical systems, enabling the control and conversion of electrical energy across a wide range of applications. Conventional power transistors, including metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and high electron mobility transistors (HEMTs), operate by modulating current flow through the application of electric fields to gate terminals. These devices have been implemented using various semiconductor materials, including silicon, silicon carbide, and gallium nitride, to address different voltage, current, and switching frequency requirements. Ilf-Nitride semiconductor materials, such as gallium nitride (GaN), aluminum nitride (AIN), and their alloys, have attracted attention for power electronics applications due to their wide bandgap properties, high breakdown fields, and strong piezoelectric characteristics. Heterostructure devices utilizing these materials can form two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channels at heterojunction interfaces due to polarization-induced charge accumulation.

[0004] However, conventional field-effect power transistors suffer from several limitations that constrain their performance in high-power applications. Traditional devices modulate current through thin channel regions where electric field effects control conductivity, which limits the volume available for current transport and creates thermal management challenges. The1325233825v3requirement for electrical gate terminals introduces complexities in high-voltage applications, including gate driver isolation requirements, switching losses associated with gate charging and discharging, and susceptibility to electromagnetic interference that can cause false triggering. Furthermore, series-connected gate configurations used to achieve higher voltage ratings introduce timing accuracy limitations and potential failure modes. Conventional devices also face compromises in drift region doping, where minimal doping is preferred for off-state voltage blocking but higher doping is desired for reduced on-state conduction losses, resulting in suboptimal performance in both states. Heat extraction in traditional devices is typically limited to a single side due to the presence of gate structures, constraining thermal dissipation capacity.

[0005] What is needed, therefore, is an improved transistor structure that enables current modulation through mechanisms other than electric field gating, allowing for increased currentcarrying volume and enhanced thermal management. A piezoelectric acoustic transistor (PAT) is one such newly realized device that uses an applied mechanical force, pressure applied to a piezo-conductive structure, to modulate the conductivity of a large volume semiconductor structure from an insulating state to a conducting state. Exemplary PAT devices are disclosed in International Patent Publication No. WO2024 / 211059, entitled "Disappearing Polarization HeteroSuperjunction Acoustic Switch (DiPHAS)," which is incorporated herein by reference in its entirety. One could use lattice mismatched structures that have different atomic spacings resulting in stored mechanical energy that increases with increasing thickness for a PAT. These lattice mismatched PAT structures would enhance the sensitivity to applied external pressure, but limits the overall thickness of the structure due to exceeding a critical thickness where the strain exceeds the energy required to form dislocations, an electrically harmful defect that can also lead to cracking of the crystalline PAT structure. Thus, such lattice mis-matched structures would be less desirable sense they would limit the thickness of the PAT to less than a critical thickness and in doing so, limit the current the PAT could carry. Given the PAT is inherently a large structure including a rigid frame and a piezoelectric actuator, the small currents a lattice mismatched structure would facilitate would find little practical use. The place of value for a PAT is in the very high current, very high voltage space where one PAT may replace sizably large utility equipment or large power circuits with a simpler, smaller and more efficient switching device. Thus, a PAT structure would benefit from lattice-matched semiconductor heterostructures where the heterostructures have the same atomic spacings and thus, can be grown without mechanical strain,2325233825v3dislocations and cracking. Such lattice matched structures permit thick, crack-free epitaxial layers while maintaining the piezoelectric properties necessary for pressure-responsive conductivity modulation, with carefully engineered doping profiles and layer configurations to achieve both high off-state resistance and low on-state resistance.SUMMARY

[0006] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] A piezoelectric acoustic transistor can include a substrate. The piezoelectric acoustic transistor can include a buffer layer disposed on the substrate. The piezoelectric acoustic transistor can include a barrier layer disposed on the buffer layer and may also include strain reduction layers. The piezoelectric acoustic transistor can include an active region disposed on the barrier layer, the active region including a plurality of periodic heterostructures, each heterostructure including a first active layer and a second active layer, wherein the first active layer and the second active layer are lattice matched. The piezoelectric acoustic transistor can include a top layer disposed on the active region. The piezoelectric acoustic transistor can include a first side contact electrode and a second side contact electrode positioned on opposite sides of the active region, wherein the active region is configured to modulate conductivity in response to applied acoustic pressure by forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at interfaces between the first active layer and the second active layer.

[0008] A piezoelectric acoustic transistor can include a substrate. The piezoelectric acoustic transistor can include a buffer layer disposed on the substrate and including a fll-nitride material. The piezoelectric acoustic transistor can include a barrier layer disposed on the buffer layer. The piezoelectric acoustic transistor can include an active region disposed on the barrier layer, the active region including at least one heterostructure having a first active layer including a first fll-nitride material and a second active layer including a second Ill-nitride material different from the first Ill-nitride material, wherein the first active layer and the second active layer are lattice matched to the buffer layer. The piezoelectric acoustic transistor can include a top layer disposed on the active region. The piezoelectric acoustic transistor can include side contact electrodes 3325233825v3configured to provide electrical contact to the active region. The piezoelectric acoustic transistor can include interfacial doping at heterojunction interfaces within the active region configured to position a Fermi level within a bandgap of the active region in an off-state and to enable formation of conducting channels at the heterojunction interfaces in an on-state responsive to applied acoustic stress.

[0009] A method of operating a piezoelectric acoustic transistor can include providing a piezoelectric acoustic transistor including a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, an active region disposed on the barrier layer including a plurality of lattice-matched heterostructures each having a first active layer and a second active layer, a top layer disposed on the active region, and side contact electrodes. The method can include maintaining the piezoelectric acoustic transistor in an off-state wherein a Fermi level is positioned within a bandgap of the active region such that substantially no free carriers are available for conduction. The method can include applying acoustic pressure to the piezoelectric acoustic transistor to transition the piezoelectric acoustic transistor to an on-state, wherein the applied acoustic pressure induces piezoelectric polarization changes that cause energy bands within the active region to bend around a pinned Fermi level position, thereby forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at heterojunction interfaces within the active region.

[0010] The foregoing general description of the illustrative embodiments and the following detailed description thereof are merely exemplary aspects of the teachings of this disclosure and are not restrictive.BRIEF DESCRIPTION OF FIGURES

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of the presently disclosed subject matter and serve to explain the principles of the presently disclosed subject matter. The drawings are not intended to limit the scope of the presently disclosed subject matter in any manner.

[0012] FIG. 1 illustrates a cross-sectional view of a piezoelectric acoustic transistor, according to examples of the disclosed technology.4325233825v3

[0013] FIG. 2 illustrates a band diagram for a doped heterostructure at zero stress, according to examples of the disclosed technology.

[0014] FIG. 3 illustrates a band diagram for a doped heterostructure under applied stress showing channel formation, according to examples of the disclosed technology.DETAILED DESCRIPTION

[0015] Piezoelectric acoustic transistors represent a class of semiconductor devices that modulate conductivity in response to applied acoustic pressure rather than through application of an electric field. Unlike conventional power transistors that rely on electrical gating to control current flow through thin channels, piezoelectric acoustic transistors respond to acoustic stress to switch current. This approach eliminates the need for an electrical gate, thereby removing complexities associated with series-connected, electrically triggered gates that can limit switching timing accuracy and contribute to device failures.

[0016] Piezoelectric acoustic transistors can utilize lattice-matched nitride semiconductor heterostructures to achieve high-performance pressure -modulated switching. Lattice matching between adjacent semiconductor layers allows for growth of structures with virtually unlimited thicknesses without the material cracking or forming defects that would otherwise degrade device performance. Because piezoelectric acoustic transistors switch large volumes of material instead of thin channels as is typical in conventional power transistors, the device architecture scales in three dimensions instead of two dimensions. This three-dimensional volumetric scaling makes practically any current and voltage achievable within the limitations of heat dissipation.

[0017] The three-dimensional scaling architecture of piezoelectric acoustic transistors provides thermal management advantages over conventional switching devices. Heat dissipation in piezoelectric acoustic transistors can be approximately 250% better than existing switching devices due to the volumetric nature of current conduction rather than confinement to thin two-dimensional channels. This improved thermal performance enables operation at higher power levels without thermal degradation.

[0018] Piezoelectric acoustic transistors can operate at utility-scale voltages in the tens to hundreds of kilovolts. The ability to handle such high voltages in a single device enables new power distribution paradigms. For example, piezoelectric acoustic transistors can enable single 5325233825v3device switching at utility scale for smart grid applications. Such smart grid technologies can redistribute selected amounts of energy anywhere on a utility grid, potentially replacing costly transformers with solid-state versions and enabling widespread adoption of point source renewable energy that would otherwise require centralized infrastructure due to excessive transformer costs.

[0019] Although various aspects of the disclosed technology are explained in detail herein, it is to be understood that other aspects of the disclosed technology are contemplated. Accordingly, it is not intended that the disclosed technology is limited in its scope to the details of construction and arrangement of components expressly set forth in the following description or illustrated in the drawings. The disclosed technology can be implemented and practiced or carried out in various ways.

[0020] It should also be noted that, as used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise. References to a composition containing “a” constituent is intended to include other constituents in addition to the one named.

[0021] Also, in describing the disclosed technology, terminology will be resorted to for the sake of clarity. It is intended that each term contemplates its broadest meaning as understood by those skilled in the art and includes all technical equivalents which operate in a similar manner to accomplish a similar purpose.

[0022] Ranges may be expressed herein as from “about” or “approximately” or “substantially” one particular value and / or to “about” or “approximately” or “substantially” another particular value. When such a range is expressed, the disclosed technology can include from the one particular value and / or to the other particular value. Further, ranges described as being between a first value and a second value are inclusive of the first and second values. Likewise, ranges described as being from a first value and to a second value are inclusive of the first and second values.

[0023] Herein, the use of terms such as “having,” “has,” “including,” or “includes” are open-ended and are intended to have the same meaning as terms such as “comprising” or “comprises” and not preclude the presence of other structure, material, or acts. Similarly, though the use of terms such as “can” or “may” are intended to be open-ended and to reflect that structure, material, or acts are not necessary, the failure to use such terms is not intended to reflect that structure,6325233825v3material, or acts are essential. To the extent that structure, material, or acts are presently considered to be essential, they are identified as such.

[0024] Herein, the use of terms such as “layer” does not preclude the existence of other layers that could also exist. For example, a channel layer may be composed of several subchannel layers. Some of these sub-channel layers may themselves be composed of several layers such as barrier and conducting layers that may impede or conduct electricity, introduce polarization discontinuities that form and deplete electrical carriers or otherwise support the function of the electrical conduction and modulation. Likewise, the semiconductor structure may be composed of additional layers such as buffer layers, strain reduction layers or insulation layers above, below or intermixed with the channel layer.

[0025] The components described hereinafter as making up various elements of the disclosed technology are intended to be illustrative and not restrictive. Many suitable components that would perform the same or similar functions as the components described herein are intended to be embraced within the scope of the disclosed technology. Such other components not described herein can include, but are not limited to, similar components that are developed after development of the presently disclosed subject matter.

[0026] Referring now to the drawings, in which like numerals represent like elements, the present disclosure is herein described. Referring to FIG. 1 , a piezoelectric acoustic transistor 100 includes a layered semiconductor structure configured to modulate conductivity in response to applied acoustic pressure. The piezoelectric acoustic transistor 100 comprises a substrate 125 positioned at a bottom of the layered structure. A buffer layer 120 is disposed on the substrate 125. A barrier layer 115 is disposed on the buffer layer 120. An active region 110 is disposed on the barrier layer 115. A top layer 105 is disposed on the active region 110. A first side contact electrode 131 and a second side contact electrode 132 are positioned on opposite sides of the active region 110.

[0027] The substrate 125 provides foundational support for the piezoelectric acoustic transistor 100. The buffer layer 120 is configured to mitigate strain and dislocations between the7325233825v3substrate 125 and layers disposed above the buffer layer 120. The barrier layer 115 separates the buffer layer 120 from the active region 110.

[0028] With continued reference to FIG. 1, the active region 110 comprises a plurality of periodic heterostructures. Each heterostructure comprises a first active layer 111 and a second active layer 112. The first active layer 111 and the second active layer 112 are lattice matched. The first active layer 111 and the second active layer 112 form an alternating pattern within the active region 110, with the alternating pattern controlling electrical and piezoelectric properties of the piezoelectric acoustic transistor 100. The piezoelectric acoustic transistor 100 can leverage lattice-matched nitride semiconductor heterostructures including GaN / AlScN and GaN / AlInN with strong piezoelectric properties.

[0029] The active region 110 is configured to modulate conductivity in response to applied acoustic pressure by forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at interfaces between the first active layer 111 and the second active layer 112. The two-dimensional electron gas and the two-dimensional hole gas can be referred to herein as conducting channels. The modulation of two-dimensional electron gas or two-dimensional hole gas densities under applied pressure enables the piezoelectric acoustic transistor 100 to switch between conductive and non-conductive states.

[0030] As further shown in FIG. 1 , the first side contact electrode 131 and the second side contact electrode 132 extend vertically along the active region 110. The first side contact electrode 131 and the second side contact electrode 132 are configured to provide electrical contact to the active region 110. The first side contact electrode 131 and the second side contact electrode 132 are precisely positioned based on structural dimensions of the piezoelectric acoustic transistor 100 to enable optimized electrical performance.

[0031] The piezoelectric acoustic transistor 100 utilizes a modular design where the periodic heterostructures of the active region 110 can be repeated. A single heterostructure block comprising the first active layer 111 and the second active layer 112 can be designed and then repeated over and over for any thickness to handle any current level. This modular approach allows the piezoelectric acoustic transistor 100 to scale to handle different current requirements by adding additional periodic heterostructures to the active region 110.8325233825v3

[0032] The substrate 125 can comprise a material selected from the group consisting of silicon, silicon carbide, gallium nitride, and aluminum nitride. The substrate 125 can also comprise any other material known to facilitate Ill-nitride epitaxy. Silicon substrates provide a cost-effective option with established manufacturing infrastructure. Silicon carbide substrates offer high thermal conductivity for improved heat dissipation. Gallium nitride substrates provide lattice matching advantages for subsequent Ill-nitride layer growth. Aluminum nitride substrates offer compatibility with aluminum- containing barrier and active layers.

[0033] The substrate 125 can have an arbitrary thickness, with no constraints on the substrate thickness range. The selection of substrate thickness can be based on mechanical handling requirements, thermal management considerations, and compatibility with downstream processing equipment. The arbitrary nature of the substrate thickness allows for flexibility in device design and manufacturing processes without imposing limitations on the overall device architecture.

[0034] The buffer layer 120 comprises a III -nitride material. The buffer layer 120 can have a thickness of 0.1 pm to 50 pm. The thickness of the buffer layer 120 is not a constraint on device performance, and the buffer layer thickness can be selected based on manufacturing considerations and compatibility with the substrate 125 and subsequent layers.

[0035] The buffer layer 120 can comprise a material selected from the group consisting of gallium nitride, aluminum nitride, aluminum scandium nitride, aluminum gallium nitride, aluminum yttrium nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z=1.0. The selection of buffer layer material provides flexibility in establishing the lattice constant for the device structure.

[0036] As described previously, the buffer layer 120 is configured to mitigate strain and dislocations between the substrate 125 and layers disposed above the buffer layer 120. The buffer layer material is chosen to select the lattice constant to be matched in subsequent barrier and active layers, establishing the lattice matching reference for the device structure. By selecting an appropriate buffer layer composition, the lattice constant of the buffer layer 120 defines the reference lattice parameter that subsequent layers, including the barrier layer 115 and the active region 110, can be lattice matched to. This lattice matching reference established by the buffer layer 120 enables growth of thick heterostructures without accumulation of strain-induced defects that would otherwise degrade electrical performance.9325233825v3

[0037] Gallium nitride buffer layers provide compatibility with gallium nitride -based active layers and offer established growth processes. Aluminum nitride buffer layers can provide compatibility with aluminum-containing barrier layers and offer high thermal conductivity. Aluminum scandium nitride, aluminum gallium nitride, aluminum yttrium nitride, and aluminum indium nitride buffer layers allow for tuning of the lattice constant to match specific active region compositions. Combinations of AlvGawScxInyYzN provide additional flexibility in selecting the lattice constant for lattice matching with subsequent layers in the device structure.

[0038] The barrier layer 115 can have a thickness of 50 nm to 5000 nm. The selection of barrier layer thickness within this range provides flexibility in device design while maintaining appropriate separation between the buffer layer 120 and the active region 110.

[0039] The barrier layer 115 can comprise a material selected from the group consisting of aluminum scandium nitride, aluminum yttrium nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z=1.0. Aluminum scandium nitride barrier layers offer strong piezoelectric properties and compatibility with gallium nitride-based active layers. Aluminum yttrium nitride barrier layers provide an alternative composition for lattice matching applications. Aluminum indium nitride barrier layers allow for tuning of lattice constant and bandgap properties. Combinations of AlvGawScxInyYzN provide additional compositional flexibility for achieving desired lattice matching and piezoelectric characteristics.

[0040] The barrier layer 115 can be lattice matched to the active region 110 and the buffer layer 120. Lattice matching of the barrier layer 115 to adjacent layers reduces strain accumulation and associated defect formation at interfaces. By selecting a barrier layer composition that provides lattice matching to both the buffer layer 120 below and the active region 110 above, the barrier layer 115 maintains structural integrity throughout the device stack.

[0041] As described previously, the barrier layer 115 separates the buffer layer 120 from the active region 110. The barrier layer 115 enhances sensitivity of doping concentrations to balance polarization charges. This balancing of polarization charges through doping sensitivity ensures high off-resistance when the piezoelectric acoustic transistor 100 is not pressure -modulated. The10325233825v3barrier layer 115 thereby contributes to maintaining the piezoelectric acoustic transistor 100 in a non-conductive state in the absence of applied acoustic pressure.

[0042] The active region 110 comprises at least one heterostructure having a first active layer 111 comprising a first Ill-nitride material and a second active layer 112 comprising a second III-nitride material different from the first Ill-nitride material. The first active layer 111 and the second active layer 112 are lattice matched to the buffer layer 120. As described previously, the active region 110 can comprise a plurality of periodic heterostructures, each heterostructure comprising the first active layer 111 and the second active layer 112.

[0043] The first Ill-nitride material of the first active layer 111 can comprise gallium nitride. The first active layer 111 can have a thickness of 2 nm to 10,000 nm. The first active layer 111 material is selected to be lattice matched to the second active layer 112 and the buffer layer 120. Gallium nitride provides a narrower bandgap material within the heterostructure that forms the conducting channels when the piezoelectric acoustic transistor 100 transitions to an on-state under applied acoustic pressure.

[0044] The second Ill-nitride material of the second active layer 112 can comprise a material selected from the group consisting of aluminum scandium nitride, aluminum indium nitride, and aluminum yttrium nitride. The second active layer 112 can have a thickness of 2 nm to 100 nm. The second active layer 112 material is selected to be lattice matched to the first active layer 111 and the buffer layer 120. Aluminum scandium nitride, aluminum indium nitride, and aluminum yttrium nitride each provide wider bandgap materials with strong piezoelectric properties that enable pressure-responsive conductivity modulation at the heterointerfaces.

[0045] The thickness of the first active layer 111 involves tradeoffs between doping sensitivity and pressure modulation. Thicker first active layers 111 comprising gallium nitride channels increase doping sensitivity, which is undesirable for maintaining precise control over the off-state characteristics. However, increased thickness of the first active layer 111 can enhance pressure modulation by providing a larger volume of material responsive to applied acoustic stress. The selection of first active layer 111 thickness within the 2 nm to 10,000 nm range balances these competing considerations based on the desired device characteristics.

[0046] The second active layer 112 controls doping sensitivity and pressure modulation within the active region 110. The second active layer 112 affects high off-resistance stability of 11325233825v3the piezoelectric acoustic transistor 100. By selecting the composition and thickness of the second active layer 112, the sensitivity of the active region 110 to doping variations can be controlled while maintaining stable high off-resistance when the piezoelectric acoustic transistor 100 is not pressure -modulated.

[0047] The lattice-matched structures of the active region 110 allow growth of virtually unlimited thicknesses without the material cracking. Lattice matching between the first active layer 111 and the second active layer 112, and between the active region 110 and the buffer layer 120, eliminates accumulation of mechanical strain that would otherwise cause relaxation and defect formation in thicker structures. The lattice-matched approach trades off the need for more pressure to achieve the same actuation effect compared to strained heterostructures. In strained heterostructures, the pre-existing mechanical strain reduces the additional pressure required to induce conductivity changes, whereas lattice-matched structures require application of greater acoustic pressure to achieve equivalent piezoelectric polarization changes. This tradeoff enables fabrication of arbitrarily thick active regions 110 that can handle higher currents while requiring higher applied pressures for switching.

[0048] The top layer can comprise a material selected from the group consisting of aluminum scandium nitride, aluminum yttrium nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l , 0<w<l , 0<x<l , 0<y<l , 0<z<l , and v+w+x+y+z=l .0. Aluminum scandium nitride top layers provide strong piezoelectric properties and compatibility with the underlying active region. Aluminum yttrium nitride top layers offer an alternative composition for achieving desired bandgap and lattice characteristics. Aluminum indium nitride top layers allow for tuning of material properties based on indium content. Combinations of AlvGawScxInyYzN provide compositional flexibility for achieving specific device performance characteristics.

[0049] The top layer can have a thickness of 50 nm to 5000 nm. The selection of top layer thickness within this range provides flexibility in device design and affects the doping sensitivity and pressure modulation characteristics of the piezoelectric acoustic transistor.

[0050] The piezoelectric acoustic transistor can have a symmetrical design where the top layer thickness matches the barrier layer thickness. In the symmetrical design configuration, matching the top layer thickness to the barrier layer thickness reduces doping sensitivity. Reduced doping12325233825v3sensitivity in the symmetrical design provides more tolerance to variations in doping concentrations during fabrication while maintaining device performance characteristics.

[0051] The piezoelectric acoustic transistor can have an asymmetrical design where the top layer thickness differs from the barrier layer thickness. In the asymmetrical design configuration, the top layer thickness between 50 nm and 5000 nm increases doping sensitivity and improves pressure modulation. The asymmetrical design enhances the responsiveness of the piezoelectric acoustic transistor to applied acoustic pressure by increasing the sensitivity of the active region to piezoelectric polarization changes induced by the applied stress.

[0052] In the off-state, a wider bandgap material for the top layer suppresses parasitic free carrier density when the top layer represents a local extremum of electrostatic potential. The wider bandgap of the top layer material creates an energy barrier that prevents accumulation of free carriers at the top surface of the device structure in the absence of applied acoustic pressure. This suppression of parasitic free carrier density contributes to maintaining high off-resistance when the piezoelectric acoustic transistor is not pressure -modulated.

[0053] The top layer may or may not be lattice matched to the buffer layer. In configurations where the top layer is lattice matched to the buffer layer, strain accumulation at the interface between the top layer and the active region is minimized. In configurations where the top layer is not lattice matched to the buffer layer, the top layer composition can be selected to optimize other device characteristics such as bandgap width or piezoelectric response independent of lattice matching constraints. This flexibility in lattice matching of the top layer allows for optimization of device performance based on the specific application requirements.

[0054] The piezoelectric acoustic transistor can have a total length of 1 pm to 5000 pm. The total length is chosen to withstand voltages ranging from 500 V to 500 kV. Longer device lengths provide greater voltage standoff capability by distributing the electric field over a larger distance, reducing the peak electric field strength within the semiconductor material. The selection of device length within this range allows for tailoring of the voltage handling capability to specific application requirements.

[0055] The piezoelectric acoustic transistor can have a total width of 0.01 mm to 10 cm. The total width is chosen in conjunction with the total thickness to handle desired current from 1 A to 100 kA. Wider devices provide greater cross-sectional area for current flow, reducing current 13325233825v3density and associated resistive losses. The combination of device width and thickness determines the total current handling capability of the piezoelectric acoustic transistor.

[0056] The total device thickness is the sum of all individual layers including the substrate, the buffer layer, the barrier layer, the active region, and the top layer. The total device thickness is designed to handle the desired current in conjunction with the device width and the active layer thickness. The total device thickness is constrained by the size of the pressure application device. For example, diamond anvil cell integration imposes constraints on the maximum device thickness that can be accommodated within the pressure application apparatus. The pressure application device determines the maximum physical dimensions of the piezoelectric acoustic transistor that can receive uniform acoustic pressure across the device structure and can be in the range of 0.1 to 5 mm.

[0057] The modular repeatable block design of the active region enables scaling of the piezoelectric acoustic transistor to handle different current and voltage requirements. Each periodic heterostructure comprising the first active layer and the second active layer forms a repeatable unit that can be added to increase current handling capability. By repeating the heterostructure block, additional conducting channels are formed in parallel when the device transitions to the on-state, with each channel contributing to the total current carrying capacity.

[0058] The three-dimensional volumetric scaling capability of the piezoelectric acoustic transistor distinguishes the device architecture from conventional power transistors that scale in two dimensions. Conventional power transistors conduct current through thin channels, limiting current handling to the two-dimensional cross-sectional area of the channel. The piezoelectric acoustic transistor conducts current through the entire volume of the active region when in the on-state, enabling three-dimensional scaling of current handling capability. This volumetric conduction allows the piezoelectric acoustic transistor to achieve current handling capabilities that scale with the cube of linear dimensions rather than the square of linear dimensions as in conventional two-dimensional channel devices.

[0059] The piezoelectric acoustic transistor can achieve resistance values lower than 1 ohm in high power configurations. For example, a 10 kV / 10 A device configuration can achieve subohm resistance when the piezoelectric acoustic transistor transitions to the on-state under applied acoustic pressure. The low on-state resistance results from the formation of high-density two- 14325233825v3dimensional electron gas and two-dimensional hole gas channels at multiple heterointerfaces within the active region, with the parallel combination of conducting channels reducing the total device resistance. The sub-ohm resistance in high power configurations enables efficient power switching with minimal resistive losses during the on-state.

[0060] The number of repeated layers in the active region determines heterojunction density, which directly affects on / off resistance characteristics of the piezoelectric acoustic transistor. Each repetition of the heterostructure comprising the first active layer and the second active layer introduces additional heterojunction interfaces where two-dimensional electron gas and two-dimensional hole gas channels can form under applied acoustic pressure. The heterojunction density increases proportionally with the number of repeated layers, with each additional heterojunction providing additional parallel conduction paths when the device transitions to the on-state.

[0061] More layers in the active region result in lower on-state resistance. As the number of repeated heterostructures increases, the number of parallel conducting channels formed at heterojunction interfaces increases correspondingly. The parallel combination of multiple conducting channels reduces the total resistance of the active region in the on-state. Each additional heterojunction contributes an additional conduction path that carries a portion of the total device current, with the parallel resistance combination yielding progressively lower total resistance as more layers are added.

[0062] Fewer layers in the active region result in higher off-state resistance. With fewer heterojunction interfaces, there are fewer potential sites where parasitic conduction could occur in the absence of applied acoustic pressure. The reduced number of interfaces limits the total area where unintended carrier accumulation could degrade off-state isolation. The relationship between layer count and off-state resistance allows for tailoring of the device characteristics based on the specific isolation requirements of the application.

[0063] The lower limit for the number of repeated layers is 1 repetition. A single repetition comprises one heterojunction, such as one GaN / AlScN heterojunction. A device with a single heterojunction provides the minimum heterostructure configuration capable of forming a conducting channel under applied acoustic pressure. The single heterojunction configuration15325233825v3provides the highest off-state resistance due to the minimal number of interfaces where carrier accumulation could occur, while providing a single conducting channel in the on-state.

[0064] The upper limit for the number of repeated layers is constrained by fabrication limits and desired device current. Fabrication limits include epitaxial growth capabilities, uniformity of layer thickness and composition across multiple repetitions, and total growth time considerations. The desired device current determines the number of parallel conducting channels needed to achieve the target current handling capability with acceptable current density in each channel. As the number of repetitions increases, the total thickness of the active region increases correspondingly, with the maximum practical thickness determined by the intersection of fabrication capabilities and application requirements. The absence of a fundamental upper limit on the number of repetitions enables scaling of the piezoelectric acoustic transistor to handle arbitrarily high currents within the constraints imposed by manufacturing processes and thermal management considerations.

[0065] The active region can comprise interfacial doping at heterojunction interfaces between the first active layer and the second active layer. The interfacial doping can have a concentration 17 3 21 3of 1X10 cm' to 5><10 cm' . The interfacial doping is configured to position a Fermi level within a bandgap of the active region in an off-state and to enable formation of conducting channels at the heterojunction interfaces in an on-state responsive to applied acoustic stress.

[0066] Doping placement within the active region is governed by the need to place average superlattice semiconductor energy bands in a position where the Fermi level is inside the bandgap to prevent conduction in the off-state. When the Fermi level is positioned sufficiently within the bandgap of all layers, substantially few electrical carriers including electrons and holes are available for conduction. The off-state can be characterized by a carrier concentration of less than1x10 cm , indicating that the Fermi level positioning achieved through interfacial doping effectively suppresses free carrier populations that would otherwise enable parasitic conduction.

[0067] Doping placement is also governed by the need to prevent the average superlattice semiconductor energy bands within each superlattice period from becoming slanted. Band slanting corresponds to an average electric field throughout the layers of the active region. If a rise in the average band energy across a period of the superlattice versus distance occurs, then the device can16325233825v3experience parts of the device that turn on while others remain off. By suppressing any average electric field throughout the layers through appropriate doping placement, uniform switching behavior across the entire active region can be achieved when acoustic pressure is applied.

[0068] The interfacial doping is configured to partially or completely neutralize polarization-induced charges at the heterojunction interfaces. In Ill-nitride semiconductor heterostructures, each unit cell has a net charge on its surfaces, with one surface positive and one surface negative. When the semiconductor composition changes at a heterojunction interface, the difference in polarization between adjacent materials creates a net polarization-induced charge at the interface. This polarization-induced charge can attract free carriers that would degrade off-state isolation. By introducing interfacial doping at concentrations sufficient to neutralize these polarization-induced charges, the active region maintains high off-state resistance in the absence of applied acoustic pressure.

[0069] For low repetition layer configurations, doping occurs at the top and bottom of the active region and at the heterojunction between the barrier layer and the substrate. This doping placement at the boundaries of the active region establishes the Fermi level position relative to the energy bands at the interfaces where the active region meets adjacent layers. The doping at the top of the active region controls the interface between the active region and the top layer, while the doping at the bottom of the active region controls the interface between the active region and the barrier layer. The doping at the heterojunction between the barrier layer and the substrate provides additional control over the energy band alignment throughout the device structure.

[0070] For high repetition layer configurations, additional doping is introduced at multiple heterojunctions within the active region. The additional doping at multiple heterojunctions partially or completely neutralizes polarization-induced charges at heterointerfaces throughout the active region. As the number of repeated heterostructures increases, the number of heterojunction interfaces where polarization-induced charges accumulate increases correspondingly. The high repetition doping configuration addresses each of these interfaces to maintain uniform Fermi level positioning and prevent band slanting across the entire thickness of the active region. This distributed doping approach ensures that each period of the superlattice maintains the same energy band configuration relative to the Fermi level, enabling uniform switching behavior when acoustic pressure is applied regardless of the total number of repeated layers in the active region.17325233825v3

[0071] The active region can further comprise strip doping layers configured to suppress free carriers in an off-state. As used herein, the term “strip doping” refers to a localized, laterally extended and vertically confined doped semiconductor region disposed within an active device structure, the region having a thickness substantially smaller than adjacent semiconductor layers and a doping concentration greater than that of the surrounding material, the region being positioned to control the local Fermi level and banned edge alignment so as to suppress free carrier population in a non-operational or off-state of the device. The strip doping layers can have a thickness of 1 nm to 50 nm and a doping concentration of 1x10 cm' to 5x10 cm' . The strip doping layers are configured to align a Fermi level at mid-bandgap to ensure high off-resistance when the piezoelectric acoustic transistor is not pressure-modulated.

[0072] The strip doping layers can be positioned within the active region at interfaces between the narrower bandgap material and the wider bandgap material. The strip doping layers provide targeted doping to suppress free carriers in the off-state by controlling the Fermi level position relative to the conduction band and valence band edges. By aligning the Fermi level at midbandgap through the strip doping layers, the energy separation between the Fermi level and both band edges is maximized, minimizing the thermal population of free carriers in both the conduction band and the valence band.

[0073] The strip doping layers enhance pressure modulation sensitivity of active region channels. By establishing a well-defined Fermi level position at mid-bandgap through the strip doping layers, the active region becomes more responsive to piezoelectric polarization changes induced by applied acoustic pressure. The enhanced pressure modulation sensitivity results from the strip doping layers creating a reference energy position around which the energy bands can pivot when acoustic stress is applied. This pivot point behavior enables the energy bands to bend symmetrically above and below the pinned Fermi level position, facilitating formation of both two-dimensional electron gas and two-dimensional hole gas channels at heterojunction interfaces under applied acoustic pressure.

[0074] The strip doping layers can comprise N-type doping configured to suppress free hole density or P-type doping configured to suppress free electron density or semi-insulating impurity dopants that pin the fermi level inside the bandgap as described later. N-type doping introduces donor impurities that provide excess electrons, which recombine with free holes to reduce the free 18325233825v3hole population in the material. P-type doping introduces acceptor impurities that provide excess holes, which recombine with free electrons to reduce the free electron population in the material. The selection of N-type or P-type doping for the strip doping layers depends on the dominant carrier type that would otherwise be present in the absence of the strip doping.

[0075] Semi-insulating dopants can be used in the strip doping layers to pin the Fermi level in the desired position. Semi-insulating dopants act as N-type in a P-type material and as P-type in an N-type material to pin the Fermi level. This amphoteric behavior of semi-insulating dopants provides self-compensating characteristics that drive the Fermi level toward mid-bandgap or toward the semi-insulating trap impurity energy regardless of the background carrier type in the surrounding material. In regions where the material would otherwise be P-type due to background acceptors or polarization-induced hole accumulation, the semi-insulating dopants act as donors to compensate the acceptors and shift the Fermi level toward mid-bandgap or toward the semiinsulating trap impurity energy. In regions where the material would otherwise be N-type due to background donors or polarization-induced electron accumulation, the semi-insulating dopants act as acceptors to compensate the donors and shift the Fermi level toward mid-bandgap.

[0076] The semi-insulating dopant behavior enables the strip doping layers to establish a pinned Fermi level position that serves as a fulcrum for the energy band bending under applied acoustic pressure. The pinned Fermi level position remains fixed while the conduction band and valence band energies change in response to piezoelectric polarization changes induced by the applied stress. This fulcrum-like behavior creates a seesaw or teeter-totter effect where the energy bands on one side of the pinned position bend upward while the energy bands on the opposite side bend downward. The seesaw behavior enables simultaneous formation of two-dimensional hole gas channels where the valence band crosses above the Fermi level and two-dimensional electron gas channels where the conduction band crosses below the Fermi level when acoustic pressure is applied.

[0077] The piezoelectric acoustic transistor can have an unintentional background doping of less than1*10 cm . Unintentional background doping refers to impurities and defects that are incorporated into the semiconductor material during epitaxial growth processes without deliberate introduction. These unintentional dopants can include residual impurities from source materials, chamber contamination, and native point defects that form during crystal growth. Maintaining 19325233825v316 3unintentional background doping below 1x10 cm reduces the population of free carriers that would otherwise contribute to parasitic conduction in the off-state.16 3

[0078] The unintentional background doping can be kept below 5X10 cm for acceptable 16 3 off-resistance performance. The unintentional background doping can be kept below 1x10 cm for improved off-resistance performance. The unintentional background doping is most preferably kept below 1x10 cm' for optimal off-resistance. Lower unintentional background doping levels reduce the baseline free carrier concentration in the active region, which directly improves the off-state isolation characteristics of the piezoelectric acoustic transistor. The reduction in unintentional background doping minimizes the need for compensating doping to achieve the desired Fermi level positioning within the bandgap.16 3

[0079] The off-state is characterized by a carrier concentration of less than 1x10 cm . The off-state can be defined as when the Fermi level is sufficiently within the bandgap of all layers such that there are substantially few electrical carriers, including electrons and holes, available for conduction. When the carrier concentration is maintained below 1x10 cm in the off-state, the piezoelectric acoustic transistor exhibits high off-resistance that provides effective isolation between the first side contact electrode and the second side contact electrode in the absence of applied acoustic pressure.

[0080] The conducting channels comprise at least one of a two-dimensional electron gas and 17 3a two-dimensional hole gas having a charge density greater than 1x10 cm' in the on-state. The interfacial doping described previously is designed to enable uniform and substantially high charge densities at heterojunctions in the on-state for low on-resistance. When acoustic pressure is applied to the piezoelectric acoustic transistor, the piezoelectric polarization changes induce band bending that causes the conduction band to cross below the Fermi level at certain heterojunction interfaces and the valence band to cross above the Fermi level at other heterojunction interfaces. This band crossing results in accumulation of free carriers at the heterojunction interfaces, forming the two-dimensional electron gas and two-dimensional hole gas channels with charge densities exceeding IxlO17cm'3.20325233825v318 3

[0081] The charge density in the on-state can be greater than 1x10 cm' . Higher charge densities in the conducting channels reduce the sheet resistance of each two-dimensional electron gas and two-dimensional hole gas channel, which reduces the total on-state resistance of the piezoelectric acoustic transistor. The charge density is greater than 1x10 cm' in the on-state for configurations requiring the lowest on-state resistance. Charge densities exceeding 1x10 cm' provide conducting channels with sheet carrier concentrations that enable sub-ohm total device resistance when multiple parallel channels are formed throughout the active region under applied acoustic pressure.16 3

[0082] The contrast between the off-state carrier concentration of less than 1x10 cm and the on-state charge density greater than1x10 cm' provides a switching ratio of at least 10 between the on-state and off-state conductivity. When the on-state charge density exceeds 1 x 1019cm' , the switching ratio between on-state and off-state conductivity exceeds 1000. This large switching ratio enables the piezoelectric acoustic transistor to function as an effective switch that transitions between a highly insulating off-state and a highly conductive on-state in response to applied acoustic pressure. When the off-state carrier concentration is less than 1 x 1016cm-3and the on-state carrier concentration is greater than 1 x 1019cm-3, even better switching ratios are realized.

[0083] The piezoelectric acoustic transistor can further comprise trap states in at least one of the substrate, the barrier layer, and the top layer. Trap states known to introduce deep energy states within the energy bandgap can be introduced to control Fermi level placement within the bandgap in a similar manner as described previously for shallower energy doping with acceptors and donors. Deep energy states are defined as states greater than 0.25 electron volts from either majority carrier band edge. The trap states are configured to pin a Fermi level within an energy bandgap, providing an alternative or complementary mechanism to the interfacial doping and strip doping approaches described previously for establishing the desired Fermi level position.

[0084] Optional trap states can be introduced in the substrate. Trap states in the substrate can compensate for unintentional background doping in the substrate material, reducing the contribution of substrate carriers to parasitic conduction paths. Optional trap states can be introduced in the barrier layer. Trap states in the barrier layer can pin the Fermi level within the bandgap of the barrier layer material, preventing accumulation of free carriers at the interface 21325233825v3between the barrier layer and adjacent layers. Optional trap states can be introduced in the top layer. Trap states in the top layer can suppress parasitic free carrier density at the top surface of the device structure, complementing the wider bandgap suppression mechanism described previously.

[0085] Optional trap states can be introduced at heterojunction interfaces. The heterojunction interfaces where trap states can be introduced include the substrate / barrier interface between the substrate and the barrier layer, the barrier / active region interface between the barrier layer and the active region, and the active region / top layer interface between the active region and the top layer. Trap states at heterojunction interfaces can compensate for polarization-induced charges that would otherwise attract free carriers to the interface, reducing carrier accumulation that would degrade off-state isolation.19 3

[0086] Bulk material traps can be introduced at concentrations of 0 to 5X10 cm" . The trap 19 3states can have a concentration of up to 5*10 cm" . Bulk material traps compensate for background doping by pinning the Fermi level to a desired energy level inside the energy bandgap. The deep energy level of the trap states, being greater than 0.25 electron volts from the majority carrier band edge, provides a stable pinning position that is less susceptible to thermal excitation of carriers compared to shallow dopant levels. By introducing bulk material traps at concentrations sufficient to exceed the background doping concentration, the Fermi level becomes pinned at the trap energy level rather than being determined by the background dopant concentration.18 3

[0087] Heterointerface traps can be introduced at concentrations of 0 to 1x10 cm" . Heterointerface traps mitigate free carrier leakage for enhanced off-resistance. The heterointerface traps capture free carriers that would otherwise accumulate at heterojunction interfaces due to polarization-induced charges or band discontinuities. By trapping these carriers at deep energy levels within the bandgap, the heterointerface traps prevent the trapped carriers from contributing to conduction in the off-state.

[0088] Trap states are used to reduce excess carrier concentrations in n-type nitride systems. Ill-nitride semiconductors commonly exhibit unintentional n-type conductivity due to native defects and residual impurities such as oxygen and silicon that act as donors. The trap states introduce deep acceptor-like levels that capture excess electrons from the conduction band,22325233825v3reducing the free electron concentration. By reducing the excess carrier concentration through trap state compensation, the off-state resistance of the piezoelectric acoustic transistor is improved.

[0089] Trap states are used to suppress parasitic conduction channels for improved off-state resistance. Parasitic conduction channels can form at interfaces and surfaces where unintended carrier accumulation occurs due to polarization effects, surface states, or band bending. The trap states capture carriers that would otherwise populate these parasitic channels, preventing the formation of conductive paths that would degrade off-state isolation. The suppression of parasitic conduction channels through trap state introduction complements the doping-based approaches described previously for achieving high off-state resistance in the piezoelectric acoustic transistor.

[0090] The piezoelectric acoustic transistor can use an alternative volume doping method where impurity doping is introduced throughout the structure rather than at discrete interfaces. In the volume doping method, beryllium doping in gallium nitride or silicon doping in aluminum nitride can be used as impurity doping throughout the structure for volume conduction. The volume doping method provides a distinct approach from the interfacial doping and strip doping methods described previously, where conductivity modulation occurs at two-dimensional sheets at heterojunction interfaces.

[0091] In the volume doping method, the entire three-dimensional structure becomes conductive under pressure rather than conduction occurring in two-dimensional sheets at interfaces. When acoustic pressure is applied to a volume-doped structure, the entire volume of the doped semiconductor material transitions from an insulating state to a conductive state. This volumetric conduction contrasts with the interfacial conduction approach where two-dimensional electron gas and two-dimensional hole gas channels form at discrete heterojunction interfaces. The volume doping method enables conduction through the full three-dimensional extent of the doped material, providing an alternative pathway for achieving high current handling capability.

[0092] The impurity doping in the volume doping method forms specific defects with broken bonds in particular directions that trap electrons and stop conduction at normal conditions. For beryllium doping in gallium nitride, the beryllium atoms and nitrogen atoms form a defect structure with a broken bond between the two atoms. This broken bond creates a trap state that captures electrons from the conduction band, rendering the material insulating in the absence of applied pressure. The trapped electrons are localized at the defect site and do not contribute to electrical 23325233825v3conduction. Similarly, silicon doping in aluminum nitride forms defect structures with broken bonds that trap electrons and prevent conduction under normal unstressed conditions.

[0093] When pressure is applied to the volume-doped structure, the atoms get closer together, the bond reforms, and the material becomes conductive. The applied acoustic pressure compresses the crystal lattice, reducing the interatomic spacing between the impurity atom and the adjacent host lattice atom. As the atoms move closer together under the applied pressure, the broken bond that was responsible for trapping electrons reforms into a complete bond. When the bond reforms, the trap state that was capturing electrons or holes is eliminated, and the previously trapped electrons or holes are released into the conduction or valence band where the electrons or holes can contribute to electrical conduction. The reformation of the broken bond under pressure transforms the material from an insulating state to a conductive state throughout the entire volume of the doped region.

[0094] The volume doping method provides fabrication advantages because the method does not require growth of multiple alternating layers with precise thickness control. A volume-doped structure can be fabricated by growing a single thick layer of gallium nitride with beryllium doping or aluminum nitride with silicon doping. The single-layer growth process can be performed using established epitaxial growth techniques at semiconductor manufacturing facilities. The simplicity of the volume-doped structure enables rapid technology transfer to existing manufacturing infrastructure without requiring development of complex multilayer growth processes.

[0095] The volume doping method and the interfacial doping method described previously represent two distinct approaches for achieving pressure-modulated conductivity in piezoelectric acoustic transistors. The interfacial doping method produces conductivity in two-dimensional channels at heterojunction interfaces, with multiple parallel channels formed when multiple heterostructure periods are included in the active region. The volume doping method produces conductivity throughout the three-dimensional volume of the doped material. Both methods achieve the transition from an insulating off-state to a conductive on-state in response to applied acoustic pressure, with the selection between methods based on fabrication considerations and specific device performance requirements.

[0096] Referring to FIG. 2, a band diagram for a doped ScAlN / GaN / ScAlN heterostructure at zero stress and zero applied voltage illustrates the off-state operation of the piezoelectric acoustic 24325233825v3transistor. The band diagram shows three distinct material regions: a first ScAlN region on the left side, a GaN region in the center shown with gray shading, and a second ScAlN region on the right side. The horizontal axis represents position Y in micrometers, ranging from 0 to 0.25 micrometers. The vertical axis represents energy in negative electron volts, ranging from approximately -4.5 to 4.5 electron volts.

[0097] Three energy levels are plotted across the structure in FIG. 2: a conduction band edge Ec shown as the top solid line, a valence band edge Ev shown as a bottom solid line, and a Fermi level Ef shown as a center dashed horizontal line positioned at approximately zero electron volts. The Fermi level Ef is positioned within the bandgap throughout the structure, indicating an insulating off-state condition. In the off-state condition, neither the conduction band edge Ec nor the valence band edge Ev crosses the Fermi level Ef to create free carriers for conduction.

[0098] With continued reference to FIG. 2, the conduction band edge Ec in the first ScAlN region begins at approximately 1.5 electron volts and rises to approximately 3 electron volts before dropping sharply at the interface with the GaN region. Within the GaN region, the conduction band edge Ec shows a sharp dip to approximately 1.5 electron volts and then drops to approximately 1.25 electron volts. At the GaN to second ScAlN interface, the conduction band edge Ec rises sharply to approximately 2.5 electron volts before continuing upward to approximately 4 electron volts at the right edge of the diagram. The valence band edge Ev follows corresponding trends at lower energies throughout the structure.

[0099] An annotation within the first ScAlN region of FIG. 2 states "No Channels at 0 Stress," indicating that under zero stress conditions, no conductive channels are formed in the structure because the Fermi-level (dashed horizontal line) is not close to or crossing over either the conduction or valence band energies. The absence of conductive channels at zero stress demonstrates the off-state operation where the piezoelectric acoustic transistor maintains high resistance between the side contact electrodes.

[0100] As described previously, the Fermi level is pinned at a specific position in the energy bandgap using semi-insulating impurities. The pinned Fermi level position creates a pivot point or teeter-totter effect where energy bands can bend around this central point under applied pressure. In the zero stress condition shown in FIG. 2, the energy bands have not yet bent around the pinned Fermi level position, and the structure remains in the insulating off-state.25325233825v3

[0101] The band diagram of FIG. 2 illustrates a method of operating a piezoelectric acoustic transistor. As described previously, the method comprises providing a piezoelectric acoustic transistor comprising a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, an active region disposed on the barrier layer comprising a plurality of lattice-matched heterostructures each having a first active layer and a second active layer, a top layer disposed on the active region, and side contact electrodes. The ScAlN / GaN / ScAlN heterostructure shown in FIG. 2 corresponds to the active region comprising the lattice-matched heterostructures, where the GaN region corresponds to the first active layer and the ScAlN regions correspond to the second active layer.

[0102] The method further comprises maintaining the piezoelectric acoustic transistor in an off-state wherein a Fermi level is positioned within a bandgap of the active region such that substantially no free carriers are available for conduction. FIG. 2 illustrates this off-state condition where the Fermi level Ef remains positioned within the bandgap throughout the GaN and ScAlN regions. Because the conduction band edge Ec remains above the Fermi level Ef and the valence band edge Ev remains below the Fermi level Ef throughout the structure, substantially no free carriers are available for conduction in the off-state. The positioning of the Fermi level Ef at approximately zero electron volts, which corresponds to approximately mid-bandgap in the GaN region, ensures that thermal excitation of carriers from either the valence band to the Fermi level or from the Fermi level to the conduction band is minimized, maintaining the high off-state resistance of the piezoelectric acoustic transistor.

[0103] Referring to FIG. 3, a band diagram for a doped ScAlN / GaN / ScAlN heterostructure under an applied stress of 4 GPa with zero applied voltage illustrates the on-state operation of the piezoelectric acoustic transistor. The band diagram shows the same three distinct material regions as FIG. 2: a first ScAlN region extending from approximately 0 to 0.1 micrometers, a GaN region extending from approximately 0.1 to 0.15 micrometers, and a second ScAlN region extending from approximately 0.15 to 0.25 micrometers. The horizontal axis represents position in micrometers, ranging from 0 to 0.25 micrometers. The vertical axis represents energy in electron volts, ranging from approximately -4.5 eV to 5 eV.

[0104] Three energy levels are plotted across the structure in FIG. 3 : a conduction band edge Ec shown as the top solid line, a valence band edge Ev shown as the bottom solid line, and a Fermi26325233825v3level Ef shown as a center dashed line positioned at approximately 0 eV. The method of operating a piezoelectric acoustic transistor comprises applying acoustic pressure to the piezoelectric acoustic transistor to transition the piezoelectric acoustic transistor to an on-state. FIG. 3 illustrates the on-state condition where the applied acoustic pressure is at least 4 GPa.

[0105] With continued reference to FIG. 3, the applied acoustic pressure induces piezoelectric polarization changes that cause energy bands within the active region to bend around a pinned Fermi level position. The significant shift of the band diagram from the zero stress condition shown in FIG. 2 to the 4 GPa stress condition shown in FIG. 3 indicates a large piezoelectric polarization is induced by the applied stress. The piezoelectric polarization changes cause significant band bending at the heterojunction interfaces between the GaN region and the adjacent ScAlN regions.

[0106] The energy bands bend around the pinned Fermi level position such that a conduction band approaches or crosses below the Fermi level at a first heterojunction interface to form the two-dimensional electron gas and a valence band approaches or crosses above the Fermi level at a second heterojunction interface to form the two-dimensional hole gas. At the interface between the first ScAlN region and the GaN region, the valence band Ev bends upward and approaches or crosses above the Fermi level Ef, indicating the formation of a two-dimensional hole gas channel as annotated in FIG. 3. At the interface between the GaN region and the second ScAlN region, the conduction band Ec bends downward and approaches or crosses below the Fermi level Ef, indicating the formation of a two-dimensional electron gas channel as annotated in FIG. 3.

[0107] As further shown in FIG. 3, the Fermi level Ef remains positioned at approximately 0 eV throughout the structure, particularly remaining in the same approximate midgap position centralluy in the GaN region., demonstrating the pinned Fermi level position around which the energy bands bend. The pinned Fermi level position serves as a pivot point or fulcrum for the energy band bending under applied acoustic pressure. The energy bands bend around the pinned central point like a teeter-totter or seesaw under applied pressure, with the valence band on one side of the GaN region bending upward above the Fermi level while the conduction band on the opposite side of the GaN region bends downward below the Fermi level. This seesaw behavior enables simultaneous formation of both the two-dimensional hole gas and the two-dimensional electron gas at the respective heterojunction interfaces.27325233825v3

[0108] The band diagram of FIG. 3 demonstrates that applying acoustic pressure to the piezoelectric acoustic transistor transitions the piezoelectric acoustic transistor to an on-state, thereby forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at heterojunction interfaces within the active region. The top and bottom interfaces of the structure remain charge free, and the channel layers formed at the heterojunction interfaces within the GaN region are conducting in the on-state.

[0109] As described previously, maintaining the piezoelectric acoustic transistor in the off-state comprises maintaining a carrier concentration of less than | xlOlficm-3. Transitioning the piezoelectric acoustic transistor to the on-state comprises forming the at least one of the two-dimensional electron gas or the two-dimensional hole gas having a charge density greater than IxlO17cm-3. The charge density can be greater than 1 x 1019cm-3in configurations requiring the lowest on-state resistance. The large contrast between the off-state carrier concentration and the on-state charge density provides the switching behavior that enables the piezoelectric acoustic transistor to function as an effective power switch responsive to applied acoustic pressure.

[0110] Alternative Embodiment: Dual Active Region Two-Channel Piezoelectric Acoustic Transistor with Stackable Unit Cell Architecture[OHl] In an alternative embodiment, the piezoelectric acoustic transistor employs a stackable unit cell architecture that enables arbitrarily thick epitaxial layer structures while maintaining lattice-matched heterostructures throughout the active region. This embodiment addresses the practical requirements for high-current applications by providing a scalable design where multiple unit cells can be stacked to achieve desired current-carrying capacity without compromising structural integrity or introducing critical thickness limitations.

[0112] The stackable unit cell configuration comprises lattice-matched Ill-nitride material layers where strategic doping with trap states creates an “energy fulcrum” mechanism for band diagram bending under applied uniaxial compressive stress. Trap states are energy states within the forbidden energy gap that would normally not exist in a pure semiconductor but are introduced by addition of one or more impurities such as Fe, C, Be or similar impurities in GaN known to create charged “trap states” inside the energy bandgap. Specifically, trap states are positioned at selected physical locations within selected layers to pin the Fermi level (i.e. Fermi-energy) at predetermined energy positions within the bandgap. Fermi-level pinning occurs when the local 28325233825v3energy around the trap state is solely or mostly determined by the local charge at the trap state so that external influences like applied external electric fields or in the PAT case, changes in polarization due to applied pressure have no effect on the Fermi-level position near the trap. Critically, the Fermi-level but can still vary at positions far away from the trap. Once pinned by the high density of trap states, the conduction and valance energy bands rotate clockwise and counterclockwise raising and lowering the conduction and valance bands above and below the fermi-energy. In the case of the PAT, this happens when the structure is subjected to uniaxial compressive stress, where these trap states serve as fixed energy pivot points or energy fulcrums around which the conduction and valence energy bands undergo substantial bending due to piezoelectric polarization changes induced by the applied stress.

[0113] In the off-state at zero applied stress, the trap states maintain the Fermi level positioned approximately at mid-bandgap (or near the trap energy position withing the bandgap) throughout the active region, resulting in an electron density less than 1 x 108cm-3and a hole density less than IxlO7cm-3, thereby providing a very high channel resistance suitable for ultra-high voltage blocking in the off-state. Since this is the “as-grown” condition (i.e. no or small external stress applied) the PAT is a highly desirable normally off device. The trap state concentration can range from IxlO14cm-2to IxlO19cm-3depending on the specific layer and interface requirements and the specific energy associated with the impurty(ies) used to create the trap.

[0114] Upon application of uniaxial compressive stress of up to approximately 4 GPa, the piezoelectric polarization changes cause the energy bands to bend around the pinned Fermi level positions established by the trap states. This band bending mechanism operates analogously to a mechanical teeter-totter or seesaw, where the trap states function as the fulcrum and the applied stress provides the force causing rotation. The band bending around the trap state fulcrums causes both the conduction band and valence band to cross the Fermi level at heterojunction interfaces, thereby forming simultaneous two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) channels at the interfaces on opposite ends of the same epitaxial layer.

[0115] In the on-state at up to 4 GPa applied stress, the electron density in each 2DEG channel exceeds IxlO18cm-3, and similar charge densities are achieved in the 2DHG channels. For a structure comprising 10 alternating layers forming 5 unit cell periods, the channel resistance modulates between an off-state resistance exceeding IxlO11Ohm and an on-state resistance below29325233825v3approximately 100 Ohms per unit cell period. The stackable architecture enables scaling to 200 or more alternating layers ( 100 or more unit cell periods) to achieve on-state resistance values below 1 Ohm while maintaining ultra-high off-state resistance suitable for high-voltage power switching applications. Given the PAT structures are lattice matched, any number of stacked unit cells can be used to achieve any desirable on-state resistance and any amount of current carrying capability.

[0116] The stackable unit cell embodiment can further include interfacial doping at heterojunction interfaces configured to compensate polarization-induced charges and position the Fermi level within the bandgap in the off-state. The interfacial doping concentration can range from IxlO17cm-3to 5X1021cm-3.

[0117] Alternative Embodiment: Dual Active Region Multi-Channel Piezoelectric Acoustic Transistor

[0118] In another alternative embodiment, the piezoelectric acoustic transistor comprises a dual active region architecture that also provides equal numbers of electron channels and hole channels in the on-state, but uses one or more thin (several nm) and separate layers to form dual electron and hole channels, thereby achieving charge neutrality and enabling faster switching characteristics.

[0119] The dual active region piezoelectric acoustic transistor comprises a substrate, a buffer layer disposed on the substrate, a bottom active region disposed on the buffer layer, a spacer layer disposed on the bottom active region, and a top active region disposed on the spacer layer. The buffer layer can comprise a fll-nitride material such as gallium nitride (GaN) having a thickness ranging from 1 micrometer to 20 micrometers. The bottom active region comprises a plurality of alternating heterostructure layers, each heterostructure comprising a first fll-nitride layer and a second Ill-nitride layer that are lattice-matched to the buffer layer. Similarly, the top active region comprises a plurality of alternating heterostructure layers with lattice-matched Ill-nitride materials. The spacer layer separates the bottom active region from the top active region and can comprise scandium aluminum nitride (ScAlN) with a thickness ranging from 0.5 micrometers to 5 micrometers.

[0120] The dual active region multi-channel architecture employs strategic doping with trap states to facilitate formation of balanced electron and hole channels. The trap states are positioned to serve as fulcrums for bending the band diagram when the piezoelectric acoustic transistor 30325233825v3structure is subjected to uniaxial compressive stress. Specifically, trap states can be positioned at an interface at the bottom of the buffer layer at concentrations ranging from l><1014cm’2to IxlO15cm-2to pin the Fermi level at a predetermined energy position, such as 0.2 eV below midbandgap, and approximately midway between the electron and hole channels of each unit cell. These trap states function as fixed pivot points around which the conduction bands and valence bands rotate under applied stress, analogous to a mechanical fulcrum supporting a lever or teeter-totter.

[0121] The bottom active region comprises P-type interfacial doping at heterojunction interfaces between the alternating layers. The P-type interfacial doping concentrations can vary across different interfaces, for example ranging from 1 ,8X1013cm-2to 2.1xl013cm-2at different heterojunction interfaces. Conversely, the top active region comprises N-type interfacial doping at 12 2 13 2 heterojunction interfaces, with concentrations ranging from 5x10 cm' to 2.5x10 cm' at different interfaces.

[0122] In the off-state at zero applied stress, the strategic combination of trap states and interfacial doping ensures the Fermi level is positioned at mid-bandgap throughout both the bottom active region and the top active region, resulting in high resistance. The trap states and interfacial doping work synergistically to suppress free carriers in the off-state, with the trap states providing the Fermi level pinning mechanism and the interfacial doping neutralizing polarization-induced charges at the heterojunction interfaces. The off-state is characterized by negligible electron and hole densities, maintaining ultra-high channel resistance suitable for high-voltage blocking.

[0123] Upon application of uniaxial compressive stress of up to approximately 4 GPa, the piezoelectric polarization changes at the top and bottom interfaces of the spacer layer induce band bending that causes the energy bands to rotate around the pinned Fermi level positions established by the trap state fulcrums. The change in piezoelectric polarization under applied stress creates electric fields that pull the entire bottom active region valence band and the entire top active region conduction band toward the Fermi level. This coordinated band bending mechanism results in the valence band crossing above the Fermi level at heterojunction interfaces in the bottom active region to form two-dimensional hole gas (2DHG) channels, while simultaneously the conduction band crosses below the Fermi level at heterojunction interfaces in the top active region to form two-dimensional electron gas (2DEG) channels.31325233825v3

[0124] The dual active region architecture achieves equal numbers of electron channels and hole channels in the on-state in each unit cell, providing charge neutrality within the device structure. For example, a configuration comprising 5 alternating ScAlN / GaN layers in the bottom active region and 5 alternating ScAlN / GaN layers in the top active region forms 5 hole channels in the bottom active region and 5 electron channels in the top active region when subjected to 4 GPa of applied stress. This balanced configuration of equal electron and hole channels enables faster switching characteristics compared to single-channel unipolar designs. The equal distribution of positive and negative charges minimizes internal electric fields that could otherwise impede switching speed, thereby enhancing the overall switching performance of the piezoelectric acoustic transistor.

[0125] The disclosed technology can be further understood according to the following clauses:

[0126] Clause 1 : A piezoelectric acoustic transistor, comprising: a substrate; a buffer layer disposed on the substrate; a barrier layer disposed on the buffer layer; an active region disposed on the barrier layer, the active region comprising a plurality of periodic heterostructures, each heterostructure comprising a first active layer and a second active layer, wherein the first active layer and the second active layer are lattice matched; a top layer disposed on the active region; and a first side contact electrode and a second side contact electrode positioned on opposite sides of the active region, wherein the active region is configured to modulate conductivity in response to applied acoustic pressure by forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at interfaces between the first active layer and the second active layer.

[0127] Clause 2: The piezoelectric acoustic transistor of clause 1, wherein the substrate comprises a material selected from the group consisting of silicon, silicon carbide, gallium nitride, and aluminum nitride.

[0128] Clause 3 : The piezoelectric acoustic transistor of clause 1 , wherein the buffer layer has a thickness of 0.1 pm to 50 pm.

[0129] Clause 4: The piezoelectric acoustic transistor of clause 1, wherein the buffer layer comprises a material selected from the group consisting of gallium nitride, aluminum nitride, aluminum scandium nitride, aluminum gallium nitride, aluminum yttrium nitride, aluminum32325233825v3indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z=1.0.

[0130] Clause 5 : The piezoelectric acoustic transistor of clause 1 , wherein the barrier layer has a thickness of 50 nm to 5000 nm.

[0131] Clause 6: The piezoelectric acoustic transistor of clause 5, wherein the barrier layer comprises a material selected from the group consisting of aluminum scandium nitride, aluminum yttrium nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z=1.0.

[0132] Clause 7 : The piezoelectric acoustic transistor of clause 1 , wherein the first active layer comprises gallium nitride and has a thickness of 2 nm to 100 nm.

[0133] Clause 8: The piezoelectric acoustic transistor of clause 7, wherein the second active layer comprises a material selected from the group consisting of aluminum scandium nitride, aluminum indium nitride, and aluminum yttrium nitride, and has a thickness of 2 nm to 100 nm.

[0134] Clause 9: The piezoelectric acoustic transistor of clause 1, wherein the top layer comprises a material selected from the group consisting of aluminum scandium nitride, aluminum yttrium nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z=1.0.

[0135] Clause 10: The piezoelectric acoustic transistor of clause 9, wherein the top layer has a thickness of 50 nm to 5000 nm.

[0136] Clause 11 : The piezoelectric acoustic transistor of clause 1 , wherein the active region comprises interfacial doping at heterojunction interfaces between the first active layer and the 17 3 21 3second active layer at a concentration of 1x10 cm' to 5x10 cm' .

[0137] Clause 12: The piezoelectric acoustic transistor of clause 11, wherein the active region further comprises strip doping layers configured to suppress free carriers in an off-state, the strip 17 3 doping layers having a thickness of 1 nm to 50 nm and a doping concentration of 1x10 cm' toci 1 -35x10 cm .325233825v3

[0138] Clause 13 : The piezoelectric acoustic transistor of clause 1 , wherein the piezoelectric 16 3 acoustic transistor has an unintentional background doping of less than 1*10 cm .

[0139] Clause 14: The piezoelectric acoustic transistor of clause 1, further comprising trap states in at least one of the substrate, the barrier layer, and the top layer at a concentration of up to 1X10 cm' , wherein the trap states are configured to pin a Fermi level within an energy bandgap.

[0140] Clause 15: A piezoelectric acoustic transistor, comprising: a substrate; a buffer layer disposed on the substrate and comprising a llf-nitride material; a barrier layer disposed on the buffer layer; an active region disposed on the barrier layer, the active region comprising at least one heterostructure having a first active layer comprising a first llf-nitride material and a second active layer comprising a second Ill-nitride material different from the first Ill-nitride material, wherein the first active layer and the second active layer are lattice matched to the buffer layer; a top layer disposed on the active region; side contact electrodes configured to provide electrical contact to the active region; and interfacial doping at heterojunction interfaces within the active region configured to position a Fermi level within a bandgap of the active region in an off-state and to enable formation of conducting channels at the heterojunction interfaces in an on-state responsive to applied acoustic stress.

[0141] Clause 16: The piezoelectric acoustic transistor of clause 15, wherein the interfacial 17 3 21 3doping has a concentration of 1 x 10 cm' to 5x10 cm' .

[0142] Clause 17: The piezoelectric acoustic transistor of clause 16, wherein the interfacial doping is configured to partially or completely neutralize polarization-induced charges at the heterojunction interfaces.

[0143] Clause 18: The piezoelectric acoustic transistor of clause 15, wherein the first llf-nitride material comprises gallium nitride and the second Ill-nitride material comprises a material selected from the group consisting of aluminum scandium nitride, aluminum indium nitride, and aluminum yttrium nitride.

[0144] Clause 19: The piezoelectric acoustic transistor of clause 18, wherein the active region comprises a plurality of periodic heterostructures, each heterostructure comprising the first active layer and the second active layer.34325233825v3

[0145] Clause 20: The piezoelectric acoustic transistor of clause 15, wherein the conducting channels comprise at least one of a two-dimensional electron gas and a two-dimensional hole gas 17 3having a charge density greater than I x 10 cm' in the on-state.

[0146] Clause 21: The piezoelectric acoustic transistor of clause 20, wherein the charge 19 3density is greater than 1x10 cm' in the on-state.

[0147] Clause 22: The piezoelectric acoustic transistor of clause 15, wherein the off-state is 16 3characterized by a carrier concentration of less than 1*10 cm .

[0148] Clause 23: The piezoelectric acoustic transistor of clause 15, further comprising strip doping layers within the active region having a thickness of 1 nm to 5000 nm, wherein the strip doping layers are configured to align a Fermi level at mid-bandgap.

[0149] Clause 24: The piezoelectric acoustic transistor of clause 23, wherein the strip doping layers comprise N-type doping configured to suppress free hole density or P-type doping configured to suppress free electron density.

[0150] Clause 25: A method of operating a piezoelectric acoustic transistor, the method comprising: providing a piezoelectric acoustic transistor comprising a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, an active region disposed on the barrier layer comprising a plurality of lattice-matched heterostructures each having a first active layer and a second active layer, a top layer disposed on the active region, and side contact electrodes; maintaining the piezoelectric acoustic transistor in an off-state wherein a Fermi level is positioned within a bandgap of the active region such that substantially no free carriers are available for conduction; and applying acoustic pressure to the piezoelectric acoustic transistor to transition the piezoelectric acoustic transistor to an on-state, wherein the applied acoustic pressure induces piezoelectric polarization changes that cause energy bands within the active region to bend around a pinned Fermi level position, thereby forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at heterojunction interfaces within the active region.

[0151] Clause 26: The method of clause 25, wherein the applied acoustic pressure is at least 4 GPa.35325233825v3

[0152] Clause 27: The method of clause 25, wherein maintaining the piezoelectric acoustic 16 3 transistor in the off-state comprises maintaining a carrier concentration of less than 1*10 cm .

[0153] Clause 28: The method of clause 27, wherein transitioning the piezoelectric acoustic transistor to the on-state comprises forming the at least one of the two-dimensional electron gas or 17 3the two-dimensional hole gas having a charge density greater than I x 10 cm' .

[0154] Clause 29: The method of clause 28, wherein the charge density is greater than 1 x 1019cm'3.

[0155] Clause 30: The method of clause 25, wherein the energy bands bend around the pinned Fermi level position such that a conduction band crosses below the Fermi level at a first heterojunction interface to form the two-dimensional electron gas and a valence band crosses above the Fermi level at a second heterojunction interface to form the two-dimensional hole gas.

[0156] Clause 31: The piezoelectric acoustic transistor of clause 1, wherein each of the plurality of periodic heterostructures defines a repeatable unit cell of the active region, the repeatable unit cell comprising the first active layer and the second active layer.

[0157] Clause 32: The piezoelectric acoustic transistor of clause 31 , wherein the active region comprises N stacked repetitions of the unit cell, where N is an integer greater than or equal to 1 and less than or equal to 1000.

[0158] Clause 33: The piezoelectric acoustic transistor of clause 32, wherein N is at least 5, at least 10, or at least 50.

[0159] Clause 34: The piezoelectric acoustic transistor of clause 32, wherein an on-state resistance of the piezoelectric acoustic transistor decreases as N increases, due to formation of additional parallel conducting channels at heterojunction interfaces of the repeated unit cells.

[0160] Clause 35: The piezoelectric acoustic transistor of clause 34, wherein the on-state resistance is less than 1 ohm when the piezoelectric acoustic transistor is configured for a blocking voltage of at least 10 kV.

[0161] Clause 36: The piezoelectric acoustic transistor of clause 1, wherein, in an on-state under an applied acoustic pressure, the active region is configured to form a first conducting channel comprising a two-dimensional hole gas at a first heterojunction interface of the active 36325233825v3region, and a second conducting channel comprising a two-dimensional electron gas at a second heterojunction interface of the active region.

[0162] Clause 37: The piezoelectric acoustic transistor of clause 36, wherein the first heterojunction interface and the second heterojunction interface are located on opposite sides of a same first active layer comprising gallium nitride.

[0163] Clause 38: The piezoelectric acoustic transistor of clause 36, wherein each of the first 17 conducting channel and the second conducting channel has a charge density greater than I x 10 cm' in the on-state.

[0164] Clause 39: The piezoelectric acoustic transistor of clause 1, wherein the active region comprises: a first active region comprising a first conduction region in which, in the on-state, a two-dimensional hole gas is formed at a first heterojunction interface; and a second active region comprising a second conduction region in which, in the on-state, a two-dimensional electron gas is formed at a second heterojunction interface.

[0165] Clause 40: The piezoelectric acoustic transistor of clause 39, wherein the first active region and the second active region are disposed in series between the first side electrode and the second side electrode, and are located on opposite sides of a same epitaxial layer in the active region.

[0166] Clause 41: The method of clause 25, wherein the active region is formed by repeating a unit cell heterostructure comprising the first active layer and the second active layer, the unit cell being repeated N times between the first side electrode and the second side electrode, where N is an integer greater than or equal to 1 and less than or equal to 1000.

[0167] Clause 42: The method of clause 25, wherein applying the acoustic pressure causes a valence band at a first heterojunction interface of the active region to bend above a pinned Fermi level to form the two-dimensional hole gas and causes a conduction band at a second heterojunction interface of the active region to bend below the pinned Fermi level to form the two-dimensional electron gas.

[0168] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other implementations are within the scope of the following claims.37325233825v3

Claims

CLAIMS1. A piezoelectric acoustic transistor, comprising:a substrate;a buffer layer disposed on the substrate;a barrier layer disposed on the buffer layer;an active region disposed on the barrier layer, the active region comprising a plurality of periodic heterostructures, each heterostructure comprising a first active layer and a second active layer, wherein the first active layer and the second active layer are lattice matched;a top layer disposed on the active region; anda first side contact electrode and a second side contact electrode positioned on opposite sides of the active region, wherein the active region is configured to modulate conductivity in response to applied acoustic pressure by forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at interfaces between the first active layer and the second active layer.

2. The piezoelectric acoustic transistor of claim 1, wherein the substrate comprises a material selected from the group consisting of silicon, silicon carbide, gallium nitride, and aluminum nitride.

3. The piezoelectric acoustic transistor of claim 1, wherein the buffer layer has a thickness of 0.1 pm to 50 pm.

4. The piezoelectric acoustic transistor of claim 1 , wherein the buffer layer comprises a material selected from the group consisting of gallium nitride, aluminum nitride, aluminum scandium nitride, aluminum gallium nitride, aluminum yttrium nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z= 1.0.

5. The piezoelectric acoustic transistor of claim 1, wherein the barrier layer has a thickness of 50 nm to 5000 nm.

6. The piezoelectric acoustic transistor of claim 5, wherein the barrier layer comprises a material selected from the group consisting of aluminum scandium nitride, aluminum yttrium38325233825v3nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z=1.0.

7. The piezoelectric acoustic transistor of claim 1, wherein the first active layer comprises gallium nitride and has a thickness of 2 nm to 100 nm.

8. The piezoelectric acoustic transistor of claim 7, wherein the second active layer comprises a material selected from the group consisting of aluminum scandium nitride, aluminum indium nitride, and aluminum yttrium nitride, and has a thickness of 2 nm to 100 nm.

9. The piezoelectric acoustic transistor of claim 1, wherein the top layer comprises a material selected from the group consisting of aluminum scandium nitride, aluminum yttrium nitride, aluminum indium nitride, and combinations of AlvGawScxInyYzN where 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l, and v+w+x+y+z=1.0.

10. The piezoelectric acoustic transistor of claim 9, wherein the top layer has a thickness of 50 nm to 5000 nm.

11. The piezoelectric acoustic transistor of claim 1 , wherein the active region comprises interfacial doping at heterojunction interfaces between the first active layer and the second active layer at a concentration of l*10A17 cmA-3 to 5X10A21 cmA-3.

12. The piezoelectric acoustic transistor of claim 11, wherein the active region further comprises strip doping layers configured to suppress free carriers in an off-state, the strip doping layers having a thickness of 1 nm to 50 nm and a doping concentration of 1 x 10Al 7 cmA-3 to 5x10A21 cmA-3.

13. The piezoelectric acoustic transistor of claim 1, wherein the piezoelectric acoustic transistor has an unintentional background doping of less than 1 x 10A16 cmA-3.

14. The piezoelectric acoustic transistor of claim 1 , further comprising trap states in at least one of the substrate, the barrier layer, and the top layer at a concentration of up to 1 x 10A19 cmA-3, wherein the trap states are configured to pin a Fermi level within an energy bandgap.

15. A piezoelectric acoustic transistor, comprising:a substrate;a buffer layer disposed on the substrate and comprising a llf-nitride material;39325233825v3a barrier layer disposed on the buffer layer;an active region disposed on the barrier layer, the active region comprising at least one heterostructure having a first active layer comprising a first Ill-nitride material and a second active layer comprising a second Ill-nitride material different from the first Ill-nitride material, wherein the first active layer and the second active layer are lattice matched to the buffer layer;a top layer disposed on the active region;side contact electrodes configured to provide electrical contact to the active region; and interfacial doping at heterojunction interfaces within the active region configured to position a Fermi level within a bandgap of the active region in an off-state and to enable formation of conducting channels at the heterojunction interfaces in an on-state responsive to applied acoustic stress.

16. The piezoelectric acoustic transistor of claim 15, wherein the interfacial doping has a concentration of 1x10A17 cmA-3 to 5x10A21 cmA-3.

17. The piezoelectric acoustic transistor of claim 16, wherein the interfacial doping is configured to partially or completely neutralize polarization-induced charges at the heterojunction interfaces.

18. The piezoelectric acoustic transistor of claim 15, wherein the first Ill-nitride material comprises gallium nitride and the second Ill-nitride material comprises a material selected from the group consisting of aluminum scandium nitride, aluminum indium nitride, and aluminum yttrium nitride.

19. The piezoelectric acoustic transistor of claim 18, wherein the active region comprises a plurality of periodic heterostructures, each heterostructure comprising the first active layer and the second active layer.

20. The piezoelectric acoustic transistor of claim 15, wherein the conducting channels comprise at least one of a two-dimensional electron gas and a two-dimensional hole gas having a charge density greater than 1 x 10A17 cmA-3 in the on-state.

21. The piezoelectric acoustic transistor of claim 20, wherein the charge density is greater than 1 x 10A19 cmA-3 in the on-state.40325233825v322. The piezoelectric acoustic transistor of claim 15, wherein the off-state is characterized by a carrier concentration of less than 1><1OA16 cmA-3.

23. The piezoelectric acoustic transistor of claim 15, further comprising strip doping layers within the active region having a thickness of 1 nm to 50 nm, wherein the strip doping layers are configured to align a Fermi level at mid-bandgap.

24. The piezoelectric acoustic transistor of claim 23, wherein the strip doping layers comprise N-type doping configured to suppress free hole density or P-type doping configured to suppress free electron density.

25. A method of operating a piezoelectric acoustic transistor, the method comprising: providing a piezoelectric acoustic transistor comprising a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, an active region disposed on the barrier layer comprising a plurality of lattice-matched heterostructures each having a first active layer and a second active layer, a top layer disposed on the active region, and side contact electrodes;maintaining the piezoelectric acoustic transistor in an off-state wherein a Fermi level is positioned within a bandgap of the active region such that substantially no free carriers are available for conduction; andapplying acoustic pressure to the piezoelectric acoustic transistor to transition the piezoelectric acoustic transistor to an on-state, wherein the applied acoustic pressure induces piezoelectric polarization changes that cause energy bands within the active region to bend around a pinned Fermi level position, thereby forming at least one of a two-dimensional electron gas or a two-dimensional hole gas at heterojunction interfaces within the active region.

26. The method of claim 25, wherein the applied acoustic pressure is at least 4 GPa.

27. The method of claim 25, wherein maintaining the piezoelectric acoustic transistor in the off-state comprises maintaining a carrier concentration of less than I I (F l 6 cmA-3.

28. The method of claim 27, wherein transitioning the piezoelectric acoustic transistor to the on-state comprises forming the at least one of the two-dimensional electron gas or the two-dimensional hole gas having a charge density greater than I 10Al 7 cmA-3.41325233825v329. The method of claim 28, wherein the charge density is greater than 1 x 10A19 cmA- 3.

30. The method of claim 25, wherein the energy bands bend around the pinned Fermi level position such that a conduction band crosses below the Fermi level at a first heterojunction interface to form the two-dimensional electron gas and a valence band crosses above the Fermi level at a second heterojunction interface to form the two-dimensional hole gas.

31. The piezoelectric acoustic transistor of claim 1, wherein each of the plurality of periodic heterostructures defines a repeatable unit cell of the active region, the repeatable unit cell comprising the first active layer and the second active layer.

32. The piezoelectric acoustic transistor of claim 31, wherein the active region comprises N stacked repetitions of the unit cell, where N is an integer greater than or equal to 1 and less than or equal to 1000.

33. The piezoelectric acoustic transistor of claim 32, wherein N is at least 5, at least 10, or at least 50.

34. The piezoelectric acoustic transistor of claim 32, wherein an on-state resistance of the piezoelectric acoustic transistor decreases as N increases, due to formation of additional parallel conducting channels at heterojunction interfaces of the repeated unit cells.

35. The piezoelectric acoustic transistor of claim 34, wherein the on-state resistance is less than 1 ohm when the piezoelectric acoustic transistor is configured for a blocking voltage of at least 10 kV.

36. The piezoelectric acoustic transistor of claim 1, wherein, in an on-state under an applied acoustic pressure, the active region is configured to form a first conducting channel comprising a two-dimensional hole gas at a first heterojunction interface of the active region, and a second conducting channel comprising a two-dimensional electron gas at a second heterojunction interface of the active region.

37. The piezoelectric acoustic transistor of claim 36, wherein the first heterojunction interface and the second heterojunction interface are located on opposite sides of a same first active layer comprising gallium nitride.42325233825v338. The piezoelectric acoustic transistor of claim 36, wherein each of the first conducting channel and the second conducting channel has a charge density greater than I xIO17cm-3in the on-state.

39. The piezoelectric acoustic transistor of claim 1, wherein the active region comprises:a first active region comprising a first conduction region in which, in the on-state, a two-dimensional hole gas is formed at a first heterojunction interface; anda second active region comprising a second conduction region in which, in the on-state, a two-dimensional electron gas is formed at a second heterojunction interface.

40. The piezoelectric acoustic transistor of claim 39, wherein the first active region and the second active region are disposed in series between the first side electrode and the second side electrode, and are located on opposite sides of a same epitaxial layer in the active region.

41. The method of claim 25, wherein the active region is formed by repeating a unit cell heterostructure comprising the first active layer and the second active layer, the unit cell being repeated N times between the first side electrode and the second side electrode, where N is an integer greater than or equal to 1 and less than or equal to 1000.

42. The method of claim 25, wherein applying the acoustic pressure causes a valence band at a first heterojunction interface of the active region to bend above a pinned Fermi level to form the two-dimensional hole gas and causes a conduction band at a second heterojunction interface of the active region to bend below the pinned Fermi level to form the two-dimensional electron gas.43325233825v3

Images