A method implemented in a compilation computer to improve parallelism during the linking of a program by a compiler and a non-transient machine-readable medium.

Abstract

 

Description

"METHOD IMPLEMENTED IN A COMPILE COMPUTER TO IMPROVE PARALLELISM DURING THE LINKING OF A PROGRAM BY A COMPILER AND A NON-TRANSIENTIAL MACHINE-READABLE MEDIUM" FIELD OF THE INVENTION

[0001] The configurations of the invention as illustrated and described herein relate to software compilation and a system and methods for improving the parallelism generated in the link-time compilation process for object code generated during the compilation process. BACKGROUND

[0002] The creation of computer software is a multi-phase process. Computer software is initially written as source code. The source code may be written in a computer language such as C, C++, or a similar high-level computer language. While these high-level computer languages ​​are generally understood by human programs, computers are generally unable to execute programs written in said high-level computer languages. The source code is converted into a computer-executable language, sometimes referred to as an assembly language or processor instruction set. This conversion process is referred to as compilation, which is performed by software referred to as a "compiler".

[0003] In some computer systems, multiple processors or parallel processing capabilities are feasible. The source code may be organized or designated by a programmer to be executed in parallel by the multiple processors or processing capabilities. Programmers may identify sections of the source code that are capable of parallel execution based on the relative independence in the operation of those sections of source code. However, the identification of such parallelism by programmers may be inaccurate and inconsistent. As a result, the Petition 870220019259, dated 07 / 03 / 2022, page 17 / 102 2 / 36 Compiling the source code for execution on multiple processors may be suboptimal. The use of multiple processors, multi-core processors, and similar devices continues to grow. This has become an important aspect in improving the processing power of computers and similar devices. Therefore, improving the identification of parallelism in source code and the compilation of source code to exploit parallelism will be crucial for the proper utilization of the expanded power of these processing devices. In 1988, a paper on a parallelization compiler was presented; this paper is described in ZIMA HP ET AL, SUPERB: A tool for semi-automatic MIMD / SIMD parallelization, PARALLEL COMPUTING, ELSEVIER PUBLISHERS, AMSTERDAM, NL, vol. 6, no. 1, hereinafter Zima. Zima describes the design of an interactive system for the semi-automatic transformation of FORTRAN 77 programs into parallel programs for the SUPERNUM machine.The system is characterized by a powerful analysis component, a catalog of MIMD and SIMD parallelization transformations, and a flexible dialog feature. It contains specific knowledge about the parallelization of an important class of numerical algorithms. Although this work has achieved some parallelization, the work of the Zima parallelization compiler, and subsequent similar efforts, have achieved only partial solutions to the problem, and the solutions have been restricted to for-loop parallelization.

[0004] In the early 1990s, the static simple assignment (SSA) form was invented. The SSA form readily supports interprocedural data analysis; the idea behind the SSA form was that each assignment to a variable was considered to uniquely define a variant of that variable. Most often, the SSA form is implemented as a syntax tree annotation, with information captured from data flowchart analysis. Petition 870220019259, dated 07 / 03 / 2022, page 18 / 102 3 / 36 Like the AST plus graphical representations used by Zima, the SSA form preserves the program structure; therefore, there is a clear relationship between the computation flow in the optimized program and that specified in the program's source code. The final intermediate representations of SSA and Zima are decorated abstract syntax trees that generally preserve the original program structure; in fact, Zima requires control and data flow graphs, along with data dependency graphs, to decorate an AST to generate parallel code. This limits the opportunities to identify parallelism and transform a program to take advantage of available opportunities. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The configurations of the invention are illustrated by way of examples and not by way of limitation in the figures accompanying the drawings in which similar references indicate similar elements. It should be noted that references to “a” or “an” configuration of the invention in this invention are not necessarily the same configuration, and they mean at least one. Figure 1 is a flow map of a compilation process configuration. Figure 2 is a flow map of a process configuration for generating a functional data flow map. Figure 3 is a diagram of a configuration of a set of basic functional data flow nodes. Figure 4 is a diagram of a configuration of a set of examples of control flow structures. Figure 5 is a diagram of a configuration of a set of examples of control flow structures. Figures 6-8 are diagrams of example programs constructed as integral program graphs; Petition 870220019259, dated 07 / 03 / 2022, page 19 / 102 4 / 36 Figure 9 is a diagram of a computer system configuration implementing the compilation process. DETAILED DESCRIPTION

[0006] In the following description, numerous specific details are set forth. However, it will be understood that configurations of the invention may be practiced without these specific details. In other instances, well-known circuit structures, techniques, and circuits have been shown in detail, so as not to obscure the understanding of this description. It will be appreciated, however, by a person skilled in the art, knowledgeable in the state of the art, that the invention may be practiced without said specific details. This person skilled in the art, with the descriptions included, will be able to implement appropriate functionality without undue experience.

[0007] The operations depicted in the flow diagrams in the attached Figures will be described with reference to the configurations shown in the attached Figures. However, it should be understood that the operations depicted in the flow diagrams may be performed by configurations of the invention other than those discussed with reference to the diagrams in the attached Figures; other configurations of the invention may perform operations different from those discussed with reference to the flow diagrams in the attached Figures.

[0008] The techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an extreme station, a network element, etc.). Said electronic devices store and communicate (internally and / or with other electronic devices over a network) code and data using a non-transient machine-readable or computer-readable medium, such as a non-transient machine-readable or computer-readable storage medium (e.g., magnetic disks, optical disks, random access memory, read-only memory, flash memory devices, and phase-change memory) and computer-readable transmission medium. Petition 870220019259, dated 07 / 03 / 2022, page 20 / 102 5 / 36 transient (e.g., electrical, optical, acoustic, or other form of propagated signals, such as carrier waves, infrared signals, digital signals). In addition, said electronic devices typically include a set of one or more processors coupled to one or more components, such as one or more storage devices, user input / output devices (e.g., a keyboard, a touch screen, and / or a display), and network connections.

[0009] A “set” as used here refers to any positive integer number of items. The coupling of the processor set and other components is typically through one or more buses and bridges (also called bus controllers). Storage devices represent one or more non-transient readable machines or computer-readable storage media and non-transient readable machines or computer-readable communication media. Thus, the storage device of a given electronic device typically stores code and / or data for execution in the set of one or more processors of those electronic devices. Evidently, one or more parts of a configuration of the invention may be implemented using different software, firmware, and / or hardware configurations.

[00010] As used herein, a network element (e.g., a router, switch, point, etc.) is a piece of network equipment, including hardware and software, that communicatively interconnects with other equipment on the network (e.g., network elements, end stations, etc.). Some network elements are “multi-service network elements” that provide support for multiple network functions (e.g., routing, bridging, switching, Layer 2 aggregation, border control section, multicast, and / or subscriber management) and / or provide support for multiple application services (e.g., data, voice, and video). Petition 870220019259, dated 07 / 03 / 2022, page 21 / 102 6 / 36

[00011] The terms “function” and “procedure” are commonly used interchangeably in computer science, and generally refer to an implemented computer process defined in software. In mathematics, a “function” acts on its arguments to produce a result and has no other effects on its environment. Here, “function” is used in the mathematical sense and “procedure” is used in the computer science sense.

[00012] Figure 1 is a flow map of a compilation process setup. The compilation process transforms source code into object code (Block 101). The source code may be software or a set of computer programs expressed in a computer programming language. The source code may be in any computer programming language such as C, C++, Fortran, or a similar computer language.Object code expresses the same software in another computer programming language, or a similar software description methodology. In an exemplary configuration, the object code may be an assembled language, or a similar low-level programming language, and may be in an executable form. Object code may also contain an intermediate code format with standard representations and formatting for primary use within stages or modules of the compiler process. The compilation process may transfer the source code in any state from the object code.

[00013] The compilation process may perform object linking and linking time parallelization (Block 103). The process of identifying parallelism will be described below with reference to Figures 2-6. The compilation process may also specialize the source code for a target hardware or platform (Block 105). The object code may be transferred or transformed into target code, for example, a language (e.g., assembly level) for the target hardware or platform (Block 107). Any type of compilation process and any standard language may be used. The Petition 870220019259, dated 07 / 03 / 2022, page 22 / 102 7 / 36 The compilation process may be directed towards a single platform or a set of related platforms with variations in the executable pattern for various differences between the platforms.

[00014] Figure 2 is a flowchart of a process configuration for generating an integral program dependency graph. The integral program dependency graph exposes the parallelism in the computer program. The program reports in the computer program are converted into reports in a canonical form and a global table of procedures in the computer program being constructed (Block 201). The canonical form prepares the program for conversion and can be any type of pseudo-code format or organization. The canonical form may remove syntax and similar aspects of the program code to prepare it for conversion. The global procedures table contains a name or similar identifier for each procedure along with a pointer or position information to the abstract syntax tree (AST) to be constructed for each procedure. This table can be used during the traversal program as described below.

[00015] These ASTs are constructed for each procedure in the program code (Block 203). Abstract syntax trees are tree-like (i.e., directed graphs having a root, branches, and leaves) representations of the structure of computer programs or, in this case, the procedures in the program code. Each node (i.e., root, branch, or leaf) in the tree represents a structure in the program code such as variables, operators, procedure calls, and similar structures. In other settings, concrete syntax trees may be used instead of ASTs.

[00016] Within the ASTs, recursive procedures are identified. Recursive procedures are procedures that are directly (within their definition) or indirectly (within the definitions of the referenced procedures) self-referential. Recursive procedures are identified and Petition 870220019259, dated 07 / 03 / 2022, page 23 / 102 8 / 36 Expanded or Flattened (Block 205). Expanding or flattening procedures removes the recursive definition by reformulating the recursive definition of the procedure into an iterative or similar procedure. Similarly, indirect procedure calls are detected and converted into tables and switch nodes. Indirect procedure calls (also referred to as indirect function calls) are procedures that are not explicitly called in the program code. Preferably, a pointer or similar reference to the procedure is used, and this may even include the use of a variable to reference a product. Expanding or flattening these indirect procedures may involve placing the indirectly referenced function in-line (i.e., in the position where the reference occurs), or similarly constructing the AST to remove it in one direction.The global procedure table is updated to connect each AST with the procedure name or similar identifier.

[00017] Once the program products are prepared, each having a complete AST without recursion or indirection, the integrity of the program's dependency graph can be generated by traversing the program starting from the first line of the main procedure, function, method, or a similar starting position in the computer program. The program AST is traversed to construct a functional data flowchart, where each non-control flow report and each control structure is converted to a corresponding node as discussed below (Block 207). Explicit procedure calls are expanded in-line in the code by using the global procedure table that was previously prepared for reference. Each explicit procedure call is viewed in the global procedure table to identify and retrieve the associated AST for insertion into the functional data flowchart.Control flow decisions are represented by a set of nodes in the functional data flowchart. Control flow decisions are represented by a set of types. Petition 870220019259, dated 07 / 03 / 2022, page 24 / 102 9 / 36 special node structure. Similarly, the matrix or set of operations is represented as a set of first nodes. Arcs connecting nodes represent data items or sets. Thus, in the data flowchart, nodes represent computation while arcs represent data.

[00018] At this point, the functional data flowchart represents all fine-grained task parallelism (computations involving independent input variables) but no parallelism data where the same computations are performed for different data items. To extract parallelism data, the functional data flowchart can be traversed to identify each loop in the graph that can be executed in parallel (Block 209). Each of these loops is transformed into an operation set by converting the arcs connecting the nodes of the single item representations to representations of the indexed collections of similar data items in the functional data flowchart (Block 211) and removing the logical loop.

[00019] Further optimization and parallelism may then be sought in the resulting object code. Such optimizations may be specific to the platforms and resources of those platforms (Block 213). Functions may be composed (combined into single graph nodes) or decomposed (divided into multiple nodes), loops may be split, with the logical loop replicated and independent calculations to form bodies to separate loops. Loop analysis may be performed and conversion to establish the form may be performed to extract as much parallelism as possible. This use of sets may extract more parallelism than the target can support, in this case established oriented operations being converted back to the loop forming while retaining some fixed degree of parallelism. This is an optimization step - for hardware conversion, the problem being replicated in circuits, for software, the problem being memory and network topology.

[00020] Figure 3 is a diagram of a computer system configuration implementing the compilation process. The system of Petition 870220019259, dated 07 / 03 / 2022, page 25 / 102 10 / 36 computer 301 may include a processor or set of processors 303 to execute a compiler 305 implementing the compilation processes described herein. In another configuration, the compiler 305 and associated processes may be executed in a distributed manner across multiple computer systems communicating with each other. For the sake of clarity, a configuration executed within a single computer system will be described below. However, a person skilled in the art will understand that the principles and structures described herein are consistent with other configurations having other configurations as distributed implementations.

[00021] In one configuration, the compiler 305 includes a front-end compiler 307, a middle-end compiler (linker) 309, and a back-end compiler (code generator) 311, which divides the responsibilities of generating the target object code. The front-end compiler 307 performs a set of checks on the program's source code 315 to determine if the program has correct programming language syntax and semantics. Improper syntax and semantics are reported and may cause the compilation process to fail at the end of this stage. The front-end compiler 307 may also perform a type check to confirm that all data is properly handled by the program's source code type 315. If the syntax, semantics, and type are correct, then the front-end 307 generates an intermediate code 317 based on the source code for processing by the middle-end compiler 309.Intermediate code 317 is a representation of the program for internal use by compilers that facilitates conversion to object code 321.

[00022] The median extreme compiler 309 reconstructs the ASTs procedure from the intermediate code 318, then performing recursion removal, transformation to the functional dependency graph, and oriented established transformation to generate the functional data flow shape. A Petition 870220019259, dated 07 / 03 / 2022, page 26 / 102 11 / 36 transformation to the functional dependency graph automatically achieves a number of traditional architecture-independent optimizations, including: removal of redundant, unused, and unreachable code; propagation of constant values, extraction of non-variant loops, and similar optimizations. The median extreme compiler 309 may generate other intermediate code 317 to be further processed by the subsequent extreme compiler 311, although the typical case is for the subsequent extreme compiler to be a second stage of the executable linker.

[00023] The 309 median extreme compiler is separate from the front-end extreme compiler and can run as a parallel process, especially for large programs. This is a step in which the conversion to functional data flow graphs occurs as described in relation to Figure 2. The 309 median extreme compiler reads objects in all modules, collecting a global variable table, a global type table, and local module variable tables (at least one per module), which builds the global procedures table. A transformation of recursive functions into iterative form is performed. Indirect function calls are converted to switch tables and indicated to be generated for the switches. Starting with the primary procedure or function of the program (e.g., “main” in C binding languages), an AST step is performed.Each procedure call is effectively expanded inline during this process, and a dependency graph of the integral program is then constructed. In some configurations, a loop analysis may be performed and the set conversions may be carried out to extract as much parallelism as possible. This use of sets may allow for more parallelism than the target can support, so it is normal to convert established operations oriented back to loop form while retaining some fixed degree of parallelism. This is an optimization step – for hardware conversion, the issue being replicated in-circuit; for software, the issue being memory and network topology. Petition 870220019259, dated 07 / 03 / 2022, page 27 / 102 12 / 36

[00024] In one configuration, the extreme post compiler 311 converts the intermediate code 317 into object code 321, a set of object files or similar code. The prepared intermediate code 317 is converted into another programming language that is executable or partially executable by a target processor or platform. This process may involve instruction substitution and rearrangement. The process may also include resource allocations such as register transfers and similar details. The extreme post compiler also lends itself to identifying and implementing a level of parallelization specific to the target platform hardware by attempting to transfer the code for execution on each of a set of processors or execution units.For hardware translation, the subsequent extreme compiler can translate the specialized functional data flowchart into a Petri net to follow and form an asynchronous hardware configuration (GALS - globally asynchronous, locally asynchronous) processing to complete the conversion.

[00025] In an additional configuration, for the generation of executable code, it will be necessary to aggregate the graph nodes (otherwise, task scheduling overhead becomes a problem), to determine a memory table (which memory is used when, it is not an issue for conventional approximations), and to optimize the graph node-level code and map the graph structure to a model at runtime). Then, the extreme later compiler can still convert the intermediate code 3154 into an executable 329. The extreme later compiler 311 links together the object code generated by the compiler to create the executable 329 that can run on the target platform. The extreme later compiler 311 combines the individual object code 321 with the library code and other object code to enable platform-specific operation and source code execution 315. Petition 870220019259, dated 07 / 03 / 2022, page 28 / 102 13 / 36

[00026] The median extreme compilation process may also utilize a global procedure table 327, a matrix of first variable references 319, and a wavefront table 323. The global procedure table 327 pre-locates the processed procedures for subsequent use in the compilation process. The global procedure table 327 may have entries corresponding to the names or identifiers of the procedures with relative object codes, intermediate codes, source codes, as well as ASTs for each procedure. The matrix of first variable references 319 locates the initial value for each variable in the computer program. The wavefront table 323 locates the most recent value of the variables during the compilation process.

[00027] Processors 303 can communicate via a bus 313, chip-level or area network system, or similar communication systems with a working memory 325 storing the source code 315, intermediate code 317, object code 321, and executable 329. The working memory 325 may be any type of storage device such as a solid-state random access memory 329. The working memory 325 may store any of the above-mentioned data structures (i.e., global procedure table, array of first variable references 319, wavefront table 323, and similar data structures). In addition to storing compiled code, the working memory 325 and persistent storage devices (not shown) are responsible for storing the execution of compilers and linkers 327.

[00028] Working memory 325 may be in communication with processors 303 via bus 313. However, a person skilled in the art will understand that bus 313 does not strictly mean that only one bus separates processors 303, and bus 303 may include intermediate hardware, firmware, and software components that implement communication between processor 303 and compiler 305. One Petition 870220019259, dated 07 / 03 / 2022, page 29 / 102 14 / 36 A person skilled in the art will understand that computer system 301 is provided by way of example and not limited to well-known structures and components of a computer system 309 having been omitted for clarity.

[00029] Introduction to Functional Data Flow

[00030] In the early 1990s, Ferrante and Cytron introduced the static single assignment (SSA) form. In the SSA form, each variable is assigned only once; each assignment of a variable in the source program introduces a new variant. References to variables in the source program are replaced with “δ” functions that select the variant assignment procedure. The SSA form enables a number of optimizations of the integral program. This affects the compiled toolchain where time-bound optimization is now possible. SSA can be applied to applicable parallelism, but with questionable results. The problem is that SSA locates dependencies even though it is parallel decomposition; execution still follows a single logical control flow path. Functional data flow provides a replacement for the SSA form that directly supports the extraction of parallelism.In data flow execution models, programs are defined as a combination of a graph that governs the execution sequence and a collection of “actors” that execute parts of the program. Each node in the graph is occupied by an actor, each edge connecting the linked vertices (also referred to as “arcs”) carrying data (“tokens”). Individual nodes “fire” when all their input arcs carry tokens; after the lighting is complete, the tokens are placed on the output arcs. The functional data flow form (as defined here) is a program representation in which actors are functions with zero or more inputs to a single output, except for actors that manage the control flow: these are treated as nodes of special types. Additionally, arcs may represent sets (collections of unnamed items), and there are special node types for handling subsets of sets. Petition 870220019259, dated 07 / 03 / 2022, page 30 / 102 15 / 36 selecting and replacing elements in a set or adding elements to a set.

[00031] It should be noted that the specific form of data flow established here is provided by way of example rather than limitation. A person skilled in the art will understand that alternative representations may be used consistent with the principles and structures described herein. Any form of data flow may be used that explicitly represents the sets and the control flow to enable optimization processes.

[00032] With SSA forms, the optimizations made possible by data flow models occur primarily at link time or at the median extreme compiler, and that median extreme compiler (i.e., a linker) can be a parallel program. In this process, there are no restrictions on program transformation other than the program outputs between executions of the parallelized program and its equivalent sequential version.

[00033] The Functional Data Flow Model

[00034] This process begins with the generation of a dependency graph; while graphs for modules are generated by separate compiler invocations, they are stitched together at link time to form an integral program dependency graph. Assignment reports become nodes in the graph, with each node representing a calculation, control flow, or manipulation set. Figure 4 is a diagram of a basic data flow node configuration. These basic nodes include function nodes, merge nodes, stream nodes, select nodes, and aggregate nodes. Nodes are connected by arcs representing data items.

[00035] A “function” node (a) converts a set of inputs into a single (or zero) output. A “fusion” node (b) accepts an input from multiple possible sources and outputs an input value; this is the equivalent of a function. Petition 870220019259, dated 07 / 03 / 2022, p. 31 / 102 16 / 36 Φ in SSA form and represents a reference to a value that can be set in multiple places. A “transmission” node (c) takes a single input and output that goes into multiple destinations. Transmission nodes may also represent data storage elements; a transmission node with a single output is guaranteed to be a “storage” node that can be referenced multiple times. This is normal behavior for internal loop referencing. A “derivation” node (d) evaluates a control input to select one of several output arcs to route data to. This is a usual way to handle conditional reports. Derivation nodes handle all control flow operations. A “selection” node (c) selects an item or sub-item from a set (like aggregated data). A simple example is selecting an element from an array, in this case A[j] is the jth (j being the selector) element in array A.An “update” node (f) to update the element values ​​in a set or add to the set. A simple example is A[j] = value, but dynamic operational sets are also possible.

[00036] “Function” nodes represent normal calculations of values ​​in a program, while “merge” nodes represent references to a variable whose last assignment may have occurred in multiple places in a program (consider an if .. a = x.. also.. a = y.. then report, which could be x or y, depending on which alternative was chosen). “Transmission” nodes complement “merge” nodes; they represent unique assignments that are referenced at multiple points in a program.

[00037] Arrays are a common feature of programming languages, and are a way to package items without having to name each variable. This is a convenient way to abstract large datasets, but unskillful for dependency graphs. The functional data flow model incorporates basic sets of operations such as item / subitem selection replacement or inclusion. All sets are indexed - they have to be Petition 870220019259, dated 07 / 03 / 2022, p. 32 / 102 17 / 36 Some form of extracting a single item from a set for processing, followed by selecting the next item, imposes an ordering on the index. Multi-dimensional arrays are treated as arrays of arrays: A[i][j] is the jth entry in the set A[i][.]. This makes it possible for data sets, including the determination that establishes operations that can be executed in parallel and that must be executed in an ordered sequence.

[00038] Set of business operations with parallelism such that: f({a,b...}) = {f(a),f(b),...} for functions of a single variable and f({ai}, {bi}, {a}, ...) = {f(a,bi,a...)} for functions of multiple variables.

[00039] Extensions of control nodes to sets are simple; diffusion and fusion differ only in having oriented values, while deviations with sets of control values ​​are equivalent for establishing deviations for individual control values. Similarly, oriented, selected, and aggregated nodes may have suboriented control values. In the extension to establish the operation, arcs may represent sets not only with a single data item. For main programming languages, sets are derived: there are no sets in the initial transformation to form functional data flow, but they are derived in subsequent rewritten graphs.

[00040] Figure 5 is a diagram of a configuration of an example set of control flow structures. The derivation node is used to implement familiar control flow constructs, in the case of “... also ...” and a “for” loop; the “C” switch statement is another common example. The transformation of a derivation structure into form is not necessarily one-to-one, being one-to-many with one derivation per assigned variable. Example (a) in Figure 5 is very simple, depending on the control value, the input data is derived to Petition 870220019259, dated 07 / 03 / 2022, page 33 / 102 18 / 36 “true” input or “false” input, the result of computation f or g is then input into the following function node.

[00041] Example (b) in Figure 5 is more complex: it represents how to loop (start(); condition(); next()), although start() is omitted to simplify the graph (the index arcs will have two origins, initial() and following(), merged). The complexity rises from the mixing of control and data calculations. Example (c) in Figure 5 shows the effect of having a set of control values, multiple derived outputs being activated.

[00042] Functional data flow has very simple rewrites. Successive function nodes can be composed; functions can be moved through control nodes (data paths). Rewritten sets can be used to extract loop parallelism; these features are discussed in detail below; Construction of the Functional Data Flow Chart

[00043] The following is an example of a detailed configuration of the process described above with respect to Figure 5. The first step is to convert reports in the program to canonical form. Specifically, for each assignment report in the program of the form value = expression, the following is performed: a. Replace function calls in the assignment report, for example, f(x), with only temporary variables called, as an example, assume that tTemp could be like a temporary variable. b. - proceed with the assignment report using the tTemp = f(x); report, as for all other temporary items introduced. With the exception of the control flow specification, all reports in the program are now in one of the following forms: • a = expression (b, ...) • a = f(...) assignment of the results of a call to f() • f(...) procedure call Petition 870220019259, dated 07 / 03 / 2022, page 34 / 102 19 / 36 2. Construct an abstract syntax tree (AST), or equivalent representation, for each procedure / function specified in the program's source code and build a global procedure table relating the procedure name to its AST. This construction can be done while applying the rewritten step 1, that is, in parallel with step 1. 3. During construction, trace all indirect function assignments (called through pointers). For each indirect function, construct the equivalent direct function in the form of a "switch" with a unique index corresponding to each function. Replace the variable indirect function with a variable index, the number of functions assigned to the indirect function, and replace the assignment reports with the assignment index.

[00044] Once the global procedure table is built, the individual procedure ASTs are processed to identify the recursive procedures. For each procedure to function, 2 stacks are maintained: One records the state of an AST (pre-order traversal), while the other contains the names of the procedures in the “called” tree. For recursive procedures, a set of procedure names—an established name that invokes (directly or indirectly) the entry in the global procedure table. For each global procedure table entry not yet labeled as recursive: 1. Press the procedure name on the call stack. 2. As procedure modules are found, check to see if (a) the node is a recursive call to the global procedure table entry and if so, label the table entry as recursive and add the contents of the name stack to the set; (b) the procedure has been labeled as recursive; then continue operating; (c) if the node is present in the name stack, the label of the corresponding entry in the global procedure table as recursive will continue to operate. Conversely, if the node is not a procedure node, continue the operation; if it is Petition 870220019259, dated 07 / 03 / 2022, p. 35 / 102 20 / 36 a procedure node, press the AST current operation node on the status stack. Press the procedure name found on the call stack; find the AST procedure in the table, and start the AST procedure operation. 3. In completing an AST operation, raise the top of the state stack and resume processing of the call tree of the item raised from the state stack.

[00044] Once all nodes have been labeled, rewrite the recursive procedures to remove the recursion. As before, 2 stacks will be maintained. 1. Operate on the tree by copying nodes until a recursive procedure node is found. 2. When the recursive node is found (referenced by another node that is the entry in the global procedure table), check if the entry in the global procedure table has the established name for the found procedure; if so, save the state, insert a label for the found procedure, and start the AST operation for the found node. If not, copy the node and continue. 3. For a reference to the global procedure table or an element of the call stack: a. Create a unique numeric identifier; add the equivalent “additional identifier for the stack, and to the relevant label” to the AST. b. Continue adding nodes to the new continuation of the AST associated with the identifier. If inside a conditional statement, the alternative will not be copied; if inside a loop, rewrite the loop appropriately (partially unwound with inline loops - and "before" the loop, the call to the recursive procedure and "after" the loop). c. Upon returning from the global procedure table entry, continue adding the identified tree to the end of the alternative chain (end). Petition 870220019259, dated 07 / 03 / 2022, page 36 / 102 21 / 36 of the tree if not in a conditional front); the next alternative is added to the new entry in the AST table and thus the nodes are added to both trees identified in the new AST table. 4. After the table entry procedure is completed, process the continuation identified ASTs; this will add a trailer in the form of a stack having inputs = stack.lift()){ Switch(i){ Case 1: Continuation 1 Pause Case 2: Continuation 2 Pause; ...}} 4. Continue until all recursive entries in the table have been rewritten. Replace the previous AST with rewritten versions.

[00045] The next step is to construct the integral program graph using the ASTs procedure as a template. Rewriting the recursive procedures may be deferred for graph construction, but the above process may be more efficient.

[00046] The process for creating the integral program graph will be described in relation to the implementation example shown below. A person skilled in the art will understand that the principles and structures described can be applied to other implementations. Each uncontrolled flow report becomes a node in the graph. Two tables are maintained during the construction of the graph. One contains matrices of the first references of each variable (local variables are plotted when they are in the Petition 870220019259, dated 07 / 03 / 2022, page 37 / 102 22 / 36 scope and forgotten when they go out of scope; this table is the “reference” table) and contains assignment matrices (the front wave table). When each assignment is processed, the assigned variable is added to the front wave table (which may replace a previous assignment) and referenced variables are linked to a previous occurrence in the front wave table or noted in the reference table. When procedure nodes are found, procedures are expanded inline.

[00047] The control flow complicates the construction process and adds multiple versions of the wavefront table. Upon input to a control structure, the wavefront table is replicated. For a multi-alternative construction, upon completion of the first alternative, the active wavefront is saved, and the next alternative is processed using another copy of the wavefront table input; upon completion of that alternative, the wavefront table is merged (inserting merge nodes when necessary) with the saved wavefront table. Alternatives can be processed in parallel; the critical issue is maintaining the partial ordering reflected in normal execution. Successful alternatives are processed in the same way; after the last alternative is processed, the input table and the merged table are used for inserting the derivation nodes.Loops are handled similarly; after loop processing, the input table and the active front wave table are inserted to insert derivation nodes linking the loop end to the loop beginning for each element in the table. GOTO reports and their corresponding labels are handled with the aid of a map associating labels with saved front waves, except for syntax which is handled similarly but using a stack to trace the context. In another configuration, an empty front wave table is introduced at the decision points instead of copying the current table, and linking the corresponding input tables as part of the merge operation. When a variable is referenced in a nested front wave table before any... Petition 870220019259, dated 07 / 03 / 2022, page 38 / 102 23 / 36 assignments to that variable, a merge node is inserted into the table as a placeholder to start the assignment.

[00048] The construction of the graph begins with the program's entry procedure (for example, a primary procedure such as "mainO" for CC++ and related languages). The graph for that procedure is constructed, including the reference to the wavefront table. Calls and stacks, when procedure references are found, are aligned as described in the recursion identification step. At the end of this process, all references have been resolved, and the result is a functional dependency graph that exposes the functional parallelism in the application.

[00049] Indexed Sets and Matrix Parallelism

[00050] The above process effectively extracts all functional parallelism—parallelism not associated with loops—but no data parallelism (loop and matrix parallelism). To extract data parallelism, it will be necessary to convert loops to parallel operations on indexed sets. Indexed sets are common in programming languages. An indexed set is a set of elements where each element can be referenced by a unique index value. In common programming languages, A{3} is the element in the array A associated with the index value 3. Other types of indexed sets occur in programming languages, including associative arrays or algorithmic tables (each element in an associative array is associated with an accessor value).Even non-indexed sets are typically indexed; the index is merely hidden from view, only becoming apparent through interaction across the set when it's possible to access the first element in a set followed by the second element. Looping over an array is equivalent to repeatedly performing the same set of operations using a single index for each iteration. The loop specification orders the iteration indices: consider the C constructs. Petition 870220019259, dated 07 / 03 / 2022, page 39 / 102 24 / 36 For(int i=0; i <n; i++) A[i]=6;

[00050] This loop assigns the zero element the value 6, so the first element will be established. Given the operation performed, assigning the value of 6 to each element, there is no reason why these operations must be done in any particular order; the assignments can easily be done in parallel.

[00051] Other loops could be replaced with an equivalent parallel loop provided the assignments that would be made in place. Consider the loop for (int i=0; i <n; i++) a[i] = a[i] + a[(i+1)% n]

[00052] This loop can be parallelized but cannot be done in place, that is, it will be necessary to transform a matrix a into a matrix b in b = malloc(sizeof(a)); for (int i=0; i <n; i++) b[i] = a[i] + a[(i+1)% n] a = b se o loop for em vez para (int i=0; i<n; i++) a[i] = a[i] + a[(i+n-1)% n]

[00053] So it cannot be paused: each iteration depends on the result of the previous one. On the other hand, the loop for (int i=2; i <n; i++) a[i] = a[i] + a[i-2]

[00055] It may be parallelized at least partially in the computation of the goals and elements for (int i=2; i <n; i+=2) a[i] = a[i] + a[i-2]

[00056] It runs in parallel with Petition 870220019259, dated 07 / 03 / 2022, page 40 / 102 25 / 36 for (int i=3; i <n; i+=2) a[i] = a[i] + a[i-2]

[00057] These examples cover a range of possibilities: if the loop operates on a single indexed value in each iteration, then it can be parallelized in place. If the loop operates on multiple indexed values, none of which precede the assigned elements, then the loop can be parallelized but not in place. Other loops can be partially parallelized if the iteration dependencies pause at the index set in the sub-indices (odd indices in the last example); these are the loops for which polyhedral methods are appropriate. Arrays are not the only sets that can be expressed in programs. Sets can occur as linked lists, binary trees, and other complex data structures. Provided that the operations can be identified within the loops, it will be possible to distinguish sets and indices for said data structures.This may be difficult in the general case, but modern languages ​​like C++ and Java have collections of canonical navigation classes and methods that simplify the analysis. Functional data flow makes it possible to alter the set representation as an optimization: matrices can be distributed across processing nodes in a parallel machine; binary trees can be represented as heaps (matrix representation of a binary tree; A[i] has children A[2i] and A[2i+1]) and distributed across processing nodes that can be represented as linked structures or collections of nodes and edges (various representations).

[00058] In a configuration, the algorithm to determine the specified order in a loop is required, or whether the loop can be executed in parallel is easy: a) During the construction of the functional dependency graph, collect the index values ​​for all array accesses for the loop, distinguishing referenced values ​​from assigned values, also Petition 870220019259, dated 07 / 03 / 2022, page 41 / 102 26 / 36 collecting addresses / references for all assignment nodes in the matrix on the graph. b) If there are only assignments for one matrix, skip to 4. c) For each assignment node, determine the matrix dependencies through a pre-order operation, first using the node's back cross-section to start the loop. For each matrix referenced in step 4, accumulate a list of dependencies from the result of the pre-order operations. Expand the dependencies of each matrix: if A depends on BC and B depends on D while C depends only on C, then the dependency list A is {B,C,D}. Determine the disjointed sets of matrix dependencies by processing each one separately. d) Each array in a dependency set compares a maximum reference index to a minimum assignment index (assuming the loop process index values ​​are in ascending order, reverse of descending order). If all arrays have reference indices that are less than or equal to their assignment indices, the loop may be processed in a disordered (parallel) manner. e) If the loop is unordered, rewrite the loop as a series of set operations. If there is only one index value, the sets are subscripted, and thus new sets will be created and written to go to 4, processing the next set dependency.

[00059] As mentioned above, this does not extract all parallelism from the loops; polyhedral methods may be applied in the remaining cases or the “dimension space” of the polytope model is also captured in the set model used here. This algorithm is presented by way of example for limitation. Other processes to determine whether the ordering specified in the loop is required may be used consistent with the principles and structures of the invention. Petition 870220019259, dated 07 / 03 / 2022, page 42 / 102 27 / 36

[00060] More generally, the analysis is done by collecting information from a deep first-order cross-section of the data flow graph; the data flowchart may be rewritten during an operation. Typical rewrites include: 1.) applying the distributive law to loop bodies to transform a multipath loop into multiple loops before conversion to establish the formula, 2.) the transformation to establish the formula, and 3.) the transformation of the node group (successive sets of operations, for example, or combinations of arithmetic operations into forms that lead to the most ideal code generation.

[00061] Synchronization and collective operation.

[00062] It should be noted that there is an implicit synchronization after each transformation set, and that the familiar “collective” operations are sets of operations that return a scaling value. There are restrictions on what constitutes a collective operation: the binary operation that combines the result of the set of calculation elements must be both associated and commutative. Since scaling variables can be used to accumulate values ​​through loop iterations, the above process should be modified to include scaling variables that have matrix dependencies. Furthermore, any assignment nodes that depend on the assigned variable will need to be rewritten: a=a op expression becoming a. b=expression; b. temp=a op b;

[00063] For the first occurrence, subsequent dependencies on a are replaced with dependencies on aeb; subsequent assignments to that dependent on a are converted and updated on b, which is re-evaluated at the temperature. At the end of the loop, a is assigned the value of a=a op b. op must not be commutative or associative, or different operations must be used, and thus the computation of a is order-dependent. Petition 870220019259, dated 07 / 03 / 2022, page 43 / 102 28 / 36

[00064] Data type composite

[00065] Composite data types of atomic types are a special case. They are treated as atomic only for creation. Assignments of composite data types are treated as “gaging” assignments of the individual variable fields. If a and b are instances of a composite data type with fields x, y, z, then a=b is treated as ax=bx, ay=by, az=bz. While fields in a composite data type can represent sets, composite data types cannot.

[00066] This makes it possible to optimize some fields in a composite data type: in languages ​​supporting classes, it will not be uncommon to use some fields in a class for transient computation; object-oriented programming styles that can propagate and approach CEFORTRAN languages ​​that lack direct class support.

[00067] Examples The following examples show the conversion of specific programs to graphs for integral program dependency that extract parallelism in the programs. The features demonstrated in these examples include parallelism task / marker; recursion; loop to establish conversion, procedure expansion and simple reporting.

[00068] Example 1: surface and volume computation (Java-like code) int length = 5; int width = 7; int height = 3; main() { int volume = getVolume(); int area = getArea; System,out.println (“Volume = “+ volume + area; “ area = “area)} int getVolume () { Return length * width * height}; Petition 870220019259, dated 07 / 03 / 2022, page 44 / 102 29 / 36 int getArea() { return 2 * (length * width + length * height + width * height)};

[00069] Figures 6A-6E are diagrams illustrating the conversion of the above program into a dependency diagram of the integral program. The first step is to analyze and construct ASTs for each procedure (i.e., main(), getVolume(), and getArea()), as well as constructing a table of initial values ​​for global variables. In this case, the initial value table is established and determined from the set of declared variables and their values ​​at the beginning of the program. Variable Initial Value Length 5 Width 7 Height 3 TABLE 1

[00070] Figures S-6C are diagrams of the ASTs for each of the procedures, principal(), getVolume(), and getArea(), for a surface and volume computation program. Each AST represents a complete abstract tree representation of the respective procedure. Figure 6D is a diagram of the representation of the initial variables and their values ​​for the integral program. These nodes represent the inputs to the graph to be constructed. After operating and traversing principal() in line with getVolume() and getArea(), Figure 6E is a representation of the integral program where getVolume() and getArea() are represented by sets of function nodes, as shown in Figure 4. In Figure 6E.These function nodes are shown on the left, taking the initial values ​​as inputs and outputting the respective volume and area results to the function node representing the rest of the AST of the main procedure(), which culminates with the output of the value on the right side of the graph via the println report. Petition 870220019259, dated 07 / 03 / 2022, page 45 / 102 30 / 36

[00071] Example 2: Fibonacci Numbers (Recursion) Void fibonacci (int n){ If ((n==0) II (n ==1)) Return 1; Return fibonacci (n-1) + fibonacci (n-2;}

[00072] Figures 7A-7C are diagrams illustrating the conversion of the above program into a dependency graph of the integral program. The first step is to analyze and construct ASTs for the single procedure Fibonacci(). In this example, there are no initial values ​​or global variables. Figure 7A is a diagram of the AST for the procedure, fibonacci(), a well-known algorithm. This AST represents the abstract full tree representation of the respective procedure. After operating on or traversing fibonacci(), Figures 7B and 7C are a representation of the integral program, where the complete graph is created by superimposing different colored nodes of the sub-graphs. In Figures 7B and 7C, the AST is shown converted using the nodes from Figure 4 to represent the graph of the integral program with planar recursion.

[00073] Example 3: Multiple vector matrix int[][] matrix = {{ 1,2], {3,4}, {5,6}}, int[] vector = {7, 8]; int[] transform (int[]m, int [] v) { int[] result = new int[3]; for (int i=0; i<3; i++)} for (int j=0; j<2; j++){ result[i] - matrix[i][j]*vector[j]; } Petition 870220019259, dated 07 / 03 / 2022, p. 46 / 102 31 / 36

[00074] Figures 8A-C are diagrams illustrating the conversion process to a multiple array vector. The Figures demonstrate the conversion of the above program. These Figures include diagrams of the final oriented parallel form. Figure 8A is a diagram illustrating the AST for the multiple array vector program. Figure 8B is a diagram illustrating the functional dataflow loop form for the multiple array vector, with the logical loop highlighted. Figure 8C is a diagram illustrating the functional dataflow version of the multiple array vector, with all parallelism removed. The loops are, by definition, semantically equivalent to the unwound form. This makes it necessary to add some form of synchronization to avoid passing some of the iterations. In Figure 8B, this is implemented by inserting the “sync” function nodes.These nodes “handle” interactions so that the updated logic (i++ or j++ in this example) for the loop is only executed after all computations in the interaction process have been performed. Figure 8C has two elements: the complete set of the multiple matrix-vector version, and a cutaway of the central computer logic for matrix [i][] + vector [] to calculate result [i]. The complete version includes cross-product nodes: these are not normally inserted into a constructed graph, but are here to help clarify the set logic. The + node in the cutaway sums a set (the sum of j of matrix [i][j] * vector [j] to produce a single value; and, in terms of parallel computing, without a “collective” operation).

[00075] Figure 9 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system within which a set of instructions, to motivate the machine to perform any one or more of the methodologies discussed here, may be executed. In alternative configurations, the machine may be connected (e.g., networked) to other machines on a Local Area Network (LAN), an intranet, an extranet, or a Petition 870220019259, dated 07 / 03 / 2022, page 47 / 102 32 / 36 Internet. The machine may operate as a server or a client machine in a client-server network environment or as a machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a mobile phone, a network application, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or not) that specify actions to be taken by that machine. Furthermore, while only a single machine is illustrated, the term "machine" should still be understood to include any collection of machines (e.g., computers) that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[00076] The exemplary computer system includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random-access memory (DRAM) with synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM(, etc.)), a static memory 906 (e.g., flash memory, static random-access memory (SRAM), etc.), and a secondary memory 918 (e.g., a data storage device), which communicate with each other via a bus.

[00077] Processing device 902 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be a microprocessor (CISC) with a limited instruction set, a microprocessor (RISC) with a reduced instruction set, a microprocessor (VLIW) with a long instruction word, a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Petition 870220019259, dated 07 / 03 / 2022, page 48 / 102 33 / 36 instructions. The 902 processing device may also be one or more special-purpose processing devices such as an application-specific integrated circuit (ASIC), a programmable field-pass array (FPGA), a digital signal processor (DSP), a network processor, or similar. The 902 processing device is configured to run a 926 compiler to perform the operations and steps discussed herein.

[00078] The computer system 900 may also include a network interface device 908. The computer system may also include a video display unit 910 (for example, a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (for example, a keyboard), a cursor control device 914 (for example, a mouse), and a signal generation device 916 (for example, a loudspeaker).

[00079] Secondary memory 918 may include a machine-readable storage medium 928 (or more specifically a non-transient computer storage medium) in which one or more instruction sets (e.g., the compiler 926) incorporating one or more of the methodologies or functions described herein (e.g., the compiler 926) are stored. The compiler 926 (i.e., including the front end, middle end or linker and / or rear end) may also reside, wholly or at least partially, within main memory 904 and / or within the processing device 902 during its execution by the computer system 900; main memory 904 and the processing device still constituting the machine-readable storage medium. The compiler 928 may also be transmitted or received over a network via the network interface device 908.

[00080] The machine-readable storage medium 928, which may be a non-transient computer-readable storage medium, may also be used to persistently store the compiler module 926. Petition 870220019259, dated 07 / 03 / 2022, page 49 / 102 34 / 36 While the non-transient computer-readable storage medium is shown in an exemplary configuration to be a single medium, the term "non-transient computer-readable storage medium" shall be understood to include a single medium or multiple media (e.g., a distributed or centralized database, and / or associated provisions or servers) that store one or more instruction sets. The term "non-transient computer-readable storage medium" may also be understood to include any medium capable of storing or encoding a set of instructions for execution by the machine that motivates the machine to perform any one or more of the methodologies of the present invention. The term "non-transient computer-readable storage medium" shall thus be understood to include, but not be limited to, solid-state memories, and magnetic and optical media.

[00081] The 900 computer system may additionally include the 926 compiler to implement the compilation process functionalities described above. The module, components, and other features described herein may be implemented as discrete hardware components or integrated into the functionality of hardware components such as ASICs, FPGAs, DSPs, or similar devices. In addition, the module may be implemented as firmware or functional circuitry within hardware devices. Furthermore, the module may be implemented in any combination of hardware devices and software components.

[00082] Some parts of the detailed descriptions that follow are presented in terms of algorithms and symbolic representations in bits of data within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art to more effectively convey the substance of their work to other those skilled in the art. An algorithm is here, and generally conceived, to be a highly consistent sequence of steps leading to a desired result. Petition 870220019259, dated 07 / 03 / 2022, pages 50 / 102 35 / 36 The steps are those requiring manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of magnetic or electrical signals capable of being stored, transferred, combined, compared, and conversely manipulated. It will sometimes be convenient, mainly for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or others.

[00083] It should be noted, however, that all these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless specifically stated otherwise, as apparent from the following discussion, it will be understood that through description, discussions using terms such as “executing”, “determining”, “establishing”, “converting”, “building”, “traversing” or similar, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other information storage, transmission or display devices.

[00084] Configurations of the present invention also relate to an apparatus for performing operations herein. This apparatus may be specially constructed for required purposes, or may comprise a general-purpose computer system selectively programmed by software stored in the computer system. Said software may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk including optical disks, CD-ROMs, magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, media of Petition 870220019259, dated 07 / 03 / 2022, page 51 / 102 36 / 36 magnetic disk storage, optical storage media, flash memory devices, other types of machine-accessible storage media, or any type of media suitable for storing electronic instructions, each coupled to a computer bus system.

[00085] The algorithms and displays presented here are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs according to their teachings, or it may be convenient to construct a more specialized apparatus to perform the required steps of the methods. The required structure for a variety of such systems will appear set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the invention as described herein.

[00086] It should be understood that the above description is intended to be illustrative and not restrictive. Many other configurations will be apparent to a person skilled in the art after reading and understanding the above description. Although the present invention has been described with specific exemplary configurations, it will be recognized that the invention is not limited to the configurations described, but may be practiced with modifications and alterations within the spirit and scope of the appended claims. Accordingly, the descriptive report and drawings are to be related in an illustrative rather than a restrictive sense. The scope of the invention shall be determined with reference to the appended claims along with the full scope of equivalents to which said claims are entitled.

Claims

1. - “METHOD IMPLEMENTED IN COMPUTER COMPITION TO IMPROVE PARALLELISM DURING THE LINKING OF A PROGRAM BY A COMPILER” comprising conversion reports of the program (201) to a canonical form removing syntax and similar aspects of the program code; and the construction (203) of the abstract syntax tree (AST) for each program procedure characterized by a cross representation (207) the program constructs a functional data flow graph in which an assignment or call or functional report is represented as an ordinary node with a single outgoing edge, with a single outgoing edge, each edge connecting edge driven typed data; a control flow decision being represented by a special set of node types;a matrix or set being represented as a first set of nodes, and arcs connecting nodes representing data items or sets, the nodes of the functional data flow graph represent computation while arcs represent data; and extraction of parallelism data, the functional data flow graph can be traversed to identify each loop in the graph that can be executed in parallel (209); transformation of each loop in a graph that can be executed in parallel into an operational set by converting the arcs connecting the nodes from representations of single items to representations of indexed collections of similar data items in the functional data flow graph (211) and removal of the logical loop.

2. "METHOD", according to claim 1, characterized by comprising identifying a recursive procedure in AST, and transforming the recursive procedure into an iterative form, by expanding or flattening (block 205) the procedures by removing the recursive definition and reformulating the recursive definition of the procedure into an iterative or similar form.

3. “METHOD”, according to claim 1, characterized by comprising the identification of indirect procedure calls AST, and the conversion of indirect procedure calls to tables or switch nodes in AST; indirect function call procedures are detected and converted to table and switch nodes by expansion or flattening which comprises placing the indirectly referenced function in-line or constructing the AST to remove in one direction and updating the global procedure table to connect each AST with the procedure name or similar identifier.

4. “METHOD”, according to claim 1, characterized in that the traversal further comprises repairing a global procedure table; calling expanding procedures, and searching for each explicit procedure call seen in the global procedure table to identify and retrieve the associated AST for insertion into the functional data flowchart.

5. "METHOD", according to claim 1, further characterized by comprising the creation of nodes representing initial global variable values, and the addition of nodes representing the initial global variable values ​​as input nodes for AST.

6. “METHOD”, according to claim 1, characterized in that the construction of the cross-sectional representation comprises the analysis of program code to identify control structures governing alternative reports, and the transformation of each control structure into a subgraph with a conditioning function and with alternative reports represented to separate paths in the graph that subsequently merge and loop. Petition 870220019259, dated 07 / 03 / 2022, p. 54 / 102 3 / 4 7. "METHOD", according to claim 8, characterized by comprising linking the subgraph structure to the functional data flowchart through the input and output interfaces of linking the subgraph structure to surround the nodes of the functional data flowchart.

8. "METHOD", according to claim 1, characterized by further comprising a flowchart of output data from the program to a compiler to guide the parallelized compilation of the program.

9. "METHOD", according to claim 1, further characterized by determining whether a loop can be executed in parallel, by: a) collecting the index values ​​for all array accesses for the loop, distinguishing referenced values ​​from assigned values, also collecting addresses / references for all array assignment nodes in the graph; b) collecting addresses or references of all array assignment nodes in the functional dependency graph; c) if there are only assignments for one array, skip to i); d) determining for each assignment node the array dependencies through a pre-order, firstly, through the posterior cross-sectional graph of the node to start the loop.e) accumulate a list of matrix dependencies from the result of preorder traversals, for each matrix referenced in the loop; f) expand the dependencies for each matrix; g) determine disjoint sets of matrix dependencies; h) process each defined matrix dependency separately; i) compare the maximum reference index with the minimum assignment index, for each matrix in a set of dependencies; j) if all matrices have reference indices less than or equal to their assignment indices, the loop can be processed in parallel; Petition 870220019259, dated 07 / 03 / 2022, page 55 / 102 4 / 4 k) rewrite the loop as a series of set operations, if the loop can be processed in parallel; l) if there is only one index value, the set operations are overwritten; otherwise, new set operations are created and written; m) repeating i) and processing the next set of dependencies.

10. "Non-transient machine-readable medium having instructions stored therein," which, when executed by a computer system, implements a method according to any one of claims 1 through 8.

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