Apparatus and Method for Improving Locking Time

Abstract

The present invention provides an apparatus for improving the lock time of a phase-locked loop. The apparatus includes: a ring oscillator including at least two delay stages, each of the delay stages having a controllable delay; and a multi-phase frequency monitor coupled to the ring oscillator to monitor the frequencies at the outputs of at least two delay stages of the ring oscillator.

Description

[0001] Priority Claim

[0002] This application claims the benefit of priority of U.S. Provisional Application No. 62 / 530,063, filed Jul. 7, 2017, entitled “Apparatus and Method for Improving Lock Time,” which is hereby incorporated by reference in its entirety for all purposes. Background of the Invention

[0003] In clock systems using ring oscillator-based phase-locked loops, multi-band oscillators are typically used for power equalization, dynamic range, and temperature drift adjustment ranges. However, existing clock sources have long lock times, which increase the latency in entering a low-power state or the latency present when entering and exiting a low-power state. Brief Description of the Drawings

[0004] Embodiments of the present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the disclosure. However, it should not be understood that the disclosure is limited to the specific embodiments, but is for explanation and understanding only.

[0005] Figure 1A A ring oscillator capable of coarse / fine delay adjustment is shown in accordance with some embodiments.

[0006] Figure 1B A graph showing frequencies and codes for different coarse-grain and fine-grain adjustments is shown in accordance with some embodiments.

[0007] Figure 2 A counter-based frequency measurement device is shown in accordance with some embodiments of the present disclosure.

[0008] Figure 3 A clock system having a multi-phase frequency measurement device coupled to a ring oscillator is shown in accordance with some embodiments of the present disclosure.

[0009] Figure 4 A phase-locked loop (PLL) having an apparatus for improving lock time is shown in accordance with some embodiments of the present disclosure.

[0010] Figure 5A A timing diagram showing the lock time of a conventional PLL is shown.

[0011] Figure 5B A timing diagram showing a reduced lock time of a PLL using a multi-phase frequency measurement device is shown in accordance with some embodiments.

[0012] Figure 6 A PLL having an apparatus for improving lock time is shown in accordance with some embodiments of the present disclosure.

[0013] Figure 7 A flowchart of a method for reducing lock time according to some embodiments is shown.

[0014] Figure 8 A chip intelligent device or computer system or SoC (system-on-chip) having a device for improving lock time according to some embodiments of the present disclosure is shown. Detailed implementation manners

[0015] To save power, a narrower adjustment range is required for the ring oscillator of the phase-locked loop (PLL), which is just sufficient to cover voltage and temperature (e.g., -40 to 125 °C) drifts. To cover a wide frequency range, coarse-grained adjustment is used according to the application. For example, the coarse-grained adjustment range for the core clock of a processor such as a general-purpose processor can be in the range of 1.6 GHz to 4.0 GHz, while the fine-grained adjustment range can be in the range of + / -10%. Here, the term "coarse-grained code" refers to a digital code used to calibrate or adjust electrical parameters such as the propagation delay of circuit elements in a coarse-grained amount.

[0016] In contrast, the term "fine-grained code" refers to a digital code used to calibrate or adjust electrical parameters in an amount smaller than the coarse-grained amount used by the coarse-grained code. Generally, the coarse-grained code is applied to the circuit element before applying the fine-grained code. The terms "adjustment" or "calibration" with reference to the coarse / fine attribute generally refer to adjusting the value of the coarse-grained code or the fine-grained code. Here, the term "code" refers to a digital signature of two or more bits.

[0017] Calibrating the coarse-grained adjustment / fine-grained adjustment of the ring oscillator to select the correct frequency band or target frequency band can directly affect the lock time of the phase-locked loop PLL (or frequency-locked loop FLL). The lock time is a performance parameter indicating when the PLL or FLL has obtained phase and / or frequency lock relative to the reference clock. Generally, when the PLL is declared locked, the downstream logic can safely use the output of the PLL. The lock time may affect the frequency at which the system enters the low-power mode (e.g., sleep state) and returns to the active mode (e.g., operating state) to save power. For example, after the PLL announces successful lock, the operating state or active state will be announced. In some low-power states, the PLL power supply voltage is reduced or turned off, resulting in the PLL losing lock. To regain lock, the PLL must start phase and frequency adjustment until lock is obtained again. This process is time-consuming and directly affects the speed at which the processor enters the operating state from the low-power state.

[0018] When accelerating the adjustment process of the coarse-grained / fine-grained code to improve the lock time, it may lead to a loss of precision. The inaccurate frequency adjustment due to the acceleration of the coarse-grained / fine-grained calibration may result in a longer lock time (e.g., cycle slips) or, in extreme cases, an inability to lock.

[0019] Various embodiments improve the lock time through multi-phase frequency measurement. Some embodiments describe a device that shortens the frequency measurement time with the same precision (as in the case of long or traditional frequency measurement times) by utilizing the intermediate phases available in a ring oscillator. For example, the intermediate phases from each delay stage or element in the ring oscillator are monitored to determine the frequency of the oscillator. Then, this frequency information from the intermediate phases is used to calibrate the coarse-grained code, which results in a faster adjustment of the oscillator frequency towards the target frequency. After determining the coarse-grained code, the fine-grained code is adjusted to finely adjust the oscillator frequency to reach the target frequency or the desired frequency. Some embodiments directly show an improvement in the lock time that is proportional to the number of stages in the ring oscillator. Since the lock time is mainly determined by the coarse-grained adjustment, the shortened frequency measurement time can directly shorten the lock time in the PLL. From the various embodiments and the drawings, other technical effects will become apparent.

[0020] In the following description, many details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present disclosure.

[0021] Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more component signal paths, and / or have arrows at one or more ends to indicate the main information flow. Such indications are not intended to be restrictive. Instead, these lines are used in conjunction with one or more exemplary embodiments to facilitate an easier understanding of the circuit or logic unit. As indicated by design needs or preferences, any represented signal may actually include one or more signals that can propagate in either direction and can be implemented with any suitable type of signal scheme.

[0022] Throughout the specification and in the claims, the term "connected" refers to a direct connection between the objects being connected, such as an electrical connection, a mechanical connection, or a magnetic connection, without any intermediate device. The term "coupled" refers to a direct or indirect connection through one or more passive or active intermediate devices, such as a direct electrical connection, a mechanical connection, or a magnetic connection or an indirect connection between the connected objects. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural forms. The meaning of "in" includes "in" and "on".

[0023] The term "scaling" generally refers to converting a design (schematic and layout) from one processing technology to another and then reducing its layout area. The term "scaling" generally also refers to shrinking the layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or accelerating - i.e., shrinking or magnifying respectively) the signal frequency with respect to another parameter (e.g., power level). The terms "substantially", "near", "approximate", "close to", and "about" generally refer to within + / - 10% of the target value.

[0024] Unless otherwise specified, the use of ordinal adjectives "first", "second", "third", etc. to describe a common object only indicates that different instances of similar objects are being referred to and is not intended to imply that the objects so described must be given an order in time, space, rank, or any other way.

[0025] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0026] In the specification and claims, the terms "left", "right", "front", "rear", "top", "bottom", "above", "below", etc. (if any) are used for descriptive purposes and not necessarily to describe a permanent relative position. For the purposes of this disclosure, the terms "spin" and "magnetic moment" are used equivalently. More precisely, the direction of spin is opposite to the direction of the magnetic moment, and the charge of the particle is negative (e.g., in the case of an electron).

[0027] For the purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are metal oxide semiconductor (MOS) transistors or derivatives thereof, where the MOS transistors include a drain, a source, a gate, and a body terminal. The transistors and / or MOS transistor derivatives also include Tri-Gate and FinFET transistors, cylindrical fully-depleted surround gate transistors, tunneling FETs (TFETs), square wire or rectangular strip transistors, ferroelectric FETs (FeFETs), or other devices that implement transistor functionality, such as carbon nanotubes or spintronic devices. The symmetric source and drain terminals of a MOSFET are the same terminals and can be used interchangeably herein. On the other hand, a TFET device has asymmetric source and drain terminals. Those skilled in the art will understand that other transistors, such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., can be used without departing from the scope of the present disclosure.

[0028] It should be noted that Figure 3 those elements having the same reference numerals (or names) as the elements of any other figure can operate or function in any manner similar to the manner described, but is not limited thereto.

[0029] Figure 1A An annular oscillator 100 capable of performing coarse-grained / fine-grained delay adjustment is shown in accordance with some embodiments. Figure 1A An example of a coarse-grained / fine-grained adjustment architecture is shown, where the coarse-grained adjustment sets a frequency target, and the fine-grained adjustment adjusts the frequency based on the operating environment through capacitive adjustment.

[0030] In this example, the annular oscillator 100 has five delay stages or elements 101. Each delay stage includes circuit knobs to adjust its propagation delay (e.g., the delay from input "in" to output "out") in coarse-grained and fine-grained measures. In some embodiments, the delay stage 101 includes a plurality of inverters (e.g., 101 a1 to 101 aN ) coupled in parallel with each other, and the inverters can be enabled or disabled to increase or decrease the drive strength of the delay stage. In some embodiments, each inverter (e.g., 101 a1 ) can be enabled or disabled by turning on or off devices MP and MN coupled to the inverter. These devices receive a coarse-grained code that determines which devices to turn on or off, and thus determines the enabled inverters. Here, the coarse-grained adjustment devices are MP1 to MP N and MN1 to MN N。These devices are serially coupled to the transistors of the inverter. For example, the p-type transistor of the inverter is serially coupled to the MP device, and the n-type transistor of the inverter is serially coupled to the MN device. In some embodiments, fine-grained adjustment is performed by capacitor devices C1 to C N using controllable switches SW1 to SW N coupled to the output “out” of the delay stage. The fine code is applied to switches SW1 to SW N which couple or decouple the capacitor devices to the output node. N

[0031] In some embodiments, switches SW1 to SW N are implemented as devices such as n-type transistors, p-type transistors, or a combination of both. In some embodiments, the capacitor devices are implemented as transistors configured as capacitors, metal capacitors, or a hybrid of transistors and metal capacitors. Each embodiment is not limited to a specific architecture of the ring oscillator. For example, instead of the coarse adjustment devices of MP1 to MP N and MN1 to MN N each delay stage of the ring oscillator may include a large capacitor device for coarse adjustment and a small capacitor device for fine adjustment, and digital control switches may be used to add capacitor devices to the output node. Although a ring oscillator 100 with five delay stages is shown, the ring oscillator may have at least two delay stages coupled together in a ring form. The maximum number of delay stages may be based on the target frequency requirements. N

[0032] Figure 1B A graph 120 showing the frequency and code for different coarse-grained and fine-grained adjustments according to some embodiments is shown. The figure shows that the coarse-grained setting selects the main frequency range identified by codes code1 to code N and then the fine-grained adjustment achieves the operating frequency target of the selected coarse code to compensate for process, voltage, and temperature (PVT) drifts. As described above, the PLL lock time performance is directly affected by the coarse-grained / fine-grained code selection. For example, slowly selecting the target coarse-grained code for the target frequency may slow down the PLL lock time. Conversely, attempting to quickly select the coarse-grained code may cause PLL loop stability problems and other inaccuracies.

[0033] Figure 2FIG. 200 shows a counter-based frequency measurement device according to some embodiments of the present disclosure. In some embodiments, the circuitry of device 200 is coupled to each delay stage of oscillator 101. For example, the output of delay stage 101 of oscillator 100 is coupled to counter 202, and the output of another delay stage 101 of oscillator 100 is coupled to another counter 202 (not shown). In some embodiments, counter 202 is an incrementing counter that counts the rising and / or falling edges of the signal at node “out” of the delay stage coupled to the counter. In this way, counter 202 determines the frequency of the output of the delay stage. In other embodiments, counter 202 can be a decrementing counter that counts down from a known value. Any suitable counter can be used to implement counter 202.

[0034] In certain embodiments, the output of counter 202 is sampled by flip-flop 203, where flip-flop 203 uses a clock that is slower than the reference clock of the PLL. For example, a frequency divider 205 is provided that divides the reference clock RefClk by a factor “N” and provides the divided clock Clk to flip-flop 203 to sample the output of counter 202. By sampling the output of counter 202 using the divided clock, a filtering mechanism is introduced. In this way, a more accurate frequency is determined. The output of flip-flop 203 is the measured frequency of the signal generated by the delay stage of the oscillator.

[0035] In various embodiments, a finite state machine (FSM) 204 is provided that receives measured frequency data from the outputs of two or more delay stages of the ring oscillator and uses this data to determine the average frequency. Then, FSM 204 compares the average frequency with the target frequency to determine whether to increase or decrease the value of the coarse-grained code. Then, the coarse-grained code is provided to all delay stages of the ring oscillator for coarse-grained adjustment. In one example, the measurement accuracy is 2 / N(f REF ), where f REF is the frequency of the reference clock. In a ring oscillator with a minimum frequency band interval of 20 MHz, the required accuracy is 10 MHz. Using a 100 MHz reference clock, N is 20. Using a binary search algorithm with a 10-bit coarse-grained adjustment design, it will take 200 clock cycles to find the best frequency band. This may result in a lock time consumption of 2 microseconds. In some embodiments, FSM204 applies Figure 7 of the flowchart to implement a fast lock architecture.

[0036] Figure 3 FIG. 300 shows a clock system 300 having a multi-phase frequency measurement device 301 coupled to a ring oscillator 100 according to some embodiments of the present disclosure.

[0037] Through the intermediate node of the tapping oscillator 100, more edges (information) are available. In some embodiments, for each delay stage, the polyphase frequency monitor 301 has a structure as shown in Figure 2 (minus the FSM 204 and oscillator delay stage). By tapping into different phases, the frequency measurement accuracy is increased by a factor of M. For example, for the same number of reference clock cycles, the increased accuracy is (2 / (MN))f REF . To achieve the same accuracy, as described above, according to some embodiments, the lock time is reduced by a factor of M. In some embodiments, the FSM 304 / 204 averages the results from various counters coupled to the respective delay stage taps. The averaged result improves the accuracy.

[0038] To illustrate how the accuracy is improved, assume that the oscillation frequency (fosc) is 40.4f REF . In the original scheme of counting the final output of the oscillator 100, the ideal measurement result is "41" after one reference clock cycle. However, in Figure 3 , assume a 5-stage oscillator is used, and the results of counting the frequency at the output of each delay stage are [41 41 40 40 40]. The average result is "40.4". By tapping into different phases, the fractional accuracy is improved. Further optimization can be achieved by measuring the rising and falling edges, thereby reducing the coarse-grained lock time by a factor of 2, for example, saving 10 times the lock time. In this way, the lock time of the processor is improved, thereby increasing the system response speed. The improved system response ability can maximize the opportunity to enter the low-power state when the clock is turned off.

[0039] Figure 4 FIG. shows a phase-locked loop (PLL) 400 having means for improving the lock time according to some embodiments of the present disclosure. In some embodiments, the PLL 400 includes a phase detector (PD), a phase-frequency detector (PFD), or a time-to-digital converter (TDC) 401, a controller 402, a digital loop filter (DLF) 403, an oscillator 100, a polyphase frequency monitor 404, a frequency divider 405, a lock detector 406, and a Σ-Δ modulator 407 coupled together as shown. The PD, PFD 401 generate up / down pulses or signals based on the phase difference between the reference clock (RefClk) and the feedback clock (FbClk). The PD is a circuit that generates an up signal and a down signal that represent the phase difference between RefClk and FbClk. The PFD can generate up pulses and down pulses that contain the phase and frequency differences between RefClk and FbClk.

[0040] The control machine 402 receives up / down pulses and generates digital codes for coarse-grained adjustment and fine-grained adjustment. Then, the digital codes are filtered by a digital loop filter (DLF). The output of the DLF is the coarse F and the fine F, which are used to adjust the delay of each delay stage of the oscillator 100. The divider 405 receives the output "oscillator clock" of the oscillator 100 and divides it to generate a feedback clock (FbClk). In some embodiments, the Σ-Δ modulator 407 is used to generate the division ratio N of the divider. The division ratio N can be an integer or a fraction.

[0041] Here, two feedback loops are shown. The first feedback loop is a short loop and includes the control machine 402, the DLF 403, the oscillator 100, and the polyphase frequency monitor 404. The second feedback loop is a longer loop and includes the PD or PFD, 401, the control machine 402, the DLF 403, the oscillator 100, and the divider 405. In some embodiments, when the PLL wakes up from a reset or low-power state that requires the PLL to relock, the first feedback loop is enabled. The first feedback loop is used to quickly determine the coarse code that brings the oscillator output close to the target frequency. In the first feedback loop, the divider 405 and the PFD 401 are bypassed to achieve a faster response. In one such embodiment, the up and down outputs from the PFD 401 are ignored by the control machine 402, and the output measurements from the polyphase frequency monitor 404 are used to determine the coarse-grained code. In some embodiments, the digital loop filter 403 can also be bypassed in the first feedback loop.

[0042] In some embodiments, the polyphase frequency monitor 404 monitors the outputs out1 to out of each delay stage of the oscillator 100 N at the frequency and determines the clock frequency at the output of each delay stage. Then, the frequencies from each delay stage are averaged by the FSM 304 (which is part of the polyphase frequency monitor 404 here), and the average output is the measurement value. Then the output measurement value is received by the control machine 402, which adjusts the coarse-grained and / or fine-grained codes to speed up the lock time. The lock detector outputs a lock indicator based on the up / down signal and / or the reference clock (RefClk) and the feedback clock (FbClk).

[0043] After the FSM 304 determines that the oscillator clock frequency is close to the target frequency (e.g., within 10%), the first feedback loop is disabled and the second feedback loop is enabled. For example, the control machine 402 now uses the up signal and the down signal to control the coarse-grained code and the fine-grained code and bypasses the output measurements. This switching mechanism can be implemented by a multiplexer (not shown). Since the coarse-grained code has been determined by the first feedback loop, the second feedback loop uses the coarse-grained code generated by the first feedback loop to perform fine-grained adjustment.

[0044] In some embodiments, the PD or PFD 401 is replaced by a time-to-digital converter (TDC) 401 that generates a digital bitstream indicative of the phase error between RetClk and FbClk. This digital bitstream replaces the up / down signal. The TDC is a circuit that converts the phase error between RefClk and FbClk into a digital output. The digital output can be in the form of an up / down signal or encoded in other formats. These other formats can include an output that can be a real number representing the phase error. For example, the real number can indicate that RefClk leads FbClk by 10 ps. In another example, another format can indicate a number such as RefClk leads FbClk (e.g., output = 1) or RefClk lags behind FbClk (e.g., output = 0).

[0045] In some embodiments, the lock detector 406 receives the digital output of the TDC 401 to determine when lock is indicated. For example, when the digital output indicates an error below a threshold (e.g., predetermined or programmable), the lock detector 406 then indicates lock. In some embodiments, when the first feedback loop is enabled, the control machine 402 ignores the output of the TDC 401 and uses the output measurement to adjust the coarse-grained code (which is then filtered by the digital loop filter 403). Once the target coarse-grained code is determined, the first feedback loop is disabled, and then the control machine 402 uses the digital output of the TDC 401 to adjust the fine-grained code.

[0046] Figure 5A A timing diagram 500 is shown that shows the lock time of a conventional phase-locked loop. Figure 5B A timing diagram 520 is shown that shows the reduced lock time of a phase-locked loop using a multi-phase frequency measurement device according to some embodiments. In the timing diagram 500, the lock time starts after reset (e.g., a signal that causes the PLL to start locking). After reset, the PLL uses its conventional feedback loop to determine the coarse-grained code. Once the coarse-grained code is determined, a "done" signal is determined, and the fine-grained code is set for final locking of the PLL. In the timing diagram 500, the search for the coarse-grained code starts immediately after reset using a short feedback loop. In this way, the determination of the coarse-grained code is faster (e.g., 10 times faster) compared to the conventional case in the timing diagram 500. Once the coarse-grained code is determined, the signal "done" is determined, and the first feedback loop (or short feedback loop) is disabled, and the second feedback loop (or normal long feedback loop) is enabled to determine the fine-grained code. Once the fine-grained code is set (e.g., within tolerance), the lock signal is determined.

[0047] Figure 6Shows a PLL 600 having means for improving lock time according to some embodiments of the present disclosure. The PLL 600 includes a PD, PFD or TDC 601, a loop filter 603, an oscillator 100, a polyphase frequency monitor 404, a divider 405, a lock detector 606, and a Σ-Δ modulator 407. The PD, PFD or TDC 601 generates a phase error based on the phase difference between a reference clock (RefClk) and a feedback clock (FbClk). As discussed in reference Figure 4 When using a PD, PFD, an up pulse or signal and a down pulse or signal are generated to indicate the phase error. Similarly, when using the TDC 601, a digital bit stream will be generated to indicate the phase error. In Figure 6 , the TDC 601 is used to illustrate the means. The loop filter 602 filters the phase error and generates a fine-grained code. In this case, within its tolerance range, a coarse-grained code is determined prior to setting the fine-grained code. Compared with Figure 4 , the first feedback loop here is much shorter and is used to determine the coarse-grained code. The first feedback loop includes the oscillator 100 and the polyphase frequency monitor 404. The second feedback loop includes a PD or TDC 601, a loop filter 602, an oscillator 100, and a divider 405. In this embodiment, the coarse-grained code does not pass through the loop filter 602. Once the coarse-grained code is determined, the first feedback loop is disabled and the coarse-grained code is locked. Then, the PLL uses a conventional long loop (or second loop) to adjust the fine-grained code. When the fine-grained code approaches a predetermined tolerance level, the phase error is small enough for the clock detector 606 to declare lock.

[0048] Figure 7 Shows a flowchart 700 of a method for reducing lock time according to some embodiments. At block 701, the PLL starts to lock (e.g., after reset, after the clock is powered off). At block 702, the first feedback loop (or short loop) is enabled to determine the coarse-grained code. At block 703, the FSM 304 determines whether the coarse-grained code results in an oscillation frequency close to the target frequency. For example, as shown in Figure 1B , a coarse-grained code is selected that causes the target frequency to be substantially in the middle of the range of that coarse-grained code. If the coarse-grained code is still far off and the propagation delay of the delay stage needs to be further adjusted by the coarse-grained code, the process continues to block 702 and another coarse-grained code is selected. In another embodiment, when the target frequency is approximately in the middle of the range of the coarse-grained code, the coarse-grained code is frozen as shown in block 704. Then, the process continues to block 705, where the second feedback loop (or normal feedback mode) is enabled and the fine-grained code is set. When the fine-grained code jitters near the target frequency, the PLL declares lock.

[0049] Figure 8 Shown is a smart device or computer system or SoC (System on Chip) having an apparatus for improving lock time, in accordance with some embodiments of the present disclosure. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, mobile phone, or smart phone, a wireless-enabled electronic reader, or other wireless mobile device. It will be understood that certain components are generally shown and all components of such a device are not shown in computing device 1600.

[0050] In some embodiments, according to some of the embodiments discussed, computing device 1600 includes a first processor 1610 having an apparatus for improving lock time. According to some embodiments, other blocks of computing device 1600 may also include an apparatus for improving lock time. Various embodiments of the present disclosure may also include a network interface within 1670, such as a wireless interface, so that system embodiments can be incorporated into wireless devices, such as cellular phones or personal digital assistants.

[0051] In some embodiments, processor 1610 (and / or processor 1690) may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. Processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and / or device functions are executed. Processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, and / or operations related to connecting computing device 1600 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0052] In some embodiments, computing device 1600 includes an audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone output, as well as microphone input. Devices for such functionality may be integrated into computing device 1600 or connected to computing device 1600. In one embodiment, a user interacts with computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0053] In some embodiments, computing device 1600 includes a display subsystem 1630. The display subsystem 1630 represents hardware (e.g., a display device) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with the computing device 1600. The display subsystem 1630 includes a display interface 1632, which includes a particular screen or hardware device for providing a display to the user. In one embodiment, the display interface 1632 includes logic separate from the processor 1610 to perform at least some processing related to the display. In one embodiment, the display subsystem 1630 includes a touchscreen (or touchpad) device that provides both output and input to the user.

[0054] In some embodiments, computing device 1600 includes an I / O controller 1640. The I / O controller 1640 represents hardware devices and software components related to interaction with a user. The I / O controller 1640 is operable to manage hardware that is part of the audio subsystem 1620 and / or the display subsystem 1630. Additionally, the I / O controller 1640 shows connection points for attaching additional devices to the computing device 1600, through which a user can interact with the system. For example, devices that may be attached to the computing device 1600 can include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices used with specific applications such as a card reader or other devices.

[0055] As described above, the I / O controller 1640 can interact with the audio subsystem 1620 and / or the display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, an audio output can be provided instead of, or in addition to, the display output. In another example, if the display subsystem 1630 includes a touchscreen, the display device also acts as an input device, which can be at least partially managed by the I / O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I / O functions managed by the I / O controller 1640.

[0056]

[0056] In some embodiments, the I / O controller 1640 manages devices such as an accelerometer, a camera, a light sensor, or other environmental sensors, or other hardware that may be included in the computing device 1600. The input can be part of a direct user interaction as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, firing a flash for a camera application, or other features).

[0057] In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, battery charging, and features related to power-saving operations. Memory subsystem 1660 includes storage devices for storing information in computing device 1600. The memory may include non-volatile (the state does not change if power to the storage device is interrupted) and / or volatile (the state is indeterminate if power to the storage device is interrupted) storage devices. Memory subsystem 1660 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of computing device 1600.

[0058] Elements of the embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disk, CD-ROM, DVD ROM, RAM, EPROM, EEPROM, magnetic or optical card, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) that may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or network connection) by a data signal via a computer.

[0059] In some embodiments, computing device 1600 includes connectivity 1670. Connectivity 1670 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 1600 to communicate with external devices. Computing device 1600 may be a separate device, such as other computing devices, wireless access points or base stations, and peripheral devices, such as headsets, printers, or other devices.

[0060] Connection 1670 can include various different types of connections. Generally speaking, computing device 1600 is shown as having a cellular connection 1672 and a wireless connection 1674. Cellular connection 1672 generally refers to a cellular network connection provided by a wireless carrier, such as a cellular network connection provided via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, or other cellular service standards. Wireless connection (or wireless interface) 1674 refers to a non-cellular wireless connection, which can include a personal area network (such as Bluetooth, near field, etc.), a local area network (such as Wi-Fi), and / or a wide area network (such as WiMax) or other wireless communications.

[0061] In some embodiments, computing device 1600 includes a peripheral connection 1680. Peripheral connection 1680 includes a hardware interface and connector for making peripheral connections and software components (such as drivers, protocol stacks). It will be understood that computing device 1600 can be both a peripheral device to other computing devices ("to" 1682) and have peripheral devices connected thereto ("from" 1684). Computing device 1600 typically has a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) the content on computing device 1600. Additionally, the docking connector can allow computing device 1600 to connect to certain peripheral devices 1600 that allow computing device 1600 to control the output of content to, for example, an audio-visual or other system.

[0062] In addition to proprietary docking connectors or other proprietary connection hardware, computing device 1600 can also make peripheral connections 1680 via common or standard-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any of many different hardware interfaces), display ports including Mini DisplayPort (MDP), High-Definition Multimedia Interface (HDMI), FireWire interfaces, or other types.

[0063] References in the specification to "one embodiment", "an embodiment", "some embodiments" or "other embodiments" refer to embodiments that include a particular feature, structure, or characteristic described in connection with at least some embodiments, but not necessarily all embodiments. Multiple occurrences of "one embodiment", "an embodiment" or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may", "might", or "could" be included, inclusion of the particular component, feature, structure, or characteristic is not required. If the specification or claim refers to "a" or "an" element, it does not mean that there is only one element. If the specification or claim refers to "additional" elements, it does not exclude the presence of more than one additional element.

[0064] In addition, in one or more embodiments, specific features, structures, functions, or characteristics may be combined in any suitable manner. For example, wherever the specific features, structures, functions, or characteristics associated with a first embodiment and a second embodiment are not mutually exclusive, the first embodiment may be combined with the second embodiment.

[0065] Although the present disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. The embodiments of the present disclosure are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0066] Additionally, to simplify the drawings and discussion, and not to obscure the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Further, to avoid obscuring the present disclosure and also in view of the fact that details regarding the implementation of such a block diagram arrangement highly depend on the platform within which the present disclosure is to be implemented (i.e., these details should be entirely within the capabilities of those skilled in the art), the arrangement may be shown in block diagram form. In cases where specific details (e.g., circuits) are set forth to describe example embodiments of the present disclosure, it should be apparent to those skilled in the art that the present disclosure may be practiced without these specific details or with variations of these specific details. Accordingly, the description is to be regarded as illustrative rather than restrictive.

[0067] The following examples relate to additional embodiments. Details in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0068] Example 1: A device, comprising: an oscillator including at least two delay circuits coupled together in a ring form, wherein each delay circuit has an adjustable propagation delay; and a first counter coupled to an output of a first one of the at least two delay circuits; a second counter coupled to an output of a second one of the at least two delay circuits, wherein the delay of the at least two delay circuits is adjusted based on outputs of the first counter and the second counter.

[0069] Example 2: The device of Example 1, wherein each delay circuit includes a first circuit for controlling a first delay of the delay circuit and a second circuit for controlling a second delay of the delay circuit, wherein the first delay is greater than the second delay.

[0070] Example 3: The device of Example 1 includes: a first timing circuit coupled to an output of the first counter; a second timing circuit coupled to an output of the second counter.

[0071] Example 4: The device of Example 3 includes a frequency divider coupled to the first timing circuit and the second timing circuit, wherein the frequency divider provides a clock to sample inputs of the first timing circuit and the second timing circuit.

[0072] Example 5: The device of Example 1 includes logic for generating an average value of outputs of the first timing circuit and the second timing circuit.

[0073] Example 6: The device of Example 1 includes a frequency divider coupled to an output of the oscillator.

[0074] Example 7: The device of Example 6 includes one of a phase detector, a phase frequency detector, or a time-to-digital converter coupled to an output of the oscillator.

[0075] Example 8: The device of Example 7 includes a lock detector coupled to an output of the phase frequency detector.

[0076] Example 9: The device of Example 8 includes a loop filter for receiving an output of the phase frequency detector, wherein an output of the loop filter is coupled to the oscillator.

[0077] Example 10: The device of Example 9, wherein the output of the loop filter is for adjusting the delay of each delay circuit by a first delay amount, wherein the outputs of the first counter and the second counter are for adjusting the delay of each delay circuit by a second delay amount, and wherein the first delay amount is shorter than the second delay amount.

[0078] Example 11: A device, comprising: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multi-phase frequency monitor coupled to the ring oscillator to monitor frequencies at outputs of at least two delay stages of the ring oscillator.

[0079] Example 12: The apparatus of Example 11, wherein the multiphase frequency monitor includes at least two counters that count the respective frequencies of the at least two delay stages.

[0080] Example 13: The apparatus of Example 11 includes logic for generating an average frequency based on the respective frequencies of at least two delay stages.

[0081] Example 14: The apparatus of Example 13, wherein the logic adjusts the delays of at least two delay stages of a ring oscillator based on the average frequency.

[0082] Example 15: The apparatus of Example 11, wherein each delay stage includes a first circuit that controls a first delay of the delay stage and a second circuit that controls a second delay of the delay stage, wherein the first delay is greater than the second delay.

[0083] Example 16: The apparatus of Example 11, wherein the ring oscillator is part of a phase-locked loop.

[0084] Example 17: A system, comprising: a memory; a processor coupled to the memory, wherein the processor includes a phase-locked loop that includes an apparatus according to any one of Examples 1 to 10; a wireless interface that allows the processor to communicate with another device.

[0085] Example 18: A system, comprising: a memory; a processor coupled to the memory, wherein the processor includes a phase-locked loop that includes an apparatus according to any one of Examples 11 to 15; a wireless interface that allows the processor to communicate with another device.

[0086] Example 19: An apparatus, comprising: means for enabling a first electrical loop that includes an oscillator and a multiphase monitor coupled to the oscillator; means for determining a first code to adjust a propagation delay of a delay circuit of the oscillator, wherein the first code is determined based on one or more outputs of the multiphase monitor; means for applying the first code to the delay circuit; means for freezing the first code when a lock indicator indicates that the frequency of the oscillator is substantially close to a target frequency; means for disabling the first electrical loop; means for enabling a second electrical loop that includes a frequency divider, a phase detector, a filter, and an oscillator, wherein the second electrical loop provides a second code to the oscillator to adjust the delay of the delay circuit.

[0087] Example 20: The apparatus of Example 19, including means for monitoring a phase error and determining whether to increase or decrease the value of the second code.

[0088] Example 21: A method includes: enabling a first electrical loop including an oscillator and a multiphase monitor coupled to the oscillator; determining a first code to adjust a propagation delay of a delay circuit of the oscillator, wherein the first code is determined based on one or more outputs of the multiphase monitor; applying the first code to the delay circuit; freezing the first code when a lock indicator indicates that a frequency of the oscillator is substantially close to a target frequency; disabling the first electrical loop; enabling a second electrical loop including a frequency divider, a bit detector, a filter, and an oscillator, wherein the second electrical loop provides a second code to the oscillator to adjust a delay of the delay circuit.

[0089] Example 22: The method of Example 21 includes monitoring a phase error and determining whether to increase or decrease a value of the second code.

[0090] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. It should be understood that the abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment.

Claims

1. An apparatus for improving lock time, the apparatus comprising: means for enabling a first electrical loop, the first electrical loop including an oscillator and a multiphase monitor coupled to the oscillator; means for determining a first code to adjust the propagation delay of a delay circuit of the oscillator, wherein the first code is determined according to one or more outputs of the multiphase monitor; means for applying the first code to the delay circuit; means for freezing the first code when a lock indicator indicates that the frequency of the oscillator is substantially close to a target frequency; means for disabling the first electrical loop; and means for enabling a second electrical loop, the second electrical loop including a frequency divider, a phase detector, a filter, and an oscillator, wherein the second electrical loop provides a second code to the oscillator to adjust the delay of the delay circuit.

2. The apparatus according to claim 1, comprising means for monitoring a phase error and determining whether to increase or decrease the value of the second code.

3. The apparatus according to claim 1, wherein the first code is a coarse-grained code and the second code is a fine-grained code.

4. The device according to claim 3, wherein The lock indicator indicating that the frequency of the oscillator is substantially close to the target frequency includes: selecting a coarse-grained code that causes the target frequency to be substantially at the middle value of the range of the coarse-grained code.

5. The apparatus according to claim 4, wherein, If the coarse-grained code is far from the middle value of the range of the coarse-grained code, the propagation delay of the delay circuit is further adjusted by the coarse-grained code.

6. A method for improving lock time, the method comprising: enabling a first electrical loop, the first electrical loop including an oscillator and a multiphase monitor coupled to the oscillator; determining a first code to adjust the propagation delay of a delay circuit of the oscillator, wherein the first code is determined according to one or more outputs of the multiphase monitor; applying the first code to the delay circuit; freezing the first code when a lock indicator indicates that the frequency of the oscillator is substantially close to a target frequency; disabling the first electrical loop; and enabling a second electrical loop, the second electrical loop including a frequency divider, a phase detector, a filter, and an oscillator, wherein the second electrical loop provides a second code to the oscillator to adjust the delay of the delay circuit.

7. The method according to claim 6, comprising: Monitoring the phase error and determining whether to increase or decrease the value of the second code.

8. The method according to claim 6, wherein the first code is a coarse-grained code and the second code is a fine-grained code.

9. The method according to claim 8, wherein, The lock indicator indicating that the frequency of the oscillator is substantially close to the target frequency includes: selecting a coarse-grained code that causes the target frequency to be substantially at the middle value of the range of the coarse-grained code.

10. The method according to claim 9, wherein If the coarse-grained code is far from the middle value of the range of the coarse-grained code, the propagation delay of the delay circuit is further adjusted by the coarse-grained code.

11. A system for improving lock time, comprising: a memory; a processor coupled to the memory, wherein the processor includes a phase-locked loop, and the phase-locked loop includes the apparatus according to any one of claims 1 to 5; and A wireless interface that allows the processor to communicate with another device.

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