Neuromorphic methods and devices with multi-bit neuromorphic operations

Abstract

A neuromorphic device configured to process a multi-bit neuromorphic operation includes a single axon circuit, a single synapse circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive the i-th bit of an n-bit axon as a first input. The single synapse circuit is configured to store the j-th bit of an m-bit synaptic weight as a second input, and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight based on the output synaptic operation value. The controller is configured to determine the i-th bit and the j-th bit to be sequentially allocated to the single axon circuit and the single synapse circuit for each time period of different time periods, respectively.

Description

Technical Field

[0001] The present disclosure relates to neuromorphic methods and devices with multi-bit neuromorphic operations. Background Art

[0002] A neuromorphic processor is a dedicated computing hardware processor that includes a neuron circuit and a synapse circuit. By way of example only, a neuron circuit may generate an activation or processing result, or a signal corresponding to such an activation or processing result, relative to other activations or processing results (or corresponding signals) of the neuron circuit, for example in a hierarchical manner, to generate an overall result. The synapse circuit may be configured to provide a connection between nodes or processing devices (e.g., processing units) of the neuron circuit. Such a neuromorphic processor, as a non-limiting example, may be used to drive various neural networks, such as convolutional neural networks (CNNs), recursive neural networks (RNNs), and feedforward neural networks (FNNs), and as a non-limiting example, may also be used in the fields of data classification or image recognition. Summary of the invention

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0004] In one general aspect, a neuromorphic device is configured to process a multi-bit neuromorphic operation, the neuromorphic device comprising a single axon circuit, a single synapse circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive the i-th bit of an n-bit axon as a first input. The single synapse circuit is configured to store the j-th bit of an m-bit synaptic weight as a second input, and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight based on the output synaptic operation value. The controller is configured to determine the i-th bit and the j-th bit to be sequentially assigned to the single axon circuit and the single synapse circuit for each time period of different time periods, respectively, and obtain the multi-bit neuromorphic operation result from a low bit value to a high bit value, wherein n and m are each natural numbers, i is a natural number between 1 and n, and j is a natural number between 1 and m.

[0005] The controller may be further configured to map i and j such that the i-th bit and the j-th bit are combined differently for different time periods.

[0006] The controller may be further configured to sequentially change the values ​​of i and j of the i-th bit and the j-th bit in increasing order of bit value.

[0007] The total number of combinations of the i-th bit and the j-th bit may correspond to a value obtained by multiplying n by m.

[0008] A single axon circuit and a single synapse circuit may each process a single bit value for different time periods.

[0009] The single neuron circuit may include a single adder configured to perform an addition operation using synaptic operation values ​​output from the single neuron circuit for different time periods.

[0010] The single neuron circuit may be configured to perform an addition operation using a single adder to obtain each bit value of a multi-bit neuromorphic operation result, the addition operation using as input at least one of a preset initial value, a synaptic operation value output from the single synaptic circuit in a previous time period of a different time period, a synaptic operation value output from the single synaptic circuit in a current time period of a different time period, an addition value processed by the single adder in a previous time period of the different time period, and a carry value determined by the single adder in a previous time period of the different time period.

[0011] At least one of the addition value and the carry value output from the single adder may correspond to a value of one of the bits of the multi-bit neuromorphic operation result.

[0012] A single adder may be reused to obtain the value of each bit of the multi-bit neuromorphic operation result after obtaining the value indicating one of the bits of the multi-bit neuromorphic operation result.

[0013] The single adder may be further configured to perform an addition operation by receiving as input a synaptic operation value corresponding to the same bit position between intermediate products used to obtain the multi-bit neuromorphic operation result.

[0014] The controller may be further configured to determine the first input and the second input to be allocated in each time period so that each bit indicating a result of the multi-bit neuromorphic operation is sequentially obtained by the single neuron circuit from a value of a least significant bit (LSB) to a value of a most significant bit (MSB).

[0015] The single neuron circuit may be further configured to determine whether to output a spike upon receiving each bit of the multi-bit neuromorphic operation result by comparing the multi-bit neuromorphic operation result with a preset threshold.

[0016] In another general aspect, a multi-bit neuromorphic operation method includes: determining the i-th bit of an n-bit axon to be sequentially assigned to a single axon circuit for each of different time periods as a first input; determining the j-th bit of an m-bit synaptic weight to be assigned to a single synaptic circuit for each of the different time periods as a second input; receiving the determined first input from the single axon circuit; storing the determined second input in the single synaptic circuit and outputting a synaptic operation value as a function between the first input and the second input; and obtaining, by a single neuron circuit, each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight based on the output synaptic operation value. The first input and the second input are determined for different time periods until the multi-bit neuromorphic operation result is obtained sequentially from a lower bit value to a higher bit value. n and m are each natural numbers, i is a natural number between 1 and n, and j is a natural number between 1 and m.

[0017] i and j may be determined such that the i-th bit and the j-th bit are combined differently for each of different time periods.

[0018] The values ​​of i at the ith bit and j at the jth bit may be sequentially changed in increasing order of bit value.

[0019] The total number of combinations of the i-th bit and the j-th bit may correspond to a value obtained by multiplying n by m.

[0020] The obtaining may include obtaining each bit value based on an addition operation of a single adder using synaptic operation values ​​output from a single neuron circuit at different times.

[0021] Obtaining may include performing an addition operation using a single adder to obtain each bit value of the multi-bit neuromorphic operation result, the addition operation using as input at least one of a preset initial value, a synaptic operation value output from a single synaptic circuit in a previous time period of a different time period, a synaptic operation value output from a single synaptic circuit in a current time period of a different time period, an addition value processed by the single adder in a previous time period of the different time period, and a carry value determined by the single adder in a previous time period of the different time period.

[0022] At least one of an addition value and a carry value output from the single adder may correspond to a value indicating one of the bits of the multi-bit neuromorphic operation result.

[0023] The obtaining step may include obtaining a value indicative of one of the bits of the multi-bit neuromorphic operation result after obtaining a value indicative of another of the bits of the multi-bit neuromorphic operation result.

[0024] The obtaining step may further include performing an addition operation by receiving, as an input to a single adder, synaptic operation values ​​corresponding to the same bit positions between intermediate products used to obtain the multi-bit neuromorphic operation results.

[0025] The first input and the second input to be allocated in each of the different time periods may be determined so that each bit indicating a multi-bit neuromorphic operation result is sequentially obtained by a single neuron circuit from a value of a least significant bit (LSB) to a value of a most significant bit (MSB).

[0026] The method may further include: determining, by the single neuron circuit, whether to output a spike by comparing the multi-bit neuromorphic operation result with a preset threshold when each bit of the multi-bit neuromorphic operation result is received.

[0027] A non-transitory computer-readable recording medium having a program recorded thereon, when the program is executed by a computer, performs a method according to an aspect of the present disclosure.

[0028] In another general aspect, a neuromorphic processor includes a controller. The controller is configured to sequentially determine, for each of time periods, one of n bits assigned to a single axon circuit; determine one of m bits assigned to a single synaptic circuit, the single synaptic circuit configured to output a synaptic operation value as a function of one of n bits and one of m bits; and one of each bit value of a multi-bit neuromorphic operation result between one of n bits and one of m bits based on the synaptic operation value output by the single neuron circuit. The controller accumulates the multi-bit neuromorphic operation result for each of the time periods of n bits and m bits in byte order, and n and m are each natural numbers.

[0029] The n bits and m bits can be stored in external memory.

[0030] A neuromorphic chip may include a neuromorphic processor.

[0031] The neuromorphic chip may further include external memory.

[0032] A single neuron circuit may include a single adder and comparator.

[0033] The single adder may be configured to receive the initial value as the summand, the synaptic operation value as the addend, and the initial value as the carry value during a first time period of the time periods.

[0034] The single adder can be configured to perform an addition operation to output an addition value and a carry value, wherein the addition value corresponds to a least significant bit (LSB) of the multi-bit neuromorphic operation result and the carry value is input as a carry value of the addition operation to be performed in a second time period of each time period.

[0035] The single adder may be further configured to, for a second time period, perform another addition operation to output another addition value and another carry value, wherein the another addition value corresponds to another bit value of the multi-bit neuromorphic operation result, and the another carry value is input as another carry value of a subsequent addition operation to be performed in a third time period of the time periods.

[0036] Neuromorphic processors may be included in electronic devices used to drive neural networks.

[0037] In another general aspect, a neuromorphic processor includes: an axon circuit; a synapse circuit connected to the axon circuit; and a neuron circuit connected to the synapse circuit and including an adder, wherein the neuron circuit is configured to perform a multiplication operation between a multi-bit activation input to the axon circuit and a multi-bit synaptic weight input to the synapse circuit by reusing the adder in a time-division manner.

[0038] The adder is a full adder.

[0039] The adder is a single adder.

[0040] The neuromorphic processor further includes a controller configured to control the time-division manner.

[0041] In another general aspect, a neuromorphic device includes: a neuromorphic processor including an axon circuit, a synapse circuit connected to the axon circuit, and a neuron circuit connected to the synapse circuit and including an adder; and a memory storing data processed by the neuromorphic processor, wherein the neuromorphic processor performs a multiplication operation between a multi-bit activation input to the axon circuit and a multi-bit synapse weight input to the synapse circuit by reusing the adder included in the neuron circuit in a time-division manner.

[0042] The neuromorphic processor further includes a controller configured to determine an i-th bit of the multi-bit activation input and a j-th bit of the multi-bit synaptic weight input to be combined differently, an i-th lower bit of the multi-bit activation input and a j-th lower bit of the multi-bit synaptic weight input to be processed in a time-division manner by an adder.

[0043] The axon circuit and the synapse circuit correspond to a single axon circuit and a single synapse circuit, respectively, that process the value of a single bit.

[0044] The memory stores a multi-bit activation input to be provided to the axon circuit, a multi-bit synaptic weight input to be provided to the synapse circuit, and a result of performing the multiplication operation.

[0045] Other features and aspects will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1is a diagram of an example of a mathematical model related to the operation of a biological neuron.

[0047] Figure 2 is a diagram of an example configuration of a two-dimensional (2D) array circuit that performs neuromorphic operations.

[0048] Figure 3A is a diagram of an example of symbols used to describe components of a neuromorphic processor in a neuromorphic device.

[0049] Figure 3B is a diagram of an example of a symbol used to describe components of a single neuron circuit of a neuromorphic processor.

[0050] Figure 4 is a block diagram of an example of a hardware configuration of a neuromorphic device.

[0051] Figure 5 is a diagram depicting an example of the inputs to each individual circuit of a neuromorphic processor.

[0052] Fig. 6A is a diagram depicting examples of multi-bit neuromorphic operations that may be performed by a neuromorphic device.

[0053] Figure 6B is a diagram depicting an example of a mapping of operands to axon and synaptic weights, respectively, to perform a multi-bit neuromorphic operation (ie, a multi-bit multiplication operation).

[0054] Figure 6C is a diagram depicting an example of a neuromorphic processor processing operands and intermediate products of a multi-bit neuromorphic operation (ie, a multi-bit multiplication operation) in a time-division manner.

[0055] Fig.6D is a diagram depicting an example of a virtual synapse array mapping for a neuromorphic processor to process multi-bit neuromorphic operations in a time-division manner.

[0056] Fig. 7A and Figure 7B is a diagram describing an example of an order in which synaptic operations are to be performed by a neuromorphic processor in a time-division manner to process multi-bit neuromorphic operations.

[0057] Figure 7C is a diagram describing an example of the order in which a general neuromorphic processor performs synaptic operations.

[0058] FIG. 8A to FIG. 8G is a diagram describing an example of a process in which a neuromorphic processor performs a multi-bit neuromorphic operation in a time-division manner.

[0059] Fig. 9 is an overview and description FIG. 8A to FIG. 8G FIG. 1 is an example of a process of FIG.

[0060] FIG. 10A to FIG. 10E is a diagram describing an example of a processing result of a 3-bit×3-bit multiplication operation by a neuromorphic processor.

[0061] Fig.11 is a diagram describing an example of a processing result of a 3-bit×2-bit multiplication operation by a neuromorphic processor.

[0062] Fig.12 is a diagram describing an example of a processing result of a 4-bit×4-bit multiplication operation by a neuromorphic processor.

[0063] Fig.13 is a diagram depicting an example of hardware resources of a neuromorphic processor compared to hardware resources of a general-purpose neuromorphic processor.

[0064] Fig.14 is a flow chart of an example of a method of processing multi-bit neuromorphic operations performed by a neuromorphic device.

[0065] Fig.15 is a block diagram of an example of a configuration of an electronic system. DETAILED DESCRIPTION

[0066] The following specific embodiments are provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, various changes, modifications and equivalences of the method, device and / or system described herein will be apparent after the understanding of the disclosure of the present application. For example, the order of operations described herein is only an example, and is not limited to those proposed herein, but as will be apparent after the understanding of the disclosure of the present application, the order of operations described herein can be changed except that the operations must occur in a certain order. In addition, the description of features known in the prior art can be omitted for greater clarity and simplicity.

[0067] The features described herein may be embodied in different forms and are not to be considered limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein that will be apparent after an understanding of the disclosure of the present application.

[0068] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood in the field to which the disclosure of the present application belongs in the context of the disclosure of the present application and based on the understanding of the disclosure of the present application. For example, terms defined in commonly used technical dictionaries are to be interpreted as having the same meaning as they have in the context of the relevant field and consistent with the disclosure of the present application, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such here.

[0069] In the specification, when a region is “connected” to another region, the region may be not only “directly connected” but also “electrically connected” via another device therebetween. In addition, when a part “includes” or “comprises” an element, unless there is a specific description to the contrary, the part may further include other elements without excluding the other elements.

[0070] Although terms such as "first," "second," and "third" may be used herein to describe various parts, components, regions, layers, or portions, these parts, components, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one part, component, region, layer, or portion from another part, component, region, layer, or portion. Therefore, a first part, component, region, layer, or portion mentioned in the examples described herein may also be referred to as a second part, component, region, layer, or portion without departing from the teachings of the examples.

[0071] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" when preceding a list of elements modify the entire list of elements and do not modify the individual elements of the list.

[0072] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. The articles "a", "an" and "the" are intended to include plural forms, unless the context clearly indicates an exception. The terms "include", "comprise" and "have" specify the presence of the features, numbers, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof.

[0073] As will be apparent after understanding of the disclosure of the present application, the features of the examples described herein may be combined in various ways. In addition, although the examples described herein have various configurations, as will be apparent after understanding of the disclosure of the present application, other configurations are possible.

[0074] Figure 1 is a diagram of an example of a mathematical model 11 that simulates the operation of a physical neuron.

[0075] The biological neuron can be simulated by the mathematical model 11. The mathematical model 11 is an example of a neuromorphic operation that can be simulated by a hardware computing element or processor and may include a multiplication operation in which information from multiple neurons is multiplied by a synaptic weight, a multiplication operation in which the value ω of each synaptic weight is multiplied by the information from multiple neurons. 0 x 0 ,ω 1 x 1 and ω 2 x 2The addition operation Σ of , and the operation in which the characteristic function bias (b) and the activation function f are applied to the addition operation result. The simulated neuromorphic operation result can be provided via the disclosed neuromorphic operation, where x 0 、x 1 、x 2 The values ​​of ω and ω may correspond to the simulated axon values ​​and 0 ,ω 1 ,ω 2 The values ​​of etc. may correspond to simulated synaptic weights. Here, it is noted that with respect to examples or embodiments, for example, with respect to what an example or embodiment may include or implement, the use of the term "may" means that there is at least one example or embodiment that includes or implements such a feature and at the same time all examples and embodiments are not limited to these examples.

[0076] Figure 2 is a diagram of an example configuration 20 of a 2-dimensional (2D) array circuit for performing neuromorphic operations.

[0077] refer to Figure 2 , the 2D array circuit configuration 20 includes N axon circuits A 1 To A N 210, M neuron circuits N 1 To N M 230, and N×M synapse arrays S 11 To S NM 220, where N and M are each any natural number. Here, relative to Figure 1-Figure 15 In the examples and descriptions of the invention, as well as the remaining examples, the invention content and the claims, the use of the term "neuron" is not intended to mean that "neuron" has any other meaning beyond the technical meaning, that is, it is not intended to mean that the "neuron" of the term below is structurally and operationally the same or similar in hardware and hardware implementation with respect to chemical and neurological neuron implementations. Similarly, for the Figure 1-Figure 15 The terms "neuron circuit", "synapse", "synaptic circuit", "axon" or "axon circuit" in the examples and descriptions of the invention, as well as the remaining examples, the invention content and the claims, the use of the terms "neuron", "synapse", "axon" or "axon circuit" does not mean that "neuron", "synapse", "axon" or "axon circuit" have any other meaning beyond the technical meaning, that is, it does not mean that the terms "neuron", "synapse", "axon" or "axon circuit" in the following are structurally and operationally the same or similar in hardware and hardware implementation relative to chemical and neurological neuron implementations. For example, an artificial neural network can be hardware configured to have multiple layers of hardware nodes, that is, hardware referred to as such "neurons" below.

[0078] Synaptic Array S11 To S NM Each synapse 220 can be arranged in a circuit A from an axon 1 To A N The first direction line extending in the first direction of 210 and the first direction line extending in the first direction of the neuron circuit N 1 To N M Here, for ease of description, the first direction is the row direction and the second direction is the column direction, but the first and second directions are not limited to these examples, and as a non-limiting example, the first direction may be the column direction and the second direction may be the row direction.

[0079] Axon Circuit A 1 To A N Each of 210 can receive and send activations (e.g., axons a 1 to a n ) to the first direction line. Activation corresponds to a neurotransmitter transmitted through the neuron and can represent input to the axon circuit A 1 To A N 210. At the same time, the axon circuit A 1 To A N Each of 210 may include a memory, a register, or a buffer for storing input information. Meanwhile, the activation may be a binary activation having a binary value. For example, a binary activation may include 1-bit information corresponding to a logical value of 0 or 1. However, the activation is not limited to these examples and may have a ternary value or a multi-bit value.

[0080] Synaptic Array S 11 To S NM Each of 220 can store a synaptic weight corresponding to the connection strength between neurons. Figure 2 For ease of description, w 1 to w m The diagram shows an example of a synaptic weight to be stored in each synapse, but other synaptic weights may be stored in each synapse in addition. 11 To S NM Each synapse of 220 may include a memory device for storing synaptic weights, or may be connected to another memory device for storing synaptic weights. Here, such a memory device may be a memristor, for example.

[0081] Synaptic Array S 11 To S NM Each of 220 can receive the signal from the axon circuit A through the corresponding first direction line. 1 To A NEach of 210 may send an activation input, or may output a result of a neuromorphic operation between the activation input and the stored synaptic weight. For example, the neuromorphic operation between the activation input and the synaptic weight may be a multiplication operation (i.e., an AND operation), but is not limited to this example. In other words, the result of the neuromorphic operation between the activation input and the synaptic weight may be a value obtained via another appropriate operation for reflecting the strength or size of the activation adjusted based on the connection strength between neurons.

[0082] From axon circuit A 1 To A N 210 sent to neuron circuit N 1 To N M The size or strength of the signal at 230 can be adjusted according to the neuromorphic operation between the activation input and the synaptic weight. Thus, the operation of adjusting the size or strength of the signal sent to the next neuron according to the connection strength between neurons can use the synaptic array S 11 To S NM 220 achieved.

[0083] Neuronal Circuit 1 To N M Each of the neuron circuits 230 may receive the result of the neuromorphic operation between the activation input and the synaptic weight via the corresponding second direction line. 1 To N M Each of 230 may determine whether to output a spike based on the result of the neuromorphic operation. 1 To N M Each of the neuron circuits 230 may output a spike when the accumulated value of the result of the neuromorphic operation is equal to or greater than a preset threshold. 1 To N M The spikes outputted by 230 may correspond to activation inputs to the axonal circuits of the next level.

[0084] Neuronal Circuit 1 To N M 230 located at synaptic array S 11 To S NM The back end of 220, and therefore, can be referred to as a post-synaptic neuron circuit. 1 To A N 210 located at synaptic array S 11 To S NM The front end of 220, and therefore, can be referred to as a pre-synaptic neuron circuit.

[0085] Figure 3A is a diagram of an example of symbols used to describe components of a neuromorphic processor 30 in a neuromorphic device.

[0086] refer to Figure 3A , the neuromorphic processor 30 may include a single axon circuit 310, a single synapse circuit 320, and a single neuron circuit 330. Here, the single synapse circuit 320 may receive a synaptic weight from an N×M synapse memory array 325 included in another external memory device.

[0087] refer to Figure 2 The configuration of the described 2D array (N×M) circuit can be used, for example, Figure 3A The single axon circuit 310, the single synapse circuit 320 and / or the single neuron circuit 330 are specifically implemented. For example, Figure 2 Axonal circuit A 1 To A N 210 may correspond to a single axon circuit 310, a synapse array S 11 To S NM 220 corresponds to a single synaptic circuit 320, and / or a neuron circuit N 1 To N M 230 corresponds to a single neuron circuit 330 .

[0088] For the sake of Figure 2 Axonal circuit A 1 To A N 210 operation, a single axon circuit 310 processes axon inputs in a time-division manner in the neuromorphic processor 30. In addition, similarly, in order to Figure 2 Synaptic array S 11 To S NM 220 operation, a single synaptic circuit 320 can store synaptic weights in a time-division manner in the neuromorphic processor 30 .

[0089] For example, a single axon circuit 310 may be 1 Operation Figure 2 Axonal circuit A 1 , at time t 2 Operation Figure 2 Axonal circuit A 2 , and so on, and then at time t N Operation Figure 2 Axonal circuit A N In addition, a single synaptic circuit 320 may be 1-1 Operation Figure 2 Synaptic S 11 , at time t 1-2 Operation Figure 2 Synaptic S 12 , and so on, and then at time t N-M Operation Figure 2 Synaptic SNM At the same time, a single neuron circuit 330 can also be operated in the same manner as a neuron circuit N 1 To N M 230. Here, the times are all arbitrary times and are represented by different reference numerals so as to be distinguishable.

[0090] Thus, when each of the single axon circuit 310, the single synapse circuit 320, and the single neuron circuit 330 operates at a specific time point or period in a time-division manner, the neuromorphic processor 30 may operate as if a plurality of circuits N×M are operating even though only a single circuit (1×1) is included. In other words, Figure 2 The configuration 20 of the 2D array (N×M) circuits may be embodied as a neuromorphic processor 30 of a single circuit (1×1) by operating each single circuit in a time division manner.

[0091] Figure 3B is a diagram of an example of symbols used to describe components of a single neuron circuit 330 of the neuromorphic processor 30 .

[0092] refer to Figure 3B , a single neuron circuit 330 of the neuromorphic processor 30 may include a single adder 321 and a comparator 323 .

[0093] A single adder 321 can represent a summand B 1 、Addend B 2 and carry digit C 0 The three inputs and non-carry and S 1 and the new carry C 1 In other words, the single adder 321 may correspond to a full adder.

[0094] The comparator 323 compares the addition result C of the single adder 321. 1 S 1 Here, the preset threshold corresponds to the standard for determining whether to output a spike to the next neuron. When the comparator 323 determines that the addition result C 1 S 1 When the value is equal to or greater than a preset threshold, the single neuron circuit 330 may output a spike.

[0095] Figure 4 is a block diagram of an example of a hardware configuration of the neuromorphic device 100 .

[0096] refer to Figure 4, the neuromorphic device 100 includes a neuromorphic chip 110 on which a neuromorphic processor 112 and an on-chip memory 114 are mounted, and an external memory 120. The neuromorphic processor 112 includes a single axon circuit 1121, a single synapse circuit 1122, a single neuron circuit 1123, and a controller 1124. However, Figure 4 Only components of the neuromorphic device 100 that are relevant to the current example are illustrated. Figure 4 In addition to the components shown, examples include a neuromorphic device 100 that further includes other general components such as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a sensor module, and a communication module.

[0097] The neuromorphic processor 112, the single axon circuit 1121, the single synapse circuit 1122, and the single neuron circuit 1123 may correspond to Figure 3A A neuromorphic processor 30 , a single axon circuit 310 , a single synapse circuit 320 , and a single neuron circuit 330 .

[0098] The neuromorphic processor 112 may include a Figure 3A The neuromorphic processor 112 may include a single processing unit (or a single processor core) of the neuromorphic processor 30, but is not limited to this example, and the neuromorphic processor 112 may include each specifically implemented as Figure 3A Multiple processing units (or processor cores) of the neuromorphic processor 30.

[0099] The neuromorphic device 100 may be or correspond to various types of electronic devices, such as devices included in server devices, mobile devices, and embedded devices. The neuromorphic device 100 may be or correspond to a hardware component included in a smart phone, a tablet device, an augmented reality (AR) device, an Internet of Things (IoT) device, an autonomous driving vehicle, a robot, or a medical device that can perform speech recognition, image recognition, image classification, etc. by using a neural network. In other words, the neuromorphic device 100 may be or correspond to a dedicated hardware (HW) accelerator installed on such an electronic device, and may represent an electronic device, and the neuromorphic device 100 may be a HW accelerator operating like a neural processing unit (NPU), a tensor processing unit (TPU), a neural engine, TrueNorth, or Loihi as a dedicated module for neural network driving, but note that the examples are not limited to these examples.

[0100] The neuromorphic chip 110 may control the overall function for driving the neural network in the neuromorphic device 100. For example, the neuromorphic processor 112 of the neuromorphic chip 110 may generally control the neuromorphic device 100 by accessing neuromorphic data (e.g., axon input values, synaptic weight values, etc.) stored in the external memory 120 in the neuromorphic device 100 to execute a neuromorphic-related program. The neuromorphic chip 110 may drive the neural network according to the control of a CPU, GPU, AP, etc. provided inside or outside the neuromorphic device 100.

[0101] The external memory 120 is implemented in hardware and can be used to store various types of neuromorphic data processed in the neuromorphic chip 110, including data processed by or to be processed by the neuromorphic chip 110. In addition, the external memory 120 can store applications, drivers, etc. to be driven by the neuromorphic chip 110. The external memory 120 may include a random access memory (RAM) (such as a dynamic random access memory (DRAM) or a static random access memory (SRAM)), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a CD-ROM, a Blu-ray or another optical disk storage device, a hard disk drive (HDD), a solid-state drive (SSD), or a flash memory.

[0102] The on-chip memory 114 of the neuromorphic chip 110 can read from the external memory 120 and store (or cache) neuromorphic data (axon values, synapse values, etc.) for the pre-synaptic neuron circuit, and execute the neural network by using the stored neuromorphic data—e.g., Figure 3A The N×M synaptic memory array 325 may correspond to the on-chip memory 114. The on-chip memory 114 may store data for the post-synaptic neuron circuit, such as spike values, results of neuromorphic operations generated via execution results of the neural network, and the like.

[0103] The specific operations and functions of the single axon circuit 1121, the single synapse circuit 1122, the single neuron circuit 1123, and the controller 1124 will be described in more detail below with reference to other drawings.

[0104] Figure 5 is a diagram depicting examples of inputs to each individual circuit of the neuromorphic processor 112 .

[0105] refer to Figure 5, the controller 1124 of the neuromorphic processor 112 determines a first input of an i-th lower bit of an n-bit axon 510 to be assigned to a single axon circuit 1121 at each time point, and a second input of a j-th lower bit of an m-bit synaptic weight 520 to be assigned to a single synapse circuit 1122 at each time point. Here, n and m are each a natural number, wherein i is a natural number between 1 and n and j is a natural number between 1 and m.

[0106] exist Figure 5 , for ease of description, the axon 510 and the synaptic weight 520 each have a total of 3-bit values ​​(n=3 and m=3); however, the axon 510 and the synaptic weight 520 according to the current example may have various bit values.

[0107] The controller 1124 determines at which specific time point (eg, time t x ) which bit position (i.e., the i-th lowest bit) of the 3-bit axon 510 (n=3) is to be assigned to the single axon circuit 1121 as the first input. In other words, the controller 1124 determines i to determine which bit position (i.e., the i-th lowest bit) of the 3-bit axon 510 (n=3) is to be assigned to the single axon circuit 1121 as the first input. x For example, i may have a value from 1 to 3. When i is 1, the first low bit of the first input corresponds to the bit value of the least significant bit (LSB) of the axon 510, and when i is 3, the third low bit of the first input corresponds to the bit value of the most significant bit (MSB) of the axon 510.

[0108] Here, it is noted that the endianness of the byte order described using MSB and LSB with respect to the examples in the present disclosure may be expressed in a big endian format or a little endian format.

[0109] In addition, the controller 1124 determines at which specific time point (eg, time t y ) which bit position (i.e., the jth lowest bit) of the 3-bit synaptic weight 520 (m=3) is to be assigned to the single synaptic circuit 1122 as the second input. In other words, the controller 1124 determines j to determine which bit position (i.e., the jth lowest bit) of the 3-bit synaptic weight 520 (m=3) is to be assigned to the single synaptic circuit 1122 as y For example, j may have a value from 1 to 3. When j is 1, the first lower bit of the second input corresponds to the bit value of the LSB of the synaptic weight 520, and when j is 3, the third lower bit of the second input corresponds to the bit value of the MSB of the synaptic weight 520.

[0110] Thus, the controller 1124 repeatedly determines the first input and the second input to be assigned to the single axon circuit 1121 and the single synapse circuit 1122, respectively, by changing the values ​​i and j at each time point until the multi-bit neuromorphic operation results in a result from the output of the neuromorphic processor 112 based on the byte order of the low and high bit values. In this example, the low bit value may represent the bit value of the LSB of the multi-bit neuromorphic operation result, and the high bit value may represent the bit value of the MSB of the multi-bit neuromorphic operation result. At the same time, the terms first input and second input merely represent the values ​​of the bit positions determined by the controller 1124, wherein the values ​​are newly updated by the controller 1124 at each time point.

[0111] The controller 1124 may map i and j so that the i-th lower bit and the j-th lower bit are combined differently at each time point. For example, the controller 1124 may change and map the values ​​of i and j so that combinations ranging from a combination of the i-th lower bit (e.g., LSB) and the j-th lower bit (e.g., LSB) mapped so that the sum of i and j is the smallest to a combination of the i-th lower bit (e.g., MSB) and the j-th lower bit (e.g., MSB) mapped so that the sum of i and j is the largest are sequentially assigned to each of the single axon circuit 1121 and the single synapse circuit 1122. Here, the total number of combinations of the i-th lower bit and the j-th lower bit corresponds to a value obtained by multiplying n by m, and in Figure 5 In the example of , there are a total of 9 (3×3) combinations. For example, the controller 1124 may initially map the bit value of the LSB (i=1) of the axon 510 (first input) and the bit value of the LSB (j=1) of the synaptic weight 520 (second input) at the initial time, and finally map the bit value of the MSB (i=3) of the axon 510 (first input) and the bit value of the MSB (j=3) of the synaptic weight 520 (second input) at the final time.

[0112] The single axon circuit 1121 of the neuromorphic processor 112 receives a first input of the i-th lower bit of the n-bit axon 510 determined by the controller 1124. In addition, the single synapse circuit 1122 of the neuromorphic processor 112 stores a second input of the j-th lower bit of the m-bit synapse weight 520 determined by the controller 1124.

[0113] Each of the single axon circuit 1121 and the single synapse circuit 1122 is a circuit capable of processing a single bit value (i.e., 1 bit value). Therefore, the single axon circuit 1121 and the single synapse circuit 1122 can process only the bit value of a certain position of the axon 510 (first input) and the bit value of a certain position of the synapse weight 520 (second input), respectively.

[0114] When the j-th lower-order second input is stored in the single synapse circuit 1122, the single synapse circuit 1122 outputs a synaptic operation value between the first input received from the single axon circuit 1121 and the second input stored in the single synapse circuit 1122. The synaptic operation performed by the single synapse circuit 1122 may be a multiplication operation of the first and second inputs (i.e., an AND operation), but is not limited to these examples.

[0115] The single neuron circuit 1123 of the neuromorphic processor 112 obtains each bit value of the multi-bit neuromorphic operation result between the n-bit axon 510 and the m-bit synaptic weight 520 based on the synaptic operation value output from the single synaptic circuit 1122. This is described in more detail below with reference to the corresponding drawings.

[0116] Fig. 6A is a diagram depicting examples of multi-bit neuromorphic operations that may be performed by a neuromorphic device.

[0117] refer to Fig. 6A , as an example of a multi-bit neuromorphic operation, a multi-bit multiplication operation between 3-bit binary values ​​is illustrated. A multi-bit multiplication operation represents a multiplication operation in which at least one operand includes multiple bits. When the first operand 611 of the multi-bit multiplication operation is ABC as a 3-bit binary value 2 , and the second operand 612 is DEF as a 3-bit binary value 2 When , the multiplication operation of the first operand 611 and the second operand 612 may be performed by calculating intermediate products through bit-by-bit multiplication and then adding the calculated intermediate products according to the same bit positions.

[0118] For example, GHI as the first intermediate product 613 is obtained by converting DEF as the second operand 612 2 The LSB of F and the first operand 611 ABC 2 The second intermediate product 614 JKL is obtained by multiplying 2 The second lowest E and ABC 2 The MNO as the third intermediate product 615 is obtained by taking DEF 2 The third lowest bit (ie, MSB) of D is compared with ABC as the first operand 611. 2 Then, the first to third intermediate products 613 to 615 are added according to the same bit positions to obtain PQRSTU which is a multi-bit multiplication operation result 616 between the first operand 611 and the second operand 612. 2 In the following, the above-mentioned Figure 4 The neuromorphic processor 112 performs Fig. 6A Methods for performing multi-bit neuromorphic operations (i.e., multi-bit multiplication operations) of the present invention.

[0119] Figure 6B is a diagram depicting an example of mapping operands to axons 610 and synaptic weights 620 , respectively, to perform a multi-bit neuromorphic operation (ie, a multi-bit multiplication operation).

[0120] refer to Figure 6B , as Fig. 6A The first operand of 611 is ABC 2 Each bit value (A, B, and C) of the first operand 611 is mapped to the synaptic weight 620. The MSB of the first operand 611 is mapped to the MSB of the synaptic weight 620, and the LSB of the first operand 611 is mapped to the LSB of the synaptic weight 620.

[0121] In the same way, as Fig. 6A The second operand of DEF 612 2 Each bit value (D, E, and F) of the second operand 612 is mapped to the axon 610. The MSB of the second operand 612 is mapped to the MSB of the axon 610, and the LSB of the second operand 612 is mapped to the LSB of the axon 610.

[0122] However, the embodiments are not limited to these examples and Figure 6B Different from the mapping method described in Fig. 6A The first operand 611 and the second operand 612 may be mapped to the bit positions of the axon 610 and the synaptic weight 620 in different mapping schemes. However, when other mapping methods are applied, the controller 1124 may determine the combination of i and j in a manner different from the above corresponding to the positions of the mapped bits.

[0123] Figure 6C is a diagram depicting an example of the neuromorphic processor 112 processing operands and intermediate products of a multi-bit neuromorphic operation (ie, a multi-bit multiplication operation) in a time-division manner.

[0124] refer to Figure 6C , as referenced Figure 6B As described, ABC as the first operand 631 2 Each bit value (A, B, and C) of is mapped to the synaptic weight 620 and is used as the DEF of the second operand 632. 2 Each bit value (D, E, and F) is mapped to axon 610.

[0125] The bit value of each of the first intermediate product GHI 633, the second intermediate product JKL 634, and the third intermediate product MNO 635 is obtained in a time-division manner via the first operand ABC. 2 Each bit value (A, B and C) of 631 and the second operand DEF 2632 is generated by multiplying each bit value (D, E and F) of GHI 632. For example, the bit value I of the first intermediate product GHI 633 can be generated at time t 0 The bit value H of the first intermediate product GHI 633 can be obtained at time t 1 The bit value L of the second intermediate product JKL 634 can be obtained at time t 2 , and so on, and the bit value M of the third intermediate product MNO 635 can be obtained at time t 8 get.

[0126] Time t 0 to 8 Indicates different times. For example, from time t 0 The time to start delaying the preset time may be time t 1 , from time t 1 The time to start delaying the preset time may be time t 2 ; however, the embodiments are not necessarily limited to these examples. In addition, throughout the specification, time t is not used to limit a specific moment, but is used to distinguish the timing or time period when the relevant operation is performed. Therefore, after understanding the present disclosure, it will be understood that the operations described in the specification as being performed at a specific time point may not necessarily be performed at the same time.

[0127] First operand ABC 2 631 and the second operand DEF 2 The result 636 of the multi-bit neuromorphic operation (i.e., multi-bit multiplication operation) of 632 is PQRSTU 2 .

[0128] Results PQRSTU 2 The U corresponding to the LSB in 636 is obtained via the I of the first intermediate product GHI 633. The result PQRSTU 2 T in 636 is obtained by summing H of the first intermediate product GHI 633 and L of the second intermediate product JKL 634. The result PQRSTU 2 The S in 636 is obtained by summing the G of the first intermediate product GHI 633, the K of the second intermediate product JKL 634, the O of the third intermediate product MNO 635, and the carry value obtained from the previous bit position. Thus, the result PQRSTU 2 636 can be obtained sequentially from U corresponding to the LSB to P corresponding to the MSB. In other words, the result PQRSTU 2 636 can be based on the time t 0 To time t 8 The sum of the bit values ​​of the first to third intermediate products 633 to 635 obtained sequentially is obtained.

[0129] Fig.6D is a diagram depicting an example of a virtual synapse array mapping for the neuromorphic processor 112 to process multi-bit neuromorphic operations in a time-division manner.

[0130] refer to Fig.6D As described above, the neuromorphic processor 112 includes a single axon circuit 1121, a single synapse circuit 1122, a single neuron circuit 1123, and a controller 1124, but when the neuromorphic processor 112 operates in a time-division manner, the neuromorphic processor 112 may operate as if it were a 2D synapse array including at least one axon circuit, at least one synapse, and at least one neuron circuit. In the current embodiment, the 2D synapse array simulated as being processed by the neuromorphic processor 112 in a time-division manner is referred to as a virtual synapse array 640, but may alternatively be referred to by another term. In other words, the physical circuit configuration of the virtual synapse array 640 (e.g., at least one axon circuit, at least one synapse, and at least one neuron circuit) may not actually be implemented in the neuromorphic processor 112.

[0131] Fig.6D The diagram will be related to the above reference Figures 6A to 6C The multi-bit neuromorphic operations described above (3-bit x 3-bit multiplication operations) describe a 3 x 3 virtual synapse array 640. However, arrays including various numbers of rows and columns may alternatively be used.

[0132] In the 3×3 virtual synapse array 640, Figure 6C The second operand DEF 2 632 mapped to axon a 3 、a 2 and a 1 ,and Figure 6C The first operand of ABC 2 631 is mapped to the synaptic weight w 3 、w 2 and w 1 When in axon a 1 and the synaptic weight w 1 When the synapses provided by each other cross each other, the axons (position value a 1 =F) and synaptic weight (bit value w 1 =C) synaptic operation, we can get Figure 6C The first intermediate product GHI 633 has a value of I. Similarly, when the axon a 3 、a 2 and a 1 With synaptic weight w 3 、w 2 and w 1 The synaptic operation is performed in the synapses provided when crossing each other in the 3×3 virtual synapse array 640, as shown in FIG. Fig.6DThe bit values ​​of the first to third intermediate products 633 to 635 are mapped as shown.

[0133] The controller 1125 determines each axon and synaptic weight to be provided to the single axon circuit 1121 and the single synapse circuit 1122 so that mapping is performed in the above-described manner of the virtual synapse array 640 .

[0134] Fig. 7A and Figure 7B is a diagram describing an example of an order in which synaptic operations are to be performed by the neuromorphic processor 112 in a time-division manner to process multi-bit neuromorphic operations.

[0135] refer to Fig. 7A , a synaptic operation between the axons and the synaptic weights is performed in a synapse at the intersection between the axons and the synaptic weights of the virtual synapse array 710. The neuromorphic processor 112 may perform the synaptic operation at the intersection of the virtual synapse array 710 in a time-division manner.

[0136] According to the above reference FIG. 6A to FIG. 6D The mapping method described above, the neuromorphic processor 112 at time t 0 The axon a 1 Provided to a single axon circuit 1121 and the synaptic weight w 1 Provided to a single synaptic circuit 1122, and obtain axon a 1 and the synaptic weight w 1 Then, the neuromorphic processor 112 at time t 1 The axon a 1 Provided to a single axon circuit 1121 and the synaptic weight w 2 Provided to a single synaptic circuit 1122, and obtain axon a 1 and the synaptic weight w 2 In a similar manner, the neuromorphic processor 112 sequentially performs synaptic operations until time t 8 .

[0137] refer to Figure 7B , Fig. 7A The order described in is indicated by arrows. In this example, the steps from time t to time t are sequentially performed in an order corresponding to the diagonal direction in the virtual synapse array 710. 0 To time t 8 synaptic operation.

[0138] Therefore, this order is based on the method of changing and mapping the values ​​of i and j by the controller 1124. The values ​​of i and j are mapped from the combination with the smallest sum of i and j to the combination with the largest sum of i and j. Such a combination of the i-th lowest bit and the j-th lowest bit is sequentially assigned to each of the single axon circuit 1121 and the single synapse circuit 1122 as described above.

[0139] Figure 7C is a diagram used to describe the order of synaptic operations performed by a general neuromorphic processor. Figure 7C , the general neuromorphic processor cannot perform multi-bit neuromorphic operations, but can perform only 1-bit neuromorphic operations (1-bit×1-bit multiplication operations). In other words, referring to the virtual synapse array 720, each axon and each synaptic weight does not correspond to some bit values ​​of a multi-bit operand, but corresponds to the 1-bit operand itself. In addition, the general neuromorphic processor can perform only 1-bit neuromorphic operations (1-bit×1-bit multiplication operations). Figure 7C The synaptic operations are performed in the order of the column direction shown, and thus at time t 0 The obtained synaptic operation value and at time t 3 The obtained synaptic operation values ​​are independent synaptic operation values ​​that are not related to each other.

[0140] On the other hand, according to the current example, the neuromorphic processor 112 assigns some bit values ​​of the multi-bit operands to the axons and synaptic weights of the virtual synapse array 710 and Figure 7B The synaptic operations are performed in a time-division manner in the order of the diagonal direction of , and thus, unlike general-purpose neuromorphic processors, multi-bit neuromorphic operations are possible.

[0141] FIG. 8A to FIG. 8G is a diagram describing an example of a process in which a neuromorphic processor performs a multi-bit neuromorphic operation in a time-division manner.

[0142] By using the above reference FIG. 6A to FIG. 7B The examples described in FIG. 8A to FIG. 8G The process of performing multi-bit neuromorphic operations is described in .

[0143] Figure 4 The single neuron circuit 1123 of the neuromorphic processor 112 is based on Figure 4 The synaptic operation value output by the single synaptic circuit 1122 of the embodiment is used to obtain each bit value of the multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight. The single neuron circuit 1123 includes a single adder 810.

[0144] Fig. 8A The diagram is at time t 0 processing.

[0145] The controller 1124 at time t 0 The axon a 1Assigned to a single neuron circuit 1123, and the synaptic weight w 1 Assigned to a single synaptic circuit 1122.

[0146] Synapse 800 stores synaptic weight w 1 . In storing the synaptic weight w 1 Afterwards, synapse 800 executes axon a 1 and the synaptic weight w 1 The synaptic operation between them is obtained with time t 0 The corresponding synaptic operation value.

[0147] The single adder 810 receives a preset initial value 0 as an addend, receives a predetermined initial value 0 as an addend and receives a predetermined initial value 0 as an addend and a time t 0 The corresponding synaptic operation value and the preset initial value 0 received as the carry value. Upon receiving all the inputs, the single adder 810 performs an addition operation to output an addition value S 0 and carry value C 0 Additive value S 0 Corresponds to the LSB among the bits indicating the result of a multi-bit neuromorphic operation (multi-bit multiplication operation). In addition, the carry value C 0 It is input as the carry value for the addition operation to be performed next.

[0148] Figure 8B The diagram is at time t 1 and t 2 processing.

[0149] The controller 1124 at time t 1 The axon a 1 Assigned to a single neuron circuit 1123, and the synaptic weight w 2 Assigned to a single synaptic circuit 1122. When storing the synaptic weight w 2 When synapse 801 executes axon a 1 and the synaptic weight w 2 The synaptic operation between them is obtained with time t 1 The single adder 810 receives the carry value C 0 and time t 1 The corresponding synaptic operation value.

[0150] The controller 1124 at time t 2 The axon a 2 Assigned to a single neuron circuit 1123, and the synaptic weight w 1 Assigned to a single synaptic circuit 1122. When storing the synaptic weight w 1 When synapse 802 executes axon a 2 and the synaptic weight w 1 The synaptic operation between them is obtained with time t2 The corresponding synaptic operation value.

[0151] In receiving the carry value C 0 , and time t 1 The corresponding synaptic operation value and time t 2 When all the corresponding synaptic operation values ​​are input, the single adder 810 outputs the added value S by performing the addition operation. 1 and carry value C 1 Additive value S 1 The carry value C corresponds to the second lowest bit among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation). 1 It is input as the carry value for the addition operation to be performed next.

[0152] Figure 8C The diagram is at time t 3 and t 4 processing.

[0153] The controller 1124 at time t 3 The axon a 1 Assigned to a single neuron circuit 1123, and the synaptic weight w 3 Assigned to a single synaptic circuit 1122. Synapse 803 obtains 3 The corresponding synaptic operation value, and the single adder 810 receives the carry value C 1 and time t 3 The corresponding synaptic operation value.

[0154] The controller 1124 at time t 4 The axon a 2 Assigned to a single neuron circuit 1123, and the synaptic weight w 2 Assigned to a single synaptic circuit 1122. Synapse 804 obtains 4 The corresponding synaptic operation value.

[0155] In receiving the carry value C 1 , and time t 3 The corresponding synaptic operation value and time t 4 When all the corresponding synaptic operation values ​​are input, the single adder 810 outputs the added value P by performing the addition operation. 0 and carry value C 2 Additive value P 0 Used for the time t 5 The next addition operation is performed. In addition, the carry value C 2 It is input as the carry value for the addition operation to be performed next.

[0156] Fig.8D The diagram is at time t5 processing.

[0157] The controller 1124 at time t 5 The axon a 3 Assigned to a single neuron circuit 1123, and the synaptic weight w 1 Assigned to a single synaptic circuit 1122. Synapse 805 obtains 5 The corresponding synaptic operation value.

[0158] At receiving time t 5 The corresponding synaptic operation value and the previously obtained addition value P 0 When all inputs are equal to the preset carry value 0, the single adder 810 outputs the added value S by performing an addition operation. 2 and carry value C 3 Additive value S 2 The carry value C corresponds to the third lowest bit among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation). 3 It is input as the carry value for the addition operation to be performed next.

[0159] Fig. 8E The diagram is at time t 6 processing.

[0160] The controller 1124 at time t 6 The axon a 2 Assigned to a single neuron circuit 1123, and the synaptic weight w 3 Assigned to a single synaptic circuit 1122. Synapse 806 obtains 6 The corresponding synaptic operation value.

[0161] At receiving time t 6 The corresponding synaptic operation value, the preset initial value 0 and the carry value C 2 When all inputs are equal, the single adder 810 outputs the added value P by performing an addition operation. 1 and carry value C 4 Additive value P 1 As a single adder 810 at time t 7 The next addition operation is performed. In addition, the carry value C 4 It is input as the carry value for the addition operation to be performed next.

[0162] Figure 8F The diagram is at time t 7 processing.

[0163] The controller 1124 at time t 7 The axon a 3Assigned to a single neuron circuit 1123, and the synaptic weight w 2 Assigned to a single synaptic circuit 1122. Synapse 807 obtains 7 The corresponding synaptic operation value.

[0164] At receiving time t 7 The corresponding synaptic operation value and the previously obtained addition value P 1 and carry value C 3 When all inputs are equal, the single adder 810 outputs the added value S by performing an addition operation. 3 and carry value C 5 Additive value S 3 The carry value C corresponds to the bit value of the fourth lowest bit among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation). 5 It is input as the carry value for the addition operation to be performed next.

[0165] Figure 8G The diagram is at time t 8 processing.

[0166] The controller 1124 at time t 8 The axon a 3 Assigned to a single neuron circuit 1123, and the synaptic weight w 3 Assigned to a single synaptic circuit 1122. Synapse 808 obtains 8 The corresponding synaptic operation value.

[0167] At receiving time t 8 Corresponding synaptic operation value, carry value C 4 and carry value C 5 When all inputs are equal, the single adder 810 outputs the added value S by performing an addition operation. 4 and carry value C 5 Additive value S 4 and carry value S 5 The bit values ​​respectively correspond to the fifth and sixth lower bits among the bits indicating the result of the multi-bit neuromorphic operation (multi-bit multiplication operation).

[0168] As described above, a single adder 810 included in a single neuron circuit 1123 is reused at each time point to perform an addition operation. In other words, the single adder 810 can perform an addition operation when all inputs are received, and store a previous addition operation result (e.g., addition value, carry value, etc.) in a memory (buffer, register, etc.) connected to the single adder 810 to perform the next addition operation. The previous addition operation result stored in the memory can be reset and reused before performing the next addition operation. In other words, because the neuromorphic processor 112 according to the current embodiment performs a multi-bit multiplication operation by reusing a single adder 810, the circuit area for implementing the neuromorphic processor 112 can be reduced.

[0169] Fig. 9 is an overview and description FIG. 8A to FIG. 8G FIG. 1 is an example of a process of FIG.

[0170] As described above, the controller 1124 of the neuromorphic processor 112 determines at each time point (e.g., from time t 0 To time t 8 ) to be assigned to the first input of the i-th low bit of the axon 510 of the single axon circuit 1121 and at each time point (e.g., from time t 0 To time t 8 ) is assigned to the j-th lower bit of the synaptic weight 520 of the single synaptic circuit 1122, thereby obtaining the multi-bit neuromorphic operation result sequentially from the lower bit value to the higher bit value. When the second input is stored in the single synaptic circuit 1122, the single synaptic circuit 1122 outputs the synaptic operation value between the first input and the second input. The single neuron circuit 1123 obtains the bit value S of the multi-bit neuromorphic operation result between the axon 510 and the synaptic weight 520 based on the synaptic operation result output from the single synaptic circuit 1122. 5 , S 4 , S 3 , S 2 , S 1 and S 0 In other words, the neuromorphic processor 112 can perform multi-bit multiplication operations on multi-bit operands by adjusting the operation order and operation time.

[0171] At the same time, the bit value S of the result of the multi-bit neuromorphic operation 5 , S 4 , S 3 , S 2 , S 1 and S 0 Corresponds to FIG. 7A to FIG. 7B Multi-bit neuromorphic operation results PQRSTU 2 In addition, refer to FIG8A to FIG9Described with time t 0 to 8 Each corresponding synaptic operation value in corresponds to the reference Figure 6C Each bit value of the first to third intermediate products 633 to 635 is described.

[0172] FIG. 10A to FIG. 10E is a diagram depicting an example of the result of a 3-bit×3-bit multiplication operation processed by the neuromorphic processor 112 .

[0173] refer to Fig. 10A , when the 3-bit synaptic weight 011 is executed as described above 2 and 3 Axon 101 2 When performing multi-bit multiplication, a 6-bit multiplication result of 001111 can be obtained. 2 . refer to Fig. 10B , when the 3-bit synaptic weight 111 is executed as described above 2 and 3rd position axon 111 2 When performing multi-bit multiplication, a 6-bit multiplication result can be obtained. 2 . refer to Fig. 10C , when the 3-bit synaptic weight 111 is executed as described above 2 and 3rd Axon001 2 When performing multi-bit multiplication, a 6-bit multiplication result of 000111 can be obtained. 2 . refer to Fig. 10D , when the 3-bit synaptic weight 111 is executed as described above 2 and 3 Axon 010 2 When performing multi-bit multiplication, a 6-bit multiplication result of 001110 can be obtained. 2 . refer to Fig.10E , when the 3-bit synaptic weight 001 is executed as described above 2 and 3 Axon 100 2 When performing multi-bit multiplication, a 6-bit multiplication result of 000100 can be obtained. 2 .

[0174] In other words, the neuromorphic processor 112 may perform multi-bit neuromorphic operations (multi-bit multiplication operations) according to the time-division processing and distribution of bit values ​​of axon and synaptic weights described above.

[0175] Fig.11 is a diagram describing an example of the result of a 3-bit×2-bit multiplication operation processed by the neuromorphic processor 112. Hereinafter, for ease of description, a 3-bit×3-bit multiplication operation is described as an example of a multi-bit neuromorphic operation. However, there are examples in which the neuromorphic processor 112 performs multiplication operations of various other bits according to the time-division processing described above and the distribution of the bit values ​​of the axon and synaptic weights.

[0176] refer to Fig.11 , when the 3-bit synaptic weight 111 is executed as described above 2 and 2 Axon01 2 When performing multi-bit multiplication, a 5-bit multiplication result of 00111 can be obtained. 2 .

[0177] Fig.12 is a diagram illustrating an example of the result of a 4-bit×4-bit multiplication operation processed by the neuromorphic processor 112. Fig.12 , when the 4-bit synaptic weight 0101 is executed as described above 2 and 4 Axon 1010 2 When performing multi-bit multiplication, you can get an 8-bit multiplication result of 00110010 2 .

[0178] Meanwhile, in a neural network, the operation precision may be changed according to the layer and according to the processor core that processes the neural network in parallel. Here, the neuromorphic processor 112 according to the current embodiment can process data of various operation precisions required for executing the neural network without having to change the hardware components by performing the distribution of the bit values ​​of the axon and synaptic weights based on the respective operation precisions and the scheduling of the time-division processing.

[0179] Fig.13 is a diagram depicting an example of hardware resources of the neuromorphic processor 112 compared to hardware resources of a general-purpose neuromorphic processor.

[0180] refer to Fig.13 , using reference Figure 7C The general neuromorphic processor of the described method performs addition or integration on the received synaptic operation value by using the bit counter 1301 included in the neuron circuit. However, the general neuromorphic processor using the bit counter 1301 cannot perform multi-bit neuromorphic operations (multi-bit multiplication operations). Meanwhile, there is a general neuromorphic processor using the multiplier circuit 1302 included in the neuron circuit for multi-bit multiplication operations.

[0181] However, comparing the hardware resources of such a general neuromorphic processor with the hardware resources of the neuromorphic processor 112 according to the current example, unlike the general neuromorphic processor, examples of the neuromorphic processor 112 may include those that implement circuits with a small area by using fewer circuit devices while being capable of multi-bit multiplication operations.

[0182] Fig.14 is a flow chart of an example of a method of processing a multi-bit neuromorphic operation performed by the neuromorphic device 100. Fig.14, the method includes operations processed in a time sequence by the neuromorphic device 100 described above. Therefore, the details described above can be applied to Fig.14 method.

[0183] In operation 1401, the controller 1124 of the neuromorphic device 100 determines a first input to be assigned to an i-th lower bit of an n-bit axon of a single axon circuit 1121 at each time point, and a second input to be assigned to a j-th lower bit of an m-bit synaptic weight of a single synapse circuit 1122 at each time point. Here, the controller 1124 may repeatedly determine the first input and the second input to be assigned at each time point until a multi-bit neuromorphic operation result is obtained sequentially from a lower bit value to a higher bit value.

[0184] At operation 1402 , the single axon circuit 1121 receives the determined first input.

[0185] In operation 1403 , the single synapse circuit 1122 outputs a synaptic operation value between the first input and the second input while storing the determined second input.

[0186] In operation 1404 , the single neuron circuit 1123 obtains each bit value of the multi-bit neuromorphic operation result between the axon and the synaptic weight based on the output synaptic operation value.

[0187] Fig.15 is a block diagram of an example of a configuration of an embodiment of an example electronic system 1500 .

[0188] refer to Fig.15 , the electronic system 1500 can extract effective information by analyzing input data in real time based on a neural network, and determine a situation based on the extracted effective information or a control component of an electronic device on which the electronic system 1500 or the electronic system 1500 is installed. For example, the electronic system 1500 can be applied to a robot device such as a drone or an advanced driving assistance system (ADAS), a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measuring device, or an IoT device, and can be installed on at least one of various types of electronic devices.

[0189] The electronic system 1500 may include a processor 1510, a RAM 1520, a neuromorphic device 1530, a memory 1540, a sensor module 1550, and a communication (Tx / Rx) module 1560. The electronic system 1500 may further include an input / output module, a security module, a power control device, etc. At least some of the hardware components of the electronic system 1500 may be mounted on at least one semiconductor chip.

[0190] The processor 1510 controls the overall operation of the electronic system 1500. The processor 1510 may include one processor core (single core) or multiple processor cores (multi-core). The processor 1510 may process or execute programs and / or data stored in the memory 1540. According to an example, the processor 1510 may execute the program stored in the memory 1540 to control the functions of the neuromorphic device 1530. The processor 1510 may be a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP).

[0191] The RAM 1520 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 1540 may be temporarily stored in the RAM 1520 according to the control of the processor 1510 or a boot code. The RAM 1520 may be implemented as a memory such as a DRAM or an SRAM.

[0192] The neuromorphic device 1530 may implement a neural network based on the received input data and generate an information signal based on the result of the implemented operation. The neural network may include CNN, RNN, FNN, deep belief network, restricted Boltzmann machine, etc., but is not limited to these examples. The neuromorphic device 1530 may be a neural network dedicated hardware accelerator or an apparatus including the same, and may include the above-described Figure 4 A neuromorphic device 100 .

[0193] The information signal may include one of various types of recognition signals, such as a voice recognition signal, an object recognition signal, an image recognition signal, a biometric information recognition signal, etc. For example, the neuromorphic device 1530 may receive frame data included in a video stream as input data, and generate a recognition signal with respect to an object included in an image indicated by the frame data. However, the embodiments are not limited to these examples, and the neuromorphic device 1530 may receive any type of input data based on the type or function of an electronic device on which the electronic system 1500 is installed, and generate a recognition signal according to the input data.

[0194] The memory 1540 is a storage space for storing data, and may store an operating system (OS), various programs, and various types of data. According to an embodiment, the memory 1540 may store intermediate results generated during the operation of the neuromorphic device 1530.

[0195] The memory 1540 may be a DRAM, but is not limited to these examples. The memory 1540 may include at least one of a volatile memory and a non-volatile memory. Examples of non-volatile memories include ROM, PROM, EPROM, EEPROM, flash memory, PRAM, MRAM, RRAM, and FRAM. Examples of volatile memories include DRAM, SRAM, SDRAM, PRAM, MRAM, RRAM, and FeRAM. According to an embodiment, the memory 1540 may include at least one of a HDD, SSD, CF, SD, micro SD, mini SD, xD, and a memory stick.

[0196] The sensor module 1550 may collect surrounding information of the electronic device on which the electronic system 1500 is installed. The sensor module 1550 may sense or receive a signal (e.g., an image signal, a voice signal, a magnetic signal, a biometric signal, or a touch signal) from the outside of the electronic device, and convert the sensed or received signal into data. In this regard, the sensor module 1550 may include at least one of various types of sensing devices, such as a microphone, an image pickup device, an image sensor, a light detection and ranging (LIDAR) sensor, an infrared sensor, an ultrasonic sensor, a biosensor, and a touch sensor.

[0197] The sensor module 1550 may provide the converted data as input data to the neuromorphic device 1530, or be included in the neuromorphic device 1530 in an example. For example, the sensor module 1550 may include an image sensor, and may generate a video stream by photographing the external environment of the electronic device, and sequentially obtain or provide continuous data frames of the video stream to the neuromorphic device 1530 as input data. However, the embodiments are not limited to these examples, and the sensor module 1550 may provide various types of data to the neuromorphic device 1530.

[0198] The Tx / Rx module 1560 may include various wired or wireless interfaces capable of communicating with external devices. For example, the Tx / Rx module 1560 may include a local area network (LAN), a wireless LAN (WLAN) such as wireless high fidelity (Wi-Fi), a wireless personal area network (WPAN) such as Bluetooth, and a communication interface capable of accessing a mobile cellular network, such as a wireless universal serial bus (USB), ZigBee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), third generation (3G), fourth generation (4G) or long term evolution (LTE).

[0199] Perform the operations described in this application Figures 1 to 15The neuromorphic processor 112, processor 1510, RAM 1520, neural network device 1530, memory 1540, sensor module 1550, and Tx / Rx module 1560 in are implemented by hardware components configured to perform the operations performed by the hardware components described in this application. Examples of hardware components that can be used to perform the operations described in this application when appropriate include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer can be implemented by one or more processing elements, such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond to and execute instructions in a defined manner to achieve the desired result. In one example, a processor or computer includes, or is connected to one or more memories storing instructions or software executed by a processor or computer. A hardware component implemented by a processor or computer can execute instructions or software, such as an operating system (OS) and one or more software applications running on the OS, to perform the operations described in this application. The hardware component can also access, operate, process, create and store data in response to the execution of instructions or software. For simplicity, the singular term "processor" or "computer" can be used in the description of the examples described in this application, but in other examples, multiple processors or computers can be used, or the processor or computer can include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can implement a single hardware component, or two or more hardware components. The hardware components may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0200] Perform the operations described in this application Figures 1 to 15The method illustrated in the figure is performed by computing hardware implemented as described above to execute instructions or software to perform the operations described in the present application performed by the method, for example, by one or more processors or computers. For example, a single operation or two or more operations can be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations can be performed by one or more processors, or a processor and a controller, and one or more other operations can be performed by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can perform a single operation, or two or more operations.

[0201] The instructions or software for controlling computing hardware, for example, one or more processors or computers to implement hardware components and perform the methods as described above can be written as computer programs, code segments, instructions or any combination thereof, to indicate or configure one or more processors or computers individually or collectively to operate as a machine or special-purpose computer for performing the operations performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code directly executed by one or more processors or computers, such as machine code generated by a compiler. In another example, the instructions or software include high-level code executed by one or more processors or computers using an interpreter. Instructions or software can be written in any programming language based on the block diagrams and flow charts illustrated in the figure and the corresponding descriptions in the specification, which disclose algorithms for performing the operations performed by the hardware components and the methods as described above.

[0202] The instructions or software that controls computing hardware, for example, one or more processors or computers to implement hardware components and perform the methods described above, and any associated data, data files, and data structures may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), flash memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state disk, and any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide instructions or software and any associated data, data files, and data structures to one or more processors or computers so that one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over a network-coupled computer system so that the instructions or software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by one or more processors or computers.

[0203] Although the present disclosure includes specific examples, it will be apparent to those skilled in the art that various changes in form and detail can be made in these examples without departing from the spirit and scope of protection of the claims and their equivalents. The examples described here are to be considered only in a descriptive sense, and not for limitation. The description of the features or aspects in each example is considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways, and / or replaced or supplemented by other components or their equivalents, appropriate results can be achieved. Therefore, the scope of the present disclosure is not defined by the specific description, but by the claims and their equivalents, and all changes within the scope of the claims and their equivalents are considered to be included in the present disclosure.

Claims

1. A neuromorphic device configured to process a multi-bit neuromorphic operation, the neuromorphic device comprising: a single axon circuit configured to receive as a first input the i-th bit of the n-bit axon; a single synaptic circuit configured to store a j-th bit of the m-bit synaptic weight as a second input, and output a synaptic operation value between the first input and the second input; a single neuron circuit configured to obtain a value of each bit of a result of a multi-bit neuromorphic operation between an n-bit axon and an m-bit synaptic weight based on an output synaptic operation value; and a controller configured to determine, respectively, an i-th bit and a j-th bit to be sequentially allocated to a single axon circuit and a single synapse circuit for each of different time periods to obtain a multi-bit neuromorphic operation result from a low bit value to a high bit value, Where n and m are each natural numbers, i is a natural number between 1 and n, and j is a natural number between 1 and m, and The controller is further configured to determine the first input and the second input to be allocated in each time period so that each bit indicating a multi-bit neuromorphic operation result is obtained sequentially by a single neuron circuit from the value of the least significant bit LSB to the value of the most significant bit MSB.

2. The neuromorphic device of claim 1, wherein: The controller is further configured to map i and j such that the i-th bit and the j-th bit are combined differently for different time periods.

3. The neuromorphic device of claim 2, wherein: The controller is further configured to sequentially change the values ​​of i and j of the i-th bit and the j-th bit in increasing order of bit value.

4. The neuromorphic device of claim 2, wherein: The total number of combinations of the i-th bit and the j-th bit corresponds to a value obtained by multiplying n by m.

5. The neuromorphic device of claim 1, wherein: The single axon circuit and the single synapse circuit each process a single bit value for different time periods.

6. The neuromorphic device of claim 1, wherein: The single neuron circuit includes a single adder configured to perform an addition operation using synaptic operation values ​​output from a single synapse circuit for different time periods.

7. The neuromorphic device of claim 6, wherein: The single neuron circuit is configured to perform an addition operation using a single adder to obtain each bit value of a multi-bit neuromorphic operation result, the addition operation using at least one of the following as an input: a preset initial value, a synaptic operation value output from the single synaptic circuit in a previous time period of the different time period, a synaptic operation value output from the single synaptic circuit in a current time period of the different time period, an addition value processed by the single adder in a previous time period of the different time period, and a carry value determined by the single adder in a previous time period of the different time period.

8. The neuromorphic device of claim 6, wherein: At least one of the addition value and the carry value output from the single adder corresponds to a value of one of the bits of the multi-bit neuromorphic operation result.

9. The neuromorphic device of claim 6, wherein: The single adder is reused to obtain the value of each bit of the multi-bit neuromorphic operation result after obtaining the value of one of the bits of the multi-bit neuromorphic operation result.

10. The neuromorphic device of claim 6, wherein: The single adder is further configured to perform an addition operation by receiving as input a synaptic operation value corresponding to the same bit position between intermediate products used to obtain a multi-bit neuromorphic operation result.

11. The neuromorphic device of claim 1 , wherein: The single neuron circuit is further configured to determine whether to output a spike by comparing the multi-bit neuromorphic operation result with a preset threshold upon receiving each bit of the multi-bit neuromorphic operation result.

12. A multi-bit neuromorphic operation method, the method comprising: determining, for each of the different time periods, an i-th bit of an n-bit axon to be sequentially assigned to a single axon circuit as a first input; determining as a second input the j-th bit of each of the m-bit synaptic weights to be assigned to the single synaptic circuit for different time periods; receiving a determined first input from a single axon circuit; storing the determined second input in a single synaptic circuit and outputting a synaptic operation value as a function between the first input and the second input; and Through a single neuron circuit, each bit value of a multi-bit neuromorphic operation result between an n-bit axon and an m-bit synaptic weight is obtained based on the output synaptic operation value, wherein the first input and the second input are determined for different time periods until a multi-bit neuromorphic operation result is obtained sequentially from a low bit value to a high bit value, Where n and m are each natural numbers, i is a natural number between 1 and n, and j is a natural number between 1 and m, and The first input and the second input to be allocated in each of the different time periods are determined so that each bit indicating a multi-bit neuromorphic operation result is sequentially obtained by a single neuron circuit from the value of the least significant bit LSB to the value of the most significant bit MSB.

13. The method of claim 12, wherein: i and j are determined so that the i-th bit and the j-th bit are combined differently for each of different time periods.

14. The method of claim 13, wherein: The values ​​of i at the ith position and j at the jth position are sequentially changed in increasing order of position value.

15. The method of claim 13, wherein: The total number of combinations of the i-th bit and the j-th bit corresponds to a value obtained by multiplying n by m.

16. The method of claim 12, wherein: The obtaining includes obtaining each bit value using an addition operation of synapse operation values ​​output from a single synapse circuit for different time periods based on a single adder.

17. The method of claim 16, wherein: The obtaining includes performing an addition operation using a single adder to obtain each bit value of the multi-bit neuromorphic operation result, the addition operation using at least one of the following as an input: a preset initial value, a synaptic operation value output from a single synaptic circuit in a previous time period of the different time period, a synaptic operation value output from the single synaptic circuit in a current time period of the different time period, an addition value processed by the single adder in a previous time period of the different time period, and a carry value determined by the single adder in a previous time period of the different time period.

18. The method of claim 16, wherein: At least one of an addition value and a carry value output from the single adder corresponds to a value indicating one of the bits of the multi-bit neuromorphic operation result.

19. The method of claim 16, wherein: The obtaining includes obtaining values ​​indicative of each bit of the multi-bit neuromorphic operation result after obtaining values ​​indicative of one of the bits of the multi-bit neuromorphic operation result.

20. The method of claim 16, wherein: The obtaining further includes performing an addition operation by receiving, as an input to a single adder, synaptic operation values ​​corresponding to the same bit positions between intermediate products used to obtain the multi-bit neuromorphic operation results.

21. The method of claim 12, further comprising: Through a single neuron circuit, when each bit of the multi-bit neuromorphic operation result is received, it is determined whether to output a spike by comparing the multi-bit neuromorphic operation result with a preset threshold.

22. A non-transitory computer-readable recording medium storing instructions which, when executed by a processor, cause the processor to perform the method of claim 12.

23. A neuromorphic processor comprising: The controller is configured to, for each of the time periods, sequentially determine: One of the n bits assigned to a single axon circuit; a one of the m bits assigned to a single synapse circuit, the single synapse circuit configured to output a synaptic operation value as a function of the one of the n bits and the one of the m bits; one of each bit value of a multi-bit neuromorphic operation result between one of the n bits and one of the m bits based on a synaptic operation value for an output of a single neuron circuit, wherein the controller accumulates the multi-bit neuromorphic operation result for each of the n-bit and m-bit time periods in byte order, and n and m are each natural numbers, and Wherein, one bit of a multi-bit activation input and one bit of a multi-bit synaptic weight to be allocated in each time period of different time periods are determined so that each bit indicating a multi-bit neuromorphic operation result is obtained sequentially by the single neuron circuit from the value of the least significant bit LSB to the value of the most significant bit MSB.

24. The neuromorphic processor of claim 23, wherein: The n bits and m bits are stored in an external memory.

25. The neuromorphic processor of claim 23, wherein: The single neuron circuit includes a single adder and a comparator.

26. The neuromorphic processor of claim 25, wherein: The single adder is configured to receive the initial value as a summand, the synaptic operation value as an addend, and the initial value as a carry value during a first time period of each time period.

27. The neuromorphic processor of claim 26, wherein: The single adder is configured to perform an addition operation to output an addition value and a carry value, The addition value corresponds to the least significant bit (LSB) of the multi-bit neuromorphic operation result, and the carry value is input as a carry value of the addition operation to be performed in a second time period of each time period.

28. The neuromorphic processor of claim 27, wherein: The single adder is further configured to perform another addition operation for a second time period to output another addition value and another carry value, The another addition value corresponds to another bit value of the multi-bit neuromorphic operation result, and the another carry value is input as another carry value of a subsequent addition operation to be performed in a third time period of each time period.

29. The neuromorphic processor of claim 27, wherein: The neuromorphic processor is included in an electronic device for driving a neural network.

30. A neuromorphic chip comprising the neuromorphic processor of claim 23 and an external memory storing n bits and m bits.

31. A neuromorphic processor comprising: axonal circuits; a synaptic circuit connected to the axonal circuit; as well as a neuron circuit connected to the synaptic circuit and comprising an adder, wherein the neuron circuit is configured to perform a multiplication operation between a multi-bit activation input input to the axon circuit and a multi-bit synaptic weight input input to the synapse circuit by reusing the adder in a time-division manner, and Wherein, one bit of a multi-bit activation input and one bit of a multi-bit synaptic weight to be allocated in each time period of different time periods are determined so that each bit indicating a multi-bit neuromorphic operation result is obtained sequentially by the neuron circuit from the value of the least significant bit LSB to the value of the most significant bit MSB.

32. The neuromorphic processor of claim 31 , wherein: The adder is a full adder.

33. The neuromorphic processor of claim 31 , wherein: The adder is a single adder.

34. The neuromorphic processor of claim 31 , further comprising a controller configured to control the time division manner.

35. A neuromorphic device comprising: a neuromorphic processor comprising an axon circuit, a synapse circuit connected to the axon circuit, and a neuron circuit connected to the synapse circuit and comprising an adder; as well as a memory for storing data processed by the neuromorphic processor, wherein the neuromorphic processor performs a multiplication operation between a multi-bit activation input input to the axon circuit and a multi-bit synaptic weight input input to the synapse circuit by reusing the adder included in the neuron circuit in a time-division manner, and Wherein, one bit of a multi-bit activation input and one bit of a multi-bit synaptic weight to be allocated in each time period of different time periods are determined so that each bit indicating a multi-bit neuromorphic operation result is obtained sequentially by the neuron circuit from the value of the least significant bit LSB to the value of the most significant bit MSB.

36. The neuromorphic device of claim 35, wherein: The neuromorphic processor further includes a controller configured to determine an i-th bit of a multi-bit activation input and a j-th bit of a multi-bit synaptic weight input to be combined differently, an i-th lower bit of the multi-bit activation input and a j-th lower bit of the multi-bit synaptic weight input to be processed in a time-division manner by the adder.

37. The neuromorphic device of claim 35, wherein: The axon circuit and the synapse circuit correspond to a single axon circuit and a single synapse circuit, respectively, processing a value of a single bit.

38. The neuromorphic device of claim 35, wherein: The memory stores a multi-bit activation input to be provided to the axon circuit, a multi-bit synaptic weight input to be provided to the synapse circuit, and a result of performing a multiplication operation.

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