Class-D amplifier circuit and electronic device including the same

Abstract

A class-D amplifier circuit for amplifying an input signal, the class-D amplifier circuit including a controller configured to control the class-D amplifier circuit to selectively transition between an open-loop operation mode and a closed-loop operation mode based on an indication of the amplitude of the input signal.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 24, 2015, the application number of 201580058056.5, and the title of "Class D amplifier circuit". Technical Field

[0002] The present invention relates to a class D amplifier circuit, and more particularly to a class D amplifier that selectively changes signal components for driving an amplifier output stage based on signal amplitude. Background Art

[0003] Figure 1 An embodiment of a conventional class D amplifier is illustrated. A modulator 101 controls a class D output stage 102 based on an input signal to generate an output signal Vout, which is a digital input signal Din in this embodiment. The output stage 102 includes a plurality of switches for switching the output stage 102 between a plurality of voltages (e.g., a supply voltage VDD and a ground voltage, or a positive supply voltage +VDD and a negative supply voltage -VDD). As will be understood by those skilled in the art, the output stage 102 may include a half-bridge switch arrangement or a full-bridge switch arrangement, and is switched to output an analog output signal Vout, which may be a differential output signal in some embodiments.

[0004] The modulator 101 receives an input signal (which is a digital signal Din in this embodiment) and derives at least one appropriate control signal for the output stage 102. A standard digital modulator 101 has a well-defined transfer function, e.g., flat and having a defined gain over a certain passband frequency range. Ideally, this digital domain signal processing provides high performance and avoids the non-zero signal attenuation associated with noise, component mismatch, and non-linearity in analog circuitry.

[0005] However, the output signal Vout is an analog signal, and its performance is limited by analog effects in any output driver stage of the amplifier. For example, output driver transistor on-resistance, finite rise and fall times, propagation delay, power supply ripple, and output impedance. Additionally, any power supply ripple causes a proportional gain change in the output driver stage.

[0006] Negative feedback techniques are commonly used to suppress signal distortion caused by these reasons. Figure 1 The class D amplifier thus has a feedback path including an analog-to-digital converter (ADC) 103 and a subtractor 104.

[0007] The ADC 103 is adapted to receive an analog output signal Vout and generate a digital signal representative of this output signal. This digital signal is then subtracted from a digital input signal Din by a subtractor 104 to generate an error signal. A loop filter 105 (which can be, for example, a digital integrator) filters this error signal to generate a modulator input signal that is supplied to the digital modulator 101.

[0008] The performance of such an amplifier circuit is limited by the noise, resolution, and linearity of the ADC 103. To avoid introducing unwanted noise into the amplifier circuit, the ADC must have good noise characteristics, which typically requires the use of a relatively high-performance continuous-time ADC. Such an ADC is relatively large (in terms of silicon area in an integrated circuit) and has a relatively high power consumption in use.

[0009] Typically, class-D amplifier circuits have been used in relatively high-power applications such as audio devices powered by a main power supply where size and power consumption are not critical. However, class-D amplifiers are increasingly being considered for applications in portable devices and the like. With the development of silicon manufacturing processes towards smaller geometries, it is advantageous to use circuits that are mainly digital. Class-D amplifiers can include architectures that are largely digital, and thus class-D amplifiers are increasingly being proposed for driving small speakers such as in portable devices and the like, or even for earbud / headphone applications where the power is typically relatively low. In such applications, size and power efficiency are factors to be considered for the amplifier circuit. Summary of the Invention

[0010] Accordingly, it is desirable to provide a class-D amplifier circuit that at least mitigates some of the above disadvantages.

[0011] According to the present invention, there is provided a class-D amplifier circuit for receiving a digital input signal and outputting an analog output signal, comprising:

[0012] A class-D output stage;

[0013] A digital modulator for generating at least one control signal for controlling the class-D output stage based on a modulator input signal;

[0014] An error block for generating an error signal based on the output signal and the digital input signal;

[0015] A signal selector block configured to receive the error signal at a first input, a form of the digital input signal at a second input, and generate the modulator input signal; wherein:

[0016] The signal selector block can operate in a first operating mode and a second operating mode, wherein:

[0017] In the first mode, the modulator input signal is at least partially based on the error signal; and

[0018] In the second mode, the modulator input signal is based on the digital input signal and is independent of the error signal; and

[0019] A signal selection controller, configured to control the operating mode of the signal selector block based on an indication of the magnitude of the digital input signal.

[0020] The signal selector block may include a first signal path between the first input and a selector module, and may include a second signal path between the second input and the selector module. The selector module may be configured to generate the modulator input signal from signals from the first signal path and the second signal path.

[0021] The selector module may operate in a combiner state to combine the signal from the first signal path with the signal from the second signal path to provide the modulator input signal, and / or may operate in a pass-through state to provide the signal from the second signal path as the modulator input signal. The signal selection controller may be configured to control the selector module in the combiner state in the first mode and in the pass-through state in the second mode.

[0022] In some embodiments, the selector module is configured to select the signal from the first signal path or the signal from the second signal path to provide the modulator input signal. The signal selection controller may be configured to control the selector module to select the signal from the first signal path in the first mode and the signal from the second signal path in the second mode.

[0023] In some embodiments, the first signal path includes at least one variable gain element. The signal selection controller may be configured to control the at least one variable gain element to provide a first gain setting in the first mode and a second gain setting in the second mode. The second gain setting may be zero.

[0024] In some embodiments, the signal selection controller is configured to control the at least one variable gain element to provide a controlled gain transition between the first gain setting and the second gain setting that involves at least one intermediate gain setting. The controlled gain transition may include a gain ramp.

[0025] In some embodiments, the variable gain element includes a multiplier.

[0026] The first signal path may include a loop filter. The at least one variable gain element may be located in the first signal path downstream of the loop filter. Additionally or alternatively, in some embodiments, the loop filter has variable gain and the at least one variable gain element may include the loop filter. The loop filter may include an integrator and the signal selection controller may be configured to control the integrator time constant of the integrator to change the gain of the loop filter. The signal selection controller may be configured to enable the loop filter in a first mode and disable the loop filter in a second mode.

[0027] In some embodiments, the error block includes an analog-to-digital converter (ADC) coupled to receive the output signal. The error block may further include a subtractor that may generate an error signal based on the output of the ADC and the digital input signal. The signal selection controller may be configured to enable the analog ADC in a first mode and disable the ADC in a second mode.

[0028] The amplifier circuit may further include an envelope detector for determining an envelope value of the digital input signal. The signal selection controller may be configured to use the envelope value as an indication of the amplitude of the digital input signal.

[0029] The envelope detector may impose a predetermined delay between any drop in the detected signal envelope and a decrease in the envelope value. In some embodiments, the envelope detector receives a form of the digital input signal.

[0030] In some embodiments, the signal selection controller is configured to receive an indication of a volume control setting and use the indication of the volume control setting as an indication of the amplitude of the digital input signal.

[0031] The signal selection controller may be configured to transition from a first operating mode to a second operating mode if an indication of the amplitude of the digital input signal drops below a first amplitude threshold. It may also be configured to transition from the second operating mode to the first operating mode if an indication of the amplitude of the digital input signal rises above a second amplitude threshold. The first threshold may be the same as the second threshold, or the thresholds may be different.

[0032] The signal selection controller may be configured to initiate any transition between the first mode and the second mode when the amplitude of the input signal is at or below a first amplitude level. The class D amplifier circuit may include a low level detector that is configured to detect when the amplitude of the input signal is at or below the first amplitude level.

[0033] Embodiments also relate to an integrated circuit including a class D amplifier circuit as described in any of the variations above. Still further embodiments relate to an electronic device including such an integrated circuit or an amplifier circuit as described in any of the variations above. The device may be at least one of the following: a portable device; a battery-powered device; a computing device; a communication device; a gaming device; a mobile phone; a personal media player; a laptop computer, a tablet computer, or a notebook computing device.

[0034] According to another aspect of the present invention, there is provided a method of operating a class D amplifier circuit, comprising: receiving a digital input signal; and providing a modulator input signal to a digital modulator to control a class D output stage to produce an output signal; wherein the method includes selectively changing between a first operating mode and a second operating mode based on an indication of the amplitude of the digital input signal; wherein, in the first operating mode, the modulator input signal is at least partially based on an error signal that is generated based on the output signal and the digital input signal; and in the second operating mode, the modulator input signal is based on the digital input signal and is independent of the error signal.

[0035] In yet another aspect of the present invention, there is provided a class-D amplifier circuit for receiving an input signal and outputting an output signal, the amplifier circuit comprising: a class-D output stage; a controller for generating at least one control signal to control the output stage; and an error block for deriving an error signal from the output signal and the input signal; wherein the controller is capable of operating in a first operating mode, wherein the at least one control signal is at least partially based on the error signal, and is further capable of operating in a second operating mode, wherein the at least one control signal is based on the input signal and does not include any component from the error signal; and wherein the controller is configured to selectively change between the first operating mode and the second operating mode based on an indication of the amplitude of the input signal.

[0036] In yet another aspect, there is provided a class-D amplifier circuit that changes between open-loop operation and closed-loop operation based on an indication of the amplitude of an input signal.

[0037] In yet another aspect of the present invention, there is provided a class-D amplifier circuit that controllably transitions between an open-loop operating mode and a closed-loop operating mode in response to a characteristic of the amplitude of an input signal.

[0038] In yet another aspect of the present invention, there is provided a class-D amplifier circuit for amplifying an input signal, the class-D amplifier circuit selectively transitioning between an open-loop operating mode and a closed-loop operating mode in response to a characteristic of the amplitude of the input signal.

[0039] In yet another aspect of the present invention, there is provided a class-D amplifier circuit for receiving a digital input signal and outputting an analog output signal, comprising:

[0040] a class-D output stage;

[0041] a digital modulator for generating at least one control signal for controlling the class-D output stage based on a modulator input signal;

[0042] an error block for generating an error signal, the error block comprising an analog-to-digital converter for receiving an indication of the analog output signal, and a subtractor for generating the error signal based on the output of the analog-to-digital converter and the digital input signal;

[0043] a signal selector block, comprising:

[0044] a selector module;

[0045] a first signal path located between a first input for receiving the error signal and the selector module; and

[0046] A second signal path, located between a second input for receiving the digital input signal and the selector module;

[0047] wherein the selector module is configured to generate the modulator input signal from signals from the first signal path and the second signal path; and

[0048] A signal selection controller, configured to change the gain applied in the first signal path based on an indication of the amplitude of the digital input signal.

[0049] In a further aspect of the present invention, there is provided a class-D amplifier circuit for receiving an amplifier input signal and outputting an output signal, comprising: a class-D output stage; a modulator for generating at least one control signal for controlling the class-D output stage based on a modulator input signal; an error block for generating an error signal based on the output signal and the amplifier input signal; a signal selector block configured to receive the error signal at a first input and the digital input signal at a second input and generate the modulator input signal; and a signal selection controller configured to control the amplifier circuit to change the degree to which the error signal contributes to the modulator input signal based on an indication of the amplitude of the amplifier input signal. Description of the Drawings

[0050] Figure 1 Illustrates an embodiment of a known class-D amplifier circuit;

[0051] Figure 2 Illustrates a class-D amplifier circuit according to an embodiment of the present invention;

[0052] Figure 3 Illustrates a flowchart of an embodiment of a method of swapping between a first operating mode and a second operating mode;

[0053] Figure 4 Illustrates an embodiment of an analog-to-digital converter suitable for use in an embodiment of the present invention;

[0054] Figure 5 Illustrates an embodiment of a current-controlled oscillator;

[0055] Figure 6 Illustrates an embodiment of a digital modulator;

[0056] Figure 7 Illustrates an embodiment of an output driver stage suitable for use in an embodiment of the present invention;

[0057] Figure 8An embodiment of a loop filter suitable for use in one embodiment of the present invention is illustrated;

[0058] Figure 9 A class D amplifier circuit according to another embodiment of the present invention is illustrated;

[0059] Figure 10 A class D amplifier circuit according to yet another embodiment of the present invention is illustrated;

[0060] Figure 11 A class D amplifier circuit according to yet another embodiment of the present invention is illustrated;

[0061] Figure 12 A class D amplifier circuit according to another embodiment of the present invention is illustrated; and

[0062] Figure 13 An apparatus having a class D amplifier circuit according to one embodiment of the present invention is illustrated. DETAILED DESCRIPTION

[0063] As previously mentioned, a class D amplifier for receiving an input signal and generating an output signal typically includes a modulator for controlling a class D output stage based on a modulator input signal. An error block may be provided, which may include, for example, an ADC and a subtractor in a feedback path, to generate an error signal based on the output signal and the input signal, e.g., the difference between a converted form of the output signal and the input signal. Embodiments of the present invention relate to a class D amplifier circuit in which the degree of contribution of the error signal to the modulator input signal is variable based on an indication of the amplitude of the input signal. In some embodiments, the amplifier circuit may selectively vary between at least two operating modes based on the amplitude of the input signal. In a first operating mode, the modulator input signal may be at least partially based on the error signal. In a second operating mode, the modulator input signal may be based on the input signal but may be independent of the error signal. At relatively high signal amplitudes, the amplifier may operate in the first operating mode, and at relatively low signal amplitudes, the amplifier may operate in the second mode (e.g., an open-loop operating mode).

[0064] Thus, at high signal levels, the error signal is used to help reduce any distortion in the output signal. However, at low signal levels, the degree of any distortion is less significant and thus the feedback error signal is not used. Since the error signal is only used at relatively high signal levels, the noise requirements on components of the error block, such as the ADC, are relaxed compared to conventional implementations where the error signal is always used during steady-state operation. In fact, at low signal levels where the noise floor of the amplifier circuit is more significant, the error signal is not used. This means that, for example, a smaller and / or lower-power ADC can be implemented in the error block than would otherwise be required, thus reducing the size of the amplifier circuit and / or increasing the power efficiency of the amplifier circuit without any significant reduction in signal quality or noise performance. In some embodiments, as will be described in more detail later, some components associated with generating or processing the error signal can even be disabled in a second operating mode to provide additional power savings.

[0065] Figure 2 A class D amplifier circuit according to one embodiment of the present invention is illustrated generally at 200. A modulator 201 (a digital modulator in this embodiment) controls the class D output stage 202 as described above with reference to Figure 1 In some embodiments, the output driver stage 202 can be a full H-bridge class D amplifier output stage or a half-bridge class D amplifier output stage or any other suitable amplifier output stage.

[0066] In Figure 2 the embodiment of, the input to the digital modulator 201 is the modulator input signal Dm received from a signal selector block 203. The signal selector block 203 receives the error signal ε at a first input 204 from an error block 205. The signal selector block also receives a form of the input signal Din at a second input 206.

[0067] The error block 205 generates the error signal ε from the digital input signal Din and the analog output signal Vout. In this embodiment, the error signal is based on a comparison between the digital input signal Din and the analog output signal Vout.

[0068] As Figure 2As illustrated, the error block 205 may include an analog-to-digital converter (ADC) 207 that receives an analog output signal Vout and outputs a digital signal representative of the analog output signal. A digital subtractor 208 receives the output of the ADC 207 and a form of the digital input signal Din and generates an error signal ε. In some embodiments, the analog output signal Vout may be input to the ADC 207 after being filtered by a low-pass filter 209. This helps provide suppression of any high-frequency signals and transients at the output to avoid their downmixing to audio frequencies due to imperfections of the ADC.

[0069] The signal selector block 203 is operable to autonomously vary the degree to which the error signal ε contributes to the modulator input signal Dm based on an indication of the magnitude of the input signal Din. In one embodiment, the signal selector block 203 may operate in two operating modes. In the first mode, the modulator input signal Dm is at least partially based on the error signal. Thus, the first mode corresponds to the closed-loop operating mode of the amplifier circuit. However, in the second mode, the modulator input signal Dm is based on the digital input signal Din and is independent of the error signal ε. Thus, the second mode corresponds to the open-loop operating mode of the amplifier circuit.

[0070] The signal selector block 203 thus includes a first signal path between its first input 204 and a first input of a selector module 210, and a second signal path between its second input 206 and a second input of the selector module 210. The selector module 210 is configured to obtain signals from one or both of the first signal path and the second signal path to provide the modulator input signal Dm. The signal selector module 210 may be implemented in a variety of ways, as will be described in more detail later.

[0071] The first signal path is thus the signal path for the error signal ε. This signal path may include a loop filter 211 for filtering the error signal in a manner similar to that described above with respect to Figure 1 The open-loop gain of the loop including the loop filter 211 should preferably be high at audio frequencies and also remain stable at higher frequencies. The loop filter 211 may thus be, for example, a first-order integrator or possibly a higher-order filter, having high gain at the audio signal band and low gain at higher frequencies.

[0072] The second signal path is the signal path for the input signal Din. Figure 2 It is illustrated that there is no signal processing in the second signal path, but if desired, one or more signal conditioning components, such as filters located in this signal path, may be present.

[0073] As mentioned above, the signal selection block 203 can operate in a first mode in which the modulator input signal is at least partially based on the error signal. Thus, in the first operating mode, there is an error signal component from the first signal path to the modulator input signal Dm. In the second operating mode, the modulator input signal is based on the input signal Din and is independent of the error signal. Thus, in the second operating mode, there is an input signal component from the second signal path to the modulator input signal Dm, and practically no signal component from the first signal path (at least no signal component corresponding to the error signal).

[0074] There are various ways to enable the first and second operating modes, and as mentioned above, the selector module 210 can take various forms. For example, in some embodiments, the selector module can receive signal components from the first and second signal paths and can select the signal from the first signal path or a second signal from the second signal path to provide the modulator input signal Dm. The selector module 210 can thus include a switching module that switches its output between the two signal paths. The selector module 210 can be controlled by a signal selection controller 212. The switching module can include one or more physical switch elements and / or can be implemented by a digital switch, which can be a physical multiplexer including combinational logic elements or can, for example, change the address of a register from which signal data is obtained. Thus, in such an embodiment, the signal from the first signal path (e.g., the filtered error signal) is used in the first mode (with no component from the second signal path), and the signal from the second signal path (e.g., the input signal Din) is used in the second mode with no any component from the first signal path. However, in such an embodiment, there may be a gross transient during the mode switch, for example, because the loop filter stabilizes after the change to the first mode or because the error component is removed when switching to the second mode.

[0075] Thus, in some embodiments, the selector module 210 can be a combiner for combining signals from the first and second signal paths to provide the modulator input signal Dm at least in the first mode. In the first mode, the selector module 210 can thus be a combiner acting as an adder. In such an embodiment, the filtered error signal from the first signal path can be added to the input signal from the second signal path in the first mode. In the second mode, the signal from the second signal path can be the sole contribution to the modulator input signal Dm.

[0076] The combiner selector module 210 can thus operate in two states: State 1, which is the combiner operation state to combine signals from the first signal path and the second signal path in the first mode; and State 2, which is the low-pass operation state, in which only the signal from the second signal path is used. The relevant operation state of the selector module 210 can be controlled by the controller 212. Additionally or alternatively, the amplifier circuit can be configured such that no signal-related component of the error signal is received at the selector module 210 in the second mode. In other words, in the second mode, the signal received from the second signal path at the combiner selector module 210 has a constant, non-signal-related static value, e.g., zero. In this case, the selector module 210 can include a simple adder or the like. The adder can operate in the same manner in the first mode and the second mode, but in the second mode, there is no signal component received from the error signal at the adder, and thus the modulator input signal Dm will be independent of the error signal. However, in some embodiments, preferably, the controller 212 operates the combiner selector module 210 in the through state in the second operation mode, even when there is no signal-related component received from the second signal path, to avoid the computational expense of repeatedly adding zero to the signal from the first signal path.

[0077] There are various ways to remove the contribution of the error signal to the input of the selector module 210. For example, the signal in the first signal path can be effectively blocked or attenuated to zero in the second mode. In some embodiments, there can be at least one variable gain element 213 with an applied controlled gain located in the first signal path. The signal selection controller 212 can be configured to control the at least one variable gain element 213 to provide a first gain setting in the first mode, which is a nominal non-zero gain setting. In the second mode, the gain can be set to zero. Additionally or alternatively, the loop filter 211 can have a variable gain, which can be set to zero by the controller 212 in the second operation mode.

[0078] In some embodiments, the error signal may not be generated in the second operation mode. For example, one or more components of the error block 205 can be controlled such that the output of the error block is a constant zero, so that there is no error signal received at the first input of the signal selector block 203 in the second operation mode, and thus no signal-related component of the error signal is received at the selector module.

[0079] Thus, it will be apparent that in some embodiments, when the signal selection block 203 operates in the first mode, the (signal-related) error signal is added to the input signal from the second signal path to form the modulator input signal Dm. However, in the second mode, only the input signal from the second signal path is used for the modulator input signal. In such embodiments, any overall transient associated with the mode switch may be lower than the overall transient discussed above for embodiments that simply step change between using only the input signal or only the error signal.

[0080] In some embodiments, to minimize or eliminate any unwanted transients, during a mode change between the first mode and the second mode, there may be a controlled gain transition applied in the first signal path. For example, as mentioned, there may be a variable gain element in the first signal path, such as the digital multiplier 213. Figure 2 The variable gain element 213 is illustrated as being downstream of the loop filter 211, but equally, the gain element may additionally or alternatively be upstream of the loop filter 211 and / or as mentioned, the gain of the loop filter 211 itself may be variable. The signal selection controller 212 may be configured to control at least one variable gain element, such as the multiplier 213, to provide the first non-zero gain setting in the first mode and a second gain setting in the second mode. The second gain setting may be zero, but in some embodiments may be a non-zero gain setting lower than the first gain setting. The variable gain element may be controlled to provide a controlled gain transition involving at least one intermediate gain setting between the first gain setting and the second gain setting. For example, there may be a gain ramp over a particular time period. For example, consider that the signal selector block changes mode from the first operating mode to the second operating mode. In the first operating mode, the gain applied to the first signal path is at the first gain setting. The controller 212 may then initiate a controlled gain transition during the mode change to the second mode. The gain applied by the multiplier 213 may then be controllably ramped down to the second gain setting over a defined time period. The second gain setting may be zero, in which case the second mode is enabled when the gain reaches zero. However, in other embodiments, the second gain setting may be a small but non-zero gain setting that is low enough such that if the selector module 210 is switched to the through state in the second operating mode, there will be no significant transient.

[0081] The signal selection controller 212 determines whether to operate in the first operating mode or the second operating mode based on an indication of the magnitude of the input signal Din. In some embodiments, as Figure 2As illustrated in, an envelope detector 214 can be provided to derive an envelope value ENV of the digital input signal, and the envelope value ENV is provided to the controller 212. In some embodiments, the envelope detector 214 can receive the input digital signal Din. However, in some embodiments, alternatively, the signal from the signal path of the amplifier circuit can be used to determine the envelope value, for example, the signal derived from the modulator 201. However, it should be appreciated that alternatively, an indirect indication of the amplitude of the digital input signal Din can be provided. For example, the volume control signal Vol can be considered an indication of the maximum amplitude. In other arrangements, a signal (such as the envelope value) can be determined upstream and provided to the amplifier circuit, or the downstream load characteristics can be used as an indication of the signal amplitude.

[0082] In Figure 2 the embodiment of, the controller 212 receives the envelope value ENV and determines whether to operate in the first operating mode or the second operating mode. If ENV indicates that the input signal has a relatively large amplitude, the first operating mode is selected, that is, the closed-loop operating mode of the amplifier. If ENV indicates that the input signal has a relatively small amplitude, the second operating mode is selected, that is, in this embodiment, the open-loop operating mode. In some embodiments, the signal selection controller 212 can be configured to transition from the first operating mode to the second operating mode if the envelope value (i.e., an indication of the amplitude of the digital input signal Din) drops below a first amplitude threshold, and to transition from the second operating mode to the first operating mode if the envelope value rises above a second amplitude threshold. The first amplitude threshold and the second amplitude threshold can be the same or different, for example, to apply some hysteresis.

[0083] Accordingly, when the signal is relatively low, the error signal is not used because the low-amplitude input signal results in an output signal that is less affected by any inherent distortion in the output driver stage (e.g., caused by any potential power supply ripple or other error sources). The background noise of the amplifier system is thus mainly determined by the digital modulator 201, which can be designed accordingly. However, when the amplitude of the digital input signal Din is relatively high, the output signal will suffer more inherent distortion. Thus, at higher amplitudes, the amplifier operates in a closed-loop mode so that the error caused by these distortions can be reduced. Accordingly, components of the error block, such as the ADC 207, are designed to reduce distortion, etc. at higher signal levels. However, at higher signal levels, the background noise performance of the ADC 207 is less important and thus the ADC 207 can be designed under relaxed constraints compared to a conventional class-D amplifier that always operates in a steady-state operation with such a feedback loop. This dual operating mode of the class-D amplifier (i.e., open-loop operating mode / closed-loop operating mode) advantageously allows the use of a smaller ADC and / or an ADC that consumes less power compared to other cases. By being able to switch between the closed-loop operating mode and the open-loop operating mode, the system as a whole enables optimization of the power consumption of the ADC while still maintaining a high-performance response. Additionally, being able to transition between the closed-loop operating mode and the open-loop operating mode in a controlled manner advantageously minimizes any output signal artifacts.

[0084] Figure 3 Illustrates an embodiment of how the amplifier illustrated in Figure 2 can transition between modes. A flowchart of an embodiment is shown.

[0085] If the signal peak level decreases 301a, the envelope detector value ENV can decrease 302a according to the decay time constant and possibly the hold time of the envelope detector. To avoid often unnecessary mode changes, the envelope detector 214 can apply the hold time before decreasing the envelope value in response to a decrease in the peak signal level, and can apply a relatively slow decay constant. If the signal peak level increases 301b, the envelope detector value ENV can increase 302b according to the attack time constant. If the envelope detector block 214 employs a relatively short attack time, this will ensure that a fast spike in the digital input signal Din will result in a fast response of the envelope detection circuit 214, and thus a fast response can be made to transition to the closed-loop operation mode, and ensure that a feedback loop is implemented to reduce any error caused by a higher signal in the output driver stage. In contrast, a long decay time will avoid unnecessary switching of the operation mode, as it is likely that a high-amplitude signal peak will be followed quickly by another high-amplitude signal. In some embodiments, pre-emphasis filtering can also be used to increase and accelerate the rising edge of the signal.

[0086] The signal selection controller 212 monitors a signal 303 indicative of the amplitude of the input signal, e.g., the envelope value. The controller 212 can compare the signal ENV with at least one predetermined threshold, for example, to automatically determine whether to enter the open-loop mode (second mode) or the closed-loop mode (first mode). There can be a single amplitude threshold, or there can be different amplitude thresholds: one threshold for changing from the first mode to the second mode; and another different threshold for changing from the second mode to the first mode, in order to apply hysteresis to the mode change.

[0087] If the amplitude of the signal does not change relative to the relevant predetermined threshold, the operation mode does not change, and the signal selection controller continues to monitor the signal ENV 303.

[0088] If the indication signal ENV drops below a relevant predetermined threshold, the signal selection controller 212 will decide to enter the open-loop mode (i.e., the second mode), as in step 304. In this embodiment, the gain applied by the variable gain element (such as the multiplier 213) in the first signal path is ramped down from the first gain setting to zero in step 305. A predetermined gain ramp will be applied over a relatively short time period, but a sufficient time period such that it does not cause significant transients in the output signal. Once the gain has reached zero, the ADC 207 and / or the loop filter 211 can be disabled in step 306. Disabling the ADC and / or the loop filter when not needed helps save power and improve the efficiency of the amplifier circuit. In step 307, the selector module 210 can also be placed in the through mode so as to use only the input signal from the second signal path. By allowing the gain ramp applied by the variable gain element 212 to go to zero before disabling the ADC or placing the selector module in the through mode, any total transients are reduced and thus the output signal artifacts that would be caused only by suddenly disabling the ADC or switching (i.e., step-changing) the selector module to the through mode are reduced. It should be noted that both step 306 and step 307 are optional and one or both steps may not be used in some embodiments. Additionally, the order of step 306 and step 307 can be reversed. Further, in some embodiments, the step 306 of disabling a component (such as the loop filter) is only implemented if the signal amplitude remains low over a certain time period and / or if the signal amplitude drops below another lower threshold. It may take time and / or power to re-enable the loop filter and thus it can only be disabled, for example, when it may be disabled for more than a very short time.

[0089] Returning to reference step 303, if the indication signal ENV exceeds a relevant predetermined threshold, the signal selection controller 212 will decide to enter the closed-loop mode (first mode), as in step 308. In this embodiment, the ADC 207 and / or the loop filter 211 are first enabled in step 309. This may involve waiting for a short time period to allow the ADC / loop filter to stabilize. Since the amplifier circuit is still in the open-loop mode at this stage, the gain applied by the variable gain element (e.g., multiplier 213) will already have been set to zero, although if the loop filter 211 is a variable gain element and has been disabled, it should be re-enabled with zero gain. If the filter 211 has been running, it may have a non-zero output that could be incorrect, and thus the output of the loop filter 211 can be reset to zero. In step 311, the selector module is placed in the combiner state, in which it combines the signals from the first signal path and the second signal path. However, since the gain applied to the first signal path is still zero, there is no contribution from the first signal path at this stage, and thus no transients. In step 312, the gain applied by the variable gain element (e.g., multiplier 213) is then ramped up to the nominal first gain setting of the first signal path, with the ramp applied over a suitable time frame to avoid any significant transients. Similar to what was described above, this control by the signal selection controller 212 helps to reduce any overall transients in the signal and thus helps to reduce artifacts in the signal that would otherwise be audible.

[0090] To further reduce any transients that occur on the transition between modes, the signal selector controller 212 can be configured to initiate the transition between modes only when the instantaneous value of the input signal is at or below a low amplitude level or threshold (e.g., at or near zero). The amplifier circuit can include a low-level detector, such as a zero-crossing detector, to detect the low instantaneous signal amplitude, and the signal selector controller can wait for a zero-crossing to initiate the transition between modes.

[0091] In the open-loop mode, the amplifier gain from Din to Vout is defined by the gains of the digital modulator and the output driver and any other elements included in the signal path from Din to Vout. In the closed-loop mode, the gain from Din to Vout is defined by the reciprocal of the conversion gain of the ADC and a similar allowance scaled by any gain in the signal paths from Vout and Din to the subtractor 208, and is independent of the value of the gain of the variable gain element in the loop filter path if the open-loop loop gain is high enough. These open-loop amplifier gains and closed-loop amplifier gains can be designed, calibrated, or continuously adjusted to be nominally equal in use. However, any signal artifacts caused by the mismatch of the amplifier gain from Din to Vout between the first mode and the second mode will also be reduced by a gradually controlled transition or ramp of the variable gain.

[0092] As mentioned above, embodiments of the present invention can be implemented with an ADC that consumes less space and / or power compared to the ADCs used in conventional amplifier circuits without a corresponding reduction in the amplifier noise performance.

[0093] Figure 4 An example of an ADC 207 according to an embodiment of the present invention is illustrated. In this example, the ADC 207 includes a voltage-to-current conversion block 401 and a current-controlled oscillator 402. The number of pulses of the output of the current-controlled oscillator 402 is counted by a counter 403. The counter output is output as an ADC output signal via a calibration block 404. Compared with a voltage control circuit, the transfer function of this current control circuit is less affected by process and temperature.

[0094] As Figure 5 shown, the current-controlled oscillator 402 can be implemented by a simple ring oscillator of CMOS inverters, as will be appreciated by those skilled in the art.

[0095] The conversion gain of the current-controlled oscillator 402 is process-related and can be adjusted by calibration at startup under the control of a calibration engine 405. This will generate a total gain correction factor p that can be applied by the calibration block 404 and / or a polynomial correction by a coefficient q i of.

[0096] The noise characteristics of the ADC 207 can thus dominate the total amplifier noise performance in the closed-loop mode, but since the closed-loop mode is only used at high signal amplitudes, the background noise is not so significant. For low signal levels, the open-loop mode is used, and the digital modulator performance thus defines the system performance in terms of noise.

[0097] The digital modulator 201 can be, for example, as Figure 6Illustrated is a simple digital ramp modulator. The modulator input signal Dm can be latched (i.e., temporarily stored) in a storage element such as a clock-controlled register 601 controlled by a clock signal CK. The output of the storage element 601 is compared with the output signal of a counter 603 by a digital comparator 602. The counter 603 is supplied with a relatively fast clock signal CKF and the clock signal CK also supplied to the register 601, and generates a digital ramp signal, as will be understood by those skilled in the art. The digital ramp signal output from the counter 603 will be a PWM-type signal having a cycle period defined by the relatively slow clock signal CK and a pulse timing resolution defined by the fast clock CKF. It will of course be appreciated that a closed-loop ramp modulator or a hysteretic self-oscillating modulator can be implemented if desired.

[0098] As mentioned above, the output stage can be any suitable class-D output stage. Figure 7 An embodiment of an output driver stage 202 that can be implemented in one embodiment of the present invention is illustrated. In this embodiment, the output driver stage 202 includes a pre-driver and a class-D three-level half-bridge. It should be appreciated that as an alternative, a two-level half-bridge or a two-level full-bridge or a three-level full-bridge can be implemented.

[0099] The advantage of using a three-level half-bridge is that for small signals, the output is grounded most of the time. Therefore, the availability of the ground signal can reduce EMI and switching power consumption, and can improve the power supply rejection of the output driver stage 202.

[0100] Figure 8 An embodiment of a loop filter 209 according to one embodiment of the present invention is illustrated. This is an embodiment of a digital integrator loop filter, where the integrator time constant can be changed by changing α. This effectively changes the gain applied by the loop filter to the error signal ε. It should be appreciated that a second-order loop filter can also be used.

[0101] Figure 9 An embodiment of a class-D amplifier circuit according to one embodiment of the present invention is illustrated. In this figure, components similar to those Figure 2 described are given the same reference numerals.

[0102] As can be seen, multiple signal conditioning blocks 901 can be implemented in multiple signal paths and at multiple different locations within the amplifier circuit. These signal conditioning blocks 901 can include multiple signal conditioning circuits and perform multiple signal conditioning functions, as will be readily appreciated and understood by those skilled in the art. A non-exhaustive list of examples of such signal conditioning blocks that can be used in a variety of configurations and combinations includes: filter blocks (high-pass / low-pass / band-pass, etc.); gain blocks; attenuation blocks; upsamplers; downsamplers; interpolators; word length reduction / increase blocks, etc. Additionally, in this implementation, the positions of the variable gain element 213 and the loop filter 211 have optionally been reversed.

[0103] Other intermediate operations may also be included. For example, if the speaker acts as the load receiving the analog output signal Vout, the class-D amplifier circuit can include a speaker voice coil excursion limiting function. The impedance of the coil can be extracted based on the voice coil current and voltage, and thereby the excursion of the voice coil can be estimated. Alternatively, the voice coil excursion can be predicted based on the input digital signal and a predetermined or calibrated electromechanical model of the voice coil. If the excursion of the voice coil indicates a risk of causing mechanical damage or overheating of the speaker, the digital input signal can be attenuated.

[0104] In addition to Figure 2 and Figure 3 the normal control mechanisms described above, there may be other conditions that are desirable for an open-loop operating mode. For example, these conditions can include fault conditions where the output appears unexpectedly overloaded or where the loop may appear to oscillate or lock due to a total EMI event. Thus, the envelope detector 214 can also receive, via the ADC, a signal from the digital modulator 201, the loop filter 211, or the output node indicating that there is some clipping or that another fault condition has occurred at a particular node.

[0105] Figure 10 Illustrates a class-D amplifier circuit according to an embodiment of the present invention. In this figure, components similar to those described with reference to Figure 2 are given the same reference numerals.

[0106] In this implementation, the error block 205 includes a digital-to-analog converter (DAC) 1001 that receives the digital input signal and outputs an analog signal representative of the digital input signal, which is input to an analog subtractor 1002 together with the output signal Vout. The ADC 207 has been relocated to receive the signal from the output of the analog subtractor 1002. This has the advantage that the requirements on the ADC can be even more relaxed compared to the embodiment described with reference to Figure 2 since the ADC now only has to receive the analog error signal, which may be a relatively small signal.

[0107] Figure 11 Illustrates a class D amplifier circuit according to an embodiment of the present invention. In this figure, components similar to those described with reference Figure 2 are given the same reference numerals.

[0108] In this embodiment, the input signal is an analog input signal Ain.

[0109] The analog input signal Ain may be supplied to a main signal path 1101, which outputs a digital input signal Din representing the analog input signal Ain. This digital input signal is supplied as a digital input signal to a signal selector block 203.

[0110] In this embodiment, the error block 205 receives the analog input signal Ain instead of the digital input signal Din. Ain and the analog output signal Vout are input together to an analog subtractor 1002.

[0111] Similar to the embodiment described with reference Figure 10 the ADC 206 has been relocated to receive the error signal from the output of the analog subtractor 1002.

[0112] The envelope detector 114 may be an analog envelope detector, which receives the analog input signal Ain or it may receive the digital form Din generated by the ADC 1101.

[0113] Figure 12 Illustrates a class D amplifier according to an embodiment of the present invention. In this figure, components similar to those described with reference Figure 2 are given the same reference numerals.

[0114] In this embodiment, the error block only includes the analog subtractor 1002, and receives the analog input signal Ain and the analog output signal Vout. The error signal thus generated is analog, and the signal selector block 203 receives the analog input signal and the analog error signal. The ADC 1201 is then positioned to receive the output of the signal selector block, which, in addition to implementing analog components, functions similar to that described with reference Figure 2 and outputs a digital signal for input to the digital modulator 201.

[0115] As mentioned above, the class D amplifier circuit according to an embodiment of the present invention is particularly suitable for portable devices such as mobile phones or laptop computers, notebook computers or tablet computing devices, etc.

[0116] Figure 13Apparatus 1300 is illustrated that includes a class D amplifier circuit according to one embodiment of the present invention. The apparatus may have wireless communication capabilities and may receive transmissions via, for example, antenna 1301. The apparatus has at least one speaker 1302. It should be appreciated that there may be more than one antenna and more than one speaker. Audio hub 1303 receives audio signals from a number of possible sources. For example, audio hub 1303 (i.e., an audio codec) may receive signals from modem 1304, which may encode received signals from the antenna into a digital format. Audio hub 1303 may transfer such received audio signals to a class D amplifier 1305 according to the present invention, which outputs an analog signal to be input to speaker 1302. Additionally or alternatively, audio data may be received at audio hub 1303 from audio data memory 1306. Additionally or alternatively, in some cases, the class D amplifier may be supplied with signal data, coefficient data, or software code stored in program / data memory 1307. This memory may be, for example, an EEPROM or a static RAM and stores data or code in a persistent or non-transitory form. The apparatus may include a power supply 1308 and a form of user interface 1309, which may be a keyboard, a touch screen, or an external controller. The apparatus may be a portable device, such as an mp3 player or a portable computer, or a portable communication device, such as a cellular phone or a tablet computer.

[0117] As used herein, the term block refers to a functional unit or functional module that may be implemented by one or more circuit components and which may, for example, include dedicated circuitry. A block may additionally or alternatively include, for example, one or more software modules running on a general-purpose processor or a suitably programmed FPGA array, etc. The components of a block need not be physically located in the same place, and some components of one block may be shared with some components of another block in some applications.

[0118] In the case of a signal selection block, it will be appreciated that the inputs to the signal selection block need not be defined terminals of the amplifier circuit, and the inputs to the relevant block may simply be any node along the relevant signal path leading to the components forming the block.

[0119] It should be noted that the embodiments mentioned above illustrate rather than limit the present invention, and those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may implement the functions of several units recited in the claims. Additionally, the term "gain" does not exclude "attenuation", and vice versa. Any reference signs or labels in the claims should not be construed as limiting their scope.

Claims

1. A class-D amplifier circuit for amplifying an input signal, the class-D amplifier circuit including a controller configured to control the class-D amplifier circuit to selectively transition between an open-loop operation mode and a closed-loop operation mode based on an indication of the amplitude of the input signal.

2. The class-D amplifier circuit according to claim 1, wherein the controller is configured to control the class-D amplifier circuit to be in the open-loop operation mode if an indication of the amplitude of a digital input signal is below a first amplitude threshold, and to control the class-D amplifier circuit to be in the closed-loop operation mode if the indication of the amplitude of the digital input signal is above the first amplitude threshold.

3. The class-D amplifier circuit according to claim 1, the class-D amplifier circuit including a forward signal path and a feedback path, the forward signal path being configured to receive the input signal, wherein the controller includes a signal selector for controlling the extent to which a signal in the feedback path contributes to the forward signal path.

4. The class D amplifier circuit according to claim 1, wherein the class D amplifier circuit comprises: A class-D output stage; and, a modulator for generating at least one control signal to control switching of the class-D output stage; wherein the controller includes a signal selector configured such that: in the closed-loop operation mode, the input of the modulator is based on a combination of the input signal and a feedback signal; and, in the open-loop operation mode, the input of the modulator is based on the input signal and has no component from the feedback signal.

5. The class-D amplifier circuit according to claim 4, the class-D amplifier circuit including an error block for generating an error signal based on the input signal and the feedback signal, wherein the signal selector is configured to select the error signal as the input of the modulator in the closed-loop operation mode.

6. The class-D amplifier circuit according to claim 5, wherein the error block includes an analog-to-digital converter coupled to receive the feedback signal, and wherein the signal selector is configured to enable the analog-to-digital converter in the closed-loop operation mode and to disable the analog-to-digital converter in the open-loop operation mode.

7. The class-D amplifier circuit according to claim 5, including at least one variable gain element for applying a variable gain to the feedback signal or the error signal, wherein a signal selection controller is configured to control the at least one variable gain element to provide a first non-zero gain setting in the closed-loop operation mode and a second zero gain setting in the open-loop operation mode.

8. The class-D amplifier circuit according to claim 7, wherein the controller is configured to control the at least one variable gain element to provide a controlled gain transition between a first gain setting and a second gain setting involving at least one intermediate gain setting.

9. The class-D amplifier circuit according to claim 7, wherein the at least one variable gain element includes a loop filter having a variable gain.

10. The class-D amplifier circuit according to claim 1, the class-D amplifier circuit further comprising an envelope detector for determining an envelope value of the input signal, wherein the controller is configured to use the envelope value as an indication of the amplitude of the digital input signal.

11. The class-D amplifier circuit according to claim 10, wherein the envelope detector is configured to apply a predetermined delay between any drop in the detected signal amplitude and a decrease in the envelope value.

12. The class-D amplifier circuit according to claim 1, the controller being configured to initiate any transition between the open-loop operation mode and the closed-loop operation mode at a zero-crossing point of the input signal.

13. The class-D amplifier circuit according to claim 12, the class-D amplifier circuit including a zero-crossing detector for detecting a zero-crossing point of the input signal.

14. An electronic device comprising the class-D amplifier circuit according to claim 1.

15. The electronic device according to claim 14, wherein the device is at least one of the following: a portable device; a battery-powered device; a computing device; a communication device; a gaming device; a mobile phone; a personal media player; a laptop computer, a tablet computer or a notebook computing device.

16. A class-D amplifier circuit, the class-D amplifier circuit including a controller configured to control an operation mode of the class-D amplifier circuit, the controller being configured to change between open-loop operation and closed-loop operation based on an indication of the amplitude of an input signal, so as to provide closed-loop operation at a relatively high signal amplitude and open-loop operation at a relatively low signal amplitude.

17. The class-D amplifier circuit according to claim 16, wherein the controller includes a signal selector configured to receive the input signal and a feedback signal, and the signal selector is configured to output a signal based on a combination of the input signal and the feedback signal during closed-loop operation, and to output a signal based on the input signal and not based on any component from the feedback signal during open-loop operation.

18. The class-D amplifier circuit according to claim 16, wherein the controller is configured to transition from closed-loop operation to open-loop operation if the indication of the amplitude of the input signal drops below a first amplitude threshold, and to transition from open-loop operation to closed-loop operation if the indication of the amplitude of the input signal rises above a second amplitude threshold.

19. A class-D amplifier circuit configured to controllably transition between an open-loop operation mode and a closed-loop operation mode in response to a characteristic of the amplitude of an input signal, so as to operate in the closed-loop operation mode at a first signal amplitude and in the open-loop operation mode at a second lower signal amplitude.

20. The Class D amplifier circuit according to claim 19 includes a signal selector configured to receive a first signal and selectively output the first signal to a modulator in a closed-loop operation mode and not output the first signal in an open-loop operation mode, the first signal having a signal component derived from a feedback signal.

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