Integrated circuit with buried power rail and method of manufacturing the integrated circuit

Abstract

An integrated circuit with a buried power rail and a method for manufacturing the integrated circuit are provided. The method includes: forming a first dielectric layer on an upper surface of a first semiconductor substrate; forming a plurality of power rail grooves in the upper surface of the first dielectric layer; forming a buried power rail in the plurality of power rail grooves; forming a second dielectric layer on the upper surface of the first dielectric layer and on the upper surface of the buried power rail; forming a third dielectric layer on a donor wafer; bonding the third dielectric layer to the second dielectric layer; and forming a plurality of active semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rail is encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rail is below the plurality of active semiconductor devices.

Description

[0001] This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 863,606, filed on June 19, 2019, and U.S. Non-Provisional Application No. 16 / 562,291, filed on September 5, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure generally relates to integrated circuits having buried power rails and methods of fabricating the same. Background Art

[0003] Power is supplied to the semiconductor chip through a power delivery network (PDN). The PDN includes a series of vias and conductors connected to the VDD / VSS terminals of the chip for delivering power to individual devices (p-type FETs (pFETs), n-type FETs (nFETs), inverters, NAND gates, NOR gates, flip-flops, and / or other logic circuits) in the active semiconductor devices.

[0004] In prior art semiconductor chips, the PDN is connected to individual active semiconductor devices through a series of vias and interconnects in the back-end-of-line (BEOL) of the semiconductor chip above the active semiconductor devices. For example, in some prior art semiconductor chips, the PDN is connected to metal line 2 (M2) or metal line 1 (M1) in the BEOL. However, as chip scaling increases to have high device density, the size of active semiconductor devices and interconnects decreases, which causes congestion in the BEOL circuit interconnect design. This congestion in the BEOL circuit interconnect design can cause reliability issues such as electromigration (EM) and voltage (IR) drop. Summary of the invention

[0005] The present disclosure relates to various embodiments of a method of manufacturing an integrated circuit with a buried power rail. In one embodiment, the method includes: forming a first dielectric layer on an upper surface of a first semiconductor substrate; forming a plurality of power rail trenches in the upper surface of the first dielectric layer; forming a buried power rail in the plurality of power rail trenches; forming a second dielectric layer on the upper surface of the first dielectric layer and on the upper surface of the buried power rail; forming a third dielectric layer on a donor wafer; bonding the third dielectric layer to the second dielectric layer; forming a plurality of active semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rail is encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rail is below the plurality of active semiconductor devices.

[0006] The step of forming the first dielectric layer may include: thermally oxidizing the upper surface of the first semiconductor substrate.

[0007] The step of forming the first dielectric layer may include depositing a dielectric material layer on the upper surface of the first semiconductor substrate to form the first dielectric layer.

[0008] The step of forming the buried power rail may include: forming a liner in each of the power rail trenches; forming a conductive material on the liner in each of the power rail trenches; and performing chemical mechanical planarization.

[0009] The conductive material may have a thermal stability of at least about 700°C.

[0010] The method also includes annealing the second dielectric layer at a temperature of at least about 700°C.

[0011] The conductive material may be a refractory metal.

[0012] The refractory metal may be tungsten or ruthenium.

[0013] The first dielectric layer may be a thermal oxide layer having a thickness ranging from about 0.05 μm to about 9.8 μm, the second dielectric layer may be a deposited oxide layer having a thickness ranging from about 0.05 μm to about 0.1 μm, and the third dielectric layer may be a thermal oxide layer having a thickness ranging from about 0.05 μm to about 0.1 μm.

[0014] In one or more embodiments, a method of manufacturing an integrated circuit with a buried power rail includes the following steps: forming a first dielectric layer on an upper surface of a first semiconductor substrate; forming a conductive material layer on an upper surface of the first dielectric layer; etching the conductive material layer to form a buried power rail; forming a second dielectric layer on an upper surface of the first dielectric layer and around the buried power rail; forming a third dielectric layer on an upper surface of the second dielectric layer and on an upper surface of the buried power rail; forming a fourth dielectric layer on a donor wafer; bonding the fourth dielectric layer to the third dielectric layer; and forming a plurality of active semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rail is encapsulated by the first dielectric layer, the second dielectric layer, and the third dielectric layer, and the buried power rail is below the active semiconductor device.

[0015] The step of forming the first dielectric layer may include: thermally oxidizing the upper surface of the first semiconductor substrate.

[0016] The step of forming the first dielectric layer may include depositing a dielectric material layer on the upper surface of the first semiconductor substrate to form the first dielectric layer.

[0017] The method may further include forming a liner on each of the buried power rails; and performing chemical mechanical planarization to remove the liner along an upper surface of each of the buried power rails.

[0018] The buried power rail may have a thermal stability of at least about 700°C.

[0019] The method may further include annealing the third dielectric layer at a temperature of at least about 700°C.

[0020] The layer of conductive material may be or may include a refractory metal.

[0021] The refractory metal may be tungsten or ruthenium.

[0022] The second dielectric layer may be a thermal oxide layer having a thickness ranging from about 0.05 μm to about 9.8 μm, the third dielectric layer may be a deposited oxide layer having a thickness ranging from about 0.05 μm to about 0.1 μm, and the fourth dielectric layer may be a thermal oxide layer having a thickness ranging from about 0.05 μm to about 0.1 μm.

[0023] The donor wafer may include silicon (Si), silicon germanium (SiGe), Ge, III-V materials, or combinations thereof.

[0024] The donor wafer may have a thickness ranging from about 30 nm to about 10 μm.

[0025] The present disclosure also relates to various embodiments of an integrated circuit. In one embodiment, the integrated circuit includes: a first semiconductor substrate; a first dielectric layer on the first semiconductor substrate; a buried power rail embedded in the first dielectric layer; a second dielectric layer on the first dielectric layer and the buried power rail; and a plurality of active semiconductor devices, vias, and metal interconnects on the second dielectric layer.

[0026] The present summary is provided to introduce a selection of concepts that are further described below in the detailed description. The present summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features can be combined with one or more other described features to provide a processable device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The features and advantages of the embodiments of the present disclosure will be better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings. In the accompanying drawings, like reference numerals are used throughout the drawings to indicate like features and components. The drawings are not necessarily drawn to scale.

[0028] Figure 1 is a side view of an integrated circuit including a buried power rail according to one embodiment of the present disclosure;

[0029] Figure 2 is a flow chart illustrating the tasks of a method of manufacturing an integrated circuit with buried power rails according to one embodiment of the present disclosure;

[0030] FIG. 3A to FIG. 3E Describes the basis Figure 2 The task of manufacturing an integrated circuit having a buried power rail in an embodiment of the present invention;

[0031] Figure 4 is a flow chart illustrating the tasks of a method of manufacturing an integrated circuit with buried power rails according to another embodiment of the present disclosure; and

[0032] FIG. 5A to FIG. 5E Describes the basis Figure 4 The embodiment of the present invention is a task of manufacturing an integrated circuit with a buried power rail. DETAILED DESCRIPTION

[0033] The present disclosure relates to various embodiments of integrated circuits with buried power rails and various methods of manufacturing integrated circuits with buried power rails. The buried power rails of the integrated circuits according to various embodiments of the present disclosure can be configured to free up wiring space above active semiconductor devices (e.g., one or more p-type FETs (pFETs), n-type FETs (nFETs), inverters, NAND gates, NOR gates, flip-flops, and / or other logic circuits) in the integrated circuit and reduce the cell height of the integrated circuit compared to prior art integrated circuits in which the power rails are above the active semiconductor devices. Freeing up wiring space above the active semiconductor devices enables the metal pitch of the metal interconnects above the active semiconductor devices to be relaxed, which can reduce electromigration (EM) and voltage (IR) drops that may otherwise occur in prior art integrated circuits due to scaling of the integrated circuits.

[0034] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always indicate the same elements. However, the present invention may be implemented in various forms, and the present invention should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person with ordinary skill in the art to fully understand the aspects and features of the present invention may not be described. Unless otherwise specified, the same reference numerals represent the same elements throughout the drawings and written descriptions, and therefore, their descriptions may not be repeated.

[0035] In the accompanying drawings, for the sake of clarity, the relative sizes of elements, layers and regions can be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "under ... ", "under ... ", "under ... ", "above ... ", "on ", etc. can be used to describe the relationship between an element or feature and another (other) element or feature as shown in the drawings. It will be understood that the spatial relative terms are intended to include different orientations of the device in use or operation except for the orientation depicted in the drawings. For example, if the device in the drawings is turned over, the element described as "under" or "under" or "below" other elements or features will then be positioned as "above" the other elements or features. Therefore, the example terms "under ... " and "under ... " can include both above and below. The device can be positioned in addition (for example, rotated 90 degrees or at other orientations) and the spatial relative descriptors used here should be interpreted accordingly.

[0036] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present invention, the first element, first component, first region, first layer or first part discussed below may be referred to as the second element, second component, second region, second layer or second part.

[0037] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0038] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limitations of the present invention. As used herein, unless the context clearly indicates otherwise, the singular form "one (kind / person)" is also intended to include plural forms. It will also be understood that when the terms "comprising" and its variations, "including" and its variations are used in this specification, the features, integral bodies, steps, operations, elements and / or components stated are explained, but one or more other features, integral bodies, steps, operations, elements, components and / or their groups are not excluded from existence or addition. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Expressions such as "at least one of ..." modify the elements of the entire column when after a column of elements and do not modify the individual elements in the column.

[0039] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent variation in measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the present invention, the use of "may" refers to one or more embodiments of the present invention. As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively. In addition, the term "exemplary" is intended to indicate an example or illustration.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0041] Now refer to Figure 1 An integrated circuit 100 according to an embodiment of the present disclosure may include a first semiconductor substrate 101, a first dielectric layer 102 located on the first semiconductor substrate 101, a series of buried power rails 103 in power rail trenches 104 extending downward from an upper surface 105 of the first dielectric layer 102 toward the first semiconductor substrate 101, a second dielectric layer 106 located on the first dielectric layer 102 and the buried power rails 103, a series of active semiconductor devices 107 (e.g., one or more p-type FETs (pFETs), n-type FETs (nFETs), inverters, NAND gates, NOR gates, flip-flops, and / or other logic circuits) in a front-end-of-line (FEOL) of the integrated circuit 100, and a series of vias 108 and metal interconnects 109 in a back-end-of-line (BEOL).

[0042] Additionally, in the illustrated embodiment, the integrated circuit 100 may include a liner 110 separating a buried power rail 103 from the first dielectric layer 102 in the power rail trench 104. Metal interconnects 109 and vias 108 interconnect and connect the active semiconductor devices 107 to the buried power rail 103. In the illustrated embodiment, the buried power rail 103 may be completely surrounded or encapsulated by a dielectric material (e.g., the buried power rail 103 may be completely surrounded or encapsulated by the first dielectric layer 102 and the second dielectric layer 106).

[0043] In one or more embodiments, the first semiconductor substrate 101 may be a bare semiconductor wafer such as a bare silicon (Si) wafer. In one or more embodiments, the first dielectric layer 102 may have a thickness ranging from about 0.1 μm to about 10 μm. In one or more embodiments, one or more vias 108 (e.g., vias 108 connecting one of the metal interconnects 109 to one of the buried power rails 103) may include a metal such as, for example, ruthenium (Ru), tungsten (W), copper (Cu), cobalt (Co), or any other suitable metal.

[0044] The buried power rail 103 may be configured to receive power from a power delivery network (PDN) and supply the power received from the PDN to the active semiconductor device 107. In one or more embodiments, the PDN may include a series of vias and conductors connected to the VDD / VSS terminals of a semiconductor chip in which the integrated circuit 100 is included. In addition, in the illustrated embodiment, the buried power rail 103 may be disposed below the active semiconductor device 107, which frees up wiring space above the active semiconductor device 107 in the integrated circuit 100 (i.e., frees up wiring space in metal layers (M0, M1, M2, etc.) in the BEOL of the integrated circuit 100) and reduces the cell height of the integrated circuit 100 compared to prior art integrated circuits in which the power rail is disposed above the active semiconductor device. Freeing up wiring space above the active semiconductor device 107 may enable the metal pitch of the metal interconnect 109 above the active semiconductor device 107 to be relaxed, which may mitigate electromigration (EM) and voltage (IR) drops that may otherwise occur in prior art integrated circuits due to scaling of the integrated circuit.

[0045] In one or more embodiments, the buried power rail 103 may include any suitable metal, such as, for example, a refractory metal, such as tungsten (W) or ruthenium (Ru). In one or more embodiments, the buried power rail 103 may have a thermal stability greater than about 700° C., such as, for example, greater than about 800° C. or greater than about 900° C.

[0046] Now refer to Figure 2and Figure 3A A method 200 of fabricating an integrated circuit 300 with a buried power rail according to one embodiment of the present disclosure may include a task 205 of preparing, obtaining, or manufacturing a first semiconductor substrate 301 (eg, a bare semiconductor wafer such as a bare silicon (Si) wafer).

[0047] In the illustrated embodiment, the method 200 may also include a task 210 of forming a first dielectric layer 302 on the upper surface 303 of the first semiconductor substrate 301. In one or more embodiments, the first dielectric layer 302 may be an oxide or any other suitable dielectric material. In one or more embodiments, the task 210 of forming the first dielectric layer 302 may include depositing a layer of dielectric material on the upper surface 303 of the bare first semiconductor substrate 301 or thermally oxidizing a portion of the upper surface 303 of the first semiconductor substrate 301 to form the first dielectric layer 302. In one or more embodiments, the first dielectric layer 302 may have a thickness ranging from about 0.1 μm to about 10 μm.

[0048] In the illustrated embodiment, method 200 may also include task 215 of forming a power rail trench or recess 304 extending downwardly toward first semiconductor substrate 301 in upper surface 305 of first dielectric layer 302. In the illustrated embodiment, method 200 may also include task 220 of forming a buried power rail 306 in power rail trench 304. In one or more embodiments, the task 220 of forming the buried power rail 306 can include the task of forming a liner 307 in each of the power rail trenches 304, the task of forming a conductive material 308 in each of the power rail trenches 304 and on the liner 307 in each of the power rail trenches 304 (e.g., after the task of forming the liner 307 in the power rail trenches 304, filling or substantially filling the remaining portion of the power rail trench 304 with the conductive material 308), and the task of performing a chemical mechanical planarization (CMP) process to polish the upper surface 305 of the first dielectric layer 302 and the upper surface 309 of the buried power rail 306 (e.g., the liner 307 and the conductive material 308) formed in each of the power rail trenches 304.

[0049] In one or more embodiments, the liner 307 can be a thin seed material configured to promote the formation of the conductive material 308. In one or more embodiments, the liner 307 can be titanium nitride (TiN). In one or more embodiments, the task 220 of forming the buried power rail 306 in the power rail trench 304 in the first dielectric layer 302 can be performing one or more embedding processes. In one or more embodiments, the conductive material 308 formed in the task 220 can be any suitable metal such as, for example, a refractory metal such as tungsten (W) and ruthenium (Ru). In one or more embodiments, the conductive material 308 formed in the power rail trench 304 can have a thermal stability greater than about 700° C. such as, for example, greater than about 800° C. or greater than about 900° C.

[0050] In the illustrated embodiment, the method 200 may also include the task 225 of forming a second dielectric layer 310 on the upper surface 305 of the first dielectric layer 302 and on the upper surface 309 of the buried power rail 306 (e.g., the liner 307 and the conductive material 308) in the power rail trench 304, respectively. After the task 225 of forming the second dielectric layer 310, the buried power rail 306 (e.g., the liner 307 and the conductive material 308 in each of the power rail trenches 304) may be completely surrounded or encapsulated by the dielectric material (e.g., the buried power rail 306 may be completely surrounded or encapsulated by the first dielectric layer 302 and the second dielectric layer 310). In one or more embodiments, the second dielectric layer 310 may include an oxide or any other suitable dielectric material. In one or more embodiments, the task 225 of forming the second dielectric layer 310 may include depositing a dielectric material layer on the upper surface 305 of the first dielectric layer 302 and the upper surface 309 of the buried power rail 306, respectively, or thermally oxidizing a portion of the upper surface 305 of the first dielectric layer 302 and a portion of the upper surface 309 of the buried power rail 306, respectively, to form the second dielectric layer 310. In one or more embodiments, the second dielectric layer 310 may have a thickness ranging from about 0.1 μm to about 10 μm. Additionally, in one or more embodiments, the task 225 of forming the second dielectric layer 310 may include performing a CMP process to polish the upper surface 311 of the second dielectric layer 310 and performing a high temperature anneal of the second dielectric layer 310. In one or more embodiments, the high temperature anneal of the second dielectric layer 310 may include annealing the second dielectric layer 310 at a temperature of about 700° C. or greater, such as greater than about 800° C. or greater than about 900° C.

[0051] Now refer to Figure 2 and Figure 3B, method 200 may also include task 230 of preparing, obtaining, or manufacturing donor wafer 312 (e.g., a bare semiconductor wafer such as a bare silicon (Si) wafer). In one or more embodiments, donor wafer 312 may include Si and / or silicon germanium (SiGe), Ge, III-V materials, or similar materials. In one or more embodiments, donor wafer 312 may have a thickness ranging from about 30 nm (0.03 μm) to about 10 μm.

[0052] In the illustrated embodiment, the method 200 may also include a task 235 of forming a third dielectric layer 313 on the upper surface 314 of the donor wafer 312. In one or more embodiments, the third dielectric layer 313 may be an oxide or any other suitable dielectric material. In one or more embodiments, the task 235 of forming the third dielectric layer 313 may include depositing a layer of dielectric material or thermally oxidizing the upper surface 314 of the donor wafer 312 to form the third dielectric layer 313 on the upper surface 314 of the donor wafer 312 (for example, the third dielectric layer 313 may be a deposited oxide or a thermal oxide). In one or more embodiments, the third dielectric layer 313 may have a thickness ranging from about 0.1 μm to about 10 μm.

[0053] In one or more embodiments, the first dielectric layer 302, the second dielectric layer 310, and the third dielectric layer 313 may be formed by the same process, may have the same or substantially the same thickness, and / or may include the same material. In one or more embodiments, the first dielectric layer 302, the second dielectric layer 310, and the third dielectric layer 313 may be formed by two or more different processes, may have two or more different thicknesses, and / or may include two or more different materials. For example, in one or more embodiments, the first dielectric layer 302 may be a thermal oxide having a thickness in a range from about 0.05 μm to about 9.8 μm, the second dielectric layer 310 may be a deposited oxide having a thickness in a range from about 0.05 μm to about 0.1 μm, and the third dielectric layer 313 may be a thermal oxide having a thickness in a range from about 0.05 μm to about 0.1 μm.

[0054] Now refer to Figure 2 and Figure 3C , method 200 may also include task 240 of bonding a third dielectric layer 313 on donor wafer 312 to a second dielectric layer 310 on upper surface 305 of first dielectric layer 302 and on upper surface 309 of buried power rail 306 (e.g., liner 307 and conductive material 308) in power rail trench 304 in first dielectric layer 302.

[0055] Now refer to Figure 2 and Figure 3D , the method 200 may also include a task 245 of singulating the donor wafer 312. In one or more embodiments, the task 245 of singulating the donor wafer 312 may include polishing the donor wafer 312 to reduce the thickness of the donor wafer 312 to a desired thickness. In one or more embodiments, the donor wafer 312 may be pre-processed with a smart cut 315 that is configured to enable de-bonding or separation of the donor wafer 312 along the smart cut 315, and the task 245 of singulating the donor wafer 312 may include de-bonding the donor wafer 312 by activating the smart cut 315 in the donor wafer 312 to achieve the desired thickness of the donor wafer 312. The smart cut 315 may be formed by any suitable manufacturing technique or process now known in the art or hereinafter developed. Smart cutting is described in M. Bruel et al., "Smart cut: a promising new SOI material technology" (Proceedings of the 1995 IEEE International SOI Conference, Tucson, Arizona, USA, 1995, pages 178-179), the entire content of which is incorporated herein by reference. In addition, in one or more embodiments in which the task 245 of singulating the donor wafer 312 can be performed by activating the smart cut 315 in the donor wafer 312, the donor wafer 312 can be implanted with hydrogen (H+) before the task of activating the smart cut 315.

[0056] Furthermore, in one or more embodiments in which the task 245 of singulating the donor wafer 312 may be performed by activating the smart cut 315 in the donor wafer 312 , the donor wafer 312 may be annealed and polished after the task of activating the smart cut 315 in the donor wafer 312 .

[0057] Now refer to Figure 2 and Figure 3EThe method 200 may include forming active semiconductor devices 316 (e.g., one or more p-type FETs (pFETs), n-type FETs (nFETs), inverters, NAND gates, NOR gates, flip-flops, and / or other logic circuits) in the front end of line (FEOL) in or on the donor wafer 312 and one or more tasks 250 of interconnecting the active semiconductor devices 316 and connecting the active semiconductor devices 316 to the buried power rails 306 vias 317 and metal interconnects 318 to complete the formation of the integrated circuit 300. In the illustrated embodiment, at least one of the vias 317 may extend from one of the metal interconnects 318 to one of the active semiconductor devices 316, and at least one of the vias 317 extends from one of the buried power rails 306 (e.g., the liner 307 and the conductive material 308 formed in one of the power rail trenches 304 in the first dielectric layer 302) to one of the metal interconnects 318 so that power may be supplied from the buried power rail 306 (the buried power rail 306 receives power from a power delivery network (PDN) connected to the VDD / VSS terminals of a chip in which the integrated circuit 300 is included) to the active semiconductor device 316. In one or more embodiments, the vias 317 (e.g., the vias 317 connected to one of the buried power rails 306) may include a metal such as, for example, ruthenium (Ru), tungsten (W), copper (Cu), cobalt (Co), or any other suitable metal.

[0058] Additionally, in the illustrated embodiment, the buried power rail 306 may be disposed below the active semiconductor device 316, which frees up routing space in the integrated circuit 300 above the active semiconductor device 316 (i.e., frees up routing space in the metal layers (M0, M1, M2, etc.) in the back end of line BEOL of the integrated circuit 300) and reduces the cell height of the integrated circuit 300 compared to prior art integrated circuits in which the power rail is disposed above the active semiconductor device. Freeing up routing space above the active semiconductor device 316 enables the metal pitch of the metal interconnect 318 above the active semiconductor device 316 to be relaxed, which may reduce electromigration (EM) and voltage (IR) drops that may otherwise occur in prior art integrated circuits due to scaling of the integrated circuit.

[0059] Now refer to Figure 4 and Figure 5A A method 400 of fabricating an integrated circuit 500 having a buried power rail according to one embodiment of the present disclosure may include a task 405 of preparing, obtaining, or fabricating a first semiconductor substrate 501 (eg, a bare semiconductor wafer such as a bare silicon (Si) wafer).

[0060] In the illustrated embodiment, method 400 may further include a task 410 of forming a first dielectric layer 502 on the upper surface 503 of the first semiconductor substrate 501. In one or more embodiments, the first dielectric layer 502 may be an oxide or any other suitable dielectric material. In one or more embodiments, task 410 of forming the first dielectric layer 502 may include depositing a dielectric material layer on the upper surface 503 of the first semiconductor substrate 501 to form the first dielectric layer 502, or thermally oxidizing the upper surface 503 of the first semiconductor substrate 501 to form the first dielectric layer 502. In one or more embodiments, the first dielectric layer 502 may have a thickness ranging from about 0.1 μm to about 10 μm.

[0061] In the illustrated embodiment, method 400 may also include task 415 of forming (e.g., depositing) a conductive material layer 504 on the upper surface 505 of the first dielectric layer 502. The conductive material of the conductive material layer 504 formed in task 415 may be any suitable metal, such as, for example, a refractory metal such as tungsten (W) or ruthenium (Ru). In one or more embodiments, the conductive material of the conductive material layer 504 formed in task 415 may have a thermal stability greater than about 700° C., such as, for example, greater than about 800° C. or greater than about 900° C.

[0062] In the illustrated embodiment, method 400 can also include task 420 of etching conductive material layer 504 to form power rails 506 (e.g., remaining portions of conductive material layer 504 not removed by task 420 of etching conductive material layer 504 can form power rails 506). In one or more embodiments, task 420 of etching conductive material layer 504 can include photolithographic patterning of conductive material layer 504 to define the configuration of power rails 506 and subtractive etching (e.g., direct etching) conductive material layer 504 to form power rails 506. In the illustrated embodiment, method 400 can also include task 425 of forming (e.g., depositing) a thin barrier layer 507 around each of power rails 506.

[0063] In the illustrated embodiment, method 400 also includes a task 425 of forming (e.g., depositing) second dielectric layer 508 on upper surface 505 of first dielectric layer 502 and around each of power rails 506. In one or more embodiments, method 400 also includes a task 430 of performing chemical mechanical planarization (CMP) along upper surface 509 of second dielectric layer 508 and along upper surface 510 of each of power rails 506. In the illustrated embodiment, after task 430 of performing CMP, thin barrier layer 507 can be removed along upper surface 510 of power rails 506 so that upper surface 510 of power rails 506 can be exposed.

[0064] In the illustrated embodiment, method 400 can also include task 435 of forming (e.g., depositing) third dielectric layer 511 on upper surface 509 of second dielectric layer 508 and upper surface 510 of each of power rails 506. After task 435 of forming third dielectric layer 511, power rails 506 (e.g., portions of conductive material layer 504 that remain after task 420 of etching conductive material layer 504) can be completely surrounded or encapsulated by dielectric material (e.g., power rails 506 can be completely surrounded or encapsulated by first dielectric layer 502, second dielectric layer 508, and third dielectric layer 511). In one or more embodiments, third dielectric layer 511 can be an oxide or any other suitable dielectric material. In one or more embodiments, the task 435 of forming the third dielectric layer 511 may include depositing a dielectric material layer on the upper surface 509 of the second dielectric layer 508 and the upper surface 510 of the power rail 506, or thermally oxidizing the upper surface 509 of the second dielectric layer 508 and the upper surface 510 of the power rail 506. In one or more embodiments, the third dielectric layer 511 may have a thickness ranging from about 0.1 μm to about 10 μm. Additionally, in one or more embodiments, the task 435 of forming the third dielectric layer 511 may include performing CMP along the upper surface of the third dielectric layer 511 and performing a high temperature anneal of the third dielectric layer 511. In one or more embodiments, the high temperature anneal of the third dielectric layer 511 may include annealing the third dielectric layer 511 at a temperature of about 700° C. or greater, such as greater than about 800° C. or greater than about 900° C.

[0065] Now refer to Figure 4 and Figure 5B , method 400 may also include task 440 of obtaining or manufacturing a donor wafer 513 (e.g., a bare semiconductor wafer such as a bare silicon (Si) wafer). In one or more embodiments, donor wafer 513 may include Si and / or silicon germanium (SiGe), Ge, III-V materials, or similar materials. In one or more embodiments, donor wafer 513 may have a thickness ranging from about 30 nm (0.03 μm) to about 10 μm.

[0066] In the illustrated embodiment, the method 400 may also include a task 445 of forming (e.g., depositing) a fourth dielectric layer 514 on the upper surface 515 of the donor wafer 513. In one or more embodiments, the fourth dielectric layer 514 may be an oxide or any other suitable dielectric material. In one or more embodiments, the task 445 of forming the fourth dielectric layer 514 may include depositing a layer of dielectric material on the upper surface 515 of the donor wafer 513, or thermally oxidizing the upper surface 515 of the donor wafer 513 to form the fourth dielectric layer 514 (e.g., the fourth dielectric layer 514 may be a deposited oxide or a thermal oxide). In one or more embodiments, the fourth dielectric layer 514 may have a thickness in a range from about 0.1 μm to about 10 μm.

[0067] In one or more embodiments, the first dielectric layer 502, the second dielectric layer 508, the third dielectric layer 511, and the fourth dielectric layer 514 may be formed by the same process, may have the same or substantially the same thickness, and / or may be formed of the same material. In one or more embodiments, the first dielectric layer 502, the second dielectric layer 508, the third dielectric layer 511, and the fourth dielectric layer 514 may be formed by two or more different processes, may have two or more different thicknesses, and / or may be formed of two or more different materials. For example, in one or more embodiments, the second dielectric layer 508 may be a thermal oxide having a thickness in the range of from about 0.05 μm to about 9.8 μm, the third dielectric layer 511 may be a deposited oxide having a thickness in the range of from about 0.05 μm to about 0.1 μm, and the fourth dielectric layer 514 may be a thermal oxide having a thickness in the range of from about 0.05 μm to about 0.1 μm.

[0068] Now refer to Figure 4 and Figure 5C Method 400 may also include task 450 of bonding fourth dielectric layer 514 on donor wafer 513 to third dielectric layer 511 on upper surface 509 of second dielectric layer 508 and upper surface 510 of each of power rails 506 .

[0069] Now refer to Figure 4 and Figure 5D, the method 400 also includes a task 455 of singulating the donor wafer 513. In one or more embodiments, the task 455 of singulating the donor wafer 513 may include polishing the donor wafer 513 to reduce the thickness of the donor wafer 513 to a desired thickness. In one or more embodiments, the donor wafer 513 may be pre-processed with a smart cut 516 that is configured to enable the donor wafer 513 to be peeled or separated along the smart cut 516, and the task 455 of singulating the donor wafer 513 may include peeling the donor wafer 513 by activating the smart cut 516 in the donor wafer 513 to achieve the desired thickness of the donor wafer 513. Smart cut 516 may be formed by any suitable manufacturing technique or process now known in the art or hereinafter developed, such as may be formed by the technique or process described by M. Bruel et al. in Smartcut: a promising new SOI material technology (1995 IEEE International SOI Conference Proceedings, Tucson, Arizona, USA, 1995, pp. 178-179). Additionally, in one or more embodiments in which the task 455 of singulating the donor wafer 513 may be performed by activating the smart cut 516 in the donor wafer 513, the donor wafer 513 may be implanted with hydrogen (H+) prior to the task of activating the smart cut 516. Additionally, in one or more embodiments in which the task 455 of singulating the donor wafer 513 is performed by activating the smart cut 516 in the donor wafer 513, the donor wafer 513 may be annealed and polished after the task of activating the smart cut 516 in the donor wafer 513.

[0070] Now refer to Figure 4 and Figure 5EThe method 400 may include forming active semiconductor devices 517 (e.g., one or more p-type FETs (pFETs), n-type FETs (nFETs), inverters, NAND gates, NOR gates, flip-flops, and / or other logic circuits) in the front end of line (FEOL) in or on the donor wafer 513 and one or more tasks 460 of interconnecting the active semiconductor devices 517 and connecting the active semiconductor devices 517 to the buried power rails 506 vias 518 and metal interconnects 519 to complete the formation of the integrated circuit 500. In the illustrated embodiment, at least one of vias 518 extends from one of metal interconnects 519 to one of active semiconductor devices 517, and at least one of vias 518 extends from one of buried power rails 506 (e.g., one of the portions of conductive material layer 504 that remain after task 420 of etching conductive material layer 504) to one of metal interconnects 519 so that power can be supplied from buried power rail 506 (buried power rail 506 receives power from a power delivery network (PDN) connected to VDD / VSS terminals of a chip in which integrated circuit 500 is included) to active semiconductor device 517. In one or more embodiments, via 518 (e.g., via 518 connected to one of buried power rails 506) can include a metal such as, for example, ruthenium (Ru), tungsten (W), copper (Cu), cobalt (Co), or any other suitable metal.

[0071] Additionally, in the illustrated embodiment, the buried power rail 506 may be disposed below the active semiconductor device 517, which frees up routing space in the integrated circuit 500 above the active semiconductor device 517 (i.e., frees up routing space in the metal layers (M0, M1, M2, etc.) in the back end of line BEOL of the integrated circuit 500) and reduces the cell height of the integrated circuit 500 compared to prior art integrated circuits in which the power rail is above the active semiconductor device. Freeing up routing space above the active semiconductor device 517 enables the metal pitch of the metal interconnect 519 above the active semiconductor device 517 to be relaxed, which may reduce electromigration (EM) and voltage (IR) drops that may otherwise occur in prior art integrated circuits due to scaling of the integrated circuit.

[0072] Although the present invention has been described in detail with specific reference to exemplary embodiments of the present invention, the exemplary embodiments described herein are not intended to be exhaustive or to limit the scope of the invention to the precise forms disclosed. It will be appreciated by those skilled in the art and technology to which the present invention pertains that substitutions and changes to the described structures, components, and methods of operation may be practiced without intentionally departing from the principles, spirit, and scope of the present invention as set forth in the claims.

Claims

1. A method of manufacturing an integrated circuit having a buried power rail, the method comprising the steps of: forming a first dielectric layer on an upper surface of the first semiconductor substrate; forming a plurality of power rail trenches in an upper surface of the first dielectric layer; forming buried power rails in the plurality of power rail trenches; forming a second dielectric layer on an upper surface of the first dielectric layer and an upper surface of the buried power rail; forming a third dielectric layer on the donor wafer; bonding the third dielectric layer to the second dielectric layer after the step of forming the third dielectric layer on the donor wafer; as well as forming a plurality of active semiconductor devices, vias and metal interconnects on or in a donor wafer, wherein the buried power rail is encapsulated by a first dielectric layer and a second dielectric layer, and Wherein, a buried power rail is below the plurality of active semiconductor devices.

2. The method according to claim 1, wherein: The step of forming the first dielectric layer includes: depositing the first dielectric layer on the upper surface of the first semiconductor substrate.

3. The method according to claim 1, wherein: The steps to form a buried power rail include: depositing a liner in each of the plurality of power rail trenches; depositing a conductive material on the liner in each of the plurality of power rail trenches; and Perform chemical mechanical planarization.

4. The method according to claim 3, wherein: The conductive material is a refractory metal.

5. The method according to claim 4, wherein: The refractory metal is tungsten or ruthenium.

6. The method according to claim 1, further comprising: depositing a liner over each of the buried power rails; as well as Chemical mechanical planarization is performed to remove the liner along an upper surface of each of the buried power rails.

7. A method of manufacturing an integrated circuit having a buried power rail, the method comprising the steps of: forming a first dielectric layer on an upper surface of the first semiconductor substrate; forming a plurality of power rail trenches in an upper surface of the first dielectric layer; forming buried power rails in the plurality of power rail trenches; forming a second dielectric layer on an upper surface of the first dielectric layer and an upper surface of the buried power rail; forming a third dielectric layer on the donor wafer; bonding a third dielectric layer to the second dielectric layer; as well as forming a plurality of active semiconductor devices, vias and metal interconnects on or in a donor wafer, wherein the buried power rail is encapsulated by a first dielectric layer and a second dielectric layer, wherein a buried power rail is below the plurality of active semiconductor devices, The step of forming the first dielectric layer includes: thermally oxidizing the upper surface of the first semiconductor substrate.

8. A method of manufacturing an integrated circuit having a buried power rail, the method comprising the steps of: forming a first dielectric layer on an upper surface of the first semiconductor substrate; forming a plurality of power rail trenches in an upper surface of the first dielectric layer; forming buried power rails in the plurality of power rail trenches; forming a second dielectric layer on an upper surface of the first dielectric layer and an upper surface of the buried power rail; forming a third dielectric layer on the donor wafer; bonding a third dielectric layer to the second dielectric layer; as well as forming a plurality of active semiconductor devices, vias and metal interconnects on or in a donor wafer, wherein the buried power rail is encapsulated by a first dielectric layer and a second dielectric layer, wherein a buried power rail is below the plurality of active semiconductor devices, wherein the step of forming the buried power rail comprises: depositing a liner in each of the plurality of power rail trenches; depositing a conductive material on the liner in each of the plurality of power rail trenches; and performing chemical mechanical planarization, and Wherein, the conductive material has a thermal stability of at least 700°C.

9. The method according to claim 8, further comprising: The second dielectric layer is annealed at a temperature of at least 700°C.

10. A method of manufacturing an integrated circuit having a buried power rail, the method comprising the steps of: forming a first dielectric layer on an upper surface of the first semiconductor substrate; forming a plurality of power rail trenches in an upper surface of the first dielectric layer; forming buried power rails in the plurality of power rail trenches; forming a second dielectric layer on an upper surface of the first dielectric layer and an upper surface of the buried power rail; forming a third dielectric layer on the donor wafer; bonding a third dielectric layer to the second dielectric layer; as well as forming a plurality of active semiconductor devices, vias and metal interconnects on or in a donor wafer, in: The buried power rail is encapsulated by a first dielectric layer and a second dielectric layer, a buried power rail beneath the plurality of active semiconductor devices, The first dielectric layer is a thermal oxide layer having a thickness ranging from 0.05 μm to 9.8 μm, The second dielectric layer is a deposited oxide layer having a thickness ranging from 0.05 μm to 0.1 μm, and The third dielectric layer is a thermal oxide layer having a thickness ranging from 0.05 μm to 0.1 μm.

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