Integrating multi-device chips and packages

Abstract

The present invention, entitled "Integrated Multi-Device Chip and Package," discloses a protection device that may include a semiconductor substrate and a thyristor-type device formed within the semiconductor substrate, wherein the thyristor device extends from a first major surface of the semiconductor substrate to a second major surface of the semiconductor substrate. The protection device may include a first PN diode formed within the semiconductor substrate; and a second PN diode formed within the semiconductor substrate, wherein the thyristor-type device is electrically arranged in series between the first and second PN diodes.

Description

Background Art Technical Field

[0001] Embodiments relate to the field of surge protection devices, and more particularly to overvoltage protection devices and resettable fuses.

[0002] Discussions in related fields

[0003] Surge protection devices include overvoltage protection devices used to protect components, devices or systems from damage due to overvoltage fault conditions, and fuses used to protect components, devices or systems from overcurrent. In the field of overvoltage protection devices, diodes (such as Zener diodes), thyristors and It is known ( SIDACtor is a trademark of Littelfuse, Inc.

[0004] In some commercial implementations, a thyristor-type device (such as a SIDACTor) can be arranged in electrical series with a first diode and a second diode to provide protection for a transmission line, including a telecommunications line. As an example, the thyristor device can be formed in a first semiconductor chip, while the first diode and the second diode are formed in a second semiconductor chip and a third semiconductor chip, respectively. These different chips can be coupled together in a single package to provide a protection device that can be placed at a desired location within the circuit to be protected. One problem with such packaging is that the lead frame structure requires a certain complexity to electrically couple the different semiconductor chips to each other and to external electrical circuits, dissipate heat, and maintain the semiconductor chips within a compact package.

[0005] It is with respect to these and other considerations that the present disclosure is provided. Summary of the Invention

[0006] Example embodiments relate to improved protection devices. In one embodiment, the protection device may include a semiconductor substrate and a thyristor-type device formed within the semiconductor substrate, wherein the thyristor device extends from a first major surface of the semiconductor substrate to a second major surface of the semiconductor substrate. The protection device may include a first PN diode formed within the semiconductor substrate; and a second PN diode formed within the semiconductor substrate, wherein the thyristor-type device is electrically arranged in series between the first PN diode and the second PN diode.

[0007] In another embodiment, a protection device assembly may include a semiconductor substrate having a first major surface and a second major surface. The semiconductor substrate may include a thyristor-type device extending from the first major surface to the second major surface, a first PN diode extending from the second major surface; and a second PN diode, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode. The protection device assembly may also include a front surface metal layer disposed on the first major surface and a lead frame disposed in contact with the second major surface.

[0008] In another embodiment, a line protection device may include a semiconductor substrate having a first main surface and a second main surface. The semiconductor substrate may include a thyristor-type device extending from the first main surface to the second main surface, a first PN diode extending from the second main surface, and a second PN diode, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode. The semiconductor substrate may also include an electrical isolation barrier extending from the first main surface to the second main surface and disposed between the second PN diode and the thyristor-type device. The line protection device may include a front surface metal layer disposed on the first main surface and a lead frame disposed in contact with the second main surface, the lead frame including a plurality of leads arranged in electrical parallel with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A side cross-sectional view of a protective device 100 according to various embodiments of the present disclosure is presented;

[0010] Figure 1B Reference device components are depicted;

[0011] Figure 2A showing a plan view of a second major surface of a protective device according to an embodiment of the present disclosure;

[0012] Figure 2B The embodiment according to the present disclosure is shown Figure 2A a perspective view of a second major surface of the protective device;

[0013] Figure 2C The embodiment according to the present disclosure is shown Figure 2A a perspective view of a first major surface of a protective device;

[0014] Figure 3A shows a top perspective view of a protective device assembly according to an embodiment of the present disclosure;

[0015] Figure 3B The embodiment according to the present disclosure is shown Figure 3A A side sectional view of a protective device assembly;

[0016] Figure 4A shows a perspective view of a lead frame at one stage of assembly according to an embodiment of the present disclosure;

[0017] Figure 4B Shown in another stage of assembly Figure 4A A perspective view of a lead frame;

[0018] Figure 4C depicts a perspective view of a protective device assembly 250,

[0019] Figure 5A shows a top perspective view of a package according to an embodiment of the present disclosure;

[0020] Figure 5B The embodiment according to the present disclosure is shown Figure 5A a bottom perspective view of the package; and

[0021] Figure 5C According to an embodiment of the present disclosure, there is provided Figure 5A Equivalent circuit representation of the package. DETAILED DESCRIPTION

[0022] Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which an exemplary embodiment is shown. These embodiments should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey their scope to those skilled in the art. Throughout the drawings, like numbers refer to like elements.

[0023] In the following detailed description and / or claims, the terms "on," "overlying," "disposed on," and "over" may be used in the following detailed description and claims. "On," "overlying," "disposed on," and "over" may be used to indicate that two or more elements are in direct physical contact with each other. Additionally, the terms "on," "overlying," "disposed on," and "over" may represent that two or more elements are not in direct contact with each other. For example, "over" may represent that one element is above another element without contacting each other, and may have another element or elements between the two elements. Additionally, the term "and / or" may mean "and," it may mean "or," it may mean "exclusive or," it may mean "one," it may mean "some, but not all," it may mean "either," and / or it may mean "both," although the scope of the claimed subject matter is not limited in this respect.

[0024] In various embodiments, protection devices and components are proposed to protect electrical components, systems or electrical lines (such as communication lines). Various embodiments may include protection devices (including SIDACtors). As is well known, SIDACTor is related to silicon-controlled rectifiers (SCRs) or thyristor-type devices, wherein the SCR is composed of a layered structure having an N-type semiconductor region or layer and a P-type semiconductor layer or region arranged in a four-layer sequence such as PNPN. In the SCR, the gate is connected to the inner layer of the four-layer device, while the SIDACtor lacks such a gate. In various embodiments, the SIDACTor is provided in a single semiconductor die ("semiconductor chip") in a manner electrically connected in series with a pair of PN diodes. The integration of the SIDACTor and a pair of diodes in a single semiconductor chip facilitates a new and lower-cost packaging component to accommodate the semiconductor chip.

[0025] Figure 1A A side cross-sectional view of a protection device 100 according to various embodiments of the present disclosure is presented. The protection device 100 may be formed within a semiconductor substrate 102, such as single crystal silicon or a similar suitable semiconductor material. The protection device 100 may include a thyristor-type device 104. The thyristor-type device 104 may be formed as a four-layer device, as is generally known in the art. Figure 1A As shown, the thyristor-type device 104 may extend from the first main surface 103 to the second main surface 105 opposite the first main surface 103. In addition to the thyristor-type device 104, the protection device 100 may further include a first PN diode 106 formed in the semiconductor substrate 102 and a second PN diode 108 formed in the semiconductor substrate 102. The arrangement of the protection device 100 may be such that the thyristor-type device 104 is disposed electrically in series between the first PN diode 106 and the second PN diode 108.

[0026] like Figure 1A As shown, the protection device 100 may include an electrical isolation barrier 110 extending from the first major surface 103 to the second major surface 105 and disposed between the second PN diode 108 and the thyristor-type device 104. In various embodiments, the electrical isolation barrier 110 may be an electrical insulator formed according to known techniques. Figure 1A As shown, the first PN diode 106 may extend from the second main surface 105 and may form part of the thyristor-type device 104. Thus, the thyristor-type device 104 is arranged in electrical series between the first PN diode 106 and the second PN diode 108, wherein the direction of current flow in normal operation is shown by the curved arrows. Figure 1AAs shown, the protection device 100 may further include a front surface metal layer 130 electrically connected to and in contact with the thyristor device 104 and the second PN diode 108 , and a front surface oxide layer 132 disposed over a region between the thyristor device 104 and the second PN diode 108 .

[0027] In order to highlight the function of the protection device 100, Figure 1B 1 shows a reference assembly 150 in side view. In this arrangement, a series of three known semiconductor chips are assembled in a package including a three-dimensional leadframe 160. Reference assembly 150 includes a semiconductor device 154 (which may be a thyristor-type device), a first PN diode 156, and a second PN diode 158, each of which is contained in a separate semiconductor chip. Arrangement 150 may include a copper inlay 159 between semiconductor device 154 and first PN diode 156. This arrangement provides semiconductor chips with a relatively simpler structure to form corresponding devices, as is known in the art. Figure 1B The arrangement of the three semiconductor chips in the embodiment of the present invention can provide the same or similar functions to the protection device 100. It is worth noting that the reference assembly 150 requires a relatively complex lead frame in order to accommodate and couple the different semiconductor chips.

[0028] In some embodiments, the thyristor-type device 104 may include a first layer 112 extending from a first major surface and disposed within a second layer 114. The first layer 112 may be an N+ layer in some embodiments, while the layer 114 is a P-type layer. The substrate 102 may constitute an N- layer, while the layer 116 extends from the second major surface and is also a P-type layer.

[0029] In some embodiments, second PN diode 108 includes layer 118, which may be a P- layer, and layer 120, which is embedded in layer 118, such as a P+ layer. Second PN diode may further include layer 122, such as an N+ layer.

[0030] In certain embodiments, the second major surface 105 of the protective device 100 or a similar device can be subdivided into multiple areas to contact multiple different lines. Figure 2A 、 Figure 2B and Figure 2C , respectively showing a plan view of the second main surface, a perspective view of the second main surface, and a perspective view of the first main surface of the protection device 200 according to an embodiment of the present disclosure. In this example, the protection device 200 may be arranged with the above-mentioned general Figure 1A Layer 116 can be divided into a first plurality of P-type regions (shown as regions 204) and a second plurality of N-type regions (shown as regions 206). By providing an insulator region 208, regions 204 can be electrically isolated from each other on second major surface 105, while regions 206 can be electrically isolated from each other on second major surface 105.

[0031] According to various embodiments of the present disclosure, a protection device, such as protection device 100 or protection device 200, can be packaged in a simplified assembly, including a simplified lead frame. Since the functionality of two PN diodes and one thyristor is included in a single semiconductor die, a package including a multi-line protection device can be constructed using a lead frame having a generally planar configuration disposed along only one side of the semiconductor die. Figure 3A A top perspective view of a protective device assembly 250 according to an embodiment of the present disclosure is shown, and Figure 3B A side cross-sectional view thereof is shown. The protection device assembly 250 may include other components, including a housing (not shown). In addition to the semiconductor substrate 102 described above, the protection device assembly 250 may further include a lead frame 212 disposed in contact with the second major surface.

[0032] Figure 4A and Figure 4B 1 and 2 show perspective views of the lead frame 212 at various stages of assembly. Figure 4A In FIG, a lead frame 212 corresponding to a single die or chip is shown. Figure 4B , a bottom perspective view of the lead frame 212 is shown showing a semi-thick edge structure for locking the lead frame 212 to an encapsulation (such as epoxy molding compound).

[0033] Figure 4C A perspective view of the protective device assembly 250 is depicted when assembled into a package 270 (including a housing 272). As shown, the protective device assembly 250 (including the semiconductor substrate 102) welded to the lead frame 212 can be disposed within the package 270 having the general shape of a rectangular prism. The housing 272 can be formed from a molded part, such as an epoxy molding compound according to some embodiments. However, these embodiments are not limited in this context.

[0034] The lead frame 212 may be disposed toward one side of the housing 272, such as Figure 5A and Figure 5B More details are shown in . Figure 5A and Figure 5B , which respectively show top and bottom perspective views of package 270. As shown, leadframe 212 may be partially exposed on the bottom surface of package 270. Although shown as a singulated structure, according to various embodiments, package 270 may be assembled from a leadframe structure of multiple dies, wherein multiple semiconductor substrates are leadframe defined, die attached, and encapsulated with housing 272 prior to singulation.

[0035] Figure 5CAn equivalent circuit representation of a package 270 according to an embodiment of the present disclosure is provided. As shown therein, a SIDACTor is disposed between a first set of four diodes (on the left) and a second set of four diodes (on the right). The diodes on the left are coupled to a set of line-in lines and ground, while the diodes on the right are coupled to corresponding line-out lines and ground.

[0036] Although the embodiments of the present invention have been disclosed with reference to certain embodiments, many modifications, changes and variations of the described embodiments are possible without departing from the spirit and scope of the present disclosure as defined in the appended claims. It is therefore intended that the embodiments of the present invention not be limited to the embodiments described, and have the full scope defined by the language of the following claims and their equivalents.

Claims

1. A protection device comprising: semiconductor substrates; a thyristor-type device formed within the semiconductor substrate, the thyristor-type device extending from a first main surface of the semiconductor substrate to a second main surface of the semiconductor substrate; a first PN diode formed within the semiconductor substrate, wherein the first PN diode forms part of a thyristor-type device; a second PN diode formed within the semiconductor substrate, wherein terminals of the thyristor-type device are arranged in electrical series between the first PN diode and the second PN diode; and An electrical isolation barrier extends from the first main surface to the second main surface and is disposed between the second PN diode and the thyristor-type device. 2 . The protection device of claim 1 , wherein the second PN diode extends from the first main surface to the second main surface. The protection device of claim 1 , wherein the first PN diode extends from the second major surface. 4 . The protection device according to claim 1 , further comprising a front surface metal layer provided on the first main surface and provided in contact with the thyristor-type device and the second PN diode.

5. The protective device of claim 1 , wherein the second major surface comprises: a first plurality of P-type regions, the first plurality of P-type regions being electrically isolated from each other; and a second plurality of N-type regions, the second plurality of N-type regions being electrically isolated from one another and equal in number to the first plurality of P-type regions.

6. A protective device assembly comprising: A semiconductor substrate having a first main surface and a second main surface, and comprising: a thyristor-type device extending from the first main surface to the second main surface; a first PN diode extending from the second major surface, wherein the first PN diode forms part of a thyristor-type device; and a second PN diode, wherein the terminals of the thyristor-type device are arranged in electrical series between the first PN diode and the second PN diode; an electrical isolation barrier extending from the first main surface to the second main surface and disposed between the second PN diode and the thyristor-type device; a front surface metal layer disposed on the first major surface; and A lead frame is provided in contact with the second major surface.

7. The protection device assembly of claim 6, the lead frame comprising: A plurality of leads are provided in contact with the second major surface.

8. The protective device assembly of claim 7, wherein the second major surface comprises: a first plurality of P-type regions, the first plurality of P-type regions being electrically isolated from each other; and a second plurality of N-type regions, the second plurality of N-type regions being electrically isolated from each other and being equal in number to the first plurality of P-type regions, wherein the first plurality of P-type regions extend along a first direction, The plurality of leads extend along the first direction and contact the first plurality of P-type regions and the second plurality of N-type regions.

9. The protection device assembly of claim 6, wherein the lead frame comprises four leads. 10 . The protection device assembly of claim 6 , wherein the second PN diode extends from the first major surface to the second major surface.

11. The protection device assembly of claim 7, further comprising an insulating housing extending around the semiconductor substrate and between adjacent ones of the plurality of leads.

12. A line protection device comprising: A semiconductor substrate having a first main surface and a second main surface, the semiconductor substrate comprising: a thyristor-type device extending from the first main surface to the second main surface; a first PN diode extending from the second major surface, wherein the first PN diode forms part of a thyristor-type device; a second PN diode, wherein the terminals of the thyristor-type device are arranged in electrical series between the first PN diode and the second PN diode; and an electrical isolation barrier extending from the first main surface to the second main surface and disposed between the second PN diode and the thyristor-type device; a front surface metal layer disposed on the first major surface; and A lead frame is provided in contact with the second main surface, the lead frame including a plurality of leads arranged in electrical parallel to each other.

13. The line protection device according to claim 12, wherein the second main surface comprises: a first plurality of P-type regions, the first plurality of P-type regions being electrically isolated from each other; and a second plurality of N-type regions, the second plurality of N-type regions being electrically isolated from each other and being equal in number to the first plurality of P-type regions, wherein the first plurality of P-type regions extend along a first direction, The plurality of leads extend along the first direction and contact the first plurality of P-type regions and the second plurality of N-type regions.

14. The line protection device of claim 12, wherein the lead frame comprises four leads. 15 . The line protection device of claim 12 , wherein the second PN diode extends from the first main surface to the second main surface. 16 . The line protection device of claim 12 , further comprising an insulating housing extending around the semiconductor substrate and between adjacent ones of the plurality of leads.

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