Contact isolation in semiconductor devices

Abstract

In a first aspect, the invention relates to a method of forming a contact isolation for a semiconductor device (900), the method comprising: (a) providing a semiconductor structure comprising a trench (400) exposing an underlying contact (600), (b) filling a bottom of the trench (400) with a sacrificial material (700), (c) infiltrating the sacrificial material (700) with a ceramic material (800), and (d) removing the sacrificial material (700).

Description

TECHNICAL FIELD

[0001] The present invention relates to providing a contact isolation during semiconductor processing, and more specifically to such a contact isolation suitable for advanced node complementary field effect transistors. BACKGROUND

[0002] In view of the desire to stick to Moore’s law and the associated requirement of ever-shrinking scales, a complementary field effect transistor (CFET) design has been proposed as a possible contender for 3 nm technology nodes and beyond. The CFET can be seen as a further development of the vertical stacked gate-all-around (GAA) nanowire transistor, where instead of stacking n-type or p-type devices, both types of devices are stacked on top of each other. For example, Ryckaert et al. propose a CFET flow where n-type vertical fins are stacked on p-type finlets (Ryckaert, J. et al. The Complementary FET (CFET) for CMOS scaling beyond N3. In: 2018 IEEE Symposium on VLSI Technology. IEEE, 2018, pp. 141-142).

[0003] One of the challenges that remains for such a CFET is the contact isolation between the bottom and top contacts. Indeed, the stacking of the devices means that the vertical space available for the bottom contact and the contact isolation is also limited, typically about 10 nm per vertical space. This limited vertical space also limits the material selection for the contact isolation, such that good isolation performance is still ensured. For architectures with a so-called contact poly pitch (CPP) of about 90 nm, the contact isolation can be provided by plasma enhanced atomic layer deposition (PEALD) of a conformal Si3N4liner and PEALD of a SiO2over spacer to protect the Si3N4liner during etch-back. However, for more advanced architectures where the trench width is only about 12-14 nm, the Si3N4liner alone can already completely fill the trench, thus rendering this approach unsuitable.

[0004] Another drawback of the conformal Si3N4liner is that its profile mirrors the profile of the underlying contact. Thus, if the contact has a curved profile (which is typically the case), the overlying Si3N4liner will likewise not have a flat top surface.

[0005] Hence, there is still a need in the art for a method of providing a contact isolation suitable for advanced node complementary field effect transistors that solves some or all of the problems outlined above. SUMMARY

[0006] It is an object of the present invention to provide a good contact isolation for a semiconductor device. It is another object of the present invention to provide a good manufacturing step in relation thereto. This object is achieved by the method and semiconductor structure according to the present invention.

[0007] It is an advantage of embodiments of the present invention that the contact isolation and the related manufacturing step are compatible with advanced technology nodes. It is another advantage of embodiments of the present invention that a contact isolation can be provided in a trench having a width of less than 20 nm.

[0008] It is an advantage of embodiments of the present invention that the contact isolation can be relatively thin (e.g. less than 10 nm or 20 nm thick). It is another advantage of embodiments of the present invention that a good contact isolation can be achieved even considering its relatively thin thickness.

[0009] It is an advantage of embodiments of the present invention that the contact isolation has a profile that can be independent of the profile of the underlying contact.

[0010] It is an advantage of embodiments of the present invention that the etch back of the sacrificial material can be well controlled.

[0011] It is an advantage of embodiments of the present invention that the method is relatively simple and economic.

[0012] In a first aspect, the present invention relates to a method of forming a contact isolation for a semiconductor device, the method comprising: (a) providing a semiconductor structure comprising a trench exposing a contact thereunder, (b) filling a bottom of the trench with a sacrificial material, (c) infiltrating the sacrificial material with a ceramic material, and (d) removing the sacrificial material.

[0013] In a second aspect, the present invention relates to a semiconductor structure of forming a contact isolation for a semiconductor device, comprising: (i) a trench, (ii) a contact adjoining a bottom of the trench, and (iii) a sacrificial material filling the bottom of the trench, infiltrated with a ceramic material.

[0014] Particular and preferred aspects of the present invention are set out in the appended dependent and independent claims. Features of the dependent claims can be combined with features of the independent claims and other dependent claims as appropriate, and not just in the specific combinations explicitly set out in the claims.

[0015] While there have been improvements, modifications and developments of the apparatus in the past, the concepts involved with the present invention are believed to represent a substantial new and novel improvement in the art, including the development of new applications of prior structures, resulting in the provision of a more effective, stable and reliable apparatus of this nature.

[0016] The above and other characteristics, features and advantages of the present application will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the application. This description is given for the sake of example only, and without limitation to the scope of the application. The reference figures cited are meant to be included but not limiting. BRIEF DESCRIPTION OF DRAWINGS

[0017] Fig. 1 schematically depicts different steps in a process of forming a contact isolation for a semiconductor device according to an exemplary embodiment of the present application.

[0018] In the different figures, like reference signs refer to like or similar elements. DETAILED DESCRIPTION

[0019] The present application will be described with respect to the figures as follows; however, the application is not limited thereto. The figures are only intended to facilitate the description of the application made to explain the principles of the application. The dimensions of some of the elements in the figures can be exaggerated and not drawn on scale for the sake of explanation.

[0020] Furthermore, the terms first, second, third, etc. can be used in this disclosure to describe various elements or components, which are not necessarily described in this order only. Rather, these terms can be used solely as labels to distinguish between various elements or components having the same or similar characteristics and / or functions presented in the examples described herein. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the application described herein are capable of operating according to other sequences, and / or under structures or configurations other than described or claimed.

[0021] Furthermore, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and / or the embodiments of the application described herein are capable of operation in other orientations than described or illustrated.

[0022] It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present application, the only relevant components of the device are A and B.

[0023] Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, but can be referring to different embodiments.

[0024] Similarly, it is to be understood that the various features described in the description of the example embodiments of the application can be combined in any manner, as would be apparent to one of ordinary skill in the art, without departing from the scope of the present application.

[0025] Furthermore, where a dependent claim enumerates several features, the application includes not only those combinations but also individual features particularly recited.

[0026] Numerous specific details are set forth in the description herein. However, it is understood that embodiments of the application can be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been described in detail in order to not obscure the understanding of this description.

[0027] Reference transistors. These transistors are devices having a first main electrode (e.g., drain), a second main electrode (e.g., source), and a control electrode (e.g., gate) for controlling the flow of charge between the first and second main electrodes.

[0028] It will be apparent to those skilled in the art that the application also applies to similar devices that can be constructed in any transistor technology, including but not limited to, for example, CMOS, BiCMOS, bipolar, and SiGe BiCMOS technologies.

[0029] The following terms are provided solely to facilitate understanding of the application.

[0030] As used herein, and unless otherwise indicated, the term "source / drain" is used to refer to "source and / or drain." Likewise, a "source / drain structure" (e.g., a source / drain region) is a "source structure and / or a drain structure" (e.g., a source region and / or a drain region).

[0031] In a first aspect, the present invention relates to a method of forming a contact isolator for a semiconductor device, the method comprising: (a) providing a semiconductor structure comprising a trench exposing an underlying contact of the semiconductor structure, (b) filling a bottom of the trench with a sacrificial material, (c) infiltrating the sacrificial material with a ceramic material, and (d) removing the sacrificial material. After removal of the sacrificial material, the ceramic material remains and forms the contact isolator.

[0032] In some embodiments, the semiconductor device can be a complementary field effect transistor. In some embodiments, the semiconductor structure can be an intermediate structure for a complementary field effect transistor. In some embodiments, the intermediate structure can comprise a semiconductor base (e.g., a Si base), an auxiliary region (e.g., a SiGe region) on the semiconductor base, and a semiconductor region (e.g., a Si region) on the auxiliary region. Such an auxiliary region (e.g., a SiGe region) can be advantageous, for example, because it can be selectively removed (e.g., relative to the Si region or the Si base), selectively recessed, or selectively oxidized (e.g., to form an internal spacer). This can be useful, for example, when forming a wrap-around gate (e.g., in a replacement metal gate module). In some embodiments, the semiconductor base can be used to define a first channel for the CFET therein. In some embodiments, the semiconductor region can be used to define a second channel for the CFET therein. In some embodiments, the semiconductor region can be covered by one or more gate lines. In some embodiments, the gate lines can each be covered by a gate cap (e.g., a Si3N4 gate cap) and flanked by a gate spacer (e.g., a Si3N4 gate spacer). In some embodiments, the trench can separate the gate spacers of two adjacent gate lines. In some embodiments, the trench can penetrate the semiconductor region and the auxiliary region.

[0033] In some embodiments, the contact can comprise a contact liner (e.g., TiN) and a contact metal (e.g., W). The contact can advantageously help reduce contact resistance and help prepare the interface. In some embodiments, the contact can cover the source / drain region. In some embodiments, the source / drain region can be a p-doped epitaxial source / drain region (e.g., B-doped embedded SiGe).

[0034] In some embodiments, step b can comprise: (bl) filling the trench with a sacrificial material, and (b2) etching back the sacrificial material. In some embodiments, step b2 can comprise H2 / He based plasma etching. H2 / He based plasma etching advantageously allows etching the sacrificial material at a relatively low etch rate (e.g. about eight to ten times slower compared to using standard O2 based plasma), thereby allowing good control of the etch depth. In some embodiments, step b2 can comprise etching back the sacrificial material to a thickness of 30 nm or less, preferably 20 nm or less, more preferably 10 nm or less, e.g. 1 to 10 nm.

[0035] In some embodiments, the sacrificial material can comprise a functional group suitable for coordination with the first precursor (see below). In some embodiments, the sacrificial material can comprise a Lewis basic functional group (e.g. an electron donor for coordination with a Lewis acid). In some embodiments, the Lewis basic functional group can comprise a heteroatom (e.g. O or N). In some embodiments, the Lewis basic functional group can comprise a carbonyl, ester, amide or amine functional group. In some embodiments, the sacrificial material can be spin-on-carbon (SoC), poly(methyl methacrylate) (PMMA) or polyphthalamide (PPA), preferably SoC or PMMA. A suitable SoC can for example be HM710 from JSR micro.

[0036] In some embodiments, the ceramic material can be an oxide of Al (e.g. AI2O3), an oxide of Hf (e.g. HfO2), an oxide of Zr (e.g. ZrO2), an oxide of Ti (e.g. TiO x ), an oxide of Ru (e.g. RuO x ) or an oxide of Si (e.g. SiO2). In some embodiments, the relative dielectric constant of the ceramic material can be 15 or less, preferably 10 or less, more preferably 5 or less. For example, Si3N4 has been commonly used as a material for contact isolation, which has a dielectric constant of about 6.2, compared to which AI2O3 has a relative dielectric constant of about 8.5-9.0 and SiO2 has a relative dielectric constant of about 3.5-4.5. According to the present application, any of the sacrificial materials defined herein can be used with any of the ceramic materials defined herein. As non-limiting examples, the sacrificial material can be SoC and the ceramic material can be an oxide of Al (e.g. AI2O3); the sacrificial material can be PMMA and the ceramic material can be an oxide of Al (e.g. AI2O3); the sacrificial material can be SoC and the ceramic material can be an oxide of Si (e.g. SiO2); or the sacrificial material can be PMMA and the ceramic material can be an oxide of Si (e.g. SiO2).

[0037] In some embodiments, step c can comprise: (cl) exposing the sacrificial material to a first precursor, and (c2) exposing the sacrificial material to a second precursor. Thus, the first precursor and the second precursor are precursors for forming a ceramic material, and can be alternatively referred to as a "first ceramic material precursor" and a "second ceramic material precursor", respectively, in this sense.

[0038] In some embodiments, the first precursor can be a Lewis acidic metal compound, wherein the second precursor can be an oxidizing agent. In some embodiments, the Lewis acidic metal compound can be selected from 2AI(CH3)3 (trimethylaluminum, TMA), HfCl4, Zn(C2H5)2, TiCl4, SiCl4, or ToRuS-mix (e.g., from Air Liquide). In some embodiments, the first precursor can selectively complex with the sacrificial material relative to other exposed materials of the semiconductor structure (e.g., gate cap, gate spacers, and semiconductor regions). In some embodiments, the oxidizing agent can be H2O or O3. In some embodiments, step c can be performed in a reaction chamber. In some embodiments, step cl can further comprise purging the reaction chamber with an inert gas (e.g., N2) after exposing the sacrificial material to the first precursor. In some embodiments, step c2 can further comprise purging the reaction chamber with an inert gas (e.g., N2) after exposing the organic sacrificial material to the first precursor.

[0039] In some embodiments, step c can comprise sequential infiltration synthesis. In some embodiments, the sequence comprising step cl and step c2 can be performed 1 to 100 times, preferably 2 to 20 times, more preferably 3 to 10 times.

[0040] In some embodiments, the method can comprise, after step c, step e: (e) growing another ceramic material on the ceramic material. In some embodiments, step e can be performed before or after step d. In some embodiments, the other ceramic material can be SiO2. In some embodiments, step e can comprise growing SiO2 on an alkyl aluminum seed layer using an alkoxysilanol (e.g., tri(tert-amyloxy)silanol, TPS; or tri(tert-butyloxy)silanol, TBS). In some embodiments, the method can comprise infiltrating the sacrificial material with an alkyl aluminum (e.g., TMA) in step c, and then growing SiO2 on the alkyl aluminum using an alkoxysilanol in step e.

[0041] In some embodiments, step d can comprise selectively removing the sacrificial material relative to the ceramic material. In some embodiments, step d can comprise an O2-based (e.g., Ar / O2) plasma etch. An advantage of such an O2-based plasma etch is that for at least some sacrificial materials (e.g., PPA), the effect of the ceramic material shrinking upon removal of the sacrificial material is observed to be more pronounced than if a reducing chemistry such as N2 / H2 were used as an alternative. In the latter case, the thickness does indeed decrease, but to a lesser extent.

[0042] It has surprisingly been recognized in the present invention that by infiltrating a sacrificial material with a ceramic material and subsequently removing the sacrificial material, the ceramic material advantageously shrinks, resulting in a contact isolation having desirable properties (e.g., sufficiently thin). This is particularly true if the thickness of the sacrificial material is already relatively thin to begin with, e.g., obtained by etching it back in a relatively slow and controlled manner (see above). In this way, the thickness of the resulting contact isolation can be effectively controlled by the thickness of the sacrificial material and the amount of ceramic material infiltrated therein (e.g., number of SIS cycles). Moreover, the resulting contact isolation typically also has a relatively flat top profile, and this top profile is independent of the top profile of the underlying layers (e.g., the contact and / or source / drain regions).

[0043] In some embodiments, the thickness of the contact isolation can be 20 nm or less, preferably 10 nm or less, more preferably 5 nm or less.

[0044] In some embodiments, any feature of any embodiment of the first aspect can be independently described accordingly in any embodiment of any other aspect.

[0045] In a second aspect, the present invention relates to a semiconductor structure forming a contact isolation for a semiconductor device, comprising: (i) a trench, (ii) a contact abutting a bottom of the trench, and (iii) a sacrificial material infiltrated with a ceramic material filling a bottom of the trench.

[0046] In some embodiments, the semiconductor structure can be obtained after step c of the first aspect.

[0047] In some embodiments, any feature of any embodiment of the second aspect can be independently described accordingly in any embodiment of any other aspect.

[0048] The present invention will now be described by a detailed description of several embodiments of the application. It is clear that other embodiments of the application can be constructed without departing from the true technical teaching of the application, which is only limited by the claims attached hereto.

[0049] Embodiment: Forming a contact isolation for a semiconductor device

[0050] By way of example, the formation of a contact spacer for a complementary field effect transistor (CFET) in accordance with the present application is described below with reference to FIG. 1.

[0051] Reference is now made to Figure 1a An intermediate structure in CFET formation is provided, comprising a Si wafer (100), a SiGe region (200) on the Si wafer (100), and a Si region (110) on the SiGe region (200); wherein the silicon wafer (100) is to define a first channel of a CFET therein, and the silicon region (110) is to define a second channel of the CFET therein. The Si region (110) is covered with gate lines (300), each of which is covered with a Si3N4 gate cap (310), and flanked by Si3N4 gate spacers (320). Trenches (400) separate the gate spacers (320) of two adjacent gate lines, and pass through the Si region (110) and the SiGe region (200), thereby exposing a B-doped embedded SiGe (eSiGe:B) p-doped epitaxial source / drain region (500) grown on the Si wafer (100) for the first channel.

[0052] Reference is now made to Figure 1b The trenches (400) are covered with TiN contact pads (not shown), and overfilled with W contact metal (610), followed by a planarization step (e.g., chemical mechanical planarization) that stops on the gate caps (310).

[0053] Reference is now made to Figure 1c The contact pads and contact metal (610) are etched back using an SF6-based plasma, to obtain a contact (600) with a target thickness (e.g., thickness of TiN+W on the source / drain region) of 10 nm.

[0054] Reference is now made to Figure 1d The trenches (400) are overfilled with a sacrificial material (700) comprising Lewis basic functional groups, such as spin-on carbon (SoC) or poly(methyl methacrylate) (PMMA).

[0055] Reference is now made to Figure 1e The sacrificial material (700) is etched back using an H2 / He-based plasma; the latter provides a relatively slow etch that allows tight control of the depth of the etch back, and thus of the amount of sacrificial material (700) remaining in the trenches (400). For example, the etch back rate of SoC is lower than 1 nm / s (about eight to ten times slower than using a standard O2-based plasma).

[0056] Reference is now made toFigure 1f The sacrificial material (700) is infiltrated with a ceramic material (800), for example selected from AI2O3, HfO2, ZrO2, TiO x , RuO x 2, or SiO2, based on a first precursor (e.g. Lewis acidic metal compound, see above) and a second precursor (e.g. oxidizing agent; see above), using a continuous infiltration synthesis. Here, a non-metal oxide (e.g. SiO2) can be preferred to minimize contamination risks.

[0057] Reference is now made to Figure 1f The sacrificial material (700) is removed using an O2-based plasma treatment, leaving the ceramic material as a contact isolator (900) with a shrinkage thickness of about 10 nm.

[0058] It is understood that while the present application has been discussed herein with regard to preferred embodiments of the device, specific configurations and arrangements, and materials, various changes or modifications can be suggested to one skilled in the art and may be made in form and detail without departing from the scope and technical teaching of the application. For example, any of the schemes given above represent only processes that can be used. Functionality can be added to or deleted from the block diagrams, and operations can be interchanged among functional blocks. Steps can be added or deleted to the methods described within the scope of the present application.

Claims

1. A method of forming a contact isolator (900) for a semiconductor device, comprising: a. providing a semiconductor structure comprising a trench (400) exposing a contact (600) thereunder, the trench (400) penetrating a semiconductor region comprising Si and an auxiliary region comprising SiGe, b. filling a bottom of the trench (400) with a sacrificial material (700), c. infiltrating the sacrificial material (700) with a ceramic material (800), and d. removing the sacrificial material (700), wherein the removing the sacrificial material (700) comprises an O2-based plasma etch.

2. The method of claim 1, wherein, The sacrificial material (700) comprises a Lewis basic functional group.

3. The method of claim 1 or 2, wherein, The sacrificial material (700) is spin-on carbon or poly(methyl methacrylate).

4. The method of claim 1 or 2, wherein, The ceramic material (800) is an oxide of Al, Hf, Zr, Ti, Ru or Si.

5. The method of claim 1 or 2, wherein, The ceramic material (800) has a relative dielectric constant of 15 or less.

6. The method of claim 1 or 2, wherein, The ceramic material (800) has a relative dielectric constant of 10 or less.

7. The method of claim 1 or 2, wherein, Step c comprises: cl. exposing the sacrificial material (700) to a first precursor, and c2. exposing the sacrificial material (700) to a second precursor.

8. The method of claim 7, wherein, The first precursor is a Lewis acidic metal compound, wherein the second precursor is an oxidizing agent.

9. The method of claim 1 or 2, wherein, Step c comprises a continuous infiltration synthesis.

10. The method of claim 1 or 2, comprising a step e after step c: e. growing another ceramic material on the ceramic material (800).

11. The method of claim 1 or 2, wherein, Step b comprises: bl. filling the trench (400) with the sacrificial material (700), and b2. etching back the sacrificial material (700).

12. The method of claim 11, wherein, Step b2 comprises an H2 / He-based plasma etch.

13. The method of claim 1 or 2, wherein, The semiconductor device is a complementary field effect transistor.

14. The method of claim 1 or 2, wherein, The isolator of the contact (600) has a thickness of 20 nm or less.

15. The method of claim 1 or 2, wherein, The isolator of the contact (600) has a thickness of 10 nm or less.

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