Photonic Emitter Driver Using Cascaded Differential Transistor Pairs to Implement Logic

Abstract

The present application relates to a photon emitter driver that implements logic using a cascaded differential transistor pair. A driver circuit includes a digital input, such as a first digital input and a second digital input. The digital input receives a voltage of a digital high voltage or a digital low voltage. The driver circuit has a clock input, an analog output, a first differential pair transistor connected to the analog output, a second differential pair transistor connected to the analog output, and a voltage limiter connected to the clock input and the second differential pair transistor. The voltage limiter provides different voltages to the second differential pair transistor, which causes the second differential pair transistor to provide analog signals to the analog output, and these analog signals are at different voltage steps at the digital high voltage, the digital low voltage, and between the digital high voltage and the digital low voltage.

Description

Technical Field

[0001] The present application relates to a photon emitter driver, and more particularly, to a photon emitter driver using a cascaded differential transistor pair. Background Art

[0002] In optical data transmission systems, emitters (emitters or transmitters) often use various types of drivers, one of which is a pulse amplitude modulation (PAM) driver. One or more modulation formats used in the electrical interface include pulse amplitude modulation (PAM-4, PAM-8, PAM-N, etc.) in formats such as non-return to zero (NRZ), 4-ary, 8-ary, N-ary, etc. PAM-4 is an example of multi-level amplitude modulation used in this application for ease of illustration and discussion, however, it should be understood by those of ordinary skill in the art that all discussions using the PAM-4 example herein are equally applicable to other modulation formats, and therefore, the claims appended hereto are intended to apply to all such formats, whether currently known or developed in the future. In this example of a PAM-4 driver, two binary bits of information (duobinary) will be processed simultaneously. In this use of and D1 represents the first binary bit, and uses And D2 represents the second bit of the binary digit.

[0003] One issue surrounding 4-level pulse amplitude modulation driver circuits involves the inability to operate at high frequencies, above 20 GHz, or with greater bandwidths. This limitation can be traced back to the many subcircuits involved in the PAM-4 implementation. Specifically, the PAM-4 implementation involves subcircuits for Gray coding, PAM-4 logic generation, buffering, analog summing, and more. When connected in cascade, each of these building blocks adds capacitive loading, reducing the overall bandwidth. The low supply voltages in sub-nanometric technology nodes limit the output swing in each subblock, requiring more cascade stages during buffering operation, which in turn results in operating speeds limited by the gain-bandwidth product of the cascaded system.

[0004] One solution to this problem is to stack transistors to achieve the higher voltage levels (e.g., 3V or higher) required to drive a commonly used photonic modulator, the Mach-Zehnder modulator (MZM). The stacking of transistors is proportional to silicon area and power consumption. Both complementary metal oxide semiconductor (CMOS) and current-mode logic (CML) devices require transistor stacking to implement various logic functions such as XOR, MUX, AND, etc. However, for any type of PAM-4 or dual binary operation, these circuits have difficulty operating at supply voltages below 1V at high data rates. Summary of the invention

[0005] Various driver circuits herein include a digital input connected to an external multiplexer and a buffer. The digital input may be a first digital input and a second digital input. The digital input receives a voltage at a digital high voltage or a digital low voltage. These driver circuits also have a clock input and a step analog output connected to a transmission modulator provided by an external laser.

[0006] A first differential pair transistor and two or more second differential pair transistors are connected to a digital input and combined to produce an analog output. In addition, a voltage limiter is connected to a clock input and the second differential pair transistor. The voltage limiter provides different voltages to the second differential pair transistor, which causes the first differential pair transistor and the second differential pair transistor to provide analog outputs with different voltage steps at a digital high voltage, a digital low voltage, and between a digital high voltage and a digital low voltage. Specifically, the threshold voltage of the transistors constituting the voltage limiter determines the different voltage steps of the output.

[0007] It should be noted that the clock input in this article is only connected to the voltage limiter, not to the first differential pair transistor. In addition, the transistors in the first differential pair transistor and the second differential pair transistor are connected to a common node and are provided with the same current. In addition, the transistors in the first differential pair transistor and the second differential pair transistor are transistors of the same size and type. However, these transistors are different in size from the transistors of the voltage limiter.

[0008] In addition, by setting the aforementioned components and electrically connecting the first transistor differential pair and the second transistor differential pair to the analog output, a logic AND circuit, a logic OR circuit, a logic XOR circuit, etc. are formed to perform Gray encoding, temperature encoding, addition, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments herein will be better understood by the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0010] Figure 1 is a schematic diagram of an optical transmitter according to various embodiments herein;

[0011] FIG. 2A to FIG. 2D They are Figure 1 Schematics of different examples of generic drivers shown, i.e. logical OR, XOR, AND, and any other logical use functions; and

[0012] FIG. 3A to FIG. 3C They are FIG. 2A to FIG. 2C Schematic diagram of logical OR, XOR, and AND circuits of the specific example shown.

[0013] Description of main reference numerals

[0014] 100 Launcher

[0015] 102 Multiplexer / Buffer

[0016] 104 Clock Generator

[0017] 106 Large Swing Modulation Driver (LSMD)

[0018] 108 PAM-4 driver, drive circuit

[0019] 108A to 108D Drivers

[0020] 110 Modulator, transmission modulator

[0021] 112 Laser

[0022] 114 Shunt Circuit

[0023] 122A First differential pair transistor

[0024] 122B to 122C Second differential pair transistor

[0025] 124, 126 Voltage limiter

[0026] 128A Logic OR Circuit

[0027] 128B Logic XOR Circuit

[0028] 128C Logic AND Circuit

[0029] 128D Any logic

[0030] CLK Clock input

[0031] D1, Digital Input

[0032] D2, Digital Input

[0033] L1 Inductor, tuning inductor

[0034] M1 to M6 transistors

[0035] M7 to M8 transistors (voltage limiters)

[0036] Out, Analog output, common output node

[0037] R1 resistor, load resistor

[0038] TX optical transmission output

[0039] VDD supply voltage. DETAILED DESCRIPTION

[0040] As mentioned above, PAM driver circuits may not be able to operate at high frequencies or greater bandwidths, and even stacked transistors have silicon area and power consumption impacts. In view of these issues, this application proposes a photon emitter driver that implements logic using the same cascaded differential transistor pairs based on power supply voltage difference steps. Again, although PAM-4 is used as an example in this discussion, all structures disclosed in this article can be implemented in other modulation formats (PAM-4, PAM-8, PAM-N, etc.).

[0041] In more detail, these exemplary structures are presented as single cell PAM-4 transmitters that pre-perform PAM-4 synthesis in one block (i.e., thermometer (unary) coding) and perform PAM-4 logic generation and summing in parallel. The drivers herein do not require additional stages for buffering and amplification. Therefore, the present application proposes a new CML logic family that uses analog outputs (similar to digital-to-analog (DAC) circuits) instead of binary outputs of classical digital logic gates. The drivers herein provide memory-based logic gates, in non-limiting embodiments, memories based on AND gates, OR gates, and XOR gates. The drivers herein utilize a combination of CML clocked buffers and unclocked buffers to share the same output at the drain. Therefore, these structures use the circuit clock at the same level as the input transistors.

[0042] As shown in the accompanying drawings and as discussed in detail below, the PAM-4 driver circuits presented as examples in this application use clock buffer layers and clock-free buffer layers, where both the input signal and the clock signal are at the same voltage level. These PAM-4 driver circuits use a single clock-free buffer and another pair of clock buffers that use the clock signal to replace one of the inputs to provide analog-type outputs at different voltage steps. In the examples given, the circuit configuration creates a memory based on AND, XOR, and OR circuits; however, a person of ordinary skill in the art will understand that other logic circuits can also be derived from this, and therefore, the logic circuits are also intended to be disclosed herein using AND, XOR, and OR circuits as examples of all such logic circuits.

[0043] Figure 1 An exemplary transmitting device 100 is shown, which includes various multiplexers and outputs various digital signals to various digital inputs D1, D2, 102. In addition, a clock generator 104 provides clock signals to various clock inputs (CLK). These signals are provided to, for example, a large swing modulation driver (LSMD) 106 that feeds a PAM-4 driver 108. Figures 2A to 3C Various versions of a PAM-4 driver 108 are shown, all of which are discussed below. The PAM-4 driver 108 outputs an analog signal to a modulator 110 which utilizes a laser 112 to provide an optical transmission output (TX).

[0044] like Figure 2AIn the example shown, the driver circuit 108 herein includes a digital input D1 connected to an external multiplexer and buffer 102, D2, Digital input D1, D2, Can be the first complementary digital input D1, and the second complementary digital input D2, Digital input D1, D2, Receives a voltage of either a digital high voltage or a digital low voltage, which represents data of zero or one, respectively. These driver circuits 108 also have a clock input (CLK) and an analog output (Out) connected to a transmission modulator 110 provided by an external laser.

[0045] Figure 2A shows the connection to the first digital input D1, A first (unclocked) differential pair transistor 122A is connected to the analog output (Out). Two or more second differential pair transistors 122B, 122C are connected to the analog output (Out). The gates of the second differential pair transistors 122B, 122C are connected to at least one second digital input D2, D2 (and sometimes also to one or more of the first digital inputs D1, D1).

[0046] in addition, Figure 2A A voltage limiter 124, 126 is shown, which includes a first digital input D1, Sometimes also connected to the second digital input D2, One or more of the first differential pair transistors 122A, 122B, 122C), the clock input (CLK), and the different sized transistors of the second differential pair transistors 122B, 122C. The voltage limiters 124, 126 provide different voltages to the second differential pair transistors 122B, 122C, which causes the second differential pair transistors 122B, 122C to provide analog signals to the analog output (Out), which are at different voltage steps at the digital high voltage, the digital low voltage, and between the digital high voltage and the digital low voltage. Therefore, the combination of the first differential pair transistors 122A and the second differential pair transistors 122B, 122C outputs three different sets of high voltages and low voltages (a total of six voltage steps), which are provided at the common output node OUT shared by the source / drain of all six differential pair transistors 122A, 122B and 122C. Specifically, the threshold voltages of the transistors making up the voltage limiters 124, 126 determine the different voltage steps output by the differential pair transistors. Thus, the second differential pair transistors 122B, 122C are (clocked) cascaded differential transistor pairs that are identical but are stepped by the supply voltage difference provided by the voltage limiters 124, 126.

[0047] It should be noted that the clock input (CLK) here is only connected to the voltage limiters 124, 126 and not to the first differential pair transistor 122A. Moreover, the transistors in the first differential pair transistor 122A and the transistors in the second differential pair transistors 122B, 122C are supplied with the same current. In addition, the transistors in the first differential pair transistor 122A and the transistors in the second differential pair transistors 122B, 122C have the same size and the same type. However, the transistors in the first differential pair transistor 122A and the transistors in the second differential pair transistors 122B, 122C are different in size from the transistors in the voltage limiters 124, 126.

[0048] like FIG. 2A to FIG. 2C As shown, the arrangement of the aforementioned components and the electrical connection of the first differential pair transistor 122A and the second differential pair transistor 122B, 122C to the analog output (Out) form any of the following modes: the logic OR circuit 128A ( Figure 2A ), logical XOR circuit 128B ( Figure 2B ), logical AND circuit 128C ( Figure 2C ), or any other logic function circuit 128D ( Figure 2D ) to perform different operation functions including Gray encoding, temperature encoding, adding, etc.

[0049] To provide a specific implementation example of the PAM-4 driver 108, FIG. 2A to FIG. 2C The logical OR, XOR, and AND drivers shown are presented in FIG. 3A to FIG. 3C However, those skilled in the art will appreciate that FIG. 2A to FIG. 2C The concept map can be found in addition to FIG. 3A to FIG. 3C The present invention can be implemented in many different circuits beyond the examples shown.

[0050] Here, the PAM-4 AND drivers 108A to 108C include a PAM-4 AND driver 108A to 108C connected to an external multiplexer and buffer 102 ( Figure 1 ) of the digital input D1, D2, Digital input D1, D2, comprising a first digital input D1, and the second digital input D2, Digital input D1, D2, Receives a voltage in the digital high or digital low (1 or 0) state. FIG. 3A to FIG. 3CAs shown, the first digital input D1, D1 receives the first real data D1 and the first supplementary data D1. The second digital input D2, Receive the second real data D2 and the second supplementary data FIG. 3A to FIG. 3C Also shown are the clock input (CLK) and analog output (Out) of the transmission modulator 110 connected to the external laser supply ( Figure 1 ).

[0051] like FIG. 3A to FIG. 3C As shown, the first differential pair transistor 122A (M1, M2) is connected to the first digital input D1, and analog output (Out, ). In addition, the diversion circuit 114 controls when the first differential pair transistors 122A (M1, M2) are connected to the nominal power supply voltage VDD. The diversion circuit 114 either diverts all currents flowing through the transistors inside the diversion circuit 114 or causes all currents to flow through the first differential pair transistors 122 (M1, M2), thereby eliminating any memory effect in the first differential pair transistors 122A (M1, M2). More specifically, the diversion circuit 114 includes a circuit for applying a voltage that causes the two digital inputs to be connected to the nominal power supply voltage VDD. A clamping transistor with the additional condition that the two transistors must be in the same state (all zero or all one) for current diversion to occur.

[0052] FIG. 3A to FIG. 3B Both the OR and XOR implementations 108A, 108B shown in FIG. 1 use the shunt circuit 114 to controllably connect the first differential pair transistors 122 (M1, M2) to VDD. Figure 3C In the AND implementation 108C shown, the shunt circuit 114 is not used, resulting in the first differential pair transistors 122A (M1, M2) being continuously connected to VDD in the AND implementation 108C. FIG. 3A to FIG. 3C In the OR or XOR implementation 108A, 108B shown, the gate of transistor M1 is connected to D1, and the gate of transistor M2 is connected to However, in Figure 3C In the AND implementation 108C shown, the gate of transistor M1 is connected to And the gate of transistor M2 is connected to D1.

[0053] exist FIG. 3A to FIG. 3C In the OR or XOR implementation 108A, 108B shown, a second differential pair of transistors 122B (M3, M4) is connected to the first digital input D1, and analog output (Out, ); and another second differential pair transistor 122C (M5, M6) is connected to the second digital input D2, and analog output (Out, ). On the contrary, due to Figure 3C The AND implementation 108C shown in the figure has a different logic function, and the second differential pair of transistors 122B (M3, M4), 122C (M5, M6) are both connected to the second digital input D2, and analog output (Out, ).

[0054] More specifically, FIG. 3A to FIG. 3B FIG. 108A and 108B show that in an OR or XOR implementation, the gates of transistors M3 and M4 are connected to D1, The gates of transistors M5 and M6 are connected to D2, contrast Figure 3C The different logical AND implementation 108C shown, wherein the gates of transistors M3 and M4 are connected to D2, The gates of transistors M5 and M6 are also connected to D2,

[0055] FIG. 3A to FIG. 3C Also shown are voltage limiters 124, 126 formed by transistors M7, M8 connected to digital input D1, D2, The clock input (CLK) and any one of the second differential pair transistors 122B, 122C. The drains of transistors M7 and M8 are directly connected to the nominal power supply voltage VDD. Voltage limiters 124, 126 provide different voltages to the second differential pair transistors 122B, 122C. Therefore, the source of M7 is connected to the sources of M3, M4, and the source of M8 is connected to the sources of M5, M6, thereby providing these different voltages.

[0056] In more detail, in Figure 3A In the illustrated OR implementation 108A, Connected to the gate of M7, Connect to the gate of M8. Figure 3B In the XOR implementation 108B shown, connected to the gate of M7, and D1 connected to the gate of M8, Figure 3C In the AND implementation 108C shown, D1 is connected to the source of M7, and Connect to the gate of M8.

[0057] therefore, FIG. 3A to FIG. 3CAs shown, the clock CLK provided to the gates of the voltage limiters M7 and M8 controls when the voltage (VDD) is provided to the second differential pair transistors 122B (M3, M4), 122C (M5, M6), and the voltage limiters M7 and M8 of different sizes result in different voltages being provided to the second differential pair transistors 122B (M3, M4), 122C (M5, M6). Therefore, this provides a clock for the second differential pair transistors 122B (M3, M4), 122C (M5, M6), and provides different voltages to the second differential pair transistors 122B (M3, M4), 122C (M5, M6), so as to provide analog-like step outputs.

[0058] The size of the inputs M7 and M8 is different from that of the input transistor pairs M1, M2 and M3, M4. The size of the clamp transistor M7 can be the same or different from that of M8. The PAM-4 analog threshold level at the output is set by the strength of M7 and M8. By adjusting the M / L ratio of M7, M8, the threshold and voltage level can be selected independently of each other. In addition, the VDD of M7 and M8 is not cascaded with M1 and M2 or M3, M4 and M5, M6. In addition, the load resistor R1 and the tuning inductor L1 are shared between the drains of the differential pairs M1, M2, M3, M4 and M5, M6. The inputs D1 and D2 have the same (balanced) fan out or parasitic load; thereby minimizing the variation of the rise time and fall time at the output.

[0059] FIG. 3A to FIG. 3C It is further shown that all sources / drains of all transistors provide the same resistance and inductance (L1, R1) to ensure balanced capacitive loading. FIG. 3A to FIG. 3C It is also shown that the first differential pair transistor 122A (M1, M2) can be provided with VDD either constantly or controllably (using the shunt circuit 114), while the second differential pair transistor 122B (M3, M4), 122C (M5, M6) is provided with a voltage different from VDD through the voltage limiter M7, M8, which enables the driver to output three different sets of high voltages and low voltages (a total of six voltage steps), which are provided at the common output node OUT shared by the source / drain of all six differential pair transistors. This provides a digital square wave ( FIG. 3A to FIG. 3C shown adjacent to each differential pair) to the simulated waveform ( FIG. 3A to FIG. 3C The digital-to-analog conversion is shown adjacent to the output terminal.

[0060] In addition, this results in the second differential pair transistors 122B, 122C providing an analog signal to the analog output (Out) that is at different voltage steps at a digital high voltage, a digital low voltage, and between the digital high voltage and the digital low voltage. Specifically, the threshold voltages of the transistors that constitute the voltage limiters 124, 126 determine the different voltage steps that the second differential pair will output.

[0061] It should be noted that the clock input (CLK) here is only connected to the voltage limiters 124, 126 (which clock the second differential pair transistors 122B, 122C), and not to the first differential pair transistor 122A (which remains unclocked). In addition, the transistors in the first differential pair transistors 122A and the second differential pair transistors 122B, 122C are connected to a common node and are provided with the same current. In addition, the transistors in the first differential pair transistors 122A and the second differential pair transistors 122B, 122C are transistors of the same size and type. However, the size of the transistors in the first differential pair transistors 122A and the second differential pair transistors 122B, 122C is different from the size of the transistors of the voltage limiters 124, 126 to help output different voltage steps.

[0062] Furthermore, these non-limiting embodiments show that the above components can be configured and the source / drain of the first differential pair transistor 122A and the second differential pair transistor 122B, 122C can be connected to the analog output (OUT, ) to form logical OR, XOR and AND circuits. However, as described above, component rearrangement and electrical connection changes known to those skilled in the art can FIG. 3A to FIG. 3C The circuits shown are converted to any other logic circuits, and the drawings accompanying this specification are intended to illustrate all of these structures and any other logic structures useful in performing processes such as Gray coding, temperature coding, addition operations, etc.

[0063] In addition, the clocked transistors (M7 and M8) introduce a memory effect. Specifically, the PAM-4 driver circuit presented here includes a differential pair M1 and M2 at the input stage, and two other differential pairs M3, M4 and M5, M6, with additional transistors (voltage limiters) M7 and M8 connected to the sources of the differential pairs M3, M4 and M5, M6. Here, M3 and M4 act as a first memory pair, and M5 and M6 act as a second memory pair. The memory analog level is set by adjusting the size of the clamping transistors M7 and M8. Similarly, the size of M7 and M8 can be the same, but different from the size of the input transistors.

[0064] Therefore, this exemplary PAM-4 driver circuit uses two inputs D1 and D2. D1 is the input of the clock-less memory-less differential pair M1, M2, while the combination of D1 and D2 is the input of the second differential pair M3, M4 and the third differential pair M5, M6. The sources of M3, M4 and M5, M6 are clamped by additional transistors M7 and M8. The differential data at the gates of M3, M4 and M5, M6 are the same to ensure balanced capacitive loading. Similarly, inputs M7 and M8 share the same load, so the input data is the same.

[0065] In addition to describing the methods and functions of the present embodiment at various stages, each corresponding figure also illustrates the logic of the method implemented in whole or in part by one or more devices and structures. Such devices and structures are configured to (i.e., include one or more components, such as resistors, capacitors, transistors, etc. connected to enable the execution of the steps) implement the above-mentioned methods. In other words, one or more computer hardware devices can be created, which are configured to implement the methods and steps described herein with reference to the drawings and their corresponding descriptions.

[0066] The embodiments herein can be used in a variety of electronic applications. The resulting devices and structures, such as integrated circuit (IC) chips, can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), bare die, or packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0067] Although the above is described in detail in conjunction with only a limited number of embodiments, it should be readily understood that the embodiments herein are not limited to such disclosures. On the contrary, the elements herein may be modified to include any number of changes, alterations, substitutions, or equivalent arrangements that have not been described so far but are commensurate with the spirit and scope of this article. In addition, although various embodiments have been described, it should be understood that the various aspects of this article may be included only by some of the embodiments described. Therefore, the appended claims should not be considered to be limited by the above description. Unless otherwise specified, references to elements in the singular form do not mean "one and only one", but "one or more". All structural and functional equivalents of the various embodiments described in this application are known or later known to those of ordinary skill in the art, are expressly included herein by reference, and are intended to be included in this disclosure. Therefore, it should be understood that changes can be made in the specific embodiments disclosed, and the disclosed embodiments are within the scope outlined by the appended claims.

Claims

1. A driving circuit, characterized in that: include: a digital input comprising a first digital input and a second digital input; Clock input; Analog output; a first differential pair of transistors connected to the first digital input and the analog output; a second differential pair of transistors connected to the second digital input and the analog output; as well as a voltage limiter connected to the clock input and the second differential pair of transistors, wherein the second differential pair of transistors provides an analog signal to the analog output, wherein the clock input is directly connected only to the voltage limiter and not directly connected to the first differential pair transistor, wherein the transistors in the first differential pair of transistors and the transistors in the second differential pair of transistors are connected to a common node and are provided with the same current, The transistors in the first differential pair of transistors and the second differential pair of transistors are transistors of the same size and type, and The transistors in the first differential pair of transistors and the second differential pair of transistors are different in size from the transistor of the voltage limiter.

2. The driving circuit according to claim 1, characterized in that: A threshold voltage of the voltage limiter determines a voltage output by the second differential pair of transistors.

3. The driving circuit according to claim 1, characterized in that: The driving circuit further includes an electrical connection connecting the first differential pair transistor and the second differential pair transistor to the analog output, wherein any one of a logical XOR circuit, a logical OR circuit, or a logical AND circuit is formed through a pattern of the electrical connection.

4. A driving circuit, characterized in that: include: a digital input connected to an external multiplexer and a buffer, wherein the digital input comprises a first digital input and a second digital input; Clock input; an analog output that connects to a transmission modulator provided by an external laser; a first differential pair transistor connected to the analog output, wherein a gate of the first differential pair transistor is connected to the first digital input; a second differential pair transistor connected to the analog output, wherein a gate of the second differential pair transistor is connected to at least the second digital input; and a voltage limiter including a transistor connected to the clock input and the second differential pair transistor, wherein the second differential pair of transistors provides an analog signal to the analog output, wherein the clock input is directly connected only to the voltage limiter and not directly connected to the first differential pair transistor, wherein the transistors in the first differential pair of transistors and the transistors in the second differential pair of transistors are connected to a common node and are provided with the same current, The transistors in the first differential pair of transistors and the second differential pair of transistors are transistors of the same size and type, and The transistors in the first differential pair of transistors and the second differential pair of transistors are different in size from the transistor of the voltage limiter.

5. The driving circuit according to claim 4, characterized in that: The threshold voltage of the voltage limiter determines the different voltage steps output by the second differential pair of transistors.

6. The driving circuit according to claim 4, characterized in that: The driving circuit further includes an electrical connection connecting the first differential pair transistor and the second differential pair transistor to the analog output, wherein any one of a logical XOR circuit, a logical OR circuit, or a logical AND circuit is formed through a pattern of the electrical connection.

7. A driving circuit, characterized in that: include: A digital input connected to an external multiplexer and a buffer, wherein the digital input includes a first digital input and a second digital input, wherein the first digital input receives a first real data D1 and a first complementary data The second digital input receives the second real data D2 and the second supplementary data Clock input; an analog output that connects to a transmission modulator provided by an external laser; a first differential pair of transistors M1, M2 connected to the first digital input and the analog output; a second differential pair of transistors M3, M4 and M5, M6 connected to the second digital input and the analog output; and a voltage limiter comprising transistors M7, M8 connected to the first digital input, the clock input and a second differential pair of transistors M3, M4 and M5, M6, The source of the transistor M7 is connected to the sources of the second differential pair of transistors M3 and M4, and the source of the transistor M8 is connected to the sources of the second differential pair of transistors M5 and M6. The second differential pair of transistors M3, M4 and M5, M6 provide analog signals to the analog output. The clock input is directly connected only to the voltage limiter and not directly to the first differential pair of transistors M1, M2. The transistors in the first differential pair of transistors M1, M2 and the second differential pair of transistors M3, M4 and M5, M6 are connected to a common node and are provided with the same current. The transistors in the first differential pair of transistors M1, M2 and the transistors in the second differential pair of transistors M3, M4 and M5, M6 are transistors of the same size and type, and The transistors in the first differential pair of transistors M1 , M2 and the second differential pair of transistors M3 , M4 and M5 , M6 are different in size from the transistors of the voltage limiter.

8. The driving circuit according to claim 7, characterized in that: The threshold voltage of the voltage limiter determines the different voltage steps output by the second differential pair of transistors M3, M4 and M5, M6.

9. The driving circuit according to claim 7, characterized in that: The driving circuit further includes electrical connections connecting the first differential pair of transistors M1, M2 and the second differential pair of transistors M3, M4 and M5, M6 to the analog output, wherein any one of a logic XOR circuit, a logic OR circuit or a logic AND circuit is formed through a pattern of the electrical connections.

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