Processor system

Abstract

A processor system and method, the processor system comprising a central processing unit (CPU) including a register for storing a stack pointer value, a non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM image including program context data. The processor system includes a random access memory (RAM) coupled to the CPU and having a first RAM region and a second RAM region. The processor system is configured to have a first operating mode that does not preserve RAM data values and a second operating mode in which the RAM is powered. The processor system changes from the first operating mode to the second operating mode by applying power to the RAM, setting the stack pointer value to an address in the second RAM region, copying the program context data from the second non-volatile memory region to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a processor system and a method of operating a processor system. BACKGROUND

[0002] A processor system can be included in other low power or portable systems such as wireless Internet of Things (IoT) devices or portable information terminals, sensors or other devices, some of which can be powered by a battery. These systems can be configured to change operational modes between a normal operation having a relatively short duration and an inactive state having a relatively long duration. For example, the inactive state can be an interval between when an RF transceiver of an IoT device or system is inactive, a wireless portable information terminal is not in use, or a sensor is operating periodically to measure temperature, pressure, current, voltage or other property. During these inactive periods, the system can switch to a low power mode or standby mode in which power consumption is significantly reduced, for example, in order to preserve battery life.

[0003] In this standby mode, the processor system preserves the contents of volatile random access memory (RAM) so that the processor system can perform a fast transition to the normal operation mode. In the normal operation mode, the processor system can perform a required function, for example, to measure temperature or pressure and then transmit the results, or to transmit and receive authentication information to unlock or lock a door. Once this task is completed, the processor system can then be in an idle state without needing to process additional tasks. At this point, the processor system can again power down to the standby mode to reduce power consumption. SUMMARY

[0004] Various aspects of the present disclosure are defined in the appended claims. In a first aspect, a processor system is provided, comprising: a central processing unit (CPU) including a register to store a stack pointer value; a random access memory (RAM) coupled to the CPU and having a first RAM region and a second RAM region; a non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM image including program context data; and wherein the processor system is configured to have a first operational mode that does not preserve RAM data values and a second operational mode in which the RAM is powered up, and is further configured to change from the first operational mode to the second operational mode by: applying power to the RAM, setting the stack pointer value to an address in the second RAM region, copying the program context data from the second non-volatile memory region to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region.

[0005] In one or more embodiments, in a first operating mode, the RAM can be powered off or reset.

[0006] In one or more embodiments, the RAM image may additionally include header data and tail data.

[0007] In one or more embodiments, the processor system may be additionally configured to copy tail data to a first RAM area.

[0008] In one or more embodiments, the header data may include a magic value, a RAM image size value, a RAM image start address, and a checksum, and the tail data may include a transmission end marker.

[0009] In one or more embodiments, the processor system may additionally include a communication interface coupled to the CPU, and wherein the RAM image additionally includes hardware configuration parameters, which include at least one of CPU register values, peripheral register values, and communication parameter values.

[0010] In one or more embodiments, hardware configuration parameters may be copied to RAM before program context data.

[0011] In one or more embodiments, the CPU may be configured to update hardware peripherals and transceivers with hardware configuration parameters while at least a portion of the program context data is copied.

[0012] In one or more embodiments, the processor system may be further configured to set the stack pointer to an address in the second RAM region and copy RAM image data from the first RAM region to the second non-volatile memory region.

[0013] In one or more embodiments, the processor system may be additionally configured to generate a RAM image by copying a hardware configuration parameter, including at least one of CPU register values ​​and hardware peripheral register values, to a first RAM region.

[0014] In one or more embodiments, the program context data may include a stack region and a heap region arranged toward opposite ends of the program context data, and wherein, in a second operating mode, the stack and heap are configured to increase in opposite directions.

[0015] In a second aspect, a method is provided for changing a processor system from a first operating mode that does not retain random access memory (RAM) data values ​​to a second operating mode, the processor system comprising: a central processing unit (CPU) including a stack pointer register; non-volatile memory coupled to the processor and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM image including program context data; RAM coupled to the CPU, the RAM having a first RAM region and a second RAM region; the method comprising: energizing the RAM, setting a stack pointer value to an address in the second RAM region as a stack, copying a RAM image from the second non-volatile memory region to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region.

[0016] In one or more embodiments, the RAM image may include header data and tail data, and the method may additionally include copying the tail data to a first RAM region.

[0017] In one or more embodiments, the RAM image may additionally include hardware configuration parameters, which include at least one of processor register values, peripheral register values, and transceiver parameters, and the method may additionally include copying the hardware configuration parameters to RAM before the processor context data, and updating the hardware peripheral register parameters and transceiver parameters with the hardware configuration parameters while at least a portion of the program context data is copied.

[0018] In one or more embodiments, the method may further include: using a second RAM region as a stack, and copying a RAM image from a first RAM region to a second region of non-volatile memory.

[0019] In one or more embodiments, the method may further include changing from a second operating mode to a first operating mode after copying the RAM image from a first RAM region to non-volatile memory.

[0020] In one or more embodiments, the RAM image may additionally include hardware configuration parameters, which include at least one of CPU register values, peripheral register values, and communication parameter values, and the method may additionally include copying the hardware configuration parameters to RAM before the program context data, and at least partially restoring the hardware configuration parameters while the program context data is being copied.

[0021] In one or more embodiments, the program context data includes a stack region and a heap region arranged toward opposite ends of the program context data, and wherein in a second operating mode, the method includes adding the stack and heap in opposite directions.

[0022] In a third aspect, a computer program product for a processor system is provided, the processor system comprising: a central processing unit (CPU) having a register for storing a stack pointer value; random access memory (RAM) coupled to the CPU and having a first RAM region and a second RAM region; and non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store the computer program product and a second non-volatile memory region configured to store a RAM image including program context data; wherein the computer program product includes instructions that, when executed by the CPU, cause the CPU to perform the steps of changing the processor system from a first operating mode that does not retain random access memory (RAM) data values ​​to a second operating mode by: energizing the RAM, setting the stack pointer value to an address in the second RAM region as a stack, copying the RAM image from the second non-volatile memory region to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region.

[0023] In one or more embodiments, the computer program product may further include instructions that cause the CPU to perform the following steps: setting the stack pointer to an address in a second RAM region and copying RAM image data from a first RAM region to a second non-volatile memory region. Attached Figure Description

[0024] In the accompanying drawings and description, the same reference numerals refer to the same features. Embodiments will now be described in detail only by way of examples shown in the accompanying drawings, in which:

[0025] Figure 1 A processor system configured to switch between a first operating mode and a second operating mode is shown according to an example embodiment.

[0026] Figure 2A Show Figure 1 The method for switching the processor system from the first operating mode to the second operating mode.

[0027] Figure 2B This indicates that the data is generated before or during the transition from the second operating mode to the first operating mode. Figure 1 A method for processing the RAM image of a processor system.

[0028] Figure 3A An example embodiment of the RAM configuration of a processor system is shown when a RAM image is generated before or during the transition from a second operating mode to a first operating mode.

[0029] Figure 3BThis illustrates a typical configuration of the processor system program memory used to hold context data.

[0030] Figure 3C The diagram illustrates the configuration of a processor system program memory for maintaining program context data according to an embodiment.

[0031] Figure 3D An example embodiment of a flash memory configuration for a processor system including RAM images is shown.

[0032] Figure 3E An example embodiment of the RAM configuration of the processor system is shown in the case where RAM image data is recovered from flash during or after the transition from a first operating mode to a second operating mode.

[0033] Figure 4 This illustrates the generation process in a processor system according to an embodiment. Figure 3A The RAM image data shown is saved to... Figure 3D The method for flash memory is shown.

[0034] Figure 5A This illustrates how RAM image data is transferred from a processor system, such as according to an embodiment. Figure 3D The flash memory shown is restored to the state shown. Figure 3E The RAM method is shown.

[0035] Figure 5B An alternative method for restoring program context data from flash memory to RAM in a processor system is shown according to an embodiment.

[0036] Figure 6A This shows the power consumption of a typical processor system configured as an IoT device under different operating modes.

[0037] Figure 6B The power consumption of a processor system configured as an IoT device according to an embodiment is shown in different operating modes.

[0038] Figure 6C The power consumption of a processor system configured as an IoT device according to an embodiment is shown in different operating modes. Detailed Implementation

[0039] Figure 1A processor system 100 configured to operate in a first mode and a second mode according to an embodiment is illustrated. One processor system in this disclosure may include any device or system configured to communicate with another device or system via wired or wireless communication. The processor system 100 may be a single device including a central processing unit (CPU) 102, which may be a microprocessor or microcontroller. The CPU 102 may include a plurality of registers, including a stack pointer register. The processor system 100 may further include: a communication interface 104, which may be, for example, a wired or wireless transceiver for communicating with other devices; a direct memory access (DMA) controller 106; random access memory (RAM) 108; and non-volatile memory 116. The processor system 100 may include a power management module 122, which may be controlled by the CPU 102 to power on or off the RAM 108 via a power control connection 124. CPU 102, transceiver 104, DMA controller 106, RAM 108, non-volatile memory 116, and power management module 122 may be coupled together via communication bus 114. In some examples, processor system 100 may be implemented on a single device, such as a system-on-a-chip (SoC). In some examples, non-volatile memory 116 and / or RAM 108 may be implemented on one or more separate devices.

[0040] The processor system 100 may also include other peripheral devices (not shown) that can be coupled to the communication bus 114. The DMA controller 106 and other peripheral devices may have interrupt connections to the CPU 102 (not shown). As used herein, the term RAM may refer to any volatile read-write memory that loses information when power is off. The term non-volatile memory may refer to any read-write memory that retains information when power is off, such as flash memory. Memory addresses mentioned herein may refer to physical addresses or virtual addresses.

[0041] RAM 108 has a first region 110 configured to store a RAM image. The RAM image includes data for a software stack used by the CPU. RAM 108 has a second region 112 that can be configured as a secondary stack. Non-volatile memory 116 has a first non-volatile memory region 118 that can be used to store software or firmware, which includes a series of instructions executed by CPU 102 in various operating modes. Non-volatile memory 116 has a second non-volatile memory region 120 that can store a RAM image.

[0042] During operation, the processor system 100 can switch between a first operating mode and a second operating mode. For example, the first operating mode can be a low-power state, such as a power-off state where the device is completely powered down or a RAM-off state where RAM 108 is powered down but other functions of the processor system 100 remain powered. In this first operating mode, the contents of RAM 108 are no longer valid. The first operating mode can also be a reset state caused by a hardware or software reset operation, in which the data in RAM is erased. The second operating mode can be a mode in which the processor system 100 is in normal operating condition and all functions are enabled. The second operating mode can include an idle state where the CPU 102 of the processor system 100 has completed all pending tasks. For embodiments of the processor system included in wireless network node devices such as Internet of Things (IoT) devices, during normal operation, the processor system 100 can, for example, record sensor values ​​such as temperature, pressure, humidity, or other values ​​via appropriate sensors (not shown), and subsequently transmit the sensor values ​​via communication interface 104. After completing this operation, the processor system 100 can then switch back from the second operating mode to the first operating mode to conserve power. For devices such as IoT devices or other battery-powered devices, minimizing power consumption is crucial, especially when inactive.

[0043] Figure 2A This shows the transition from the first operating mode to the second operating mode. Figure 1 The illustrated method of operation 130 for the network node device 100 is as follows: In step 132, RAM 108 may be enabled. In step 134, CPU 102 may use a second RAM region 112 as an auxiliary stack, and thus allocate the second RAM region 112 as a stack by, for example, changing the stack pointer to an address within the second RAM region 112. In step 136, a RAM image including program context data is copied from a second non-volatile memory region 120 to a first RAM region 110. The RAM image contains data segments typically used by CPU 102 and may include program context data, which includes initialization data segments, zero-initialization segments typically referred to as BSS segments, a stack, and a heap. In some embodiments, the stack segment may be located at a memory address lower than the heap. The RAM image may also include device-specific hardware configuration parameters, which may be included in separate segments.

[0044] In some examples, a DMA transfer, typically performed by a faster DMA controller 106, can be used to copy the RAM image from the second non-volatile memory region 120 to the first RAM region 110. In other examples, the CPU 102 can perform the memory transfer directly, in which case the DMA controller 106 can be omitted. Once the program context data has been transferred to the second RAM region 110, in step 138, the CPU 102 can begin reusing the stack restored to the RAM image in the first RAM region by changing the stack pointer to the address of the segment in the first RAM region allocated as a stack. The RAM image may contain program context data representing the state of the processor system 100. This processor system state may correspond, for example, to an idle state just before the processor system transitions to a first low-power operating mode. The RAM image may contain the software stack captured when the processor system 100 is in a second operating mode. Additionally, the RAM image may include necessary configuration data, such as hardware configuration register values, network parameter values, and CPU 102 core register values.

[0045] The inventors of this disclosure have learned that, for some processor systems, saving a RAM image to a flash (typically only once) and subsequently restoring the RAM image stored in the flash can reduce the transition time between a first operating mode and a second normal operating mode, such as a standby or power-down mode, compared to a full boot process. Power consumption during system startup can also be reduced by avoiding a complete reinitialization of the RAM.

[0046] Because the transition time between the two operating modes is reduced, the inventors have further learned that, in low-power or standby modes, the processor system 100 can completely power down the RAM 108 without compromising performance. Since the RAM 108 may consume significant leakage current even in standby operating mode, power consumption in standby mode can be significantly reduced. Using the second RAM region 112 as an auxiliary stack during transitions between operating states avoids corruption of stack information captured as part of the RAM image.

[0047] In some embodiments, RAM image data common to all devices may be written to flash memory 116 during generation and subsequently used directly by processor system 100. In other examples, processor system 100 may generate the required RAM image after the program has fully started and just before processor system 100 transitions from normal operating mode to standby operating mode.

[0048] Figure 2BA method 140 for generating a RAM image is illustrated. In step 142, CPU 102 may use the second RAM region 112 as an auxiliary stack, for example, by changing the stack pointer to an address within the second RAM region 112. Changing the stack pointer may maintain the stack state within the RAM image of the first memory region 110. In step 144, the RAM image, including program context data, may be copied or transferred from the first RAM region 110 to the second non-volatile memory region 120. This transfer may be performed directly by CPU 102 or by using DMA controller 106 to perform a DMA transfer. After transferring the program context data to the non-volatile memory 116, in step 146, the RAM is disabled or powered off, and the processor system 100 may then enter a first operating state that is ready for use.

[0049] Method 140 for generating RAM context data may typically be used very infrequently, for example, when first powered on for use within a network, or after an over-the-air or network-based software or firmware update, because using the method can cause changes to the data in the RAM image. In some example embodiments, method 140 may be used only once during the lifetime of processor system 100.

[0050] Figure 3A An example embodiment of the configuration of RAM 200 of the processor system is shown when program context data is generated before or during a transition from a second operating mode to a first operating mode. As shown, the addresses of RAM 200 can be considered to increase from left to right. RAM 200 may include a first region that includes RAM image 210. RAM image 210 may include a header 202, configuration parameters 204, program context data 206, and a tail 208.

[0051] The header may consist of a magic value 222 and a RAM image size value 224. The header 202 may also include a start address value 226, which indicates the starting address in the RAM where the configuration parameter 204 resides, or more generally, indicates the starting location for copying the RAM image from flash to RAM. In the example where only program context data 206 is saved, the start address value 226 may indicate the starting address of the program context data 206. The configuration parameter 204 may include hardware configuration parameters 212, such as hardware peripheral register values ​​in the processor system. Optionally, a configuration transfer end marker 218 may be located at the end of the configuration parameter 204.

[0052] For wireless network node devices, configuration parameter 204 may also include transceiver parameters or communication interface parameters, such as radio parameters like radio physical, MAC, and link layer parameters. Radio parameters may include amplifier tuning values, which may be specific to each device after radio transceiver calibration. Configuration parameter 204 may also include CPU register values ​​216. Program context data 206 may include data representing the state of the processor system's software stack in a second operating mode. Tail 208 includes an image transfer end marker 230 that defines the end of RAM image 210. Header 202 can be used to provide characteristics of the RAM image being recovered, and tail 208 can be used during the recovery process to determine that program context data 206 and optionally configuration parameter 204 have been correctly recovered. Physical RAM 200 also includes a second region comprising an auxiliary stack 220.

[0053] Figure 3B This illustrates a typical configuration of program context data 206 comprising multiple sections or segments. These sections or segments, in ascending order of memory address range, are: data segments 232 of any global or static variables with predefined values; uninitialized data segments 234, conventionally referred to as BSS segments; heap region 236; and stack region 238. Program code or text segments or sections reside in non-volatile memory and are therefore not part of the context data as described herein. During normal operation, stack 238 is filled in descending address order, and heap 236 is filled in ascending address order. As shown in the conventional arrangement 206, heap 236 and stack 238 fill unused memory regions 209 toward each other (i.e., converge) such that when the stack pointer and heap pointer are at the same location, no more memory is available.

[0054] Figure 3C An alternative configuration of processor or program context data 206' comprising multiple segments or fragments is shown. These segments or fragments are, in order of increasing memory address range, stack 238, data fragment 232 of any global or static variables with predefined values, bss fragment 234, and heap region 236. In the arrangement of processor context data 206', during normal operation, heap 236 and stack 238 are spaced apart from each other (i.e., diverging) to fill unused regions 209 of memory. The inventors of this disclosure have further understood that by organizing program context data 206' in this manner, the RAM image does not contain unused regions 209 of memory 200 when the RAM image is saved to flash memory. Therefore, the size of the saved RAM image is smaller, which reduces the time and power consumption required to save the RAM image to or restore the RAM image from flash memory.

[0055] Figure 3DAn example embodiment of a flash memory 240 configuration of a processor system including a RAM image is shown. The flash memory 240 includes a first region containing firmware binary 232 for execution by a processor (e.g., CPU 102 of a network node device). A RAM image 210 is located in a second region of the flash memory 240.

[0056] Figure 3E An example embodiment of the RAM configuration 200' of the processor system is shown before or during a transition from a first operating mode to a second operating mode, and after the RAM context data is recovered from flash 240. RAM 200' may include a first region comprising RAM image 210'. RAM image 210' may include configuration parameters 204, program context data 206, and a tail 208.

[0057] Figure 4 A method for generating a RAM image 250 in RAM and storing it in flash memory for a processor system according to an embodiment is illustrated. The processor system may be in an operating mode where, for example, the software has configured the context of all drivers, the hardware is fully configured, and the processor system has no other tasks pending, but the setup for any future tasks has been completed. Example future tasks may include the expiration of any timer or wireless networking for any radio event.

[0058] In step 252, the values ​​of the CPU core registers, any hardware peripheral registers, and any radio link parameters can be saved to configuration parameter field 204. Saving and restoring the CPU core registers can be performed, for example, by calling the "Setjump" and "Longjump" functions implemented in the C standard library.

[0059] In step 254, the processor can switch to using the secondary stack 220 by changing the position of the stack pointer. This operating mode can be, for example, an idle state before the processor system saves the RAM image to the flash. This prevents corruption of the RAM image saved to the flash.

[0060] In step 256, header 202 and tail 208 may be added to the RAM area storing RAM image 210. In step 258, RAM image 210 in RAM 200 may be copied to flash memory 240. This copying step 258 may be performed, for example, by CPU 102 in processor system 100. In other examples, copying step 258 may be performed by DMA transfer using DMA controller 106.

[0061] In some examples, method 250 may be implemented as part of firmware binary 232 stored in flash memory 240. In other examples, RAM image 210 may be generated by a single device implementing method 250. The resulting RAM image may then be retrieved, for example, via a JTAG interface. This RAM image may then be written as part of the generation process to flash memory in a copy of the processor system. Method 250 uses an auxiliary stack 220 to prevent RAM image 210 from being corrupted during copying.

[0062] Figure 5A A method for restoring RAM image 260 for a processor system transitioning from a first operating mode to a second operating mode is shown. This method 260 may be implemented, for example, on processor system 100.

[0063] The processor system may be in a first operating mode, such as a low-power standby state where RAM is powered off. The first operating mode may also include a reset state where RAM contents have been erased. After booting the software or firmware 232, in step 262, RAM 200 may be powered on, and the stack pointer may be set to an address in the first RAM region. Booting may be caused by, for example, a power reset, a hardware reset, or waking from a low-power mode where RAM is powered off.

[0064] In step 264, the header magic value 222 is checked. If this magic value 222 matches, method 260 proceeds to step 266, and the checksum 228 previously calculated based on magic value 222, RAM size 224, and RAM start address 226 is checked. If checksum 228 matches, the method proceeds to step 268, checking whether the image transfer end flag 230 of RAM image tail 208 is valid, and thus verifying that all data has been transferred. RAM image tail 208 is located at the position calculated based on RAM size 224. The checks in steps 264, 266, and 268 improve the robustness of the processor system if an invalid or incomplete RAM image is stored, for example, in the event of a power outage during RAM image copying. An undetected invalid RAM image may cause the processor system to fail to boot properly or not at all. The checks in steps 264, 266, and 268 ensure that the various fields in RAM image header 202 are valid and that the complete RAM image 210 has been copied to the flash. If any of the checks in steps 264, 266, and 268 do not match, the method proceeds to step 266, where the transfer process ends and the normal full startup sequence continues. If all checks in steps 264, 266, and 268 are successful, the method proceeds to step 270, and the stack pointer is changed to a second RAM area corresponding to the auxiliary stack 220 that will not be overwritten by the RAM image data 210.

[0065] In step 272, the RAM image size 224 and start address 226 of the RAM image 210 in RAM 200 can be read from the RAM image header 202. A DMA transfer can be initiated from flash 240 to RAM 200'. The DMA transfer of image data 210 does not require copying the header 202 in flash 240, but may require the tail 208 to confirm the completion of the transfer.

[0066] In step 274, a check can be performed to determine when the transfer of RAM image data 210' is complete. This check can be performed, for example, by the CPU 102 in the processor system 100 polling the status register in the DMA 106 to determine completion. Alternatively, the CPU 102 can execute a Wait-for-Interrupt (WFI) instruction and resume execution when the DMA controller 106 generates a transfer completion interrupt signal and the CPU 102 can detect a transfer interrupt line from the DMA controller 106. Alternatively or additionally, the CPU 102 can check whether an image transfer end flag 230 exists at the expected tail position 208 in RAM 200. At the start of the transfer, the value at the tail position 208 in RAM 200 is empty, and subsequently, once the transfer is complete, the value present at the tail position 208 should be equal to the image transfer end flag 230. The image transfer end flag 230 can be a predetermined value, such as 0xDEADBEEF.

[0067] Once the transfer is complete, method 260 proceeds to step 276, and the configuration parameters 204 are restored to the appropriate registers in the network node device via CPU 102. The CPU register value 216, including the stack pointer value, can be restored, for example, by implementing the Longjump function from the C standard library. Restoring the CPU register value sets the stack pointer to the first memory region now containing the restored RAM image 210.

[0068] In step 278, the processor system can continue in the second operating mode. The processor system can then continue operation, for example, by the processor revealing an interrupt, exiting an idle task, and then processing any upcoming events.

[0069] Hardware (HW) reconfiguration for configuration parameter 204 can take a considerable amount of time, which may affect the overall recovery time. Figure 5B An alternative recovery method 260' that can improve overall recovery time is shown. Hardware configuration parameters 204 may optionally include a configuration transfer end flag 218, for example, to indicate that the processing hardware configuration should be processed as a separate dedicated segment at the beginning of RAM image 210 before program context data 206.

[0070] The initial steps 262, 264, 266, 267, 268, and 270 of method 260' are the same as those described in method 260. After step 270, in step 280, the DMA transfer from flash 240 to RAM 202' of configuration parameter 204 begins.

[0071] In step 282, the transfer of configuration parameters 204 can be determined, for example, by checking whether configuration transfer end flag 218 has been copied to RAM 200'. Once the transfer is complete, method 260' proceeds to step 284 and initiates a DMA transfer of program context data 206 from flash 240 to RAM 202'. In step 286, configuration parameters 204, excluding CPU register values, can be restored to the appropriate registers in the processor system. In step 288, the transfer can be determined, for example, by checking image transfer end flags. Once the transfer of RAM image data 210 and tail 208 is complete, the method proceeds to step 289, where CPU register values ​​216, including stack pointer register values, can also be restored, for example, by calling the Longjump function in the C standard library. Therefore, the stack pointer is set to an address in a first memory region corresponding to the stack location in processor context data 206, 206'. In step 290, the processor system can continue in a second operating mode by using the first RAM region to continue program execution. The processor system can then continue operating, for example, by the CPU exposing an interrupt, exiting an idle task, and then processing upcoming events on the restored stack.

[0072] To store the hardware parameters at the beginning of RAM image 210 in the first segment, placement and inclusion of global variables for hardware recovery mechanisms may be required in the linker script. A configuration end marker 218 can be placed at the end of this hardware configuration segment 204, and this end can be checked to verify that these parameters have been recovered.

[0073] In other examples, instead of initiating a potentially time-consuming second DMA process targeting program context data 206, a single DMA transfer can be initiated against the complete RAM image 210', as in method 260. However, instead, the CPU waits for the configuration end flag 218 to be set before applying configuration parameters 204. The duration of RAM recovery method 260' is negligible compared to a complete device reinitialization. Method 260' allows for parallel execution of CPU and DMA operations, and thus reduces the power consumption of the RAM recovery mechanism, as the processor or CPU of the processor system can be active during the recovery process for other processing tasks.

[0074] Figure 6AThe diagram 300 shows power consumption on the y-axis 304 versus time on the x-axis 302 for a typical processor system configured as an IoT device under different operating modes. During the initial phase 310 after power-on, the IoT device can perform a full startup, after which it can enter a normal operation phase 312. The initial phases 310 and 312 can consume a relatively large amount of power. After completing normal operation (which may include activities such as RF announcements if the IoT device is wireless), the IoT device can transition to a low-power mode for a relatively long time period 314, during which power consumption can be divided into two elements. A first leakage current element 308 may be power consumption due to current drawn by all IoT devices, excluding RAM. A second leakage current element 306 may be current consumption due to RAM leakage current. The IoT device can then repeatedly switch between the normal operation phase 312 and the low-power operation phase 314.

[0075] Figure 6B Curve 350 shows the power consumption on the y-axis 354 versus time on the x-axis 352 for a processor system configured as an IoT device according to an embodiment in different operating modes. During the initial phase 360 ​​after the device is powered on, the IoT device can perform a full startup, after which the IoT device can be in the normal operation phase 362. After the first initial phase 362, the IoT device can use, for example, during phase 366. Figure 2B The method 140 described herein performs a RAM image data saving operation to save RAM image data to non-volatile memory, such as flash memory. The IoT device can then transition to a low-power mode during the RAM power-off period 364. In this case, since the leakage current 358 does not include leakage current due to RAM, the power consumption in low-power mode can be significantly less than that of a typical IoT device. At the end of the low-power mode phase 366, during the recovery phase 370, the IoT device can power on the RAM and recover the RAM image using the method and apparatus described herein. After the subsequent normal operation phase 362, there is no need to repeat the saving operation 366, and the IoT device can directly transition from normal operation mode 362 to low-power mode 364. However, the RAM recovery operation 370 can be repeated whenever there is a transition from low-power mode phase 364 to normal phase 362.

[0076] Figure 6CCurve 350' shows the power consumption on the y-axis 354 versus time on the x-axis 352 for a processor system configured as an IoT device according to an embodiment in different operating modes. Curve 350' illustrates an embodiment of the IoT device where RAM context data is generated offline and included in flash memory or other non-volatile memory. In this case, the complete initial startup sequence 360 ​​and RAM save sequence 366 may not be required. The IoT device can use RAM recovery operation 370 to transition from a lower power mode phase 364 to a normal mode phase 362.

[0077] Embodiments of processor systems including wireless transceivers can be included in IoT devices with inactive cycles that transition to low-power modes, such as Bluetooth Low Energy (BLE), Zigbee, GenFSK, and threading technologies. IoT devices or other network node devices may consider battery life a critical parameter to maintain and may require battery life exceeding several years. IoT devices and other network node devices can be configured for, for example, tire pressure monitoring systems (TPMS), portable information terminals for building or vehicle access using ultra-wideband radio transceivers, temperature sensors for monitoring temperature in remote locations, or any other sensors such as current sensors.

[0078] Implementations of the processor system may provide intelligent mechanisms to switch the RAM state to a disconnected mode, thereby preventing RAM leakage in low-power mode and thus avoiding increased wake-up time from low-power mode and the resulting high current consumption. Implementations of the processor system may also reduce current consumption in low-power mode and reduce current consumption during the wake-up time when transitioning to normal operating mode.

[0079] Saving RAM leakage current in low-power modes may be more important for devices employing low-transistor-size technologies, where leakage in RAM (typically SRAM) is much higher. For network node devices, such as IoT devices, which may operate in low-power modes for extended periods, the power savings could be even greater.

[0080] This disclosure describes a processor system and method. The processor system includes: a central processing unit (CPU) including registers for storing a stack pointer value; and non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM image including program context data. The processor system includes random access memory (RAM) coupled to the CPU and having the first RAM region and the second RAM region. The processor system is configured to have a first operating mode that does not retain RAM data values ​​and a second operating mode that powers on the RAM. In operation, the processor system changes from the first operating mode to the second operating mode by: applying power to the RAM, setting the stack pointer value to an address in the second RAM region, copying program context data from the second non-volatile memory region to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region.

[0081] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or machine programmed with and controlled by the executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0082] In other examples, the instruction set / methods illustrated herein, along with their associated data and instructions, are stored in a corresponding storage device, which is implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture may refer to any single or multiple components manufactured. The one or more non-transitory machine- or computer-usable media defined herein do not include signals, but such one or more media are capable of receiving and processing information from signals and / or other transient media.

[0083] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via networks, computers, or data-based devices and / or services. These may include cloud, internet, intranet, mobile devices, desktops, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0084] In one example, one or more instructions or steps discussed in this article are automated. The terms automation or automaticity (and similar variations) mean the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0085] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalization of such novel feature as expressly or implicitly disclosed herein, regardless of whether such novel feature relates to the same invention as currently claimed in any of the claims or whether such novel feature alleviates any or all of the same technical problems as those alleviated by this invention.

[0086] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the case of a single embodiment may also be provided individually or in any suitable sub-combination.

[0087] The applicant hereby reminds that new claims may be made for such features and / or combinations thereof during the examination of this application or any other application derived therefrom.

[0088] For completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude multiple, a single processor or other unit can perform the functions of several components described in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A processor system, characterized by comprising: a central processing unit, CPU, including a register for storing a stack pointer value; a random access memory, RAM, coupled to the CPU and having a first RAM region and a second RAM region; a non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM image including program context data; and wherein the processor system is configured to have a first operating mode that does not preserve the RAM data values and a second operating mode in which the RAM is powered on, and is further configured to change from the first operating mode to the second operating mode by: applying power to the RAM, setting the stack pointer value to an address in the second RAM region, copying the program context data from the second non-volatile memory region to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region; wherein program context data includes a stack region and a heap region arranged toward opposite ends of the program context data, the stack region and the heap region separated by an uninitialized data segment and a data segment, and wherein in the second operating mode, the stack and the heap are configured to increase in opposite directions.

2. The processor system of claim 1, wherein in the first operating mode, the RAM is powered off or reset.

3. The processor system according to claim 1 or 2, characterized by the RAM image further includes header data and trailer data.

4. The processor system of claim 3, wherein further configured to copy the trailer data to the first RAM region.

5. The processor system of claim 3, wherein, the header data includes a magic value, a RAM image size value, a RAM image start address, and a checksum, and the trailer data includes an end of transmission flag.

6. The processor system according to claim 1 or 2, characterized by further comprising a communication interface coupled to the CPU, and wherein the RAM image further includes hardware configuration parameters, the hardware configuration parameters including at least one of a CPU register value, a peripheral register value, and a communication parameter value.

7. The processor system of claim 6, wherein the hardware configuration parameters are copied to the RAM prior to the program context data.

8. The processor system of claim 7, wherein, the CPU is configured to update hardware peripherals and transceivers with the hardware configuration parameters while at least a portion of the program context data is being copied.

9. The processor system according to claim 1 or 2, characterized by further configured to set a stack pointer to an address in the second RAM region, and copy RAM image data from the first RAM region to the second non-volatile memory region.

10. A method of changing a processor system from a first mode of operation that does not retain random access memory (RAM) data values to a second mode of operation, the method comprising: the processor system comprising: a central processing unit, CPU, including a stack pointer register; a non-volatile memory coupled to the processor and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM image including program context data; a RAM coupled to the CPU, the RAM having a first RAM region and a second RAM region; the method comprising: powering up the RAM, setting a stack pointer value to an address in the second RAM region that is a stack, copying the RAM image from the second region of non-volatile memory to the first RAM region, and setting the stack pointer value to an address within a segment of the first RAM region; wherein the program context data comprises a stack region and a heap region arranged towards opposite ends of the program context data, the stack region and the heap region being separated by an uninitialized data segment and a data segment, and wherein in the second mode of operation, the stack and the heap are configured to increase in opposite directions.

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