Intermetallic dielectric layer and manufacturing method thereof and semiconductor device

Abstract

The present invention relates to an intermetallic dielectric layer, a manufacturing method thereof and a semiconductor device. The manufacturing method of the intermetallic dielectric layer comprises: obtaining a base structure formed with a metal structure, the surface of the metal structure being covered by an SRO layer; forming a silicon nitride layer with compressive stress on the surface of the SRO layer on the side wall of the metal structure; filling fluorine-containing silicon glass so that it covers the metal structure, the SRO layer and the silicon nitride layer as an intermetallic dielectric layer. The present invention sets a silicon nitride layer between the SRO layer and the fluorine-containing silicon glass. Since the silicon nitride layer has compressive stress, it can suppress the microscopic deformation of the metal structure caused by the thermal process (the expansion coefficient of the metal structure is larger than the expansion coefficient of the fluorine-containing silicon glass, so the microscopic deformation of the metal structure is large during the temperature change process). Furthermore, since the strength of silicon nitride is relatively large, the newly added silicon nitride layer can prevent the metal structure from being deformed and causing the SRO layer to break, and prevent the subsequent free fluorine ions in the fluorine-containing silicon glass from entering and corroding the metal structure to cause voids.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device, and also to an intermetallic dielectric layer and a manufacturing method of the intermetallic dielectric layer. Background Art

[0002] AL / Cu (0.5%) alloy is a material widely used in semiconductor back end of line (BEOL) as the lead wire of integrated circuits. Its main features include low resistance, good conductivity, easy processing to meet the design requirements of chips with different structures, and adding a proper amount of Cu to AL can also increase its anti-electromigration properties. At present, AL / Cu alloy is mainly used for metal wires with a line width of 110nm and above. As chips develop towards smaller sizes, some problems of AL / Cu alloy as metal connecting wires are gradually exposed.

[0003] Figure 1 This is an electron microscope photo of a device sample that uses Al / Cu alloy as the metal layer (metal connecting line). It can be seen that a void is formed inside the metal at the marked position (oval frame). If the void is serious, it will cause a metal short circuit. The main manifestation is that the reliability test resistor mobility is too large, resulting in reliability failure. Summary of the invention

[0004] In view of the above problems, it is necessary to provide an intermetallic dielectric layer and a manufacturing method thereof and a semiconductor device.

[0005] A method for manufacturing an intermetallic dielectric layer comprises: obtaining a base structure formed with a metal structure, the surface of the metal structure being covered by an SRO layer; forming a silicon nitride layer with compressive stress on the surface of the SRO layer on the side wall of the metal structure; and filling fluorine-containing silicon glass to cover the metal structure, the SRO layer and the silicon nitride layer as an intermetallic dielectric layer.

[0006] In one embodiment, the silicon nitride layer is a silicon nitride with a loose and porous structure so as to reduce the dielectric constant.

[0007] In one of the embodiments, the compressive stress of the silicon nitride layer is 50 MPa to 180 MPa.

[0008] In one of the embodiments, the step of forming a silicon nitride layer with compressive stress on the surface of the SRO layer is to deposit the silicon nitride layer using a plasma enhanced chemical vapor deposition process.

[0009] In one of the embodiments, the radio frequency power of depositing the silicon nitride layer is 800-900W, and the reaction pressure is 3-5 Torr.

[0010] In one of the embodiments, before the step of forming a silicon nitride layer on the surface of the SRO layer, the step further includes performing surface treatment on the SRO layer to form silicon dangling bonds on the surface of the SRO layer.

[0011] In one embodiment, the step of performing surface treatment on the SRO layer includes performing plasma bombardment treatment on the surface of the SRO layer using a gas containing a silicon source.

[0012] In one embodiment, the gas includes SiH 4 as a silicon source and helium as a carrier gas.

[0013] In one embodiment, the manufacturing steps of the metal structure include: forming an oxide layer on a substrate; forming a first adhesion layer on the oxide layer, the first adhesion layer comprising titanium and titanium nitride; forming a metal layer on the first adhesion layer, the metal layer comprising an aluminum-doped copper alloy; forming a second adhesion layer on the metal layer, the second adhesion layer comprising titanium and titanium nitride; photolithography and etching the second adhesion layer, the metal layer and the first adhesion layer to form the metal structure.

[0014] An intermetallic dielectric layer comprises a fluorine-containing silicon glass layer, wherein the fluorine-containing silicon glass layer covers a metal structure having an SRO layer formed on the surface, and further comprises a silicon nitride layer arranged between the fluorine-containing silicon glass layer and the SRO layer, wherein the silicon nitride layer has compressive stress.

[0015] In one embodiment, the silicon nitride layer is a silicon nitride with a loose and porous structure so as to reduce the dielectric constant.

[0016] In one embodiment, the sum of the thickness of the SRO layer and the silicon nitride layer does not exceed

[0017] A semiconductor device comprises a device substrate, a first metal structure, a second metal structure, an interlayer dielectric layer between the device substrate and the first metal structure, and an intermetallic dielectric layer between the second metal structure and the first metal structure, wherein the intermetallic dielectric layer is the intermetallic dielectric layer described in any of the foregoing embodiments.

[0018] In the above-mentioned intermetallic dielectric layer, its manufacturing method and semiconductor device, a silicon nitride layer is arranged between the SRO layer and the fluorine-containing silicon glass. Since the silicon nitride layer has compressive stress, it can suppress the microscopic deformation of the metal structure caused by the thermal process (the expansion coefficient of the metal structure is larger than that of the fluorine-containing silicon glass, so the microscopic deformation of the metal structure is large during the temperature change process). Furthermore, since silicon nitride has a large strength, the newly added silicon nitride layer can prevent the deformation (expansion or contraction) of the metal structure from causing microcracks or even fractures in the SRO layer, and prevent the subsequent free fluorine ions in the fluorine-containing silicon glass from entering and corroding the metal structure to cause voids. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0020] Figure 1 This is an electron microscope photo of a device sample using Al / Cu alloy as the metal layer (metal connecting wire);

[0021] Figure 2 is a flow chart of a method for manufacturing an intermetallic dielectric layer in one embodiment;

[0022] Figure 3 is a flow chart of forming a metal structure in one embodiment;

[0023] Figure 4 is a schematic cross-sectional view of a device after step S210 is completed in one embodiment;

[0024] Figure 5 is a schematic cross-sectional view of a device after step S220 is completed in one embodiment;

[0025] Figure 6 yes Figure 5 Schematic diagram of compressive stress in silicon nitride layer of the structure shown;

[0026] Figure 7 FIG. 1 is a schematic diagram of forming silicon dangling bonds on the surface of an SRO layer in one embodiment. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0029] It should be noted that when an element is referred to as "fixed on" another element, it can be directly on another element or there can also be a centered element. When an element is considered to be "connected" to another element, it can be directly connected to another element or there may be a centered element at the same time. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for the purpose of illustration. When an element or layer is referred to as "on...", "adjacent to...", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be an intermediate element or layer. On the contrary, when an element is referred to as "directly on...", "directly adjacent to...", "directly connected to" or "directly coupled to" other elements or layers, there is no intermediate element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0030] When the terms "comprise" and / or "include" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. The singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0032] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0033] As chips develop towards smaller sizes, some problems with AL / Cu alloys as metal connecting wires have gradually become apparent, such as electromigration, stress migration, and the formation of interlayer capacitance between metals that affects circuit transmission efficiency. Among them, stress migration is a stress mismatch caused by different expansion coefficients of thin film materials in each layer during chip manufacturing, resulting in different expansion and contraction ratios during thermal reactions. The stress migration phenomenon between metals and between metal layers is mainly manifested in the stress mismatch between AL / Cu alloys and intermetallic dielectrics (Inter Metal Dielectric, IMD). The reason is that the thermal expansion coefficients of AL / Cu alloys and intermetallic dielectrics are different. During the thermal reaction and subsequent testing, the internal vacancies migrate and aggregate when the aluminum strips expand and contract microscopically during the heating and cooling process, forming voids inside the AL / Cu alloy, such as Figure 1 shown.

[0034] The main solutions to stress migration in AL / Cu connections are: ① Changing the shape of metal connecting wires to release residual stress; ② Adding dummy metal wires to receive the voids caused by stress migration; ③ Changing the number and size of grain boundaries in the AL / Cu alloy through annealing at a certain temperature; ④ Adding other metals to the AL / Cu alloy and using the principle of electrochemical reaction to prevent stress migration.

[0035] The above technologies have the following disadvantages: ① Changing the shape of metal wiring requires adding more photomasks; ② When adding dummy metal wires, if the number of vacancies in the metal wires increases, it will cause short circuit risks and increase the chip area; ③ When annealing treatment changes the size of grain boundaries, their number and size are difficult to monitor; ④ When other metals are introduced into AL / Cu, the resistance of the wire may increase.

[0036] The present application introduces a layer of silicon nitride with special properties between the SRO (Silicon rich oxygen) layer and the fluorine-containing silicon glass (FSG) layer of the metal interlayer dielectric layer, and suppresses the microscopic deformation of the metal connection through the mutual transfer of film stress, thereby reducing the risk of metal voids caused by stress migration during the thermal process. Figure 2 1 is a flow chart of a method for manufacturing an intermetallic dielectric layer in an embodiment, comprising the following steps:

[0037] S210, obtaining a base structure formed with a metal structure, wherein a surface of the metal structure is covered by an SRO layer.

[0038] The metal structure is the structure of a certain metal layer. The intermetallic dielectric layer is an insulating isolation medium between different layers of metal in an integrated circuit. Therefore, the manufacture of the intermetallic dielectric layer is carried out after the formation of the lower metal layer (such as Metal-1). Before forming the lower metal layer, the front-end process of the wafer process must be completed first, such as forming a base structure including a substrate, shallow trench isolation (STI), an active area, a gate and other structures. An interlayer dielectric (ILD) layer is also formed between the bottom metal layer and the substrate.

[0039] Before forming the metal structure, a base structure may be formed using methods known in the art. In one embodiment, forming the base structure includes the following steps:

[0040] Step 1, forming STI in the substrate. Usually, the active area (AA) is defined by STI or other insulating isolation structures known in the art and serves as an isolation structure between devices. The substrate is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). In this embodiment, the constituent material of the substrate is single crystal silicon.

[0041] Step 2: forming a well region. The well region may be formed by ion implantation or other commonly used processes in the art.

[0042] Step three, forming a gate. After forming the gate dielectric layer, a gate material may be deposited on the gate dielectric layer, and then the desired gate structure may be formed by photolithography and etching. The material of the gate dielectric layer may be silicon dioxide, and the gate material may be polysilicon. In other embodiments, the gate dielectric layer may also include conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). In other embodiments, the gate material may also use metals, metal nitrides, metal silicides, or similar compounds.

[0043] Step 4: doping the active region: doping the active region structures such as source and drain by ion implantation or other doping processes known in the art to adjust the doping concentration to the required level.

[0044] Step 5: Form metal silicide on the surface of the structure that needs to be led out through the wire. The source, drain, gate and other structures need to be led out through the wire, and metal silicide can be formed on the upper surface of these structures to reduce the contact resistance.

[0045] Before forming the metal structure, an interlayer dielectric needs to be formed, and the metal structure is formed on the interlayer dielectric.

[0046] See also Figure 3 In one embodiment, forming the metal structure involves the following steps:

[0047] S110, forming an oxide layer on the substrate.

[0048] In one embodiment, a layer of silicon dioxide is deposited on the substrate on which the metal structure is to be formed.

[0049] S120, forming a first adhesion layer on the oxide layer.

[0050] The first adhesion layer includes titanium and titanium nitride. In one embodiment, titanium and titanium nitride are formed by a deposition process, specifically, they can be formed by physical vapor deposition and chemical vapor deposition, respectively.

[0051] S130, forming a metal layer on the first adhesive layer.

[0052] The material of the metal layer may be an Al / Cu alloy (aluminum-copper alloy), for example, an Al / Cu alloy with a copper mass fraction of 0.5%. The metal layer may be formed by deposition on the first adhesive layer through a deposition process.

[0053] S140, forming a second adhesive layer on the metal layer.

[0054] The material and preparation process of the second adhesive layer may be the same as those of the first adhesive layer.

[0055] S150, photolithography and etching the second adhesive layer, the metal layer and the first adhesive layer to form a metal structure.

[0056] The metal layer is then photolithographically and etched using a photomask to form a desired specific structure.

[0057] After the metal structure is formed, an SRO layer may be deposited on the surface of the metal structure through a deposition process. Figure 4 is a schematic cross-sectional view of a device after step S210 is completed in one embodiment. Since the substrate structure of the present application does not need to be changed, Figure 4The specific substrate structure is not drawn (ie, structures such as the active region, STI, gate, and ILD are not drawn). Figure 4 The structure shown includes a substrate 10 , a first adhesive layer 21 , a metal layer 22 , a second adhesive layer 23 and a SRO layer 32 .

[0058] S220, forming a silicon nitride layer with compressive stress on the surface of the SRO layer on the sidewall of the metal structure.

[0059] Figure 5 2 is a schematic cross-sectional view of the device after step S220 is completed in one embodiment. Since metal voids caused by stress migration are generally formed on the sidewalls of the metal layer 22, it is necessary to form at least a silicon nitride layer 34 on the sidewalls of the SRO layer 32. In actual manufacturing, in order not to increase the process difficulty, a complete silicon nitride layer 34 can be formed by a deposition process, such as Figure 5 shown.

[0060] S230, filling fluorine-containing silicon glass as an intermetallic dielectric layer.

[0061] Fluorine-containing silicon glass is filled to cover the metal structure, SRO layer 32 and silicon nitride layer 34 as an intermetallic dielectric layer. In one embodiment, the fluorine-containing silicon glass can be filled in the gaps between the metal structures and on the metal structures using a HDPCVD (plasma chemical vapor deposition) process.

[0062] In the above-mentioned method for manufacturing the intermetallic dielectric layer, a silicon nitride layer 34 is disposed between the SRO layer 32 and the fluorinated silicon glass. Since the expansion coefficient of the metal structure (such as aluminum) is larger than the expansion coefficient of the dielectric layer (mainly the fluorinated silicon glass), the microscopic deformation of the metal structure is large during the temperature change process. Since the silicon nitride layer 34 has compressive stress, it can suppress the microscopic deformation of the metal structure caused by the thermal process, see Figure 6 . Furthermore, due to the high strength of silicon nitride, the newly added silicon nitride layer 34 can prevent the metal structure from deforming (expanding or shrinking) and causing microcracks or even fractures in the SRO layer 32, thereby preventing the subsequent free fluorine ions in the fluorine-containing silicon glass from entering and corroding the metal structure to cause voids. Moreover, the manufacturing method of the above-mentioned intermetallic dielectric layer can reduce the impact of stress migration on reliability by optimizing the manufacturing process without changing the metal structure, adding a photomask, or introducing other metals. The process has the advantages of strong feasibility, low cost, and good effect.

[0063] In one embodiment, the stress of the silicon nitride layer 34 formed in step S220 is controlled to be between -50 MPa and -180 MPa, that is, the compressive stress of the silicon nitride layer 34 is between 50 MPa and 180 MPa.

[0064] In one embodiment, the silicon nitride layer 34 formed in step S220 has a loose and porous structure, so as to obtain a silicon nitride layer 34 with a lower dielectric constant. By making the silicon nitride layer 34 loose and porous, the dielectric constant of the silicon nitride layer 34 is reduced, which can minimize the reduction in the response speed of the integrated circuit.

[0065] In one embodiment, step S220 is to deposit the silicon nitride layer 34 using a plasma enhanced chemical vapor deposition (PECVD) process. The specific reaction parameters are a radio frequency power of 800-900W and a reaction pressure of 3-5 Torr. The deposition using the above process parameters can obtain silicon nitride with many microscopic pores and compressive stress.

[0066] Since the silicon nitride layer 34 is newly added, if the thickness of the SRO layer 32+silicon nitride layer 34 is thick, it will have an adverse effect on the electrical performance of the device, such as reducing the response speed of the device. In one embodiment, the total thickness of the SRO layer 32+silicon nitride layer 34 can be kept the same as the thickness of the original single SRO layer, which is equivalent to the thickness of the intermetallic dielectric layer not increasing after the silicon nitride layer 34 is added. Furthermore, the thickness of the SRO layer 32 and the silicon nitride layer 34 can be allocated at a ratio of 1:1.

[0067] For the device process with a line width of 110 nm to 180 nm, the sum of the thickness of the SRO layer 32 and the silicon nitride layer 34 does not exceed In one embodiment, the thickness of the SRO layer 32 is The thickness of the silicon nitride layer 34 is For the embodiment with a line width greater than 180 nm, the total thickness of the SRO layer 32 + the silicon nitride layer 34 can be adjusted appropriately, and the thickness ratio of the SRO layer 32 to the silicon nitride layer 34 can also be adjusted.

[0068] In one embodiment, between steps S210 and S220, a step of surface treating the SRO layer 32 to form silicon dangling bonds on the surface of the SRO layer 32 is also included. As mentioned above, due to the addition of the silicon nitride layer 34, the thickness of the SRO layer 32 is reduced compared to the thickness of the original SRO layer, thereby weakening the ability to block the fluorine ions in the fluorine silicon glass layer from entering the interior of the metal structure. By forming dangling bonds on the surface of the SRO layer 32, the SRO layer 32 can still have excellent performance in capturing metal ions, fluorine ions and water vapor when thinned, so that the SRO layer 32 after thinning can still block the fluorine ions in the fluorine silicon glass layer from entering the interior of the metal structure. On the other hand, the presence of silicon dangling bonds can serve as gas adsorption active sites when the silicon nitride layer 34 is deposited on the surface of the SRO layer 32 on the side wall of the metal structure in step S220, accelerate the deposition reaction of the side wall, make the silicon nitride layer 34 have better adhesion to the side wall, and prevent the silicon nitride layer 34 from peeling off in the subsequent thermal process.

[0069] In one embodiment, silicon dangling bonds are formed by plasma bombarding the surface of the SRO layer 32 using a gas containing a silicon source. Figure 7 It is a schematic diagram of silicon dangling bonds formed on the surface of the SRO layer 32 in one embodiment. It can be understood that we mainly want to form silicon dangling bonds on the surface of the SRO layer 32 on the side wall of the metal layer 22, but silicon dangling bonds will also be formed on the surface of the SRO layer 32 at other positions during actual plasma bombardment treatment.

[0070] In one embodiment, the gas source for plasma bombardment treatment includes SiH4 as a silicon source and helium as a carrier gas, wherein the carrier gas mainly plays the role of diluting and promoting the dissociation of the gas as the silicon source. In other embodiments, SiH4 can also be replaced by other suitable silicon sources, and helium can also be replaced by other inert gases as carrier gases.

[0071] In one embodiment, the radio frequency power of the plasma bombardment treatment is 100-150 W, and the reaction pressure is 2.0-5.0 Torr. In one embodiment, the gas source of the plasma bombardment treatment has a molar ratio of SiH4:He=1:10-1:12.

[0072] In one embodiment, after step S230 , the deposited fluorine-containing silicon glass may be planarized by a planarization method (eg, chemical mechanical polishing (CMP)) so that the intermetallic dielectric layer has a flat surface.

[0073] The present application accordingly proposes an intermetallic dielectric layer, comprising a fluorine-containing silicon glass layer, the fluorine-containing silicon glass layer covering a metal structure having an SRO layer formed on the surface. The intermetallic dielectric layer also includes a silicon nitride layer disposed between the fluorine-containing silicon glass layer and the SRO layer, the silicon nitride layer having compressive stress. The intermetallic dielectric layer can be manufactured by the manufacturing method of the intermetallic dielectric layer described in any of the above embodiments.

[0074] The above-mentioned intermetallic dielectric layer has a silicon nitride layer between the SRO layer and the fluorinated silicon glass. Since the expansion coefficient of the metal structure (such as aluminum) is larger than that of the dielectric layer (mainly the fluorinated silicon glass), the microscopic deformation of the metal structure is large during the temperature change process. Since the silicon nitride layer has compressive stress, it can suppress the microscopic deformation of the metal structure caused by the thermal process, see Figure 6 Furthermore, due to the high strength of silicon nitride, the newly added silicon nitride layer can prevent the metal structure from deforming (expanding or shrinking) and causing microcracks or even fractures in the SRO layer, thereby preventing the subsequent free fluorine ions in the fluorine-containing silicon glass from entering and corroding the metal structure to cause voids.

[0075] In one embodiment, the compressive stress of the silicon nitride layer is 50 MPa to 180 MPa.

[0076] In one embodiment, the silicon nitride layer is a silicon nitride with a loose and porous structure so as to reduce the dielectric constant. By making the structure of the silicon nitride layer loose and porous to reduce the dielectric constant of the silicon nitride layer, it is possible to avoid reducing the response speed of the integrated circuit as much as possible.

[0077] Since the intermetallic dielectric layer of the present application has a newly added silicon nitride layer, if the thickness of the SRO layer + silicon nitride layer is thick, it will have an adverse effect on the electrical performance of the device, such as reducing the response speed of the device. In one embodiment, the total thickness of the SRO layer + silicon nitride layer can be kept the same as the thickness of the original single SRO layer, which is equivalent to the thickness of the intermetallic dielectric layer not increasing after the silicon nitride layer is added. Furthermore, the thickness of the SRO layer and the silicon nitride layer can be allocated at a ratio of 1:1.

[0078] For the device process with a line width of 110nm to 180nm, the sum of the thickness of the SRO layer and the silicon nitride layer does not exceed In one embodiment, the thickness of the SRO layer is The thickness of the silicon nitride layer is For the embodiment with a line width greater than 180 nm, the total thickness of the SRO layer + the silicon nitride layer can be adjusted appropriately, and the film thickness ratio of the SRO layer to the silicon nitride layer can also be adjusted.

[0079] The present application also proposes a semiconductor device, including a device substrate, a first metal structure, a second metal structure, an interlayer dielectric layer between the device substrate and the first metal structure, and an intermetallic dielectric layer between the second metal structure and the first metal structure; wherein the intermetallic dielectric layer is the intermetallic dielectric layer described in any of the aforementioned embodiments.

[0080] In one embodiment, the first metal structure includes an aluminum-doped copper alloy, such as an Al / Cu alloy with a copper content of 0.5% by mass.

[0081] In one embodiment, an adhesive layer is further provided at the bottom and the top of the first metal structure. In one embodiment, the adhesive layer includes a titanium layer and a titanium nitride layer.

[0082] In one embodiment, the material of the second metal structure is the same as that of the first metal structure.

[0083] In one embodiment, the interlayer dielectric layer includes, from bottom to top, a SiON (silicon oxynitride) layer, a BPSG (phosphosilicate glass) layer, and a silicon dioxide layer (formed by a plasma enhanced tetraethyl orthosilicate (PETEOS) process).

[0084] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing an intermetallic dielectric layer, comprising: obtaining a substrate structure formed with a metal structure, wherein a surface of the metal structure is covered by a SRO layer; forming a silicon nitride layer with compressive stress on the surface of the SRO layer on the side wall of the metal structure; Filling fluorine-containing silicon glass to cover the metal structure, the SRO layer and the silicon nitride layer as an intermetallic dielectric layer; Before the step of forming the silicon nitride layer on the surface of the SRO layer, the method further includes the step of performing surface treatment on the SRO layer to form silicon dangling bonds on the surface of the SRO layer.

2. The method for manufacturing an intermetallic dielectric layer according to claim 1, characterized in that: The silicon nitride layer is a silicon nitride with a loose and porous structure so as to reduce the dielectric constant.

3. The method for manufacturing an intermetallic dielectric layer according to claim 1 or 2, characterized in that: The compressive stress of the silicon nitride layer is 50 MPa to 180 MPa.

4. The method for manufacturing an intermetallic dielectric layer according to claim 3, characterized in that: The step of forming a silicon nitride layer with compressive stress on the surface of the SRO layer is to deposit the silicon nitride layer using a plasma enhanced chemical vapor deposition process.

5. The method for manufacturing an intermetallic dielectric layer according to claim 4, characterized in that: The radio frequency power of depositing the silicon nitride layer is 800-900W, and the reaction pressure is 3-5 Torr.

6. The method for manufacturing an intermetallic dielectric layer according to claim 1, characterized in that: The step of performing surface treatment on the SRO layer includes performing plasma bombardment treatment on the surface of the SRO layer using a gas containing a silicon source.

7. The method for manufacturing an intermetallic dielectric layer according to claim 6, characterized in that: The gas includes SiH4 as a silicon source and helium as a carrier gas.

8. The method for manufacturing an intermetallic dielectric layer according to claim 1, characterized in that: The manufacturing steps of the metal structure include: forming an oxide layer on the substrate; forming a first adhesion layer on the oxide layer, wherein the first adhesion layer comprises titanium and titanium nitride; forming a metal layer on the first adhesive layer, wherein the metal layer comprises an aluminum-doped copper alloy; forming a second adhesion layer on the metal layer, the second adhesion layer comprising titanium and titanium nitride; The second adhesive layer, the metal layer and the first adhesive layer are photolithographically and etched to form the metal structure.

9. An intermetallic dielectric layer, comprising a fluorine-containing silicon glass layer, the fluorine-containing silicon glass layer covering a metal structure having an SRO layer formed on the surface, and further comprising a silicon nitride layer disposed between the fluorine-containing silicon glass layer and the SRO layer, the silicon nitride layer having compressive stress; characterized in that: The intermetallic dielectric layer is formed by the manufacturing method according to any one of claims 1 to 8.

10. The intermetallic dielectric layer according to claim 9, characterized in that: The sum of the thickness of the SRO layer and the silicon nitride layer does not exceed 11. A semiconductor device comprising a device substrate, a first metal structure, a second metal structure, an interlayer dielectric layer between the device substrate and the first metal structure, and an intermetallic dielectric layer between the second metal structure and the first metal structure, characterized in that: The intermetallic dielectric layer is the intermetallic dielectric layer according to claim 9 or 10.

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