A delay circuit and driving apparatus

Abstract

The application discloses a delay circuit and a driving device. The delay circuit can include at least two branches in parallel, each of the at least two branches has different delay; the delay circuit includes at least one register for controlling one of the at least two branches to be turned on, so that the delay circuit generates the delay corresponding to the turned-on branch. Since the greater the delay of the input signal is, the smaller the slew rate is, the slew rates of the input signal through any one of the at least two branches are different. The at least one register controls one of the at least two branches to be turned on, so that the slew rate of the output signal can be adjusted, and the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.

Description

Technical Field

[0001] This application relates to the field of electrical engineering, specifically to a time delay circuit and a driving device. Background Technology

[0002] In the field of data communication, circuit structures can be designed using either parallel or serial methods. Circuits designed using parallel data transmission require multiple transmission lines, have more chip pins, and require complex layouts on the circuit board. In parallel mode, due to the existence of multiple lines, signal coupling and interference between these lines can affect the transmission speed and distance. Furthermore, parallel data transmission requires a synchronous clock, which can cause clock skew when the lines are long. Circuits designed using serial mode require at least one pair of transmission lines and do not require a synchronous clock. Therefore, serial data transmission is more suitable for high-speed communication systems.

[0003] In communication systems, the greater the delay of the circuit output signal, the smaller the slew rate. Existing technology can delay the input signal using a buffer circuit, which incorporates multiple metal-oxide-semiconductor (MOS) transistors that delay the input signal.

[0004] Since the number and size of MOS transistors in each buffer are fixed, and the delay of the input signal after passing through the buffer is fixed, the slew rate of the output signal after passing through the buffer circuit is fixed. However, different protocols or different operating modes of the same protocol have different requirements for the slew rate of the circuit. Therefore, the circuit provided by the prior art has low compatibility with different protocols or different operating modes under the same protocol. Summary of the Invention

[0005] In view of the above, the first aspect of the present application provides a delay circuit, which may include at least two branches connected in parallel, each of the at least two branches having a different delay; the delay circuit includes at least one register, which is used to control one of the at least two branches to be turned on, such that the delay circuit generates a delay corresponding to the turned-on branch.

[0006] Since each branch has a different delay, different delays can be provided by controlling the connection of different branches through registers. Therefore, the delay circuit provided in this application embodiment can provide different delays, which is equivalent to the output signal having multiple different slew rates. By adjusting the slew rate of the output signal, the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.

[0007] Optionally, in conjunction with the first aspect, in a first possible implementation of the first aspect, the number and / or size of the MOSFETs included in each of the at least two branches are different, so that the at least two branches have different delays. In the first possible implementation of the first aspect, the different delays of each of the at least two branches can be achieved by changing the number and / or size of the MOSFETs included in each branch.

[0008] Optionally, in conjunction with the first possible implementation of the first aspect, in the second possible implementation of the first aspect, at least one register includes a first register, and at least two branches include a first branch and a second branch, wherein the first register is used to control one of the first branch and the second branch to be turned on.

[0009] In the second possible implementation of the first aspect, only one register is needed to control the connection of one of the first and second branches, and using only one register can reduce costs.

[0010] Optionally, in conjunction with the second possible implementation of the first aspect, in the three possible implementations of the first aspect, the first register includes a first input and a second input, the first input and the second input being inverted; the first branch includes a first PMOS transistor and a second PMOS transistor, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the input signal, and the gate of the second PMOS transistor is connected to the first input of the first register; the first branch also includes a first NMOS transistor and a second NMOS transistor, the source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the first NMOS transistor is connected to the input signal, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the second input of the first register. In the third possible implementation of the first aspect, the on / off state of the first branch can be controlled by the inverted first and second inputs in the first register.

[0011] Optionally, in conjunction with the third possible implementation of the first aspect, in the fourth possible implementation of the first aspect, the second branch includes a third PMOS transistor and a fourth PMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the gate of the third PMOS transistor is connected to the input signal, and the gate of the fourth PMOS transistor is connected to the second input of the first register. The second branch also includes a third NMOS transistor and a fourth NMOS transistor. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the third NMOS transistor is connected to the input signal, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the first input of the first register. In this fourth possible implementation of the first aspect, the on / off state of the second branch can be controlled by the inverted first and second inputs in the first register.

[0012] Optionally, in conjunction with the fourth possible implementation of the first aspect, in the fifth possible implementation of the first aspect, the first input of the first register is 0, the second input is 1, both the second PMOS and the second NMOS transistors are turned on, and both the fourth PMOS and the fourth NMOS transistors are turned off, thus connecting the first branch; or, the first input of the first register is 1, the second input is 0, both the second PMOS and the second NMOS transistors are turned off, and both the fourth PMOS and the fourth NMOS transistors are turned on, thus connecting the second branch. In this fifth possible implementation of the first aspect, the first and second branches can be controlled to be connected by the inverted first and second inputs in the first register.

[0013] Optionally, in conjunction with the first possible implementation of the first aspect, among the six possible implementations of the first aspect, at least one register includes a first register and a second register, and at least two branches include a first branch and a second branch. The first register controls the first branch, and the second register controls the second branch. The first branch and one of the second branches are connected. In the sixth possible implementation of the first aspect, the first register and the second register can control the connection of one of the first and second branches.

[0014] In this implementation, one register controls one branch, making the design simple and less prone to errors.

[0015] Optionally, in conjunction with the sixth possible implementation of the first aspect, in the seventh possible implementation of the first aspect, the first register includes a first input and a second input, which are inverted. The first branch includes a first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the input signal, and the gate of the second PMOS transistor is connected to the first input of the first register. The first branch also includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the first NMOS transistor is connected to the input signal, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the second input of the first register. In the seventh possible implementation of the first aspect, the first register can control the on / off state of the first branch.

[0016] Optionally, in conjunction with the seventh possible implementation of the first aspect, in the eighth possible implementation of the first aspect, the second register includes a third input and a fourth input, which are inverted. The second branch includes a third PMOS transistor and a fourth PMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the gate of the third PMOS transistor is connected to the input signal, and the gate of the fourth PMOS transistor is connected to the third input of the second register. The second branch also includes a third NMOS transistor and a fourth NMOS transistor. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the third NMOS transistor is connected to the input signal, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the fourth input of the second register. In the eighth possible implementation of the first aspect, the second register can control the on / off state of the second branch.

[0017] Optionally, in conjunction with the eighth possible implementation of the first aspect, in the ninth possible implementation of the first aspect, the first branch is turned on when the first register controls both the second PMOS transistor and the second NMOS transistor to be turned on, and the second register controls both the fourth PMOS transistor and the fourth NMOS transistor to be turned off; or, the second branch is turned on when the first register controls both the second PMOS transistor and the second NMOS transistor to be turned off, and the second register controls both the fourth PMOS transistor and the fourth NMOS transistor to be turned on. In the ninth possible implementation of the first aspect, the first register and the second register can control one of the first branch and the second branch to be turned on.

[0018] Optionally, in conjunction with the ninth possible implementation of the first aspect, in the tenth possible implementation of the first aspect, the first input of the first register is 0, the second input is 1, the third input of the second register is 1, the fourth input is 0, both the second PMOS and the second NMOS transistors are turned on, and both the fourth PMOS and the fourth NMOS transistors are turned off, thus connecting the first branch; or, the first input of the first register is 1, the second input is 0, the third input of the second register is 0, the fourth input is 1, both the second PMOS and the second NMOS transistors are turned off, and both the fourth PMOS and the fourth NMOS transistors are turned on, thus connecting the second branch. In the tenth possible implementation of the first aspect, the first register and the second register can control the connection of one of the first and second branches by changing the values ​​of the first, second, third, and fourth inputs.

[0019] A second aspect of this application provides a driving device, which may include: an N-stage delay circuit as described in the first aspect and any possible implementation of the first aspect, and an N-stage driving circuit, where N is an integer greater than 1; wherein the output of the (N-1)th stage delay circuit is connected to the input of the Nth stage delay circuit and the input of the (N-1)th stage driving circuit, respectively; the output of the Nth stage delay circuit is connected to the input of the Nth stage driving circuit; the N output signals of the first stage driving circuit to the Nth stage driving circuit together constitute the output of the driving device; the driving circuit includes at least one PMOS transistor, at least one NMOS transistor, a first resistor and a second resistor, wherein at least one PMOS transistor is connected in series with the first resistor and the gate of at least one PMOS transistor is connected to the input signal, and at least one NMOS transistor is connected in series with the second resistor and the gate of at least one NMOS transistor is connected to the input signal.

[0020] The driving device includes N stages of delay circuits, such as those in the first aspect and any possible implementation of the first aspect. The delay of the driving device can be adjusted by adjusting the number of stages of the N-stage driving circuits. At the same time, the driving device includes N stages of driving circuits. By adjusting the resistance of the N-stage driving circuits, the resistance of the driving circuits can be matched with the resistance of the load, thereby reducing the impact of signal reflection on signal quality. Furthermore, the N-stage driving circuits can enhance the driving capability of the signal.

[0021] Optionally, in conjunction with the second aspect, in the first possible implementation of the second aspect, the delay between the output and input signals of the driving device is related to at least one of the following: the number of MOSFETs in the driving device, the size of the MOSFETs, the number of stages of the N-stage delay circuit and the N-stage driving circuit, the delay of the branch connected in each stage of the N-stage delay circuit, or the delay of the N-stage driving circuit.

[0022] Optionally, in conjunction with the first possible implementation of the second aspect, in the second possible implementation of the second aspect, the delay between the output and input signal of the driving device includes the delay of the N-stage delay circuit and the delay of the N-stage driving circuit, wherein the delay of the N-stage delay circuit is related to the number of stages of the N-stage delay circuit and the delay of the branch connected by each stage of the N-stage delay circuit.

[0023] Optionally, in conjunction with any of the second possible implementations of the second aspect to the second possible implementation, in the third possible implementation of the second aspect, the delay between the output and input signal of the driving device is a*(T1+T2+……+T N )+T load Where 'a' is the correction coefficient, T1 is the delay of the first stage delay circuit in the N-stage delay circuit, T2 is the delay of the second stage delay circuit in the N-stage delay circuit, ..., T N T is the delay of the Nth stage of the Nth stage delay circuit in an N-stage delay circuit. load This is the delay for the N-stage drive circuit.

[0024] Optionally, in combination with any of the second possible implementations of the second aspect to the second possible implementation, in the fourth possible implementation of the second aspect, the delay between the output and input signal of the driving device is a*N*T. d +T load Where a is the correction coefficient, N is the number of stages in the N-stage delay circuit, and T d T represents the delay of each stage of an N-stage delay circuit. load This is the delay for the N-stage drive circuit.

[0025] This application provides a delay circuit and a driving device. The circuit may include at least two branches connected in parallel, each branch having a different delay. The delay circuit includes at least one register for controlling one of the at least two branches to be turned on, such that the delay circuit generates a delay corresponding to the turned-on branch. Since a larger delay in the input signal results in a smaller slew rate, the slew rate of the input signal passing through any one of the at least two branches is different. By controlling one of the at least two branches to be turned on through at least one register, the slew rate of the output signal can be adjusted, allowing the slew rate of the output signal to be compatible with different protocols or different modes under the same protocol. Attached Figure Description

[0026] Figure 1 A schematic diagram of a delay circuit provided for the prior art;

[0027] Figure 2 Another schematic diagram of a delay circuit provided for the prior art;

[0028] Figure 3 A schematic diagram of an embodiment of a delay circuit provided in this application;

[0029] Figure 4 A schematic diagram of another embodiment of a delay circuit provided in this application;

[0030] Figure 5 A schematic diagram of one embodiment of a driving device provided in this application;

[0031] Figure 6 This is a schematic diagram of one embodiment of a driving circuit provided in this application. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] It should be understood that in this application, "at least one (item)" means one or more, and "more than one" means two or more. The term "and / or" appearing in this application can describe a relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0034] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] In communication systems, the greater the delay of the circuit output signal, the smaller the slew rate. For example... Figure 1 As shown, in the prior art, the input signal can be delayed using a buffer. This buffer circuit contains multiple MOSFETs, which delay the input signal. Since the number and size of the MOSFETs in each buffer are fixed, the slew rate of the output signal after passing through the buffer circuit is also fixed.

[0036] Secondly, a high-speed clock signal can be introduced into the circuit, such as... Figure 2 As shown, the input signal is sampled by a high-speed clock signal, and then sequentially passed through M stages of data flip-flops (DFFs) to delay the input signal. The resulting delay is M*T, where T is the period of the high-speed clock signal. With a fixed number of stages M, the delay is determined by the period of the high-speed clock signal. Therefore, this circuit can only support one protocol or one operating mode within a protocol, and cannot be compatible with multiple protocols or multiple operating modes within a single protocol. Furthermore, this method requires a high-speed clock, which wastes chip area and increases unpredictable risks.

[0037] Therefore, Embodiment 1 of this application provides a delay circuit, such as Figure 3 As shown:

[0038] The delay circuit may include at least two branches. Figure 3 Two branches, the first and second, are given. However, there is no limitation to only two branches; a third branch, etc., may exist. The first and second branches are connected in parallel. If a third branch exists, it is also connected in parallel with the first and second branches. Each of the at least two branches has a different delay. Figure 3 In the process, the first branch and the second branch have different delays.

[0039] Specifically, to achieve the difference in delay between the first branch and the second branch, the number of MOS transistors contained in the first branch and the second branch may be different; the size of the MOS transistors contained in the first branch and the second branch may be different; or both the number and size of the MOS transistors contained in the first branch and the second branch may be different.

[0040] by Figure 3 As shown in the example, the number of MOS in the first branch is more than that in the second branch, which makes the delays of the first branch and the second branch different.

[0041] The at least two branches include at least one register, which controls one of the at least two branches to be turned on, such that the delay circuit generates a delay corresponding to the turned-on branch. Figure 3 As shown in the example, the delay circuit only includes a first register, which includes a first input and a second input, which are inverted.

[0042] The first branch includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the input signal, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the first input of the first register. The source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the first NMOS transistor is connected to the input signal, and the gate of the second NMOS transistor is connected to the second input of the first register.

[0043] The second branch includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor is connected to the input signal. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth PMOS transistor is connected to the second input of the first register. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the third NMOS transistor is connected to the input signal, and the gate of the fourth NMOS transistor is connected to the first input of the first register.

[0044] When the first input of the first register is 0 and the second input is 1, both the second PMOS and the second NMOS transistors are turned on, while both the fourth PMOS and the fourth NMOS transistors are turned off, and the first branch is connected. When the first branch is connected and the input signal is low, the first PMOS transistor is turned on, and the input signal reaches the output node of the delay circuit via the first PMOS transistor and the second PMOS transistor; when the first branch is connected and the input signal is high, the first NMOS transistor is turned on, and the input signal reaches the output node of the delay circuit via the first NMOS transistor and the second NMOS transistor.

[0045] Alternatively, the first input of the first register is 1, the second input is 0, both the second PMOS and second NMOS transistors are off, and both the fourth PMOS and fourth NMOS transistors are on, thus connecting the second branch. When the second branch is on and the input signal is low, the third PMOS transistor is on, and the input signal reaches the output node of the delay circuit via the third and fourth PMOS transistors; when the second branch is on and the input signal is high, the third NMOS transistor is on, and the input signal reaches the output node of the delay circuit via the third and fourth NMOS transistors.

[0046] Embodiment 1 of the present invention provides a delay circuit, which may include a first branch and a second branch. The delay circuit includes a first register, which controls the activation of one of the first and second branches, causing the delay circuit to generate a delay corresponding to the activated branch. Since a larger delay in the input signal results in a smaller slew rate, the slew rates of the input signal through the first and second branches are different. Controlling the activation of one of the first and second branches through the first and second inputs of the first register allows control over the output delay of the delay circuit, and using only one register reduces cost.

[0047] The delay circuit provided in Example 1 includes only one register. When the delay circuit has two branches, it can also include two registers, such as... Figure 4 As shown, Embodiment 2 provides another delay circuit.

[0048] The delay circuit includes at least two branches with different delays. Each branch may include two registers for controlling one of the branches to be turned on, so that the delay circuit generates a delay corresponding to the turned-on branch. Figure 4 The delay circuit shown includes a first register and a second register. The first register controls the first branch, the second register controls the second branch, and if there is a third branch, the third register is needed to control the third branch. Each register controls one branch.

[0049] The first register includes a first input and a second input, and the second register includes a third input and a fourth input, wherein the first input and the second input are inverted, and the third input and the fourth input are inverted.

[0050] The first branch includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the input signal, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the first input of the first register. The source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the first NMOS transistor is connected to the input signal, and the gate of the second NMOS transistor is connected to the second input of the first register.

[0051] The second branch includes a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor is connected to the input signal. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth PMOS transistor is connected to the third input of the second register. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the third NMOS transistor is connected to the input signal, and the gate of the fourth NMOS transistor is connected to the fourth input of the second register.

[0052] When the first input of the first register is 0, the second input is 1, the third input of the second register is 1, and the fourth input is 0, both the second PMOS and the second NMOS transistors are turned on, and both the fourth PMOS and the fourth NMOS transistors are turned off, thus connecting the first branch. When the first branch is connected and the input signal is low, the first PMOS transistor is turned on, and the input signal reaches the output node of the delay circuit via the first and second PMOS transistors; when the first branch is connected and the input signal is high, the first NMOS transistor is turned on, and the input signal reaches the output node of the delay circuit via the first and second NMOS transistors.

[0053] Alternatively, when the first input of the first register is 1, the second input is 0, the third input of the second register is 0, and the fourth input is 1, both the second PMOS and the second NMOS transistors are off, and both the fourth PMOS and the fourth NMOS transistors are on, thus connecting the second branch. When the second branch is on and the input signal is low, the third PMOS transistor is on, and the input signal reaches the output node of the delay circuit via the third and fourth PMOS transistors; when the second branch is on and the input signal is high, the third NMOS transistor is on, and the input signal reaches the output node of the delay circuit via the third and fourth NMOS transistors.

[0054] Embodiment 2 of the present invention provides a delay circuit, which may include a first branch and a second branch. The delay circuit includes a first register and a second register. The first register controls the first branch, and the second register controls the second branch. If a third branch exists in the delay circuit, the delay circuit also includes a third register, which controls the third branch. In this delay circuit, each branch includes at least one register, which controls the on / off state of the branch. In the delay circuit, only one branch is connected at a time, so that the delay circuit generates a delay corresponding to the connected branch. The delay circuit provided in this embodiment can include two or more branches, each branch having a different delay. Each branch is provided with at least one register to control the on / off state of the branch, allowing the delay circuit to generate two or more types of delays. Since a larger delay results in a smaller slew rate, this delay circuit can adapt to the slew rate requirements of multiple protocols or different operating modes of the same protocol.

[0055] The two embodiments above describe a delay circuit. The following describes a driving device, which may include the delay circuit described in Embodiment 1 or Embodiment 2. Figure 5 As shown, Embodiment 3 provides a driving device.

[0056] The driving device includes N-stage delay circuits as described in Embodiment 1 or Embodiment 2 and N-stage driving circuits, where N is an integer greater than 1. The output of the (N-1)th stage delay circuit is connected to the input of the Nth stage delay circuit and the input of the (N-1)th stage driving circuit, respectively; the output of the Nth stage delay circuit is connected to the input of the Nth stage driving circuit; the N output signals from the first stage driving circuit to the Nth stage driving circuit together constitute the output of the driving device.

[0057] For example, when N equals 2, the driving device includes two-stage delay circuits and two-stage driving circuits. The output of the first-stage delay circuit is connected to the input of the second-stage delay circuit and the input of the first-stage driving circuit, respectively. The output of the second-stage delay circuit is connected to the input of the second-stage driving circuit. The two output signals of the first-stage driving circuit and the second-stage driving circuit together constitute the output of the driving device.

[0058] The driving circuit includes at least one PMOS transistor, at least one NMOS transistor, a first resistor, and a second resistor. The at least one PMOS transistor is connected in series with the first resistor, and its gate is connected to the input signal. If multiple PMOS transistors are present, they are connected in series, and their gates are all connected to the input signal. The at least one NMOS transistor is connected in series with the second resistor, and its gate is connected to the input signal. If multiple NMOS transistors are present, they are connected in series.

[0059] The structure of the driving circuit can be as follows: Figure 6 The circuit structure shown includes a PMOS transistor, an NMOS transistor, a first resistor, and a second resistor. The PMOS transistor is connected in series with the first resistor; its gate is connected to the input signal, its source is connected to the power supply voltage, and its drain is connected to the first resistor. The NMOS transistor is connected in series with the second resistor; its gate is connected to the input signal, its source is grounded, and its drain is connected to the second resistor. The first and second resistors are also connected. When the input signal is low, the PMOS transistor is turned on, and the input signal reaches the output node of the drive circuit via the PMOS transistor and the first resistor. When the input signal is high, the NMOS transistor is turned on, and the input signal reaches the output node of the drive circuit via the NMOS transistor and the second resistor. This drive circuit enhances the driving capability of the input signal.

[0060] The delay between the output and input signals of the drive device is related to at least one of the following: the number of MOSFETs in the drive device, the size of the MOSFETs, the number of stages of the N-stage delay circuit and the N-stage drive circuit, the delay of the branch connected in each stage of the N-stage delay circuit, or the delay of the N-stage drive circuit.

[0061] The delay between the output and input signal of the drive device can be specifically the sum of the delay of the N-stage delay circuit and the delay of the N-stage drive circuit. The delay between the output and input signal of the drive device is a*(T1+T2+……+T N )+T loadWhere 'a' is a correction factor, related to the size and / or number of MOSFETs. For example, since there are interactions between each delay circuit in the N-stage delay circuit included in the driving device, and also interactions between each delay circuit and its corresponding driving circuit, these interactions affect the delay of the N-stage delay circuit. Multiplying the correction factor 'a' by the sum of the delays of each delay circuit in the N-stage delay circuit can offset the effects of these interactions on the delay of the N-stage delay circuit. T1 is the delay of the first delay circuit in the N-stage delay circuit, T2 is the delay of the second delay circuit in the N-stage delay circuit, ..., T N T is the delay of the Nth stage of the Nth stage delay circuit in an N-stage delay circuit. load This is the delay for the N-stage drive circuit.

[0062] If each stage of an N-stage delay circuit selects a branch with the same delay, then the delay of each stage of the N-stage delay circuit is T. d At that time, the delay between the output and input signals of the drive device can be a*N*T. d +T load Where a is the correction coefficient, N is the number of stages in the N-stage delay circuit, and T d T represents the delay of each stage of an N-stage delay circuit. load This is the delay for the N-stage drive circuit.

[0063] In this drive device design, the sum of the resistances of the N-stage drive circuit can be equal to the resistance of the transmission line to reduce signal reflection. The transmission line includes a metal line through which the signal passes through the package and board-level traces to reach the load. High-speed signals are prone to reflection problems, thus affecting signal quality. If the resistance of the N-stage drive circuit is not equal to the impedance of the transmission line, some high-speed signals will undergo secondary reflection. When the resistance of the N-stage drive circuit is equal to the impedance of the transmission line, the reflected energy will be absorbed, thus preventing secondary reflection.

[0064] The drive device can also be combined with components such as chips, transmission lines and terminal devices to form a complete product. The delay generated by this product includes not only the delay generated by the drive device, but also the delay generated by components such as chips, transmission lines and terminal devices.

[0065] The greater the output delay of the driver, the smaller the slew rate of the output signal. The slew rate is the time it takes for the power supply to charge the capacitor at the output node; slew rate = I / C, where I is the circuit current and C is the total capacitance of the output node. If the total capacitance of the output node remains constant, changing the slew rate requires changing the current magnitude. The current magnitude is determined by the number and size of the MOSFETs in the driver. The number and size of the MOSFETs in the driver also have a certain impact on the output impedance. Therefore, while the driver may meet the operating conditions of a specific protocol or a specific protocol's operating mode, its output impedance may not meet the requirements.

[0066] Embodiment 3 of the present invention provides a driving device, which may include an N-stage delay circuit and an N-stage driving circuit. The N-stage delay circuit can delay the input signal, and the N-stage driving circuit can enhance the driving capability of the input signal, so that the output of the driving device can meet different protocols or different modes of the same protocol.

[0067] The foregoing has provided a detailed description of a delay circuit and driving device according to embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A delay circuit, characterized in that, The delay circuit includes: At least two branches, the at least two branches are connected in parallel, each of the at least two branches has a different delay, and each of the at least two branches includes a different number and / or size of MOS transistors, so that the at least two branches have different delays; The delay circuit includes at least one register, which is used to control one of the at least two branches to be turned on according to different protocols or different working modes of the same protocol, so that the delay circuit generates a delay corresponding to the turned-on branch. The at least two branches include a first branch and a second branch, and the at least one register is used to control one of the first branch and the second branch to be connected; The first branch includes a first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the input signal, and the gate of the second PMOS transistor is connected to the input of the at least one register. The first branch further includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the first NMOS transistor is connected to the input signal, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the input of the at least one register. The first branch also includes two PMOS transistors and two NMOS transistors. The source of one PMOS transistor is connected to the power supply voltage, the drain of one PMOS transistor is connected to the source of the other PMOS transistor, the gate of one PMOS transistor is connected to the input signal, and the gate of the other PMOS transistor is connected to the input signal. The source of one NMOS transistor is grounded, the drain of one NMOS transistor is connected to the source of the other NMOS transistor, the gate of one NMOS transistor is connected to the input signal, the drain of the other PMOS transistor is connected to the drain of the other NMOS transistor, and the gate of the other NMOS transistor is connected to the input signal. The gates of the first PMOS transistor and the first NMOS transistor are connected to the drain of the other PMOS transistor. The second branch includes a third PMOS transistor and a fourth PMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the gate of the third PMOS transistor is connected to the input signal, and the gate of the fourth PMOS transistor is connected to the input of at least one register. The second branch also includes a third NMOS transistor and a fourth NMOS transistor. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, the gate of the third NMOS transistor is connected to the input signal, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the input of the at least one register.

2. The delay circuit according to claim 1, characterized in that, The at least one register includes a first register, which is used to control the connection of one of the first branch and the second branch.

3. The delay circuit according to claim 2, characterized in that, The first register includes a first input and a second input, the first input and the second input are out of phase, the gate of the second PMOS transistor is connected to the first input of the first register, and the gate of the second NMOS transistor is connected to the second input of the first register.

4. The delay circuit according to claim 3, characterized in that, The gate of the fourth PMOS transistor is connected to the second input of the first register; the gate of the fourth NMOS transistor is connected to the first input of the first register.

5. The delay circuit according to claim 4, characterized in that, The first input of the first register is 0, the second input is 1, both the second PMOS transistor and the second NMOS transistor are turned on, both the fourth PMOS transistor and the fourth NMOS transistor are turned off, and the first branch is connected; Alternatively, the first input of the first register is 1, the second input is 0, both the second PMOS transistor and the second NMOS transistor are turned off, both the fourth PMOS transistor and the fourth NMOS transistor are turned on, and the second branch is connected.

6. The delay circuit according to claim 1, characterized in that, The at least one register includes a first register and a second register, the first register controls the first branch, the second register controls the second branch, and the first branch and one of the second branches are connected.

7. The delay circuit according to claim 6, characterized in that, The first register includes a first input and a second input, the first input and the second input being inverted, the gate of the second PMOS transistor being connected to the first input of the first register, and the gate of the second NMOS transistor being connected to the second input of the first register.

8. The delay circuit according to claim 7, characterized in that, The second register includes a third input and a fourth input, the third input and the fourth input being inverted, the gate of the fourth PMOS transistor being connected to the third input of the second register, and the gate of the fourth NMOS transistor being connected to the fourth input of the second register.

9. The delay circuit according to claim 8, characterized in that, When the first register controls both the second PMOS transistor and the second NMOS transistor to be turned on, and the second register controls both the fourth PMOS transistor and the fourth NMOS transistor to be turned off, the first branch is connected; Alternatively, the second branch is turned on when the first register controls both the second PMOS transistor and the second NMOS transistor to be off, and the second register controls both the fourth PMOS transistor and the fourth NMOS transistor to be on.

10. The delay circuit according to claim 9, characterized in that, The first input of the first register is 0, the second input is 1, the third input of the second register is 1, the fourth input is 0, both the second PMOS transistor and the second NMOS transistor are turned on, both the fourth PMOS transistor and the fourth NMOS transistor are turned off, and the first branch is connected; Alternatively, the first input of the first register is 1, the second input is 0, the third input of the second register is 0, the fourth input is 1, both the second PMOS transistor and the second NMOS transistor are off, both the fourth PMOS transistor and the fourth NMOS transistor are on, and the second branch is connected.

11. A driving device, characterized in that, The driving device includes: The N-stage delay circuit and the N-stage drive circuit are as described in any one of claims 1 to 10, wherein N is an integer greater than 1; The output of the (N-1)th stage delay circuit is connected to the input of the Nth stage delay circuit and the input of the (N-1)th stage drive circuit, respectively. The output of the Nth stage delay circuit is connected to the input of the Nth stage drive circuit; The N output signals from the first-stage drive circuit to the Nth-stage drive circuit together constitute the output of the drive device; The driving circuit includes at least one PMOS transistor, at least one NMOS transistor, a first resistor and a second resistor. The at least one PMOS transistor is connected in series with the first resistor and the gate of the at least one PMOS transistor is connected to the input signal. The at least one NMOS transistor is connected in series with the second resistor and the gate of the at least one NMOS transistor is connected to the input signal.

12. The driving device according to claim 11, characterized in that, The delay between the output of the driving device and the input signal is related to at least one of the following: the number of MOS transistors in the driving device, the size of the MOS transistors, the number of stages of the N-stage delay circuit and the N-stage driving circuit, the delay of the branch connected in each stage of the N-stage delay circuit, or the delay of the N-stage driving circuit.

13. The driving device according to claim 12, characterized in that, The delay between the output of the driving device and the input signal includes the delay of the N-stage delay circuit and the delay of the N-stage driving circuit. The delay of the N-stage delay circuit is related to the number of stages of the N-stage delay circuit and the delay of the branch connected in each stage of the N-stage delay circuit.

14. The driving device according to any one of claims 11 to 13, characterized in that, The time delay between the output of the driving device and the input signal is a*(T1+T2+……+T) N )+T load Wherein, 'a' is a correction coefficient, T1 is the delay of the first stage delay circuit in the N-stage delay circuit, T2 is the delay of the second stage delay circuit in the N-stage delay circuit, ..., T... N For the delay of the Nth stage delay circuit in the Nth stage delay circuit, T load This is the delay of the N-stage drive circuit.

15. The driving device according to any one of claims 11 to 13, characterized in that, The delay between the output of the driving device and the input signal is a*N*T. d +T load Wherein, a is the correction coefficient, N is the number of stages in the N-stage delay circuit, and T d T represents the delay of each stage of the N-stage delay circuit. load This is the delay of the N-stage drive circuit.

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