Memory array including memory cell strings and method for forming a memory array including memory cell strings

Abstract

The present application relates to a memory array including a string of memory cells and a method for forming a memory array including a string of memory cells. A stack including a first layer and a second layer alternating vertically is formed above the conductor layer. The stack includes laterally spaced memory blocks with horizontally elongated trenches therebetween. A string of channel material extends through the first layer and the second layer. The material of the first layer has a composition different from that of the material of the second layer. The lowermost first layer of the first layer includes a sacrificial material having a composition different from that of the first layer material above it and the second layer material layer above it. The sacrificial material has a composition different from that of the uppermost portion of the conductor material of the conductor layer. The sacrificial material is selectively etched isotropically relative to the uppermost portion of the conductor material of the conductor layer, selectively relative to the first layer material above it, and selectively relative to the second layer material above it.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. Background Art

[0002] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can interconnect memory cells in a conductive manner along the columns of the array, and access lines can interconnect memory cells in a conductive manner along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is greatly prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory that is used extensively in modern computers and devices. For example, modern personal computers may have the BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of solid-state drives in place of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND may be the basic architecture of an integrated flash memory. A NAND cell device includes at least one selection device coupled in series with a series combination of memory cells (and the series combination is often referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Controls or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, such as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "rungs" or "stairs") defining contact areas for individual word lines, with vertically extending conductive vias contacting the contact areas to provide electrical access to the word lines. Summary of the invention

[0008] Aspects of the present disclosure provide a method for forming a memory array including strings of memory cells, wherein the method includes: forming a conductor layer including a conductor material on a substrate; forming a stack including a vertically alternating first layer and a second layer above the conductor layer, the stack including laterally spaced memory blocks with horizontally elongated trenches between the laterally spaced memory blocks, strings of channel material extending through the first layer and the second layer, the material of the first layer being a different composition from the material of the second layer, a lowermost portion of the first layer including a sacrificial material of a different composition from the first layer material above it and the second layer material layer above it, the sacrificial material being a different composition from the composition of an uppermost portion of the conductor material of the conductor layer; isotropically etching the sacrificial material selectively relative to the uppermost portion of the conductor material of the conductor layer, selectively relative to the first layer material above it, and selectively relative to the second layer material above it; and after the isotropic etching, forming a conductive material in the lowermost first layer, the conductive material directly electrically coupling the channel material of individual ones of the strings of channel material with the conductor material of the conductor layer.

[0009] Another aspect of the present disclosure provides a method for forming a memory array including a memory cell string, wherein the method comprises: forming a conductor layer including a conductor material on a substrate, the conductor material including n-type conductive doped polysilicon; forming a stack including a first layer and a second layer vertically alternating over the conductor layer, the stack including laterally spaced memory blocks, the laterally spaced memory blocks having horizontally elongated trenches between them, a channel material string extending through the first layer and the second layer, the material of the first layer being a different composition from the material of the second layer, a lowermost first layer of the first layers including undoped or phosphorus-doped polysilicon, a lowermost second layer of the second layers being vertically between the lowermost first layer and the conductor layer; selectively relative to the n-type conductive doped polysilicon of the conductor layer and selectively relative to the upper second layer thereof isotropically etching the undoped or phosphorus-doped polysilicon of the lowermost first layer through the first layer material and the second layer material above it, the etching using an etching fluid including tetramethylammonium hydroxide; after the isotropic etching, etching the second layer material of the lowermost second layer to expose the upper surface of the n-type conductive doped polysilicon of the conductor layer; after the isotropic etching, exposing the sidewalls of the channel material of the channel material string in the lowermost first layer; and forming a conductive material in the lowermost first layer directly against the n-type conductive doped polysilicon of the conductor layer and directly against the exposed sidewalls of the channel material of the channel material string in the lowermost first layer to directly electrically couple the channel material of the individual ones of the channel material string and the conductor material of the conductor layer together.

[0010] Another aspect of the present disclosure provides a memory array including a string of memory cells, comprising: a conductor layer including a conductor material; laterally spaced memory blocks, each of which individually includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers directly above the conductor layer, the channel material string of the memory cells extending through the insulating layers and the conductive layers, the conductive material of the lowermost conductive layer in the conductive layers directly electrically coupling the channel material of the individual ones of the string of channel materials and the conductor material of the conductor layer together; an intervening material laterally located between laterally adjacent memory blocks in the memory blocks and longitudinally along the memory blocks, the intervening material including an insulating material; and the conductor material in the conductor layer includes a conductively doped semiconductive material having one of a primary dopant producing n-type or p-type conductivity, at least the uppermost portion of the conductor material in the conductor layer including a secondary dopant of a composition different from that of the primary dopant.

[0011] Another aspect of the present disclosure provides a memory array including a string of memory cells, comprising: a conductor layer comprising n-type conductive doped polysilicon having a primary dopant producing n-type conductivity; laterally spaced memory blocks, each of which individually comprises a vertical stack comprising alternating insulating layers and conductive layers directly above the conductor layer, a string of channel materials for memory cells extending through the insulating layers and the conductive layers, a lowermost conductive layer of the conductive layers comprising n-type conductive doped polysilicon directly against the n-type conductive doped polysilicon of the conductor layer and directly against side walls of channel material of the string of channel materials in the lowermost conductive layer; an intervening material laterally between laterally adjacent memory blocks of the memory blocks and longitudinally along the memory blocks, the intervening material comprising an insulating material; and at least an uppermost portion of the n-type conductive doped polysilicon in the conductor layer comprising a secondary dopant of a composition different from the composition of the primary dopant. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate under processing in accordance with an embodiment of the present invention and is taken through line 1 - 1 in FIG. 2 .

[0013] Figure 2 It passes through Figure 1 Schematic cross-sectional view taken along line 2-2 in FIG.

[0014] Figures 3 to 5 yes Figure 1 and 2 Magnified view of a portion of.

[0015] Figures 6 to 19 is in process according to some embodiments of the present invention Figures 1 to 5 A schematic, sequential cross-sectional, expanded, enlarged and / or partial view of a structure or part thereof. DETAILED DESCRIPTION

[0016] Embodiments of the present invention encompass methods for forming memory arrays, such as arrays of NAND or other memory cells, which may have at least some peripheral control circuitry under the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, whether present or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays that are independent of the method of manufacture (e.g., NAND architecture). Reference Figures 1 to 19 A first example method embodiment is described, which may be viewed as a "gate last" or "replacement gate" process, and from Figures 1 to 5 start.

[0017] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconducting / semiconductive, or insulating / insulator / insulating (i.e., electrically conductive) material. Various materials have been vertically formed over base substrate 11. The materials may be Figures 1 to 5 Next to, vertically inside or vertically outside of the depicted material. For example, other partially or fully manufactured components of the integrated circuit system may be provided somewhere above, around or within the base substrate 11. Control and / or other peripheral circuit systems for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be manufactured, and the systems may or may not be completely or partially within the array or sub-array. In addition, multiple sub-arrays may also be manufactured and operated independently of each other, in sequence, or in other ways. In this document, a "sub-array" may also be considered an array.

[0018] A conductor layer 16 including a conductor material 17 is formed on the substrate 11. In one embodiment, the conductor material 17 includes a metal material 15 (eg, WSi x) is a conductively doped semiconductive material 13 (e.g., n-type conductively doped polysilicon) above (directly above, and, for example, directly against) the conductively doped semiconductive material 13. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 including vertically alternating insulating layers 20* and conductive layers 22* is formed above conductor layer 16 (* is used as a suffix to include all such components designated with the same numerical value that may or may not have other suffixes). An example thickness of each of layers 20* and 22* is 20 to 60 nanometers. Only a small number of layers 20* and 22* are shown, but stack 18 is more likely to include dozens, a hundred, or more layers 20* and 22*. Other circuitry that may or may not be part of the peripheral and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating materials of such circuitry may be below the lowest conductive layer 22* and / or above the uppermost conductive layer 22*. For example, one or more select gate layers (not shown) may be between the conductor layer 16 and the lowermost conductive layer 22*, and one or more select gate layers may be above the uppermost portion of the conductive layers 22*. Alternatively or in addition, at least one of the depicted uppermost and lowermost conductive layers 22* may be a select gate layer. Regardless, the conductive layer 22* (alternatively referred to as the first layer) may not include conductive material, and the insulating layer 20* (alternatively referred to as the second layer) may not include insulating material or be insulating when processed in conjunction with the “gate last” or “replacement gate” example method embodiments initially described herein.

[0019] In some embodiments, the lowermost first layer 22z is thicker than the first layer 22* above it, and in one such embodiment is at least 1.5 times the thickness of the first layer 22* above it. In one embodiment, and as shown, the lowermost first layer 22z does not directly abut the conductor material 17 of the conductor layer 16, for example where the lowermost second layer 20z is vertically between the conductor material 17 of the conductor layer 16 and the lowermost first layer 22z. Alternatively, the lowermost first layer may directly abut the conductor material of the conductor layer (not shown). In one embodiment, the lowermost second layer 20z is thinner than the second layer 20* above it. In one embodiment, the second-lowermost second layer 20x above the lowermost second layer 20z is thicker than the second layer 20* above it. In one embodiment, the lowermost second layer 20z directly abuts the top 19 of the conductor material 17 of the conductor layer 16.

[0020] The material of the first layer has a different composition than the material of the second layer. The example conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. The example insulating layer 20* includes a second material 24 (e.g., silicon dioxide) that may be fully or partially sacrificial. The lowermost first layer 22z includes a sacrificial material 21 of a different composition than the first layer material 26 above it and the second layer material 24 above it. The sacrificial material 21 has a composition that is different from the composition of the uppermost portion 23 of the conductor material 17 of the conductor layer 16. The sacrificial material 21 may have a composition that is different from all of the conductor material 17 (not shown). In one embodiment, the different composition includes different composition dopants in the sacrificial material 21 and the uppermost portion 23 of the conductor material 17. For example, and by way of example only, the sacrificial material 21 is shown as including dopants 31 indicated by stippling / dots in the figure. The example conductive doped semiconductive material 13 is also shown as including dopants 31 throughout it, and the example upper portion 23 also includes different composition dopants 33. Different composition dopants 31 and 33 may be uniformly distributed throughout the region or material receiving such dopants, or may be non-uniformly distributed. In one embodiment, and as shown, sacrificial material 21 and uppermost portion 23 of conductor material 17 have the same composition but for the different composition dopants (e.g., dopant 33 is in uppermost portion 23 and not in sacrificial material 21). Regardless, in one embodiment, different composition dopant 33 in uppermost portion 23 is at least 1 x 10 14 The dopant 33 may be provided in the uppermost portion 23 of the conductor material 17, whether or not the material 13 is a conductively doped semiconductive material (e.g., the example dopant 33 may be provided in a metallic material). In addition, as an example, the material 21 of the lowermost first layer 22z may be undoped. In the context of this document, undoped means from 0 atoms / cm3 up to 1x10 13 In one embodiment, the material 21 of the lowermost first layer 22z comprises undoped or phosphorus-doped polysilicon, and in one embodiment, the material 13 comprises phosphorus-doped polysilicon.

[0021] Regardless, in one embodiment, sacrificial material 21 comprises polysilicon, and in one such embodiment, uppermost portion 23 of conductor material 17 comprises polysilicon of a different composition than sacrificial material 21 (e.g., at least through the presence of different composition dopants 33). Regardless, in one embodiment, uppermost portion 23 of conductor material 17 of conductor layer 16 comprises polysilicon. In one embodiment, at least a second lower portion (e.g., 27) below uppermost portion 23 of conductor material 17 has the same composition as sacrificial material 21.

[0022] A channel opening 25 is formed (e.g., by etching) through the insulating layer 20* and the conductive layer 22* to the conductor layer 16. The channel opening 25 may taper radially inward as one moves deeper in the stack 18 (not shown). In some embodiments, the channel opening 25 may enter the conductor material 17 of the conductor layer 16 as shown, or may stop at the top (not shown). Alternatively, as an example, the channel opening 25 may stop at the top or inside the lowermost insulating layer 20. The reason for extending the channel opening 25 at least into the conductor material 17 of the conductor layer 16 is to provide an anchoring effect to the material within the channel opening 25. An etch stop material (not shown) may be within or atop the conductor material 17 of the conductor layer 16 to help stop etching of the channel opening 25 relative to the conductor layer 16 when such is desired. Such an etch stop material may be sacrificial or non-sacrificial.

[0023] Horizontally elongated trenches 40 are formed in stack 18 (e.g., by anisotropic etching) to form laterally spaced memory block regions 58. Trenches 40 may have respective bottoms of conductor material 17 directly against (on top or inside) conductor layer 16 (as shown). By way of example and for simplicity only, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five channel openings 25 per row and arranged in laterally spaced memory block regions 58, which will include laterally spaced memory blocks 58 in a finished circuit configuration. In this document, "block" generally includes "sub-blocks". Memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to be longitudinally extending and, for example, oriented along direction 55. Any alternative existing or future developed arrangements and configurations may be used.

[0024] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thereby including individual channel material strings that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure that is laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cell is vertically along the individual charge blocking region. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

[0025] Figures 1 to 4 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transfer material 34 have been formed vertically along insulating layer 20* and conductive layer 22* in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing their respective thin layers over stack 18 and within individual openings 25 and subsequently planarizing such transistor materials back to at least the top surface of stack 18.

[0026] Channel material 36 is also formed vertically in channel opening 25 along insulating layer 20* and conductive layer 22*, thus comprising individual operative channel material strings 53 in channel opening 25. Channel material 36 can be considered to have its lowermost surface 71. In one embodiment, string 53 of channel material has memory cell materials (e.g., 30, 32, and 34) along it, and wherein a second layer of material (e.g., 24) is horizontally located immediately between strings 53 of channel material. Due to the proportions, materials 30, 32, 34, and 36 are located horizontally between strings 53 of channel material. Figure 1 and 230, 32, 34, and 36. An example channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A stamp etch may be performed to remove materials 30, 32, and 34 from the base of channel opening 25 to expose conductor layer 16 so that channel material 36 is directly against conductor material 17 of conductor layer 16. Such a stamp etch may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur only with respect to some (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 only through separate conductive interconnects (not shown). Channel opening 25 is shown including a radially central solid dielectric material 38 (eg, spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, a radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown).

[0027] See also Figure 6 and 7 , the sacrificial material 21 (not shown) has been isotropically etched selectively relative to the uppermost portion 23 of the conductor material 17 of the conductor layer 16, selectively relative to the first layer material 26 thereabove, and selectively relative to the second layer material 24 thereabove. In one embodiment where a lowermost second layer 20z is present, and as shown, it may also be isotropically etched selectively relative to its material 24. The practitioner may choose to be able to Figure 2 The structure produced Figure 6 any existing or future developed etching chemistry (e.g., wet) and conditions of the construction of. As an example, and by way of example only, some embodiments of the present invention are facilitated in which polysilicon is the primary component in each of materials 21 and 13 and tetramethylammonium hydroxide (TMAH) is used for such isotropic etching. TMAH can be used to selectively etch polysilicon relative to silicon dioxide and silicon nitride (an example of materials 24 and 26 in a gate-last process) when the polysilicon is undoped or phosphorus doped. Adding dopants 33 (other than phosphorus) to polysilicon renders such polysilicon largely unetchable by TMAH, and thus in such examples, using an etching fluid including TMAH to achieve etching from Figure 2 The structure produced Figure 6 structure.

[0028] In one embodiment, after the isotropic etching, the second layer material 24 of the lowermost second layer 20z is etched to expose the upper surface (e.g., 19) of the conductor material 17 of the conductor layer 16 and expose the sidewalls of the channel material 36 of the channel material string 53 in the lowermost first layer 22z. Figure 8 and 9 An example such subsequent processing is shown where, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in each of layers 22z and 20z to expose sidewalls 41 of channel material 36 of channel material string 53 in layer 22z. Any of materials 30, 32, and 34 in layer 22z may be considered sacrificial material therein.

[0029] As an example, consider an embodiment in which material 13 comprises polysilicon, material 24 is silicon dioxide, and memory cell materials 30, 32, and 34 are one or more of silicon dioxide and silicon nitride layers, respectively. In such an example, the depicted construction may be produced by using modified or different chemistries to sequentially etch silicon dioxide and silicon nitride selectively relative to the other chemistry. For example, a solution of 100:1 (by volume) water to HF will selectively etch silicon dioxide relative to silicon nitride, while a solution of 1000:1 (by volume) water to HF will selectively etch silicon nitride relative to silicon dioxide. Thus, and in such an example, such etching chemistries may be used in an alternating manner, where it is desired to achieve the desired etching result from Figure 8 and 9 The example configuration shown. Those skilled in the art will be able to select other chemistries for etching other different materials, where desired. Figure 8 and 9 The structure shown.

[0030] See also Fig.10 and 11 , conductive material 42 has been formed in the lowermost first layer 22z to directly electrically couple the channel material 36 of the individual channel material strings 53 and the conductor material 17 of the conductor layer 16 together. Example conductive materials include conductively doped semiconductor materials (e.g., conductively doped polysilicon, e.g., including dopants 31 in sufficient amounts / concentrations to render the polysilicon conductive) and metal materials. In one embodiment, the conductive material 42 in the lowermost first layer 22z directly abuts against the sidewalls 41 of the channel material 36 of the channel material strings 53, and in one embodiment, the conductive material 42 in the lowermost first layer 22z directly abuts against the uppermost surface (e.g., 19) of the uppermost portion 23 of the conductor material 17 of the conductor layer 16.

[0031] See also Fig.12 and 13, conductive material 42 has been removed from trench 40, such as by a timed isotropic etch that may be selective to materials 24, 26, and 17. This may result in lateral recessing of conductive material 42 toward string of channel material 53 (not shown). This may result in some etching of conductor material 17 when exposed (not shown). An example etch chemistry where material 42 is conductively doped polysilicon, material 24 is silicon dioxide, material 26 is silicon nitride, and uppermost portion 23 of material 13 includes at least one dopant other than phosphorus (in addition thereto) is TMAH.

[0032] refer to Figures 14 to 19 , material 26 (not shown) of conductive layer 22 has been removed, for example, by isotropically etching away through trench 40, ideally selectively relative to other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive layer 22 is sacrificial and has been replaced by conductive material 48 and has thereafter been removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0033] A thin insulating liner (e.g., Al2O3 and not shown) may be formed prior to forming conductive material 48. The approximate location of transistor and / or memory cell 56 is Fig.19 Indicated by brackets, and some Fig.14 , 15 , 17 and 18 are indicated by dashed outlines, where the transistor and / or memory cell 56 is substantially annular or ring-shaped in the depicted example. Alternatively, the transistor and / or memory cell 56 may not completely surround the individual channel openings 25, so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in individual conductive layers, multiple transistors and / or memory cells surround the individual channel openings, where there may be multiple word lines per channel opening in the individual conductive layers, and not shown). The conductive material 48 can be viewed as having an end 50 ( Fig.19 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally located between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an example "gate last" process, conductive material 48 of conductive layer 22 is formed after forming channel opening 25 and / or trench 40. Alternatively, such as with respect to a "gate first" process, conductive material of the conductive layer may be formed prior to forming channel opening 25 and / or trench 40 (not shown).

[0034] The charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate regions 52. The charge blocking member may have the following functions in the memory cell: in the programming mode, the charge blocking member may prevent charge carriers from leaving the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in the erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of each memory cell. The example charge blocking region as shown includes an insulator material 30. By way of other examples, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32) where this storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the intersection of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the intersection of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may act as a charge blocking region and alternatively or additionally may act as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0035] In one embodiment and as shown, lowermost surface 71 of channel material 36 of string of channel material 53 never directly abuts any of conductor materials 17 of conductor layer 16 .

[0036] Intermediate material 57 has been formed between laterally adjacent memory blocks 58 and is formed longitudinally along the laterally adjacent memory blocks. Intermediate material 57 may provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. This may include one or more of insulating, semiconducting, and conductive materials, and in any case, may help prevent shorting of conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intermediate material 57 may include through-array vias (not shown).

[0037] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

[0038] Alternative embodiment configurations may result from the method embodiments described above or otherwise. In any event, embodiments of the present invention encompass integrated circuits that are either currently or will be developed in the future and are independent of manufacturing methods. However, such circuits may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form and / or have any of the properties described with respect to the device embodiments.

[0039] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) including a conductor material (e.g., 17). The array includes laterally spaced memory blocks (e.g., 58) that individually include a vertical stack (e.g., 18) that includes alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*) directly above the conductor layer. The channel material strings (e.g., 53) of the memory cells (e.g., 56) extend through the insulating and conductive layers. The conductive material (e.g., 42) of the lowermost portion (e.g., 22z) of the conductive layer directly electrically couples the channel material (e.g., 36) of the individual channel material strings and the conductor material of the conductor layer together. Intermediate material (e.g., 57) is laterally between laterally adjacent memory blocks and longitudinally along the memory blocks. The intermediary material includes an insulating material. The conductor material in the conductor layer includes a conductively doped semiconductive material having therein one of the primary dopants (e.g., 31) that produces n-type or p-type conductivity. A primary n-type dopant or a primary p-type dopant in this context is something that makes an otherwise semiconductive material conductive due to the concentration of such primary dopant type. At least the uppermost portion (e.g., 23) of the conductor material in the conductor layer includes at least one secondary dopant (e.g., 33) of a composition different from that of the primary dopant.

[0040] In one embodiment, the different primary and secondary dopants are the same n or p type, and in another embodiment are different n or p types. In one embodiment, the secondary dopant is one or more of carbon, nitrogen, boron, arsenic, or a metallic material. In one embodiment, the secondary dopant is one or more of Sb, Bi, Li, Al, or In. In one embodiment, the secondary dopant includes a plurality of different compositions.

[0041] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0042] In one embodiment, a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) including n-type conductivity doped polysilicon (e.g., 13) having a primary dopant (e.g., 31) therein that produces n-type conductivity. The array includes laterally spaced memory blocks (e.g., 58) that individually include a vertical stack (e.g., 18) including alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*) directly above the conductor layer. The string (e.g., 53) of channel material of the memory cell (e.g., 56) extends through the insulating and conductive layers. The lowermost portion (e.g., 20z) of the conductive layer includes n-type conductivity doped polysilicon directly against the n-type conductivity doped polysilicon of the conductor layer and directly against the sidewalls (e.g., 41) of the channel material (e.g., 36) of the string of channel material in the lowermost conductive layer. The intervening material (e.g., 57) is laterally located between the laterally adjacent memory blocks and longitudinally along the memory blocks. The intervening material includes an insulating material. At least the uppermost portion (e.g., 23) of the n-type conductive doped polysilicon in the conductor layer includes at least one secondary dopant of a composition different from that of the primary dopant. In one embodiment, the primary dopant is P and the secondary dopant is one or more of C, N, B, As, Sb, Bi, Li, Al, In, or a metallic material. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0043] The above processing or construction can be considered as an array relative to components, which are formed as a single stack or a single stack of such components or within a single stack or a single stack, which is above the underlying base substrate or as part of the underlying base substrate (but a single stack / stack may have multiple layers). Control and / or other peripheral circuits for operating or accessing such components within the array can also be formed anywhere as part of the finished product construction, and in some embodiments can be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / stacks can be provided or manufactured above and / or below the stacks / stacks shown on the way or described above. In addition, the arrays of components can be the same or different in different stacks / stacks relative to each other, and different stacks / stacks can have the same thickness or different thicknesses relative to each other. Intermediate structures can be provided between vertically adjacent stacks / stacks (e.g., additional circuits and / or dielectric layers). And, different stacks / stacks can be electrically coupled relative to each other. Multiple stacks / stacks can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks can be manufactured substantially simultaneously.

[0044] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0045] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "under", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate that the substrate can be processed relative to during manufacturing (i.e., within 10 degrees), and vertical is a direction generally orthogonal thereto. "Just horizontal" is the direction along the surface of the main substrate that the substrate can be processed relative to during manufacturing (i.e., not at an angle thereto). In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction inclined at least 45° from exactly horizontal. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending" and similar terms relative to a field effect transistor are reference to the orientation of the channel length of the transistor, and in operation, current flows between the source / drain regions along the orientation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," and the like refer to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within 10° of vertical.

[0046] In addition, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Moreover, the use of "above" without a preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components).

[0047] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may include, consist essentially of, or consist of such one or more compositions. In addition, unless otherwise stated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0048] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not uniform. If the two stated materials or regions do not directly abut against each other, then when such materials or regions are not uniform, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical contact with each other, a material, region or structure "directly abuts" another material, region or structure. In contrast, the words “over,” “on,” “adjacent,” “along,” and “against” without being preceded by “directly” encompass “directly against” as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact with each other.

[0049] Herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0050] Any use of "rows" and "columns" herein is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along such "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect at 90° relative to each other, or at one or more other angles (i.e., other than straight angles).

[0051] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductive doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0052] As used herein, any use of "selective" with respect to etching, removing, depositing, forming, and / or forming is such action performed on one stated material relative to another stated material being acted upon in a ratio of at least 2:1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or formation of one material relative to another stated material or materials for at least the first 75 angstroms in a ratio of at least 2:1 by volume.

[0053] Unless otherwise indicated, the use of "or" herein includes either and both.

[0054] in conclusion

[0055] In some embodiments, a method for forming a memory array including a string of memory cells includes: forming a conductor layer including a conductor material on a substrate. A stack including a first layer and a second layer alternating vertically is formed above the conductor layer. The stack includes laterally spaced memory blocks with horizontally elongated trenches therebetween. A string of channel material extends through the first layer and the second layer. The material of the first layer has a different composition than the material of the second layer. The lowermost portion of the first layer includes a sacrificial material having a different composition than the first layer material above it and the second layer material layer above it. The sacrificial material has a different composition than the composition of the uppermost portion of the conductor material of the conductor layer. The sacrificial material isotropically etches selectively relative to the uppermost portion of the conductor material of the conductor layer, selectively relative to the first layer material above it, and selectively relative to the second layer material above it. After the isotropic etching, a conductive material is formed in the lowermost first layer, the conductive material directly electrically coupling the channel material of the individual ones of the string of channel material with the conductor material of the conductor layer.

[0056] In some embodiments, a method for forming a memory array including a string of memory cells includes forming a conductor layer including a conductor material including n-type conductive doped polysilicon on a substrate. A stack including a first layer and a second layer that are vertically alternating is formed above the conductor layer. The stack includes laterally spaced memory blocks with horizontally elongated trenches therebetween. A string of channel material extends through the first layer and the second layer. The material of the first layer has a different composition than the material of the second layer. The lowermost portion of the first layer includes undoped or phosphorus-doped polysilicon. The lowermost portion of the second layer is vertically located between the lowermost first layer and the conductor layer. The undoped or phosphorus-doped polysilicon of the lowermost first layer is selectively isotropically etched relative to the n-type conductive doped polysilicon of the conductor layer and selectively relative to the first layer material above it and the second layer material above it. The etching uses an etching fluid including tetramethylammonium hydroxide. After the isotropic etching, the second layer material of the lowermost second layer is etched to expose the upper surface of the n-type conductive doped polysilicon of the conductor layer. After the isotropic etching, the sidewalls of the channel material of the channel material string are exposed in the lowermost first layer. The conductive material in the lowermost first layer is formed directly against the n-type conductive doped polysilicon of the conductor layer and directly against the exposed sidewalls of the channel material of the channel material string in the lowermost first layer to directly electrically couple the channel material of the individual channel material strings and the conductor material of the conductor layer together.

[0057] In some embodiments, a memory array including a string of memory cells includes a conductor layer including a conductor material. The laterally spaced memory blocks individually include a vertical stack including alternating insulating layers and conductive layers directly above the conductor layer. The channel material string of the memory cell extends through the insulating layer and the conductive layer. The lowermost conductive material of the conductive layer directly electrically couples the channel material of the individual channel material string and the conductor material of the conductor layer together. Intermediate material is laterally located between laterally adjacent memory blocks and longitudinally along the memory blocks. The intermediary material includes an insulating material. The conductor material in the conductor layer includes a conductively doped semiconductive material having one of the primary dopants that produces n-type or p-type conductivity. At least the uppermost portion of the conductor material in the conductor layer includes a secondary dopant of a composition different from the composition of the primary dopant.

[0058] In some embodiments, a memory array including a string of memory cells includes a conductor layer including n-type conductive doped polysilicon having a primary dopant therein that produces n-type conductivity. Laterally spaced memory blocks individually include a vertical stack including alternating insulating layers and conductive layers directly above the conductor layer. The string of channel materials of the memory cells extends through the insulating layer and the conductive layer. The lowermost portion of the conductive layer includes n-type conductive doped polysilicon directly against the conductor layer and directly against the sidewalls of the channel material of the string of channel materials in the lowermost conductive layer. Intermediate material is laterally between laterally adjacent memory blocks and longitudinally along the memory blocks. The intermediary material includes an insulating material. At least the uppermost portion of the n-type conductive doped polysilicon in the conductor layer includes a secondary dopant of a composition different from the composition of the primary dopant.

[0059] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array including a string of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack comprising vertically alternating first and second layers above the conductor layer, the stack comprising laterally spaced memory blocks having horizontally elongated trenches therebetween, strings of channel material extending through the first and second layers, the material of the first layer being of a different composition than the material of the second layer, a lowermost portion of the first layer being a lowermost first layer and comprising a sacrificial material of a different composition than the material of the first layer above it and the material of the second layer above it, the sacrificial material being of a different composition than the composition of the uppermost portion of the conductor material of the conductor layer; isotropically etching the sacrificial material selectively relative to the uppermost portion of the conductor material of the conductor layer, selectively relative to the first layer of material thereover, and selectively relative to the second layer of material thereover; as well as After the isotropic etch, a conductive material is formed in the lowermost first layer that directly electrically couples the channel material of individual ones of the strings of channel material with the conductor material of the conductor layer. The method of claim 1 , wherein the sacrificial material comprises polysilicon. 3 . The method of claim 2 , wherein the uppermost portion of the conductor material of the conductor layer comprises polysilicon of a composition different from that of the sacrificial material. The method of claim 1 , wherein the uppermost portion of the conductor material of the conductor layer comprises polysilicon. 5 . The method of claim 1 , wherein at least a next lower portion below the uppermost portion of the conductor material of the conductor layer has a composition that is the same as a composition of the sacrificial material.

6. The method of claim 1, wherein the different compositions include different composition dopants in the sacrificial material and the uppermost portion of the conductor material.

7. The method of claim 6, wherein the different composition dopant in the uppermost portion is at least 1 x 10 14 atoms / cm3 concentration.

8. The method of claim 6, wherein the different composition dopant in the uppermost portion comprises at least one of carbon, nitrogen, boron, arsenic, or a metallic material.

9. The method of claim 8, wherein the different composition dopant is one or more of As, Sb, Bi, Li, B, Al, or In.

10. The method of claim 6, wherein the sacrificial material and the uppermost portion of the conductor material are of the same composition except for the different composition dopant. The method of claim 1 , wherein the lowermost first layer is thicker than the first layer thereabove. 12 . The method of claim 1 , wherein the lowermost first layer does not directly abut the conductor material of the conductor layer during the isotropic etching. 13 . The method of claim 12 , wherein a lowermost second layer of the second layers is vertically located between the conductor material of the conductor layer and the lowermost first layer during the isotropic etching. The method of claim 13 , wherein the lowermost second layer is thinner than the second layer thereover during the isotropic etching. 15 . The method of claim 14 , wherein a second-lowest second layer among the second layers above the lowermost second layer is thicker than the second layer thereover during the isotropic etching.

16. The method of claim 1, wherein a lowermost surface of the channel material of the string of channel materials never directly abuts any of the conductor materials of the conductor layer.

17. The method of claim 1, wherein the conductive material in the lowermost first layer directly abuts against sidewalls of the channel material of the string of channel material.

18. The method of claim 1, wherein the conductive material in the lowermost first layer directly abuts an uppermost surface of the uppermost portion of the conductive material of the conductor layer.

19. A method for forming a memory array comprising strings of memory cells, comprising: forming a conductor layer including a conductor material on a substrate, wherein the conductor material includes n-type conductive doped polysilicon; forming a stack including vertically alternating first and second layers above the conductor layer, the stack including laterally spaced memory blocks with horizontally elongated trenches between the laterally spaced memory blocks, a channel material string extending through the first layer and the second layer, the material of the first layer being a different composition from the material of the second layer, the lowest of the first layers being a lowermost first layer and comprising undoped or phosphorus-doped polysilicon, the lowest of the second layers being a lowermost second layer and being vertically between the lowermost first layer and the conductor layer; isotropically etching the undoped or phosphorus-doped polysilicon of the lowermost first layer selectively relative to the n-type conductive doped polysilicon of the conductor layer and selectively relative to the first layer of material thereover and the second layer of material thereover, the etching using an etching fluid comprising tetramethylammonium hydroxide; After the isotropic etching, etching the second layer of material of the lowermost second layer to expose an upper surface of the n-type conductive doped polysilicon of the conductor layer; exposing sidewalls of the channel material of the strings of channel material in the lowermost first layer after the isotropic etching; as well as A conductive material is formed in the lowermost first layer directly against the n-type conductive doped polysilicon of the conductor layer and directly against the exposed sidewalls of the channel material of the channel material string in the lowermost first layer to directly electrically couple the channel material of the individual ones of the channel material string and the conductor material of the conductor layer together.

20. A memory array comprising a memory cell string, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks, each of which individually comprises a vertical stack including alternating insulating and conductive layers directly above the conductor layer, strings of channel materials of memory cells extending through the insulating and conductive layers, conductive material of a lowermost one of the conductive layers directly electrically coupling together the channel material of an individual of the string of channel materials and the conductor material of the conductor layer; an intervening material laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the intervening material comprising an insulating material; and The conductor material in the conductor layer comprises a conductively doped semiconductive material having one of a primary dopant producing n-type or p-type conductivity, and at least an uppermost portion of the conductor material in the conductor layer comprises a secondary dopant having a composition different from that of the primary dopant, the secondary dopant comprising carbon.

21. The memory array of claim 20 wherein the one dopant is the primary dopant that produces n-type conductivity.

22. The memory array of claim 20 wherein the one dopant is the primary dopant that produces p-type conductivity.

23. The memory array of claim 20 wherein the uppermost portion of the conductor material of the conductor layer comprises polysilicon.

24. The memory array of claim 20 wherein the secondary dopant in the uppermost portion is at least 1 x 10 14 atoms / cm3 concentration.

25. The memory array of claim 20 including a plurality of secondary dopants of different composition.

26. A memory array comprising a string of memory cells, comprising: a conductor layer comprising n-type conductive doped polysilicon having a primary dopant therein that produces n-type conductivity; laterally spaced memory blocks, individually comprising a vertical stack including alternating insulating and conductive layers directly above the conductor layer, strings of channel materials of memory cells extending through the insulating and conductive layers, a lowermost conductive layer of the conductive layers including polysilicon doped with n-type conductivity directly against the polysilicon doped with n-type conductivity of the conductor layer and directly against sidewalls of channel material of the string of channel materials in the lowermost conductive layer; an intervening material laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the intervening material comprising an insulating material; and At least an uppermost portion of the n-type conductive doped polysilicon in the conductor layer includes a secondary dopant of a composition different from a composition of the primary dopant, the secondary dopant including carbon.

27. The memory array of claim 26 wherein the primary dopant is phosphorus.

28. A memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks, each of which individually comprises a vertical stack including alternating insulating and conductive layers directly above the conductor layer, strings of channel materials of memory cells extending through the insulating and conductive layers, conductive material of a lowermost one of the conductive layers directly electrically coupling together the channel material of an individual of the string of channel materials and the conductor material of the conductor layer; an intervening material laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the intervening material comprising an insulating material; and The conductor material in the conductor layer comprises a conductively doped semiconductive material having one of a primary dopant producing n-type or p-type conductivity, at least an uppermost portion of the conductor material in the conductor layer comprising a secondary dopant having a composition different from that of the primary dopant, and the intermediate material having a bottom portion located above the uppermost portion.

29. A memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks, each of which individually comprises a vertical stack including alternating insulating and conductive layers directly above the conductor layer, strings of channel materials of memory cells extending through the insulating and conductive layers, conductive material of a lowermost one of the conductive layers directly electrically coupling together the channel material of an individual of the string of channel materials and the conductor material of the conductor layer; an intervening material laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the intervening material comprising an insulating material; and The conductor material in the conductor layer comprises a conductively doped semiconductive material having one of a primary dopant producing n-type or p-type conductivity, at least an uppermost portion of the conductor material in the conductor layer comprising a secondary dopant having a composition different from that of the primary dopant, the uppermost portion being located directly below the intermediate material.

30. A memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks, each of which individually comprises a vertical stack including alternating insulating and conductive layers directly above the conductor layer, strings of channel materials of memory cells extending through the insulating and conductive layers, conductive material of a lowermost one of the conductive layers directly electrically coupling together the channel material of an individual of the string of channel materials and the conductor material of the conductor layer; an intervening material laterally between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the intervening material comprising an insulating material; and The conductor material in the conductor layer comprises a conductively doped semiconductive material having one of a primary dopant producing n-type or p-type conductivity, at least an uppermost portion of the conductor material in the conductor layer comprises a secondary dopant having a composition different from that of the primary dopant, and the string of channel material has a bottom located within the uppermost portion.

31. A memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks, each of which individually comprises a vertical stack, the vertical stack comprising alternating insulating and conductive layers directly above the conductor layer, strings of channel materials of memory cells extending through the insulating and conductive layers, the lowest of the conductive layers being a lowermost first layer and the conductive material of the lowermost first layer directly electrically coupling together the channel material of an individual of the string of channel materials and the conductor material of the conductor layer; an intervening material laterally disposed between laterally adjacent ones of the memory blocks and longitudinally along the memory blocks, the intervening material comprising an insulating material; The conductor material in the conductor layer comprises a conductively doped semiconductive material having one of a primary dopant producing n-type or p-type conductivity, at least an uppermost portion of the conductor material in the conductor layer comprising a secondary dopant of a composition different from that of the primary dopant; and The conductive material in the lowermost first layer directly electrically couples together the channel material of individual ones of the strings of channel material and the conductor material of the conductor layer within the uppermost portion.

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