CMOS compatible high-speed low-power random number generator

Abstract

A CMOS-compatible high-speed, low-power random number generator and a technology for using the same are provided. In one aspect, the random number generator includes: a noise amplification unit configured to generate an amplified noise signal, wherein the noise amplification unit includes a noise amplification unit transistor having a threshold voltage (V t,amp ); and a computing unit configured to process the amplified noise signal from the noise amplifying unit to generate a random number stream, wherein the computing unit includes a computing unit transistor having a V greater than that of the noise amplifying unit transistor in the noise amplifying unit. t,amp V t,compute The absolute value of . For a digital implementation, an analog-to-digital converter configured to digitize the amplified noise signal may be employed. For an analog implementation, a sample-and-hold circuit configured to sample the amplified noise signal may be employed. A method for random number generation is also provided.

Description

Technical Field

[0001] The present invention relates to random number generation, and more particularly, to a complementary metal oxide semiconductor (CMOS) compatible high-speed low-power random number generator and its application in random number generation. Background Art

[0002] Random number generation is a crucial element of security systems and is widely used in encryption and secure communications. For example, a unique random key can be generated and transmitted between a host and a user. If the unique random key is generated based on a true random number (rather than a pseudorandom number generated using a mathematical algorithm), it is in principle impossible for other hosts or users to decode it. Random numbers are also of interest in random computing.

[0003] However, physical sources of random fluctuations often impose one or more of the following limitations: (i) they require high power to generate shot noise, such as in avalanche diodes, (ii) they require high power to amplify thermal noise, such as in resistors, (iii) they are incompatible with semiconductor technology, such as shot noise from vacuum tubes. Power consumption is an important factor in many applications where systems are already constrained by battery power for computation and signal transmission.

[0004] For example, solid-state devices such as avalanche diodes (and, to a lesser extent, Zener diodes) can generate significant shot noise, but require high bias voltage and / or current to operate under these conditions. Such devices (e.g., the reverse-biased base-emitter junction of a bipolar transistor) have been used as noise sources for random number generation. However, the required power is too high for applications such as the Internet of Things (IoT), which have strict power constraints.

[0005] Therefore, techniques for low-power, high-speed random number generation would be desirable. Summary of the Invention

[0006] From a first aspect, the present invention provides a random number generator, comprising: a noise amplifying unit transistor having a threshold voltage (V t,amp ); and a computing unit configured to process the amplified noise signal from the noise amplifying unit to generate a random number stream, wherein the computing unit includes a computing unit transistor having a V greater than the noise amplifying unit transistor in the noise amplifying unit t,amp V t,compute The absolute value of .

[0007] From another aspect, the present invention provides a method for random number generation, the method comprising the steps of: generating an amplified noise signal using a noise amplifying unit including a noise amplifying unit transistor having a V of approximately 0; t,amp ; and processing the amplified noise signal from the noise amplifying unit to generate a random number stream using a computing unit including a computing unit transistor having a V greater than the noise amplifying unit transistor t,amp V t,compute The positive absolute value of .

[0008] From another aspect, the present invention provides a random number generator, comprising: a noise amplifying unit configured to generate an amplified noise signal, wherein the noise amplifying unit comprises a V having a value of approximately 0. t,amp at least one load transistor and at least one amplifier transistor; and a computation unit comprising an analog-to-digital converter and a digital processor, wherein the analog-to-digital converter is configured to digitize the amplified noise signal, wherein the digital processor is configured to process the amplified noise signal that has been digitized by the analog-to-digital converter to generate a random number stream, and wherein the computation unit includes a computation unit transistor having a V greater than that of the at least one load transistor and the at least one amplifier transistor. t,amp V t,compute The positive absolute value of .

[0009] From another aspect, the present invention provides a random number generator, comprising: a noise amplifying unit configured to generate an amplified noise signal, wherein the noise amplifying unit comprises a V having a value of approximately 0. t,amp at least one load transistor and at least one amplifier transistor; and a calculation unit comprising a sampling and holding circuit and a comparator, wherein the sampling and holding circuit is configured to sample the amplified noise signal, wherein the comparator is configured to compare the amplified noise signal sampled by the sampling and holding circuit with a reference voltage V ref The comparison is performed to generate a random number stream, and wherein the calculation unit includes a calculation unit transistor having a V greater than at least one load transistor and at least one amplifier transistor. t,amp V t,compute The positive absolute value of .

[0010] The present invention provides a complementary metal oxide semiconductor (CMOS) compatible high-speed low-power random number generator and its application in random number generation.

[0011] In one aspect of the present invention, a random number generator is provided. The random number generator includes: a noise amplifying unit configured to generate an amplified noise signal, wherein the noise amplifying unit includes a threshold voltage (Vt,amp ) of the noise amplifying unit transistor; and a computing unit configured to process the amplified noise signal from the noise amplifying unit to generate a random number stream, wherein the computing unit computing unit transistor includes a V having a larger value than the noise amplifying unit transistor in the noise amplifying unit. t,amp V t,compute The absolute value of .

[0012] In another aspect of the present invention, another random number generator is provided. The random number generator includes: a noise amplifying unit configured to generate an amplified noise signal, wherein the noise amplifying unit includes a V having a value of about 0. t,amp at least one load transistor and at least one amplifier transistor; and a computation unit having an analog-to-digital converter and a digital processor, wherein the analog-to-digital converter is configured to digitize the amplified noise signal, wherein the digital processor is configured to process the amplified noise signal that has been digitized by the analog-to-digital converter to generate a random number stream, and wherein the computation unit includes a computation unit transistor having a V greater than that of the at least one load transistor and the at least one amplifier transistor. t,amp V t,compute The positive absolute value of .

[0013] In another aspect of the present invention, another random number generator is provided. The random number generator includes: a noise amplifying unit configured to generate an amplified noise signal, wherein the noise amplifying unit includes a V having a value of about 0. t,amp at least one load transistor and at least one amplifier transistor; and a calculation unit having a sampling and holding circuit and a comparator, wherein the sampling and holding circuit is configured to sample the amplified noise signal, wherein the comparator is configured to compare the amplified noise signal sampled by the sampling and holding circuit with a reference voltage (V ref ) to generate a random number stream, and wherein the computing unit includes a computing unit transistor having a V greater than at least one load transistor and at least one amplifier transistor t,amp V t,compute The positive absolute value of .

[0014] In another aspect of the present invention, a method for random number generation is provided. The method includes generating an amplified noise signal using a noise amplifying unit having a noise amplifying unit transistor, the noise amplifying unit transistor having a V of approximately 0. t,amp and processing the amplified noise signal from the noise amplifying unit using a computing unit to generate a random number stream, wherein the computing unit has a computing unit transistor having a V greater than the noise amplifying unit transistor t,amp V t,compute The positive absolute value of .

[0015] A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by referring to the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will now be described, by way of example only, with reference to preferred embodiments, as shown in the accompanying drawings:

[0017] Figure 1 is a diagram illustrating an exemplary numerical implementation of the random number generator of the present invention according to an embodiment of the present invention;

[0018] Figure 2 is a diagram illustrating an exemplary simulation implementation of a random number generator of the present invention according to an embodiment of the present invention;

[0019] Figure 3 is a diagram illustrating an exemplary sample and hold circuit according to an embodiment of the present invention;

[0020] Figure 4 is a diagram illustrating an exemplary comparator according to an embodiment of the present invention;

[0021] Figure 5 is a diagram showing a calibration reference voltage (V ref ) of an exemplary system;

[0022] Figure 6 FIG. 1 is a diagram showing a method for generating V according to an embodiment of the present invention. ref A diagram of an exemplary system of FIG.

[0023] Figure 7 is a diagram illustrating an exemplary fin field-effect transistor according to an embodiment of the present invention;

[0024] Figure 8 is a diagram showing an embodiment of the present invention Figure 7 FIG. 1 is a cross-sectional view of a finFET;

[0025] Figure 9 is a cross-sectional view illustrating an exemplary planar FET according to an embodiment of the present invention;

[0026] Figure 10 is a cross-sectional view illustrating solder bump bonding according to an embodiment of the present invention, the solder bump bonding being used to bond a chip including a computing unit to a chip including a noise amplification unit;

[0027] Figure 11 is a cross-sectional view illustrating an exemplary noise amplifier circuit according to an embodiment of the present invention;

[0028] Figure 12is a cross-sectional view illustrating an exemplary noise amplifier circuit having at least one modified load transistor and at least one modified amplification transistor according to an embodiment of the present invention;

[0029] Figure 13 is a cross-sectional view illustrating an Nth stage noise amplifier circuit of a multi-stage noise amplifier design according to an embodiment of the present invention;

[0030] Figure 14 is a cross-sectional view illustrating an exemplary N-stage noise amplifier circuit according to an embodiment of the present invention;

[0031] Figure 15 FIG. 1 is a diagram showing a bias transistor (M) according to an embodiment of the present invention. bias ) is a cross-sectional view of an exemplary N-stage noise amplifier circuit;

[0032] Figure 16 is a diagram illustrating an exemplary method of generating random numbers using the random number generator of the present invention according to an embodiment of the present invention;

[0033] Figure 17 is a graph illustrating how a transistor of a noise amplification unit according to an embodiment of the present invention can be biased at zero gate-to-source voltage and operated under sub-threshold conditions;

[0034] Figure 18 is an exemplary simulation graph showing simulated outputs of various stages of an exemplary high-speed, low-power noise amplification unit according to an embodiment of the present invention;

[0035] Figure 19 is a diagram illustrating an exemplary apparatus for implementing the techniques presented herein, according to an embodiment of the present invention;

[0036] Figure 20 is a diagram illustrating an exemplary method for monolithically co-fabricating a noise amplification unit with a computing unit through selective gate electrode work function modification according to an embodiment of the present invention;

[0037] Figure 21 is a diagram illustrating an exemplary method of monolithically co-fabricating a noise amplification unit with a computing unit through selective substrate doping modification according to an embodiment of the present invention;

[0038] Figure 22 is a diagram illustrating an exemplary method of monolithically co-fabricating a noise amplification unit with a computing unit by selectively increasing the SOI substrate thickness using selective SOI substrate thickness modification of epitaxial growth according to an embodiment of the present invention; and

[0039] Figure 23is a diagram illustrating an exemplary method of monolithically co-fabricating a noise amplification unit with a computing unit by selectively reducing the SOI substrate thickness using selective SOI substrate thickness modification of etching according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] As mentioned above, solid-state devices such as avalanche diodes and Zener diodes can be used as noise sources for random number generation. However, these devices require high bias voltage and / or current to operate and are therefore not suitable for ultra-low power applications such as IoT.

[0041] On the other hand, if a weak noise source is used, a high-gain amplifier is required for amplification. High-gain amplifiers require cascading (thus resulting in higher currents due to multiple stages), cascading (thus higher voltages to ensure transistors remain saturated), or both. Consequently, high-gain amplifiers also require too much power for ultra-low-power applications such as IoT.

[0042] Advantageously, a CMOS compatible high speed, low power random number generator and a technique for use in random number generation are provided herein. The random number generator is a hybrid system comprising a computation unit and a high speed, low power noise amplification unit. Preferably, the noise amplification unit has an operating frequency greater than 100 megahertz (MHz) and a power consumption less than 10 microwatts (μW). For example, in an exemplary embodiment, the noise amplification unit has an operating frequency of approximately 500 MHz and a power consumption of approximately 1 μW. As will be described in detail below, the computation unit comprises standard normally closed (enhancement mode) transistors configured into standard digital, analog, and mixed signal circuits. The threshold voltage of the normally closed transistor has an absolutely positive value (i.e., a positive threshold voltage value for an n-channel transistor and a negative threshold voltage value for a p-channel transistor). The high speed, low power noise amplification unit comprises a transistor having a threshold voltage (V t ) transistors, and these transistors are configured as an amplifier circuit for amplifying the noise generated by the transistors and the resistor bias network. For clarity, the threshold voltage of the computing unit transistor will also be referred to herein as V t,compute , and the threshold voltage of the noise amplifying unit transistor will also be referred to as V t,amp .

[0043] Each amplifier circuit includes at least one amplifier transistor and one load transistor. As described in detail below, in one exemplary embodiment, the amplifier transistor and the load transistor are biased at zero gate-to-source voltage and operate below threshold. The amplified noise generated by the amplifier circuit is then processed by a computation unit to generate a random number stream.

[0044] Figure 1 and Figure 2An overview of the random number generator of the present invention is provided. For example, according to one exemplary embodiment, a digital implementation of the random number generator is shown as Figure 1 In the system 100. Figure 1 As shown, the noise amplified by the noise amplifier 102 (having a noise amplifying unit) is digitized using an analog-to-digital converter (A / D) 104. Then, the digitized noise signal is processed using a digital processor 106 (having a computing unit) to generate a random number. For example, as an example only, when the amplified noise signal has a positive value that can register a logic "1", and when it has a negative value that can register a logic "0", or vice versa. See also the following description of Figure 18 In some embodiments, digital processor 106 is a dedicated processor dedicated to the task of generating random numbers. In other embodiments, digital processor 106 is a general-purpose processor, such as a central processing unit (CPU), that performs various computational tasks in addition to generating random numbers. The noise amplification unit may include other components, such as a battery, a voltage regulator, and / or a noise shield, as are typically used in conjunction with analog amplifier circuits. The computational unit may include or operate in conjunction with various other components of a larger computing system (e.g., see the description below). Figure 19 ).

[0045] According to another exemplary embodiment, a simulation implementation of the random number generator of the present invention is shown as Figure 2 System 200 in. Figure 2 As shown, a sample and hold (S&H) circuit 204 is used to sample the noise signal amplified by the noise amplifier 202 (ie, the noise amplification unit). A comparator 206 (having a calculation unit) compares the amplified noise signal with a reference voltage (V ref ) to generate a random number. For example, for example only, when the amplified noise signal is greater than or equal to V ref , then it can register logic '1', when the amplified noise signal is less than V ref For example, as an example only, when the drain-to-drain supply voltage V dd =1V and the source-to-source supply voltage V ss =0V is used to bias the noise amplifier 202, V ref Can be selected as V ref =V dd / 2 = 0.5 V (see, for example, Figure 18 ). Reference voltage V refCalibration can be performed by averaging (i.e., detecting) the DC level of the noise amplifier output, for example, using a low-pass filter (see below). In some embodiments, the S&H circuit 204 and the comparator circuit 206 are part of an analog or mixed-signal processor fabricated as an integrated circuit and employed in a larger computing system (e.g., see the CMOS circuit described below). Figure 19 ).

[0046] Figure 3 An exemplary sample and hold (S&H) circuit 300 that may be employed in accordance with the present technology is shown. The sample and hold circuit 300 is an analog device that samples a continuously varying noise signal (Signal In) and holds its value at a constant level (Output (Hold Value)).

[0047] Figure 4 An exemplary comparator 400 that may be employed in accordance with the present technology is shown in FIG. IN >V REF , then V OUT =+V C , and if V IN <V REF , then V OUT ::-V C To further reduce power consumption, the power to the noise amplifier 202, the comparator 400, and the S&H circuit 300 may be cut off until the desired key generation start time.

[0048] As provided above, V can be calibrated by averaging the output of the noise amplifier 502 ref For example, see Figure 5 .like Figure 5 As shown, according to an exemplary embodiment, a low pass filter 506 is used to average the DC level output of the noise amplifier 502 to generate V ref A voltage buffer 504 may be employed to protect the signal from being affected by the current drawn by the load.

[0049] Averaging the output from the noise amplifier 502 may be performed continuously to generate V ref See also Figure 6 .like Figure 6As shown, the output of the noise amplifier 502 is fed to a voltage buffer 602, which includes an operational amplifier (OP-AMP) with a unity feedback loop. Resistor R and capacitor C are present at the output of the voltage buffer 602, thereby forming a passive (RC) low-pass filter. Alternatively, the output from the noise amplifier 502 can be averaged over a desired period before the start of a random sequence (e.g., key generation). In some embodiments, the passive RC low-pass filter can be replaced with an active low-pass filter. If such an active low-pass filter has a high input impedance, the voltage buffer can be omitted.

[0050] Transistors: As mentioned above, the computational cell includes standard normally-off (enhancement-mode) transistors that are configured into standard digital, analog, and mixed-signal circuits. "Normally-off" means that the transistors in the computational cell have a positive absolute value of the threshold voltage (i.e., positive for n-channel transistors and negative for p-channel transistors).

[0051] On the other hand, as described above, the noise amplifying unit includes a transistor having a threshold voltage (V t )(i.e. V t,amp ) transistor. For example only, a V t,amp It can be 0±0.3 volts (V), that is, V t,amp From about -0.3V to about 0.3V and in a range therebetween. Typically, each transistor includes a source and a drain interconnected by a channel. A gate regulates the flow of electrons through the channel.

[0052] For field effect transistor (FET) devices, Among them, V FB is the flatband voltage, is the Fermi potential of the semiconductor channel material relative to the intrinsic Fermi level, Q B is the depletion region charge in the channel under the gate, C ox is the dielectric capacitance per unit area of ​​the gate. In addition, for n-type channel doping, For p-type channel doping, is the work function difference between the gate electrode and the channel semiconductor material, Q ox is the equivalent charge associated with the gate dielectric (including fixed charge and interface charge), V th is the thermal voltage (about 26mV at room temperature), N D is the concentration of n-type dopant (acceptor) in the semiconductor channel material, N A is the concentration of p-type dopant (donor) in the semiconductor channel, n i is the intrinsic carrier concentration in the semiconductor channel material, and in, is the work function of the gate electrode and is the work function of the semiconductor channel material Where χ is the electron affinity of the semiconductor channel material, E g is the band gap of the semiconductor channel material, and q is the electron charge. For a bulk-substrate transistor and a depletion region width W D Less than the thickness of the SOI layer T channel (i.e. W D <T channel ) partially depleted silicon-on-insulator (SOI) transistor, for n-type channel doping, Q B =- q N D W D , for p-type channel doping, Q B = q N A W D , where, for n-type channel doping, For p-type channel doping, Among them, ε S is the dielectric constant of the semiconductor channel material. For a fully depleted channel transistor, for n-type channel doping, Q B =-qNDt channel , for p-type channel doping, Q B =qN A t channel .

[0053] Therefore, V t The above parameters can be adjusted during the manufacturing process, especially the substrate doping N A or N D , gate dielectric capacitance C ox , gate electrode work function SOI thickness t channel (Applicable to fully depleted SOI) and their combinations. In addition, after the manufacturing process, the bias voltage V B applied to the body of a bulk transistor or the carrier substrate of an SOI transistor to change the V t For a bulk transistor, for p-type channel doping, the resulting V t The offset is approximately [2εSqN A (-V B )]1 / 2C ox , for n-type channel doping, the resulting V t The offset is approximately -[2 εSq N D (V B )]1 / 2 / C ox For a fully depleted SOI transistor, Vt The offset is approximately -V B C box / C ox (assuming no or small channel doping, thin SOI and / or backside channel inversion), where C box is the dielectric capacitance of the buried insulator. While the above equations are provided as a guide, it should be noted that they are approximate, have a limited range of validity, and can be combined with higher-order device models, numerical simulations, and / or experiments for fine-tuning as needed, as is generally known in the art.

[0054] Figure 7 An exemplary finFET 700 is shown in FIG. As described in detail below, the present technology can be implemented using a combination of planar and non-planar transistor structures (e.g., finFETs) or silicon-on-insulator (SOI) wafer technology. Figure 7 The description of finFET devices in FIG. 5 is for illustrative purposes only and is not intended to limit the present teachings to one particular type of transistor structure.

[0055] like Figure 7 As shown, the source and drain are interconnected by at least one (in this case, a "fin") channel. The gate electrode is offset from the source and drain by a gate spacer. In this example, finFET 700 is formed on an SOI wafer. Typically, an SOI wafer includes an SOI layer separated from the underlying substrate by a buried insulator. When the buried insulator is an oxide, it is also referred to herein as a buried oxide or BOX. Fins are patterned in the SOI layer.

[0056] As explained above, the transistors utilized in the computing unit are manufactured using parameters with standard values ​​that result in V t,compute Absolute positive V t There are many ways to achieve the V value of the transistor used for the noise amplification unit. t Adjusted to have approximately zero V t,ampvalue. For example, in one exemplary embodiment, the transistor is a high-κ / metal gate electrode transistor, such as a FinFET (bulk or silicon on insulator (SOI)), a fully depleted SOI (FDSOI) transistor, and / or a partially depleted SOI (PDSOI) transistor, wherein a high-κ gate dielectric separates the metal gate electrode from the channel. The term "high-κ" refers to a material having a relative dielectric constant κ that is much higher than the relative dielectric constant of silicon dioxide (e.g., for hafnium oxide (HfO2) dielectric constant κ=25, while for SiO2 dielectric constant κ=4). In this case, a metal gate electrode with a lower / higher work function (compared to the work function of the transistor used in the computing unit) can be used for the n-channel / p-channel high-κ / metal gate transistor, respectively, in order to achieve a V of approximately zero. t,amp For example, see Figure 8 .

[0057] Figure 8 is along the finFET 700 (see Figure 7 ) is a cross-sectional view of line AA'. Again, the description of the finFET architecture is a non-limiting example provided only for the purpose of illustrating the present technology. Figure 8 As shown, the gate dielectric separates the fin / channel from the gate electrode. According to an exemplary embodiment, the gate electrode is a metal gate and the gate dielectric is a high-κ gate dielectric. In this case, to achieve a V of approximately zero t,amp , a gate electrode metal having a lower / higher work function than that used for the computing unit can be used for n-channel / p-channel high-κ / metal gate transistors, respectively. For example, if the n-channel transistor in the noise amplification unit has a desired V t The reduction is 3V, so a gate electrode metal having a work function 0.3 electron volts (eV) lower than the work function used for the n-channel transistor in the computing unit can be used for the n-channel transistor in the noise amplification unit.

[0058] Suitable n-type work function setting gate electrode metals include, but are not limited to, titanium nitride (TiN), tantalum nitride (TaN) and / or alloys containing aluminum (Al), such as titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN) and / or tantalum aluminum carbide (TaAlC). Suitable p-type work function setting gate electrode metals include, but are not limited to, TiN, TaN and tungsten (W). When used as p-type work function setting metals, TiN and TaN are relatively thick (e.g., greater than about 2 nm). However, in an n-type work function stack, a very thin TiN or TaN layer (e.g., less than about 2 nm) can also be used under the Al-containing alloy to improve electrical properties such as gate leakage current. Therefore, there is some overlap in the exemplary n-type and p-type work function setting metals given above. Suitable high-κ gate dielectrics include, but are not limited to, HfO2 and / or lanthanum oxide (La2O3).

[0059] By way of example only, the work function of a high-κ / metal gate transistor can be increased / decreased by specifying the specific type / amount of gate electrode metal or combination of metals employed based on the work function. For example, applying an approximately 10 nm thick TaN capping layer on an approximately 3.6 nm thick TiN gate increases the effective work function (EWF) of the gate from approximately 4.3 electron volts (eV) to approximately 4.8 eV, while applying a TiN capping layer of the same thickness on a TiN gate increases the EFW to only approximately 4.6 eV. See, for example, K. Choi et al., "The Effect of Metal Thickness, Overlayer and High-k Surface Treatment on the Effective Work Function of Metal Electrode," Proceedings of the 35th European Solid State Device Research Conference, 2005 (ESSDERC 2005), pp. 101-104 (September 2005).

[0060] Alternatively, according to another exemplary embodiment, the transistors used in the noise amplifier are partially depleted (PD) and are tuned to have a threshold voltage V of approximately zero by using a lower channel doping concentration than that used for the transistors in the computing unit. t,amp Suitable n-type dopants include, but are not limited to, phosphorus (P) and / or arsenic (As). Suitable p-type dopants include, but are not limited to, boron (B). These transistors can be implemented in planar bulk or PDSOI wafer technology. See, for example, Figure 9 .

[0061] Figure 9is a cross-sectional view of a planar FET 900 that may be employed in accordance with the present technology. Again, the depiction of this particular FET architecture is a non-limiting example provided solely for the purpose of illustrating the present technology. Figure 9 As shown, the channel interconnecting the source and drain is partially depleted. The doping concentration of the partially depleted channel can be reduced compared to the doping concentration used in the computing cell to achieve a V of approximately zero. t,amp (relative to the computing unit's V t,compute ). As described above, for example, for a desired V t Reduce ΔV t Depend on Given, where the subscripts “compute” and “amp” refer to the values ​​in the computing unit and the noise amplification unit, respectively. The desired ΔV t Required N A,amp It can be determined by numerically solving the above equation.

[0062] In yet another exemplary embodiment, the V of the transistor used in the noise amplification unit is increased by using a channel doping opposite to that used for the enhancement mode transistor of the same channel type in the computing unit. t is adjusted to approximately zero, thereby creating a depletion-mode transistor in the noise amplifier unit. Note that the channel type (n-channel or p-channel) refers to the type of carriers responsible for conduction in the channel (electrons or holes, respectively), while the channel doping (n-type or p-type) refers to the type of dopant in the channel (donor or acceptor, respectively). For example, an enhancement-mode transistor with p-type channel doping is an n-channel transistor, while a depletion-mode transistor with p-type channel doping is a p-channel transistor.

[0063] In one non-limiting example, a dopant of opposite polarity (n-type or p-type dopant) is used for the channel of the enhancement mode transistor (e.g., opposite to the dopant used for its source and drain in the computing unit), while a dopant of the same polarity (n-type or p-type dopant) is used for the channel of the depletion mode transistor (e.g., the same as the dopant used for its source and drain in the noise amplification unit). For example, in this example, when the source and drain of the enhancement mode transistor are doped with n-type dopant, its channel is doped with p-type dopant, and vice versa, and when the source and drain of the depletion mode transistor are doped with n-type dopant, its channel is also doped with n-type dopant, and vice versa. The channel doping concentration of the depletion mode transistor in the noise amplification unit is selected to produce a threshold voltage of approximately zero, that is, for p-type channel doping, For n-type channel doping,

[0064] The transistors used for the noise amplification and calculation units are manufactured using standard complementary metal oxide semiconductor (CMOS) compatible technology. According to an exemplary embodiment, the noise amplification unit is manufactured monolithically with the calculation unit, for example, on the same integrated circuit chip. For example, see the following description of Figure 20-23 , which shows an exemplary overall manufacturing process flow.

[0065] Alternatively, the noise amplifier is adjusted to have V t The ≈0 V transistor can be fabricated on a separate chip and bonded to a standard chip (including the computational unit) using known bonding techniques such as flip-chip bonding. In some embodiments, this approach is advantageous because it allows for large changes in the manufacturing process flow of the transistor used in the noise amplification unit (e.g., simultaneous changes in various device parameters) without affecting the manufacturing process flow of the standard transistors used in the computational unit.

[0066] Also contemplated herein are embodiments in which both the computational unit and the noise amplification unit are fabricated on a standard chip using standard parameters resulting in absolutely positive V for all transistors. t The chips are then bonded together. A bias voltage is then applied to the substrate of the noise amplifier chip (in the case of a bulk transistor) or the carrier substrate (in the case of an SOI transistor), thereby increasing V t changes to be approximately zero. For example, see Figure 10 ,like Figure 10 As shown, solder bump bonding is used to bond a chip containing at least one transistor for a noise amplification unit (labeled "amplifier chip") to a chip containing at least one standard transistor for a computation unit (labeled "standard chip") via solder balls between metal pads on the bonding surfaces of the respective chips. An underfill material encapsulates the bond within it. The threshold voltage of the transistors in the amplifier chip is then shifted to approximately zero by applying a positive (or negative) bias to the carrier substrate of the n-channel (or p-channel) transistor. The carrier substrate of the standard chip can be connected to, for example, ground as a global ground for the system. Thus, in this exemplary embodiment, standard transistors are manufactured for both the noise amplifier and the computation unit, and the transistors for the noise amplifier are modified by selectively applying a substrate voltage bias to the noise amplifier transistors.

[0067] Noise amplifier: Figure 11 An amplifier circuit 1100 is schematically shown in FIG. 1 , which has a load transistor 1102 (“M LOAD ”) and the amplifier transistor 1104 (“M AMP ”), which have interconnected source and drain electrodes, generating an output voltage (V out). In the conventional amplifier circuit 1100, the load transistor 1102 and the amplifier transistor 1104 are standard transistors. The capacitor (C b ) is used to block the input voltage (V in ) of the DC portion. As is known in the art, a high-pass filter (e.g., b The DC portion of the signal formed by blocking the signal will inevitably also block the low-frequency portion of the signal near DC. b The larger the value, the lower the maximum frequency that is effectively blocked. 1,BIAS and R 2,BIAS ) exist in V in and drain-drain voltage (V dd ) and the source-source voltage (V ss ) between the source and the output.

[0068] With this amplifier circuit 1100, the amplifier voltage gain A V yes:

[0069]

[0070] Among them, g m,load is the transconductance of the load transistor 1102, g m,Amp is the transconductance of the load transistor 1104, r ds,Amp is the drain-source resistance of the amplifier transistor 1104, and “||” indicates a parallel connection (for two given resistors R1 and R2, the resistance resulting from the parallel connection of the two resistors is given by R1||R2=(1 / R1+1 / R2) -1 This is because M LOAD The drain terminal of M is connected to its gate terminal, so LOAD The effective output resistance is equal to 1 / gm，Load Therefore, a large voltage gain (A V =V in / V out Requires M AMP The large transistor width / length (W / L) ratio requires a large bias current, which results in high standby power consumption. Furthermore, since L is typically fixed in the fabricated integrated circuit, a large W / L ratio means a large W and, therefore, a large gate capacitance, which reduces the bandwidth. A large gate capacitance also results in large dynamic (switching) power consumption. Furthermore, the input bias network consumes standby power (in terms of M AMP Providing a positive DC gate voltage bias), which further increases power consumption. AMP A positive DC gate voltage bias is required because it has a positive V t .

[0071] By comparison, in Figure 12 A noise amplifier circuit 1200 according to the present technology is schematically depicted in FIG. Figure 12 As shown, the noise amplifier circuit 1200 includes at least one load transistor (“M LOAD ”) 1202 and at least one amplifying transistor (“M AMP ”) 1204, each having an interconnected source and drain, which together generate an output voltage (V out) The load transistor 1202 and the amplifier transistor 1204 have a V of approximately zero volts. t For example only, according to an exemplary embodiment, the load transistor 1202 and the amplifier transistor 1204 are each modified to V t From about -0.3V to about 0.3V and in the range therebetween. The above provides for facilitating V t About zero technology.

[0072] like Figure 12 As shown, a capacitor (C b ) to block the input voltage (V in ) of the DC part. The bias resistor (R bias ) exists in V in With V ss Between. C b and R bias (or M bias ) creates a high-pass filter. As described above, a high-pass filter (e.g., by C b and R bias The high-pass filter formed by the C filter inevitably blocks the low-frequency part of the signal near DC except DC. b The larger the R bias The larger (more specifically, R bias C b The larger the product of , called RC delay), the lower the maximum frequency effectively blocked by the high-pass filter (i.e., the narrower the stop band of the high-pass filter). As will be described in detail below, this paper also considers the use of bias transistor M bias Instead of R bias Example of .

[0073] Advantageously, with amplifier stage 1200, the amplifier voltage gain A V yes:

[0074] A V ≈-g m,Amp (r ds,Amp ||r ds,Load ) (1)

[0075] Among them, g mis the input of transistor 1204 (g m,Amp ), r ds,Load 、r ds,Amp are the drain-source resistances of the load transistor 1202 and the amplifier transistor 1204, respectively. This is because the gate terminal of the load transistor 1202 is connected to its source terminal, so M LOAD The effective output resistance is equal to r ds，load .because Therefore, a large A can be achieved without a large W / L and a large bias current. V (see above), as long as r ds,Amp and r ds,Load In addition, the input bias network does not consume standby power because M AMP can be biased with zero gate-to-source voltage (because V t ≈0V).

[0076] As will be described in detail below, the noise amplifier of the present invention may be used in a multi-stage (ie, N-stage) design. Figure 13 1 is a schematic diagram illustrating a single-stage noise amplifier circuit 1300 of the multi-stage noise amplifier design. Figure 12 The noise amplifier circuit 1200 described in the description, the noise amplifier circuit 1300 includes at least one load transistor ("M LOAD ”) 1302 and at least one amplifying transistor (“M AMP ”) 1304, which have interconnected sources and drains. When receiving an equivalent input noise voltage (V n,in ), the noise amplifier circuit 1300 generates an equivalent output noise voltage (V n,out ), where V at a given frequency n,out / V n,in The ratio of is equal to the voltage gain of amplifier circuit 1300 at that frequency. Load transistor 1302 and amplifier transistor 1304 have a V of approximately zero. t .

[0077] For example only, according to an exemplary embodiment, the V t From about -0.3V to about 0.3V and in the range therebetween. t The bias resistor (r bias ) exists in V in With V ss between, thus providing a span across M AMPAs will be described in detail below, this paper also considers the use of a bias transistor M biaS Instead of r bias Example of .

[0078] For the single-stage noise amplifier circuit 1300 of the multi-stage noise amplifier design of the present invention:

[0079]

[0080]

[0081]

[0082]

[0083] Furthermore, in some exemplary embodiments considered herein, the bias transistor M is used to bias the transistor M. bias Instead of R bias :

[0084]

[0085] For example, see the following Figure 15 An example of an N-level noise amplifier design using bias transistors is provided in . In the above expression, r out is the output resistance of the amplifier circuit 1300 (r out ≈r ds，Load ||r ds，Amo ), K is the Boltzmann constant, T is the absolute temperature, K is the transistor M Load and M Amp The flicker noise constant, f is the frequency, A V is the voltage gain of the amplifier circuit 1300 . and The symbols represent the spectral density (i.e., frequency spectrum) of the noise voltage and noise current, respectively. For example, It's M Load The noise current spectral density, It is R bias or M bias The noise voltage spectral density.

[0086] In equations (2)-(6) above, the noise voltage and current are given per unit bandwidth of the circuit (by definition, as is conventional). In one or more embodiments, C b and R bias (or M bias ) creates an approximate form |H(f)| 2 ≈f 2 / [1+(f / f L )2 ] is a high-pass filter with a transfer function, where for R bias , f L ≈1 / (2πR bias C b ) or for M bias , f L ≈1 / (2 πrds，bias C b ), in one or more embodiments, the capacitance C of the load output node load (e.g., the input capacitance of the A / D) or the intrinsic cutoff of the transistor (whichever is lower) creates a function with the approximate form |H(f)| 2 ≈1 / [1+(f / f H ) 2 ] is a low-pass filter with a transfer function of H ≈1 / / (2πr out C load ) or f H ≈(g m / 2πC gs ) Amp , where C gs It's M Amp Thus, according to an exemplary embodiment, the total noise voltage output (i.e., integrated over all frequencies) from a single-stage noise amplifier is determined as:

[0087]

[0088] According to an exemplary embodiment, f H ≥100MHz, for example, f H ≥500MHz, and f L is selected to be equal to or greater than M Amp 、M Load and M bias Corner frequency (f C )(i.e., f L ≥f C ). The corner frequency is the frequency at which the flicker noise becomes smaller than the thermal noise (given the 1 / f correlation of the flicker noise). That is, f C =3k gm / 8kTC ox WL. Thus, in such an embodiment, the frequency-dependent (non-white) portion of the noise (i.e., the second term on the right-hand side of equations (3), (4), and (6)) is effectively cancelled, so that L to ~1.4f H At the frequency of n,out According to an exemplary embodiment, f CIn the range from about 100 Hz to about 100 kHz and ranges therebetween, for example, from about 1 kHz to about 10 kHz and ranges therebetween. It is worth noting that the above equations (1)-(7) are first-order expressions that provide an approximate description of circuit 1300 and, therefore, can be used as a guide for describing or designing noise amplification circuits according to the present technology and are not intended to be definitive or limiting.

[0089] Figure 14 is a schematic diagram illustrating an exemplary N-stage noise amplifier circuit 1400 according to the present technology. Figure 14 As shown, the noise amplifier circuit 1400 includes a plurality of stages, namely, stages 1, 2, 3, ..., N-1 and N. For example, as described above according to Figure 12 and Figure 13 Each stage is configured as described in the description of FIG. For example, each stage includes at least one load transistor 1402 and at least one amplifier transistor 1404, each having an interconnected source and drain, which together generate an output voltage (V for stage 1). out,1 , Level 2 V out,2 As described in detail above, the load transistor 1402 and the amplifier transistor 1404 have a V of approximately zero. t By way of example only, according to an exemplary embodiment, the V t From about -0.3V to about 0.3V and in the range therebetween. t The technology of transistors such as load transistor 1402 and amplifier transistor 1404 is approximately zero.

[0090] like Figure 14 As shown, capacitors (C b ) to block the DC portion of the input voltage received from the previous stage. C b With the bias resistor (R bias ) together to create a high pass filter. In some embodiments, V out,N and computing units (such as A / D converters) that receive V out,N Place additional DC blocking capacitors (such as C b ) to block V out,N As mentioned above, C b Blocks the low-frequency near DC portion of the signal passing through it.

[0091] As mentioned above, the bias transistor M biaS Instead of R bias In this case, C b and M bias Creates a high-pass filter. For example, see Figure 15 . Figure 15 1 is a schematic diagram illustrating an exemplary N-stage noise amplifier circuit 1500 according to the present technology. The noise amplifier circuit 1500 is configured to be coupled to the noise amplifier circuit 1400 ( Figure 14 ) is the same except that the bias transistor (M bias ) 1506 replaces the bias resistor (R bias ). In this exemplary embodiment, M bias The gate and source terminals are connected to each other, thus generating a current equal to r ds,bias Equivalent bias resistance, M bias The drain-source resistance.

[0092] That is, Figure 15 As shown, the noise amplifier circuit 1500 includes a plurality of stages, namely, stages 1, 2, 3, ..., N-1, and N. For example, as described above according to Figure 12 and Figure 13 Each stage is configured as described in the description of FIG. For example, each stage includes at least one load transistor 1502 and at least one amplifier transistor 1504, each having an interconnected source and drain, which together generate an output voltage (V for stage 1). out,1 , Level 2 V out,2 As described in detail above, the load transistor 1502 and the amplifier transistor 1504 are each modified so that V t By way of example only, according to an exemplary embodiment, the V t From about -0.3V to about 0.3V and in the range therebetween. t The technology of transistors such as load transistor 1502 and amplifier transistor 1504 is approximately zero.

[0093] like Figure 15 As shown, capacitors (C b ) to block the DC from the input voltage received from the previous stage. Here, C b With bias transistor (M bias )1506 together form a high-pass filter with an RC delay of approximately r ds,bias C b . Similar to Figure 14 The amplifier circuit 1400, the DC blocking capacitor (e.g., C b ) can also be placed in V out,N and the receiving element in the computing unit.

[0094] Figure 16 is a diagram showing the use of a random number generator of the present invention, such as Figure 1system 100 (at least partially digitally implemented) or Figure 2 , a diagram of an exemplary method 1600 for generating random numbers using a system 200 (at least partially an analog implementation) of the present invention. As described above, the random number generator of the present invention is a hybrid system having a computation unit and a noise amplification unit. "Hybrid" means that different types of transistors are combined to form the random number generator, i.e., standard transistors are used in the computation unit, while V transistors are used in the noise amplification unit. t Close to zero. Specifically, the computing unit includes a transistor with an absolute positive V t The standard normally closed transistor is configured as a standard digital, analog and mixed signal circuit. On the other hand, the noise amplifier unit includes V t A transistor having approximately zero resistance and configured as an amplifier circuit for amplifying noise generated by the transistor and a resistor bias network.

[0095] Specifically, for example, in combination with the above Figure 12 and Figure 13 As described in the description, the noise amplification unit may have at least one load transistor and at least one amplifier transistor, each of which has a V t In the range from about -0.3V to about 0.3V and therebetween. In some exemplary embodiments, as described above, the load transistor and the amplifier transistor are biased at zero gate-to-source voltage and operated under a subthreshold condition. In some exemplary embodiments, as described above, by applying a positive (negative) bias to the substrate of the n-channel (p-channel) transistor (e.g., the body substrate of the bulk transistor and the carrier substrate of the SOI transistor), the V t As further described above, the V of the load transistors and the amplifier transistors can be increased by using a lower (higher) gate electrode work function for n-channel (p-channel) transistors, by using a lower doping concentration for the transistor channels, by using opposite doping types for the transistor channels, and / or by using thinner transistor channels relative to standard normally-off transistors such as those used in computing units. t can also be adjusted to approximately zero. Therefore, when modified, the V t is approximately zero, which is consistent with the V t The positive absolute value of is opposite.

[0096] In step 1602, the noise amplifier unit is used to amplify the noise generated by the transistor and the resistive bias network (based on the applied voltage V dd / V ss ) noise, as mentioned above Figure 13 The single-stage amplifier circuit 1300 and its respective Figure 14 and Figure 15The use of the multi-stage amplifier circuits 1400 and 1500 is explained in detail. For example, referring to Figure 14 and Figure 15 , M in level 1 Amp The spectral density of the input referred thermal noise voltage is given by 4kT(2 / 3g m，Amo ). Assume that all amplifier stages have the same voltage gain A V , then M Amp The contribution of the thermal noise to the spectral density of the amplifier's noise voltage output (within the amplifier bandwidth) is given by 4kT (2 / 3g m，Amp ).(A V ) 2N The amplifier output is given. The total spectral density of the noise voltage at is the sum of the spectral densities of the amplified noise contributed by each transistor and resistor in the circuit.

[0097] According to one exemplary embodiment, a digital implementation of the random number generator is employed, whereby the amplified noise from the noise amplification unit is digitized, for example, using an A / D converter. See step 1604. Alternatively, according to another exemplary embodiment, an analog implementation of the random number generator is employed, whereby the amplified noise from the noise amplification unit is sampled, for example, using an S&H circuit. See step 1606.

[0098] In step 1608, the amplified noise from the noise amplification unit is processed by the calculation unit to generate a random number stream. Using a digital implementation (see step 1604 above), the digitized amplified noise signal from the A / D converter is processed by the calculation unit to generate a random number stream. For example, as provided above, when the amplified noise signal is greater than or equal to V ref When the amplified noise signal is less than V ref When V ref = 0 when the amplified noise signal has a zero or positive value that can register a logic '1', and when it has a negative value that can register a logic '0', or vice versa. Alternatively, through an analog implementation (see step 1606 above), the sampled amplified noise signal from the S&H circuit can be compared by the calculation unit with a reference voltage (V ref ) to generate a random number stream. For example, as provided above, when the amplified noise signal is greater than or equal to the V that can register a logic '1' ref When the amplified noise signal is less than the V that can register logic '0' ref or vice versa.

[0099] Figure 171700 is a graph showing how the transistors of the noise amplifier unit can be biased at zero gate-to-source voltage and operated below threshold. In this embodiment, high-κ / metal gate body FinFET transistors are used for the amplifier transistors and load transistors in the amplifier unit, each FinFET transistor having a gate length L=30nm and a fin pitch F=100nm. pitch =80nm, and body (fin) thickness t FIN =15nm. As shown in the graph 1700, the work function of the metal gate (Φ gate ) of 4.61eV has a positive threshold voltage (about 0.5V). However, using Φ gate The metal gate of 4.28 eV lowers the threshold voltage to about zero volts (about 0.2 V), and the transistor operates below threshold at a gate-to-source voltage (VGS) of zero volts (because V GS =0V to V t ≈0.2V is approximately 0.2V lower). In some embodiments, as described above, standard transistors (Φ gate =4.61eV) and V t Near-zero transistors (Φ gate =4.28eV).

[0100] Figure 18 is an exemplary graph 1800 showing the high speed and low power characteristics of the noise amplification unit, in which the high speed and low power characteristics of the noise amplification unit are shown. Figure 17 The description of the FinFET device described (where Φ gate =4.28eV) realizes the noise amplification unit as V dd =1V, Vss=0, R bias =100MΩ, C b =1pF 4-stage amplifier. In this example, V ref Selected to be equal to V dd / 2 = 0.5V. Therefore, when the amplified noise signal has a value greater than or equal to 0.5V, the computing unit can register a logic "1", and when it has a value less than 0.5V, the computing unit can register a logic "0", and vice versa. Using this convention, for example, at 20ns, 40ns, 60ns, 80ns, and 100ns, the V out,4 Sampling can generate a random sequence 11010. Alternatively, in some exemplary embodiments, a DC blocking capacitor (eg, C b ) is placed between the output stage and the computing unit, and V ref is chosen to be zero volts. In this example, each stage consumes approximately 1 V x 10 μA = 10 μW (40 μW total for 4 stages) of DC (standby) power.

[0101] Although Figure 12-15 The transistors used in the exemplary embodiment of the present invention are n-channel transistors, but it will be appreciated that p-channel transistors may also be used (after necessary adjustments to account for the opposite bias polarity of the p-channel transistors). Preferably, all transistors used in the noise amplification unit are either n-channel or p-channel. That is, while the noise amplification unit may be implemented with a combination of n-channel and p-channel transistors (including in a single stage M Amp and M Load with opposite channel types), but for p-channel and n-channel transistors V t Adjusted to approximately zero ratio for only one channel type will V t Adjusting to approximately zero requires greater effort (e.g., a greater number of manufacturing process steps in a monolithic integrated circuit). In addition, as previously mentioned, implementing a noise amplifying cell with a single channel type (n-channel or p-channel) by applying a single bias voltage to the substrate (e.g., to the carrier substrate of an SOI transistor) helps to reduce V t Shifted to approximately zero.

[0102] By way of example only, the random number generator of the present invention may be used in a computer such as Figure 19 The invention is implemented in a computer-based device such as the device 1900. Figure 19 As shown, apparatus 1900 includes a computer system 1910 and removable media 1950. Computer system 1910 includes a processor device 1920, a network interface 1925, a memory 1930, a media interface 1935, and an optional display 1940. Network interface 1925 allows computer system 1910 to connect to a network, while media interface 1935 allows computer system 1910 to interact with media such as a hard drive or removable media 1950. Figure 19 In an exemplary embodiment of the present invention, the random number generator is fabricated on a separate chip and communicates with the processor via input / output (I / O) lines, which may be represented by way of example only as being bonded to a processor such as a processor. Figure 10 1920 .

[0103] Processor device 1920 can be configured to implement the methods, steps, and functions disclosed herein. Memory 1930 can be distributed or local, and processor device 1920 can be distributed or single. Memory 1930 can be implemented as electrical, magnetic, or optical memory, or any combination of these or other types of storage devices. Furthermore, the term "memory" should be interpreted broadly enough to encompass any information that can be read from or written to an address in the addressable space accessible to processor device 1920. Using this definition, information on a network accessible via network interface 1925 is still within memory 1930, as processor device 1920 can retrieve information from the network. It should be noted that each distributed processor comprising processor device 1920 generally contains its own addressable memory space. It should also be noted that some or all of computer system 1910 may be incorporated into a dedicated or general-purpose integrated circuit.

[0104] Optional display 1940 is any type of display suitable for interacting with a human user of device 1900. Typically, display 1940 is a computer monitor or other similar display.

[0105] As described above, in one exemplary embodiment, the noise amplification unit is fabricated monolithically with the computation unit, for example, on the same integrated circuit chip. As will now be described, this monolithic fabrication process can be implemented in a variety of different ways. In each case, a standard CMOS-compatible process flow is used, with minor modifications to enable certain steps to be selectively performed on the noise amplification portion relative to the computation portion, and vice versa. Therefore, the following description will focus on these modifications to the standard process flow, and will refer to fabrication steps performed only on the noise amplification unit transistors and fabrication steps performed only on the computation unit transistors with respect to standard common fabrication steps performed on both the noise amplification unit and computation unit transistors. As used herein, a "standard" CMOS-compatible process refers to any known, established fabrication process for monolithic fabrication of integrated circuits. As known to those skilled in the art, the details of these fabrication processes may vary between different technology nodes (e.g., between the 45nm and 14nm technology nodes) or be adopted or practiced by different research and development facilities. As described above, each transistor typically includes a source and a drain interconnected by a channel, and a gate (separated from the channel by a gate dielectric) that regulates the flow of electrons through the channel. The transistor is fabricated on a substrate, which can be a bulk semiconductor substrate or an SOI substrate with an SOI layer above a buried insulator (e.g., BOX). Source / drain and channel doping can be performed using standard ion implantation techniques with appropriate dopants at the desired concentrations, including doping type (e.g., n-type or p-type).

[0106] In one exemplary embodiment, reference is now made to Figure 20 The method 2000 is described as follows: a transistor in a noise amplification portion of an integrated circuit is fabricated using a structure and a fabrication process identical to the structure and fabrication process of a transistor of the same channel type (i.e., n-type or p-type) in a computing portion of the integrated circuit, except that a gate electrode used in the noise amplification portion is formed of a metal having a work function different from that used in the computing portion, so that the transistor in the noise amplification unit has a V of approximately zero. t .

[0107] Referring to method 2000, a bulk semiconductor or SOI substrate is provided in step 2002, and in step 2004, the noise amplification unit and the computation unit transistors are fabricated until the gate electrode metal deposition step. Next, in step 2006, the standard process flow is modified by masking the noise amplification unit (e.g., with a photoresist and / or dielectric mask) before depositing the gate electrode metal on the computation unit. With the mask formed in place above the noise amplification unit, in step 2008, the (first) gate electrode metal is deposited on the computation unit.

[0108] In step 2010, the mask is removed from the noise amplification portion, and the process is repeated to deposit the gate metal for the noise amplification portion. That is, in step 2012, the computation portion is masked (e.g., with a photoresist and / or dielectric mask), and in step 2014, a (second) gate electrode metal (different from the gate electrode metal for the computation portion) is deposited on the noise amplification portion. In step 2016, the mask is removed from the computation portion, and in step 2018, the transistor and chip fabrication process continues in a standard manner. Figure 20 As shown, the processing steps before step 2006 and after step 2016 are identical for both (noise amplification / computation) transistor types and are therefore shared across both parts of the chip (ie, performed simultaneously).

[0109] Reference now Figure 21 In another exemplary embodiment described in method 2100, transistors in the noise amplification portion of the integrated circuit are fabricated using the same structure and fabrication process as transistors of the same channel type (n-type or p-type) in the computational portion of the integrated circuit, except that the substrate in the noise amplification portion is doped to a lower concentration than that used in the computational portion, so that the V t About zero.

[0110] Referring to method 2100, in step 2102, a bulk semiconductor or SOI substrate is provided, and in step 2104, the noise amplification unit and the computation unit transistors are fabricated until the substrate ion implantation step, wherein the doping concentration of the transistor channel is defined by the ion implantation. Next, in step 2106, the standard process flow is modified by masking the noise amplification portion (e.g., with a photoresist and / or dielectric mask) prior to the ion implantation of the substrate over the computation portion. In step 2108, with the mask appropriately placed over the noise amplification portion, the substrate ion implantation of the computation portion is performed to define the channel doping concentration of the computation portion.

[0111] In step 2110, the mask is removed from the noise amplification portion, and the process is then repeated to define the channel doping concentration of the noise amplification portion. That is, in step 2112, a mask is formed on the calculation portion (for example, using a photoresist and / or dielectric mask), and in step 2114, ion implantation of the substrate is performed on the noise amplification portion (using an ion dose and / or energy different from that used for the calculation portion). In step 2116, the mask is removed from the calculation portion, and in step 2118, the transistor and chip manufacturing process continues in a standard manner. Figure 21 As shown, the processing steps before step 2106 and after step 2116 are exactly the same for both (noise amplification / computation) transistor types and are therefore shared on both parts of the chip (ie, performed simultaneously).

[0112] Reference now Figure 22 In another exemplary embodiment described in method 2200, transistors in the noise amplification portion of the integrated circuit are manufactured using the same structure and manufacturing process as transistors of the same channel type in the computing portion of the integrated circuit, except that the thickness of the SOI substrate in the noise amplification portion is thinner than that used in the computing portion, so that the V t About zero.

[0113] Referring to method 2200, in step 2202, an SOI substrate is provided. Next, in step 2204, the standard process flow is modified by masking the noise amplification portion (e.g., using a dielectric mask) and increasing the thickness of the SOI in the computation portion using selective epitaxial growth in step 2206. In step 2208, the mask is removed from the noise amplification portion, and in step 2210, the transistor and chip fabrication process continues in a standard manner. Figure 22 As shown, the processing steps before step 2204 and after step 2208 are exactly the same for both (noise amplification / computation) transistor types and, therefore, are shared across both parts of the chip (ie, performed simultaneously).

[0114] Reference now Figure 23 In yet another example embodiment described in method 2300, instead of using selective epitaxial growth to increase the thickness of the SOI in the computing portion (as described above), Figure 22 In method 2200 of ), the SOI thickness in the noise amplification unit portion is selectively reduced. For example, referring to method 2300, in step 2302, an SOI substrate is provided. Next, in step 2304, the standard process flow is modified by forming a mask on the calculation portion (for example, using a dielectric mask), and in step 2306, a selective (for example, wet) etching process US is used to reduce the SOI thickness in the noise amplification portion. In step 2308, the mask is removed from the calculation portion, and in step 2310, the transistor and chip manufacturing process continues in a standard manner. Figure 23 As shown, the processing steps before step 2204 and after step 2208 are exactly the same for both (noise amplification / computation) transistor types and, therefore, are shared across both parts of the chip (ie, performed simultaneously).

[0115] Other examples of modifications to the standard process flow for monolithic fabrication encompassed herein include, but are not limited to, using different high-κ materials and / or high-κ materials of different thicknesses for the noise amplification unit (the mask formation step will be the same as described above according to Figure 20 The description of method 2000 is the same as that described for the gate metal change), and the opposite channel doping type is used for the noise amplifier unit (the step of forming the mask will be the same as that described above according to Figure 21 The description of method 2100 is the same as the steps described for varying the channel doping concentration by ion implantation. As will be appreciated by those skilled in the art, varying multiple device parameters (e.g., both channel doping and metal work function) to tune the V t It is also feasible, but it results in a larger number of additional process steps to accommodate the co-integration of the noise amplification part in the monolithic process.

[0116] Although illustrative embodiments of the present invention have been described herein, it should be understood that the invention is not limited to those precise embodiments and that various other changes and modifications may be made by those skilled in the art without departing from the scope of the invention.

Claims

1. A random number generator comprising: A noise amplifying unit configured to generate an amplified noise signal, wherein the noise amplifying unit comprises a noise amplifying unit transistor having a threshold voltage V of approximately 0. t,amp ;as well as a computing unit configured to process the amplified noise signal from the noise amplifying unit to generate a random number stream, wherein the computing unit includes a computing unit transistor having a Vout greater than that of the noise amplifying unit transistor in the noise amplifying unit; t,amp V t,compute The absolute value of .

2. The random number generator according to claim 1, wherein The noise amplification unit and the calculation unit are monolithically integrated on the same integrated circuit chip.

3. The random number generator according to claim 1, wherein The noise amplification unit and the calculation unit are manufactured on separate integrated circuit chips bonded together.

4. The random number generator according to any one of claims 1 to 3, wherein: All of the noise amplifying unit transistors have a common channel type, and wherein the common channel type is n-channel or p-channel.

5. The random number generator according to any one of claims 1 to 3, wherein: The V of the noise amplifying unit transistor in the noise amplifying unit is lowered by applying a voltage bias to the substrate. t,amp shifted to approximately zero volts.

6. The random number generator according to any one of claims 1 to 3, wherein: The noise amplification unit transistor V t,amp ranging from about -0.3V to about 0.3V and therebetween.

7. The random number generator according to any one of claims 1 to 3, wherein: The noise amplification unit transistor includes: at least one load transistor; and At least one amplifier transistor.

8. The random number generator according to claim 7, wherein The V of the at least one load transistor and the at least one amplifier transistor t,amp Approximately 0.

9. The random number generator according to claim 7, wherein: The noise amplification unit comprises N stages of noise amplifiers, wherein at least one stage comprises: A high-pass filter comprising a DC-blocking capacitor C b and bias resistor R bias .

10. The random number generator according to claim 7, wherein The noise amplification unit comprises N stages of noise amplifiers, wherein at least one stage comprises: A high-pass filter comprising a DC-blocking capacitor C b and bias transistor M bias .

11. The random number generator according to any one of claims 1 to 3, wherein: The amplifying unit transistor is biased at zero gate-to-source voltage and operates below threshold.

12. The random number generator according to any one of claims 1 to 3, wherein the amplifying unit transistor includes a transistor configured to convert the V t,amp At least one work function setting metal is tuned to approximately zero.

13. The random number generator according to claim 12, wherein Both the calculation unit transistor and the noise amplification unit transistor include n-channel transistors, and wherein a work function of a metal gate electrode of the n-channel transistor in the noise amplification unit is lower than a work function of the metal gate electrode of the n-channel transistor in the calculation unit.

14. The random number generator according to claim 12, wherein: Both the calculation unit transistor and the noise amplification unit transistor include p-channel transistors, and wherein a work function of a metal gate electrode of the p-channel transistor in the noise amplification unit is higher than a work function of the metal gate electrode of the p-channel transistor in the calculation unit.

15. The random number generator according to any one of claims 1 to 3, wherein: The amplifying unit transistor and the calculating unit transistor have a common channel type, and wherein the amplifying unit transistor has a channel doping concentration lower than a channel doping concentration of the calculating unit transistor.

16. The random number generator according to any one of claims 1 to 3, wherein: The amplification unit transistor and the calculation unit transistor have a common channel type, and wherein the amplification unit transistor has a thinner channel than the calculation unit transistor.

17. The random number generator according to any one of claims 1 to 3, wherein: The amplifying unit transistor and the computing unit transistor have a common channel type, and wherein the amplifying unit transistor includes a channel dopant of opposite polarity to a channel dopant of the computing unit transistor.

18. The random number generator according to claim 7, wherein the calculation unit comprises an analog / digital converter and a digital processor, wherein: The analog-to-digital converter is configured to digitize the amplified noise signal, wherein the digital processor is configured to process the amplified noise signal digitized by the analog-to-digital converter to generate a random number stream, and wherein the calculation unit includes a calculation unit transistor having a V greater than that of at least one load transistor and at least one amplifier transistor. t,amp V t,compute The positive absolute value of .

19. The random number generator according to claim 7, wherein the calculation unit comprises a sample and hold circuit and a comparator, wherein: The sampling and holding circuit is configured to sample the amplified noise signal, wherein the comparator is configured to compare the amplified noise signal sampled by the sampling and holding circuit with a reference voltage V ref The calculation unit comprises a calculation unit transistor having a V greater than that of the at least one load transistor and the at least one amplifier transistor. t,amp V t,compute The positive absolute value of .

20. The random number generator according to claim 18, wherein The V of the at least one load transistor and the at least one amplifier transistor t,am All range from about -0.3V to about 0.3V and therebetween.

21. A method for generating a random number, the method comprising the following steps: An amplified noise signal is generated using a noise amplification unit, the noise amplification unit including a noise amplification unit transistor having a V of approximately 0. t,amp ; as well as Processing the amplified noise signal from the noise amplifying unit using a computing unit to generate a random number stream, wherein the computing unit includes a computing unit transistor having a V t,amp V t,compute The positive absolute value of .

22. The method according to claim 21, wherein The noise amplification unit transistor V t,amp ranging from about -0.3V to about 0.3V and therebetween.

23. The method according to claim 21 or 22, further comprising the steps of: digitizing the amplified noise signal using an analog-to-digital converter; and The amplified noise signal, which has been digitized by the analog-to-digital converter, is processed to generate the random number stream.

24. The method according to claim 21 or 22, further comprising the steps of: The amplified noise signal is sampled using a sample and hold circuit; as well as The amplified noise signal sampled by the sampling and holding circuit is compared with the reference voltage V ref A comparison is performed to generate the random number stream.

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