Diode, method for manufacturing diode, and electrical device

Abstract

The diode is composed of a dual-gate PSJ-GaN FET. The FET has a GaN layer 11, an Al x Ga 1‑x N layer 12, undoped GaN layer 13 and p-type GaN layer 14. x Ga 1‑x A source electrode 19 and a drain electrode 20 are provided on the N layer 12, a first gate electrode 15 is provided on the p-type GaN layer 14, and a second gate electrode 18 is provided on the gate insulating film 17 provided inside the groove 16 provided at the Al2O3 layer between the source electrode 19 and the undoped GaN layer 13. x Ga 1‑x In the N layer 12 , the source electrode 19 , the first gate electrode 15 , and the second gate electrode 18 are connected to each other, or the source electrode 19 and the second gate electrode 18 are connected to each other and a positive voltage relative to the source electrode 19 and the second gate electrode 18 is applied to the first gate electrode 15 .

Description

Technical Field

[0001] The present invention relates to a diode, a method for manufacturing a diode, and an electrical device, and in particular to a diode composed of a double-gate polarization super junction (PSJ) field effect transistor using a gallium nitride (GaN)-based semiconductor, a method for manufacturing the diode, and an electrical device using the diode. Background Art

[0002] Conventionally, PSJ-GaN diodes are known as high withstand voltage power diodes (see Patent Documents 1 and 2). The PSJ-GaN diodes are composed of a three-terminal PSJ-GaN field effect transistor (FET). The PSJ-GaN FET typically has a PSJ region and a contact region, wherein the PSJ region includes an undoped GaN layer, an Al2O3 layer, and a GaN layer stacked in sequence. x Ga 1-x N layer and an undoped GaN layer, wherein the contact region is disposed adjacent to the PSJ region and includes an undoped GaN layer, an Al x Ga 1-x N layer, undoped GaN layer and p-type GaN layer. In addition, a gate electrode is provided on the p-type GaN layer in the contact region, and Al2O3 is provided on both sides of the PSJ region and the contact region. x Ga 1-x A source electrode and a drain electrode are provided on the N layer, and the source electrode and the gate electrode are connected to each other. In a PSJ-GaN diode formed by the PSJ-GaN FET, the source electrode and the gate electrode form an anode electrode, and the drain electrode forms a cathode electrode.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 5828435 (see in particular paragraphs 0069, Fig.23 )

[0006] Patent Document 2: Japanese Patent No. 5669119 (see in particular paragraph 0117, Fig.34 ) Summary of the invention

[0007] Problems to be solved by the invention

[0008] However, although the above-mentioned conventional PSJ-GaN diode can perform high-power switching at high speed, since the on-state voltage is equal to or higher than that of conventional general GaN Schottky diodes, there is room for improvement in energy loss.

[0009] Therefore, the problem to be solved by the present invention is to provide a diode and a method for manufacturing the same, wherein the diode can be used as a high-voltage power diode capable of high-speed high-power switching, and can reduce the on-state voltage and energy loss compared to conventional GaN-based Schottky diodes.

[0010] Another problem to be solved by the present invention is to provide a high-performance electrical device using the above-mentioned diode.

[0011] Means used to solve problems

[0012] In order to solve the above problems, the present invention is a diode, which is composed of a double-gate super-junction GaN field effect transistor.

[0013] The dual-gate superjunction GaN field effect transistor has the following features:

[0014] A first GaN layer;

[0015] Al x Ga 1-x N layer, the Al x Ga 1-x The N layer is on the first GaN layer, 0<x<1;

[0016] The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape;

[0017] a p-type GaN layer, the p-type GaN layer being on the second GaN layer and having a second island shape;

[0018] The source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor;

[0019] A first gate electrode, the first gate electrode being electrically connected to the p-type GaN layer; and

[0020] a second gate electrode, the second gate electrode being provided on a gate insulating film provided in a groove provided in the Al2O3 layer at a portion between the source electrode and the second GaN layer; x Ga 1-x Among the N layers,

[0021] The threshold voltage of the second gate electrode is greater than 0V.

[0022] The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, or the source electrode and the second gate electrode are electrically connected to each other, and a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode,

[0023] An anode electrode is formed by the source electrode, the first gate electrode and the second gate electrode or by the source electrode and the second gate electrode, and a cathode electrode is formed by the drain electrode.

[0024] In this diode, the first GaN layer, Al x Ga 1-x The thickness, conductivity type, composition, etc. of the N layer and the second GaN layer are determined according to the contents described in Patent Documents 1 and 2, for example. x Ga 1-x The N layer is typically undoped, but may be doped with p-type impurities or n-type impurities at a low concentration as required. x Ga 1-x The Al composition x of the N layer can be determined, for example, based on the contents described in Patent Documents 1 and 2. The first gate electrode electrically connected to the p-type GaN layer is typically provided on the p-type GaN layer. In this case, in order to reduce the contact resistance, the p-type impurity concentration of the surface of the p-type GaN layer contacted by the first gate electrode is preferably set to a high concentration.

[0025] In this diode, when not working, the Al x Ga 1-x Two-dimensional hole gas (2DHG) is formed in the second GaN layer at a portion near the heterointerface between the N layer and the second GaN layer, and a two-dimensional hole gas (2DHG) is formed in the first GaN layer and the Al layer. x Ga 1-x Two-dimensional electron gas (2DEG) is formed in the first GaN layer near the heterojunction between the N layers. In this diode, the first gate electrode is controlled to be normally on, and the second gate electrode is controlled to be normally off. By controlling the first gate electrode to be normally on and the second gate electrode to be normally off, when the threshold voltage V is not applied to the second gate electrode, th When the voltage is above 20V, the 2DEG directly below the second gate electrode is interrupted, and the diode is turned off. However, when the threshold voltage V is applied to the second gate electrode, th When the voltage is above 100V, a channel including 2DEG is formed, thereby connecting the source electrode and the drain electrode, and the diode is turned on.

[0026] In order to electrically connect the source electrode, the first gate electrode and the second gate electrode to each other, an electrode is typically provided to cover the source electrode, the first gate electrode and the second gate electrode. In addition, in order to electrically connect the source electrode and the second gate electrode to each other, an electrode is typically provided to cover the source electrode and the second gate electrode.

[0027] The Al disposed at the portion between the source electrode and the second GaN layer x Ga 1-x Al in the groove part of the N layer x Ga 1-x The thickness of the N layer is usually greater than or equal to 3 nm and less than or equal to 100 nm, and typically greater than or equal to 3 nm and less than or equal to 30 nm.

[0028] The gate insulating film includes a p-type semiconductor or an insulator. The p-type semiconductor is, for example, p-type GaN, p-type InGaN, NiO x etc., but not limited thereto. Since the p-type semiconductor is a thin film, it is depleted and can be regarded as an insulator, but it is believed that the p-type has the effect of increasing the electron barrier of the channel, and the leakage current becomes smaller, so it is effective. Insulators include, for example, inorganic oxides, inorganic nitrides, inorganic nitrogen oxides, etc. Specifically, Al2O3, SiO2, AlN, SiN x , SiON, etc., but not limited to these.

[0029] The above-mentioned diode can be manufactured by various methods, but can be preferably manufactured by the following method.

[0030] That is, the present invention is a method for manufacturing a diode, wherein the diode is composed of a double-gate superjunction GaN-based field effect transistor.

[0031] The dual-gate superjunction GaN field effect transistor has the following features:

[0032] A first GaN layer;

[0033] Al x Ga 1-x N layer, the above Al x Ga 1-x The N layer is on the first GaN layer, 0<x<1;

[0034] The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape;

[0035] A p-type GaN layer, the p-type GaN layer is on the second GaN layer and has a second island shape;

[0036] The source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor;

[0037] a first gate electrode, the first gate electrode being electrically connected to the p-type GaN layer; and

[0038] A second gate electrode is provided on a gate insulating film provided in a groove, wherein the groove is provided at the Al2O3 layer at a portion between the source electrode and the second GaN layer. x Ga 1-x Among the N layers,

[0039] The threshold voltage of the second gate electrode is greater than 0V.

[0040] The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, or the source electrode and the second gate electrode are electrically connected to each other, and a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode,

[0041] The source electrode, the first gate electrode and the second gate electrode or the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, characterized in that:

[0042] The manufacturing method of the diode has the following steps:

[0043] The first GaN layer, the Al layer, and the like are sequentially grown on the entire surface of the base substrate. x Ga 1-x N layer, the second GaN layer and the p-type GaN layer;

[0044] By forming the p-type GaN layer, the second GaN layer and the Al x Ga 1-x The N layer is etched to the above Al x Ga 1-x A step of forming the groove to a depth halfway through the N layer;

[0045] A step of growing a p-type GaN layer for forming a gate insulating film on the p-type GaN layer so as to fill the groove;

[0046] The step of patterning the gate insulating film-forming p-type GaN layer and the p-type GaN layer by etching to form the second island shape and forming the gate insulating film;

[0047] In the above Al x Ga 1-xA step of forming the source electrode and the drain electrode on the N layer;

[0048] forming the first gate electrode and the second gate electrode on the p-type GaN layer for forming the gate insulating film formed into the second island shape and the gate insulating film, respectively; and

[0049] A step of forming an electrode covering the source electrode, the first gate electrode, and the second gate electrode, or an electrode covering the source electrode and the second gate electrode.

[0050] In addition, the present invention is a method for manufacturing a diode, wherein the diode is composed of a double-gate superjunction GaN field effect transistor.

[0051] The dual-gate superjunction GaN field effect transistor has the following features:

[0052] A first GaN layer;

[0053] Al x Ga 1-x N layer, the above Al x Ga 1-x The N layer is on the first GaN layer, 0<x<1;

[0054] The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape;

[0055] A p-type GaN layer, the p-type GaN layer is on the second GaN layer and has a second island shape;

[0056] The source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor;

[0057] a first gate electrode, the first gate electrode being electrically connected to the p-type GaN layer; and

[0058] A second gate electrode is provided on a gate insulating film provided in a groove, wherein the groove is provided at the Al2O3 layer at a portion between the source electrode and the second GaN layer. x Ga 1-x Among the N layers,

[0059] The threshold voltage of the second gate electrode is greater than 0V.

[0060] The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, or the source electrode and the second gate electrode are electrically connected to each other, and a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode,

[0061] The source electrode, the first gate electrode and the second gate electrode or the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, characterized in that:

[0062] The manufacturing method of the diode has the following steps:

[0063] The first GaN layer, the Al layer, and the like are sequentially grown on the entire surface of the base substrate. x Ga 1-x N layer, the second GaN layer and the p-type GaN layer;

[0064] The step of patterning the p-type GaN layer and the second GaN layer into the second island shape and the first island shape, respectively, by etching;

[0065] In the above Al x Ga 1-x A step of forming the source electrode and the drain electrode on the N layer;

[0066] By x Ga 1-x The N layer is etched to the above Al x Ga 1-x A step of forming the groove to a depth halfway through the N layer;

[0067] forming the gate insulating film inside the groove;

[0068] forming the first gate electrode and the second gate electrode on the p-type GaN layer and the gate insulating film, respectively; and

[0069] A step of forming an electrode covering the source electrode, the first gate electrode, and the second gate electrode, or an electrode covering the source electrode and the second gate electrode.

[0070] In addition, the present invention is a method for manufacturing a diode, wherein the diode is composed of a double-gate superjunction GaN field effect transistor.

[0071] The dual-gate superjunction GaN field effect transistor has the following features:

[0072] A first GaN layer;

[0073] Al x Ga1-x N layer, the above Al x Ga 1-x The N layer is on the first GaN layer, 0<x<1;

[0074] The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape;

[0075] A p-type GaN layer, the p-type GaN layer is on the second GaN layer and has a second island shape;

[0076] The source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor;

[0077] a first gate electrode, the first gate electrode being electrically connected to the p-type GaN layer; and

[0078] A second gate electrode is provided on a gate insulating film provided in a groove, wherein the groove is provided at the Al2O3 layer at a portion between the source electrode and the second GaN layer. x Ga 1-x Among the N layers,

[0079] The threshold voltage of the second gate electrode is greater than 0V.

[0080] The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, or the source electrode and the second gate electrode are electrically connected to each other, and a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode,

[0081] The source electrode, the first gate electrode and the second gate electrode or the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, characterized in that:

[0082] The manufacturing method of the diode has the following steps:

[0083] The first GaN layer, the first Al layer, and the x Ga 1-x The step of forming a p-type GaN layer for the N layer and the gate insulating film;

[0084] forming a first mask on the p-type GaN layer for forming a gate insulating film, wherein the first mask includes an inorganic insulator having the same shape as the groove;

[0085] A step of using the first mask as an etching mask to pattern the p-type GaN layer for forming a gate insulating film by etching, thereby forming the gate insulating film;

[0086] The first mask is used as a growth mask. x Ga 1-x The second Al x Ga 1-x N layer, the second GaN layer and the p-type GaN layer;

[0087] forming a second mask on the p-type GaN layer, wherein the second mask includes an inorganic insulator having the same shape as the second island shape;

[0088] A step of using the second mask as an etching mask to pattern the p-type GaN layer by etching;

[0089] forming a third mask so as to cover the second mask, wherein the third mask includes an inorganic insulator having the same shape as the first island shape;

[0090] A step of using the third mask as an etching mask to pattern the second GaN layer by etching;

[0091] In the above second Al x Ga 1-x A step of forming the source electrode and the drain electrode on the N layer;

[0092] forming the first gate electrode and the second gate electrode on the p-type GaN layer and the gate insulating film, respectively;

[0093] A step of forming an electrode covering the source electrode, the first gate electrode, and the second gate electrode, or an electrode covering the source electrode and the second gate electrode.

[0094] In addition, the present invention is an electrical device, wherein the electrical device has at least one diode.

[0095] The diode is composed of a dual-gate superjunction GaN field effect transistor.

[0096] The dual-gate superjunction GaN field effect transistor has the following features:

[0097] A first GaN layer;

[0098] Al x Ga 1-x N layer, the above Al x Ga 1-x The N layer is on the first GaN layer, 0<x<1;

[0099] The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape;

[0100] A p-type GaN layer, the p-type GaN layer is on the second GaN layer and has a second island shape;

[0101] The source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor;

[0102] a first gate electrode, the first gate electrode being electrically connected to the p-type GaN layer; and

[0103] A second gate electrode is provided on a gate insulating film provided in a groove, wherein the groove is provided at the Al2O3 layer at a portion between the source electrode and the second GaN layer. x Ga 1-x Among the N layers,

[0104] The threshold voltage of the second gate electrode is greater than 0V.

[0105] The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, or the source electrode and the second gate electrode are electrically connected to each other, and a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode,

[0106] An anode electrode is formed by the source electrode, the first gate electrode and the second gate electrode or by the source electrode and the second gate electrode, and a cathode electrode is formed by the drain electrode.

[0107] Here, electrical equipment generally includes all equipment that uses electricity, regardless of purpose, function, size, etc., such as electronic equipment, mobile objects, power devices, construction machinery, machine tools, etc. Electronic equipment includes robots, computers, game consoles, vehicle-mounted equipment, home electronic products (air conditioners, etc.), industrial products, mobile phones, mobile devices, IT equipment (servers, etc.), power conditioners used in solar power generation systems, power transmission systems, etc. Mobile objects include railway vehicles, automobiles (electric vehicles, etc.), two-wheeled vehicles, airplanes, rockets, spacecraft, etc.

[0108] Regarding the invention of the electric device, the matters other than the above-mentioned matters that have been described in connection with the invention of the diode mentioned above are established.

[0109] Effects of the Invention

[0110] According to the present invention, a diode is formed by using a dual-gate superjunction GaN-based field effect transistor, so that it can be used as a high-voltage power diode capable of high-speed high-power switching, and the threshold voltage V of the second gate electrode, which is the on-state voltage of the diode, can be easily reduced compared to the conventional GaN-based Schottky diode. th , thus reducing energy loss. Moreover, high-performance electrical equipment can be realized using this excellent diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0111] [ Figure 1 ] is a cross-sectional view showing a PSJ-GaN diode according to one embodiment of the present invention.

[0112] [ Figure 2 ] is a schematic diagram showing a connection method between electrodes of a PSJ-GaN diode according to an embodiment of the present invention.

[0113] [ Figure 3 ] is a schematic diagram showing another connection method between electrodes of a PSJ-GaN diode according to an embodiment of the present invention.

[0114] [ Figure 4 ]To show the use of Figure 2 FIG. 1 is a cross-sectional view of a PSJ-GaN diode according to an embodiment of the present invention, showing a wiring configuration.

[0115] [ Figure 5 ]To show the use of Figure 3 FIG. 1 is a cross-sectional view of a PSJ-GaN diode according to an embodiment of the present invention, showing a wiring configuration.

[0116] [ Figure 6 ] is a schematic diagram showing the current-voltage characteristics of a PSJ-GaN diode according to an embodiment of the present invention.

[0117] [ Figure 7 ] is a schematic diagram for illustrating the working principle of a PSJ-GaN diode according to an embodiment of the present invention.

[0118] [ Figure 8 ] is a schematic diagram for illustrating the working principle of a PSJ-GaN diode according to an embodiment of the present invention.

[0119] [ Fig. 9 ] is a schematic diagram for illustrating the working principle of a PSJ-GaN diode according to an embodiment of the present invention.

[0120] [ Fig.10] is a schematic diagram for illustrating the working principle of a PSJ-GaN diode according to an embodiment of the present invention.

[0121] [ Fig.11 ] is a schematic diagram for illustrating the working principle of a PSJ-GaN diode according to an embodiment of the present invention.

[0122] [ Fig.12 ] is a schematic diagram for illustrating the working principle of a PSJ-GaN diode according to an embodiment of the present invention.

[0123] [ Fig.13 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 1.

[0124] [ Fig.14 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 1.

[0125] [ Fig.15 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 1.

[0126] [ Fig.16 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 1.

[0127] [ Fig.17 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 1.

[0128] [ Fig.18 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 1.

[0129] [ Fig.19 ] is a schematic diagram showing a dual-gate PSJ-GaN system FET, which constitutes a PSJ-GaN system diode manufactured by the manufacturing method of the PSJ-GaN system diode according to Example 1.

[0130] [ Fig. 20 ] shows the I of the dual-gate PSJ-GaN FET D -V D Schematic diagram of characteristics of the dual-gate PSJ-GaN system FET constituting a PSJ-GaN system diode manufactured by the method for manufacturing a PSJ-GaN system diode according to Example 1.

[0131] [ Fig.21 ] shows the I of the dual-gate PSJ-GaN FET D -V DSchematic diagram of characteristics of the dual-gate PSJ-GaN system FET constituting a PSJ-GaN system diode manufactured by the method for manufacturing a PSJ-GaN system diode according to Example 1.

[0132] [ Fig. 22 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to a variation of Example 1.

[0133] [ Fig.23 ] is a schematic diagram showing a dual-gate PSJ-GaN system FET, wherein the dual-gate PSJ-GaN system FET constitutes a PSJ-GaN system diode manufactured by a manufacturing method of a PSJ-GaN system diode according to a modified example of Example 1.

[0134] [ Fig.24 ] is a schematic diagram showing the current-voltage characteristics of a PSJ-GaN diode manufactured by a method for manufacturing a PSJ-GaN diode according to a modified example of Example 1.

[0135] [ Fig.25 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 2.

[0136] [ Fig.26 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 2.

[0137] [ Fig. 27 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 2.

[0138] [ Fig.28 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 2.

[0139] [ Fig.29 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3.

[0140] [ Fig.30 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3.

[0141] [ Fig.31 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3.

[0142] [ Fig.32 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3.

[0143] [ Fig.33] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3.

[0144] [ Fig.34 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3.

[0145] [ Fig.35 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3.

[0146] [ Fig.36 ] is a cross-sectional view showing a method for manufacturing a PSJ-GaN diode according to Example 3. DETAILED DESCRIPTION

[0147] Hereinafter, a mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.

[0148] <One embodiment>

[0149] [PSJ-GaN diode]

[0150] A PSJ-GaN diode according to one embodiment is described. The basic structure of the PSJ-GaN diode is shown in FIG. Figure 1 The PSJ-GaN diode is composed of a double-gate PSJ-GaN FET.

[0151] like Figure 1 As shown, in the PSJ-GaN diode, GaN layer 11, undoped Al x Ga 1-x N layer 12, undoped GaN layer 13 and p-type GaN layer 14 doped with Mg. GaN layer 11 may be undoped or doped with p-type or n-type impurities at a low concentration. x Ga 1-x The Al composition x of the N layer 12 is, for example, 0.17≤x≤0.35, but is not limited thereto. The undoped GaN layer 13 has a predetermined island-shaped planar shape. The p-type GaN layer 14 has an island-shaped planar shape that is smaller than the undoped GaN layer 13. Although not shown in the figure, a p-type GaN layer 14 doped with Mg at a higher concentration than the p-type GaN layer 14 is provided on the surface of the p-type GaN layer 14. + Type GaN layer. Below, p + The p-type GaN layer is included in the p-type GaN layer 14. These GaN layers 11, undoped Al x Ga 1-x The N layer 12 , the undoped GaN layer 13 , and the p-type GaN layer 14 are the same as those of the PSJ-GaN system FETs described in Patent Documents 1 and 2, for example.

[0152] The first gate electrode 15 is provided on the p-type GaN layer 14 in ohmic contact with the p-type GaN layer 14. The first gate electrode 15 can be basically any gate electrode as long as it is in ohmic contact with the p-type GaN layer 14, for example, a Ni film, a Ni / Au stacked film, etc. x Ga 1-x A groove 16 is provided on the N layer 12. A gate insulating film 17 made of a p-type semiconductor or insulator is buried in the groove 16. A second gate electrode 18 is provided on the gate insulating film 17. The second gate electrode 18 is made of, for example, a film containing at least one metal selected from the group consisting of Ti, Ni, Au, Pt, Pd, Mo, and W. The undoped Al in the groove 16 portion x Ga 1-x The thickness of the N layer 12 is usually 3 nm to 100 nm, and typically 3 nm to 30 nm. In addition, the thickness of the gate insulating film 17 is usually 3 nm to 100 nm, and typically 3 nm to 30 nm. x Ga 1-x A source electrode 19 and a drain electrode 20 are provided on the N layer 12 so as to sandwich the undoped GaN layer 13 . The source electrode 19 is provided on a portion of the second gate electrode 18 on the opposite side to the undoped GaN layer 13 .

[0153] In the PSJ-GaN diode, the portion of the undoped GaN layer 13 from the end of the p-type GaN layer 14 on the drain electrode 20 side to the end of the undoped GaN layer 13 on the drain electrode 20 side and the GaN layer 11 and the undoped Al layer 11 directly therebelow are connected. x Ga 1-x The N layer 12 forms the PSJ region, and the p-type GaN layer 14 and the GaN layer 11 directly below it, and the undoped Al x Ga 1-x The N layer 12 and the undoped GaN layer 13 constitute a gate electrode contact region.

[0154] In this PSJ-GaN diode, when not in operation (at thermal equilibrium), the undoped Al x Ga 1-x 2DHG is formed in the undoped GaN layer 13 at a portion near the heterointerface between the N layer 12 and the undoped GaN layer 13, and 2DHG is formed in the GaN layer 11 and the undoped Al layer 13. x Ga 1-x 2DEG is formed in the GaN layer 11 at a portion near the heterointerface between the N layers 12 .

[0155] In this PSJ-GaN diode, the control by the first gate electrode 15 is a normally-on type, and the control by the second gate electrode 18 is a normally-off type. The threshold voltage of the second gate electrode 18 is typically 0V or more and 0.9V or less.

[0156] There are two types of connection methods for the source electrode 19 , the first gate electrode 15 , and the second gate electrode 18 in the PSJ-GaN diode. Figure 2 A wiring method is shown, which is a method of electrically connecting the source electrode 19, the first gate electrode 15, and the second gate electrode 18 to each other. Figure 3 Another wiring method is shown, in which the source electrode 19 and the second gate electrode 18 are electrically connected to each other and a constant voltage that is positive relative to the source electrode 19 and the second gate electrode 18 is applied to the first gate electrode 15. Figure 3 In the wiring method shown, by applying a positive constant voltage to the first gate electrode 15, there is an advantage that the number of carriers in the 2DEG channel increases, and the channel conductivity increases.

[0157] In this PSJ-GaN diode, Figure 2 In the wiring method shown in the figure, the source electrode 19, the first gate electrode 15 and the second gate electrode 18 constitute an anode electrode, and the drain electrode 20 constitutes a cathode electrode. Figure 3 In the wiring method shown, the source electrode 19 and the second gate electrode 18 constitute an anode electrode, and the drain electrode 20 constitutes a cathode electrode. The PSJ-GaN diode can operate as a diode by applying a voltage between the source electrode 19 constituting the anode electrode, the first gate electrode 15 and the second gate electrode 18 and the drain electrode 20 constituting the cathode electrode, or between the source electrode 19 and the second gate electrode 18 constituting the anode electrode and the drain electrode 20 constituting the cathode electrode.

[0158] In order to carry out Figure 2 The wiring shown is as follows Figure 4 As shown in FIG. 1 , an electrode 21 including Au or the like is formed so as to cover the source electrode 19, the first gate electrode 15, and the second gate electrode 18. Figure 3 The wiring shown is as follows Figure 5 As shown, an electrode 22 made of Au or the like is formed so as to cover the source electrode 19 and the second gate electrode 18 .

[0159] [Operation of PSJ-GaN diode]

[0160] The operation of the PSJ-GaN diode formed of a dual-gate PSJ-GaN FET will be described.

[0161] The current-voltage characteristics of the PSJ-GaN diode formed by the dual-gate PSJ-GaN FET are shown in FIG. Figure 6 .like Figure 6 As shown, the starting voltage, that is, the on-state voltage, is the threshold voltage V of the second gate electrode 18. th .exist Figure 6 For comparison, the current-voltage characteristics of a conventional GaN Schottky diode are also shown. The threshold voltage of a conventional GaN Schottky diode is about 0.9 V, whereas the threshold voltage V of the PSJ-GaN diode is about 1.2 V. th It may be at least about 0.9V or less, and typically much less than about 0.9V.

[0162] exist Figure 7 A general 3-terminal FET of the MESFET type is schematically shown in FIG. Figure 7 As shown, a gate electrode 102, a source electrode 103 and a drain electrode 104 are provided on the channel layer 101. A gate voltage V is applied to the gate electrode 102. g , the drain electrode 104 is applied with a drain voltage V d The source electrode 103 is grounded. The threshold voltage of the three-terminal FET is set to V th As is known to all, in this 3-terminal FET, the drain voltage V d When the drain current (I d )-Drain voltage (V d ) Characteristics such as Figure 8 Here, at V g >V th When d Flow. When V d When changing to the negative side, due to V d <0, so the current flows to the drain electrode 104 side. At this time, I d -V d Features appear in Figure 8 Therefore, in order for the current to flow between the source electrode 103 and the drain electrode 104, V d -V g >V th In addition, at V g =0V, at V d <-V th Current flows when V g =0V means, if Fig. 9 As shown, the voltage of the source electrode 103 and the gate electrode 102 are equal. Figure 8 Only V g =0V I d -V d Characteristics, then Fig.10 Observation Fig.10 When d -Vd The characteristic is on-state voltage = V th In other words, Fig. 9 The FET shown has Fig.11 The diode characteristics shown in Figure 1 show the starting voltage V th of Fig.12 As a result, the PSJ-GaN diode has Figure 6 Features shown.

[0163] [PSJ-GaN diode manufacturing method]

[0164] An example of a method for manufacturing a PSJ-GaN diode will be described.

[0165] An undoped or low-concentration doped GaN layer 11, an undoped Al layer 20 and a doped GaN layer 30 are sequentially grown on the entire surface of a base substrate (not shown) by a conventionally known MOCVD (metal organic chemical vapor deposition) method or the like. x Ga 1-x N layer 12, undoped GaN layer 13 and p-type GaN layer 14. As the base substrate, a general substrate used in the growth of GaN layer in the past, such as C-plane sapphire substrate, Si substrate, SiC substrate, etc. can be used. Next, the undoped GaN layer 13 and p-type GaN layer 14 are patterned, and the undoped Al x Ga 1-x The groove 16 is formed on the N layer 12, the gate insulating film 17 is embedded in the groove 16, and the first gate electrode 15, the second gate electrode 18, the source electrode 19 and the drain electrode 20 are formed, thereby manufacturing Figure 1 PSJ-GaN diode shown. It should be noted that in the undoped Al x Ga 1-x When the groove 16 is formed in the N layer 12 by etching, the undoped Al x Ga 1-x An etching stop layer made of, for example, In(Al)GaN is inserted at a depth midway in the thickness direction of the N layer 12. Figure 2 In the case of the wiring method shown, Figure 4 As shown, an electrode 21 is formed to connect the source electrode 19, the first gate electrode 15 and the second gate electrode 18. Figure 3 In the case of the wiring method shown, Figure 5 As shown, an electrode 22 connecting the source electrode 19 and the second gate electrode 18 is formed.

[0166] [Example 1]

[0167] The PSJ-GaN diode was manufactured as follows.

[0168] First, if Fig.13 As shown, by the MOCVD method, TMG (trimethylgallium) as a Ga raw material, TMA (trimethylaluminum) as an Al raw material, NH3 (ammonia) as a nitrogen raw material, N2 gas and H2 gas as carrier gases, a low-temperature grown (530°C) GaN buffer layer (not shown) with a thickness of 30nm is stacked on the entire surface of the base substrate 10, and then the growth temperature is raised to 1100°C to grow the GaN layer 11, the undoped Al x Ga 1-x N layer 12, undoped GaN layer 13 and p-type GaN layer 14. A C-plane sapphire substrate is used as the base substrate 10. The thickness of the GaN layer 11 is 1.0 μm, and the undoped Al x Ga 1-x The thickness of the N layer 12 is 40 nm, x=0.25, the thickness of the undoped GaN layer 13 is 60 nm, the thickness of the p-type GaN layer 14 is 60 nm, and the Mg concentration is 5×10 18 cm -3 , the surface p of the p-type GaN layer 14 + The thickness of the GaN layer is 3nm and the Mg concentration is 5×10 19 cm -3 .

[0169] Then, if Fig.14 As shown, the undoped Al x Ga 1-x The groove 16 is formed in the N layer 12. That is, a resist pattern (not shown) is formed on the p-type GaN layer 14, the resist pattern having an opening at a portion corresponding to a region where the groove 16 is formed, and then the p-type GaN layer 14, the undoped GaN layer 13, and the undoped Al layer 14 are formed by using the resist pattern as a mask. x Ga 1-x The N layer 12 is etched to the undoped Al x Ga 1-x The groove 16 is formed by cutting the N layer 12 from a depth of halfway in the thickness direction of the N layer 12. At this time, the undoped Al in the groove 16 portion is x Ga 1-x The thickness of the N layer 12 is set to about 10 nm. Next, a p-type GaN layer 23 is grown on the entire surface to a thickness of about 30 nm by MOCVD. The p-type GaN layer 23 is the gate insulating film 17.

[0170] Next, the GaN layer 11 and the undoped Al x Ga 1-xThe N layer 12, the undoped GaN layer 13, and the p-type GaN layer 14 are etched to a depth midway in the thickness direction of the GaN layer 11. Fig.15 As shown, the surface of the region where the second gate electrode 18, the PSJ region, and the first gate electrode 15 are formed is masked with a resist pattern (not shown) of a predetermined shape, and the p-type GaN layer 23 and the p-type GaN layer 14 are sequentially etched, thereby exposing the surface of the undoped GaN layer 13. Next, the surface of the region where the source electrode 19 and the drain electrode 20 are formed is masked with a resist pattern (not shown) of a predetermined shape, and the undoped GaN layer 13 is etched, thereby exposing the undoped Al x Ga 1-x The surface of the N layer 12 is exposed.

[0171] Next, a resist pattern (not shown) is formed, the resist pattern having openings at portions corresponding to regions where the source electrode 19 and the drain electrode 20 are to be formed, and then a Ti film (5 nm), an Al film (50 nm), a Ni film (10 nm), and an Au film (150 nm) are sequentially formed on the entire surface of the substrate by vacuum evaporation, and then the resist pattern and the Ti / Al / Ni / Au laminated film formed thereon are removed together (stripping process), as shown in FIG. Fig.16 As shown, in the undoped Al x Ga 1-x A source electrode 19 and a drain electrode 20 are formed on the N layer 12. Then, a rapid thermal annealing (RTA) is performed at 800°C for 60 seconds in a nitrogen (N2) atmosphere to bond the source electrode 19 and the drain electrode 20 to the undoped Al x Ga 1-x N layer 12 ohm contact.

[0172] Then, if Fig.17 As shown, a resist pattern (not shown) is formed, the resist pattern having an opening at a portion corresponding to the region where the first gate electrode 15 and the second gate electrode 18 are formed, and then a Ni film (30 nm) and an Au film (200 nm) are sequentially formed on the entire surface of the substrate by vacuum evaporation, and then the resist pattern and the Ni / Au laminated film formed thereon are removed together to form the first gate electrode 15 and the second gate electrode 18. Then, a heat treatment is performed at 500° C. for 3 minutes in a N2 gas atmosphere to make the first gate electrode 15 and the second gate electrode 18 ohmically contact with the p-type GaN layers 14 and 23, respectively.

[0173] Then, if Fig.18As shown, a resist pattern (not shown) is formed, which has an opening at a portion corresponding to a region spanning the second gate electrode 18 and the first gate electrode 15. Next, an Au film (300 nm) is formed on the entire surface of the substrate by vacuum evaporation, and then the resist pattern and the Au film formed thereon are removed together, thereby forming an electrode 24 that electrically connects the second gate electrode 18 and the first gate electrode 15.

[0174] Thus, the target PSJ-GaN diode was manufactured.

[0175] The equivalent circuit of the double-gate PSJ-GaN system FET constituting the PSJ-GaN system diode manufactured as described above is shown in FIG. Fig.19 .exist Fig.19 In the figure, S, D, G1, and G2 represent the source electrode 19, the drain electrode 20, the first gate electrode 15, and the second gate electrode 18, respectively, and G represents the electrode obtained by combining G1 and G2. D -V D The results of the characteristic measurements are shown in Fig. 20 The determination is made at V D =-5V~+10V, V g = -1V ~ +2V. Fig. 20 It can be seen that V th Roughly 0V.

[0176] Will Fig. 20 Only V g =0V I D -V D The results after characterization are shown in Fig.21 . Since V g =0V, so at this time I D -V D Features Fig.19 The characteristics of a 2-terminal element obtained by connecting G and S in Fig.21 It can be seen that the starting voltage, that is, the on-state voltage V on = Diode characteristics of about 0.3V.

[0177] It should be noted that Fig.21 The diode characteristics shown can be measured as a two-terminal element by connecting the source electrode 19 to the first gate electrode 15 and the second gate electrode 18 outside the element. D -V D characteristics, but if Fig. 22 As shown, the electrode 21 may be formed to cover the source electrode 19, the first gate electrode 15, and the second gate electrode 18, thereby connecting the source electrode 19, the first gate electrode 15, and the second gate electrode 18 inside the element. Fig.23As shown, the source electrode 19 (S), the first gate electrode 15 (G1) and the second gate electrode 18 (G2) are used as anode electrodes, and the drain electrode 20 (D) is used as cathode electrode. Fig.24 As shown, at this time, the anode voltage V A When set to + axis, the polarity of the current changes from Fig.21 The polarity shown is reversed and behaves as a normal diode.

[0178] [Example 2]

[0179] A PSJ-GaN diode was manufactured in the following manner.

[0180] First, the GaN layer 11, the undoped Al layer 12, and the GaN layer 13 are sequentially grown on the entire surface of the base substrate 10 in the same manner as in Example 1. x Ga 1-x N layer 12 , undoped GaN layer 13 and p-type GaN layer 14 .

[0181] Next, the GaN layer 11 and the undoped Al x Ga 1-x The N layer 12, the undoped GaN layer 13, and the p-type GaN layer 14 are etched to a depth midway in the thickness direction of the GaN layer 11. Fig.25 As shown, the p-type GaN layer 14 is patterned into a predetermined shape by etching to expose the undoped GaN layer 13, and then the undoped GaN layer 13 is patterned into a predetermined shape by etching to expose the undoped Al x Ga 1-x The N layer 12 is exposed.

[0182] Then, if Fig.26 As shown, the same operation as in Example 1 was performed in the undoped Al x Ga 1-x A source electrode 19 and a drain electrode 20 are formed on the N layer 12, and then RTA is performed at 800°C for 60 seconds in a N2 gas atmosphere to make the source electrode 19 and the drain electrode 20 bonded to the undoped Al x Ga 1-x N layer 12 ohm contact.

[0183] Then, if Fig. 27 As shown, a resist pattern (not shown) is formed, the resist pattern having an opening at a portion corresponding to a region where the second gate electrode 18 is to be formed, and then the undoped Al x Ga 1-x The N layer 12 is etched to form a groove 16. At this time, the undoped Al x Ga 1-xThe thickness of the N layer 12 is set to about 10 nm. Next, keeping the resist pattern unchanged, a NiO film (20 nm) and a TiN film (10 nm) are sequentially formed on the entire surface of the substrate by sputtering, and then the resist pattern and the NiO / TiN laminated film formed thereon are removed together. The total thickness of the NiO film and the TiN film is approximately the same as the depth of the groove 16. In this way, after the NiO film 25 corresponding to the gate insulating film 17 and the TiN film 26 thereon are formed on the groove 16 portion, heat treatment is performed in a N2 gas atmosphere for stabilization of the NiO film 25. Here, the TiN film 26 is a covering layer for preventing oxygen (O) from being released from the NiO film 25 during heat treatment.

[0184] Then, if Fig.28 As shown, a resist pattern (not shown) is formed, the resist pattern having an opening at a portion corresponding to the region where the first gate electrode 15 and the second gate electrode 18 are formed, and then a Ni film (50 nm) and an Au film (150 nm) are sequentially formed on the entire surface of the substrate by vacuum evaporation, and then the resist pattern and the Ni / Au laminated film formed thereon are removed together, thereby forming the first gate electrode 15 and the second gate electrode 18. Then, a heat treatment is performed at 500° C. for 1 minute in a N2 gas atmosphere, so that the first gate electrode 15 and the second gate electrode 18 are in ohmic contact with the p-type GaN layer 14 and the NiO film 25, respectively. Then, a resist pattern (not shown) is formed, the resist pattern having an opening at a portion corresponding to the region where the electrode 22 is formed, and then an Au film (200 nm) is formed on the entire surface of the substrate by vacuum evaporation, and then the resist pattern and the Au film formed thereon are removed together, thereby forming the electrode 22 covering the source electrode 19 and the second gate electrode 18.

[0185] Thus, the target PSJ-GaN diode was manufactured.

[0186] [Example 3]

[0187] A PSJ-GaN diode was manufactured in the following manner.

[0188] First, if Fig.29 As shown, a GaN layer 11, an undoped Al layer 12, and a GaN layer 13 are sequentially grown on the entire surface of a base substrate 10 by MOCVD. x Ga 1-x N layer 12 and p-type GaN layer 23. The thickness of GaN layer 11 is 1.0 μm, and the undoped Al x Ga 1-x The thickness of the N layer 12 is 10 nm, x=0.25, the thickness of the p-type GaN layer 23 is 60 nm, and the Mg concentration is 5×10 18 cm -3The p-type GaN layer 23 eventually becomes the gate insulating film 17. Next, a SiO2 film 27 with a thickness of 0.35 μm is formed on the p-type GaN layer 23 by vacuum deposition, and then the SiO2 film 27 is patterned into a predetermined shape corresponding to the gate insulating film 17 by etching.

[0189] Then, if Fig.30 As shown, the SiO2 film 27 patterned in this way is used as a mask to etch the p-type GaN layer 23 until the undoped Al x Ga 1-x The N layer 12 is exposed and patterned.

[0190] Then, if Fig.31 As shown, undoped Al is grown sequentially on the entire surface by MOCVD. x Ga 1-x N layer 28, undoped GaN layer 13 and p-type GaN layer 14. Undoped Al x Ga 1-x The thickness of the N layer 28 is 30 nm, x=0.25, the thickness of the undoped GaN layer 13 is 65 nm, the thickness of the p-type GaN layer 14 is 65 nm, and the Mg concentration is 5×10 18 cm -3 , the surface p of the p-type GaN layer 14 + The thickness of the GaN layer is 3nm and the Mg concentration is 5×10 19 cm -3 At this time, these undoped Al x Ga 1-x The N layer 28, the undoped GaN layer 13, and the p-type GaN layer 14 are not grown on the SiO2 film 27. In this case, the undoped Al x Ga 1-x The N layer 12 and the undoped Al x Ga 1-x The entirety of the N layer 28 corresponds to Figure 1 The undoped Al x Ga 1-x N-layer 12.

[0191] Then, if Fig.32 As shown, while retaining the SiO2 film 27, a SiO2 film 28 with a thickness of 0.2 μm is formed on the entire surface, and then the SiO2 film 28 is patterned into a shape corresponding to the p-type GaN layer 14 to be formed in the end. The SiO2 film 28 patterned in this manner is used as a mask to etch the p-type GaN layer 14 until the undoped GaN layer 13 is exposed and patterned.

[0192] Then, if Fig.33As shown in the figure, while the SiO2 films 27 and 28 are retained, a SiO2 film 29 with a thickness of 0.2 μm is further formed on the entire surface, and then the SiO2 film 29 is patterned into a shape corresponding to the undoped GaN layer 13 to be finally formed, and the undoped GaN layer 13 is etched using the SiO2 film 29 patterned in this way as a mask until the undoped Al x Ga 1-x The N layer 28 is exposed and patterned.

[0193] Then, if Fig.34 As shown, the same operation as in Example 1 was performed in the undoped Al x Ga 1-x The source electrode 19 and the drain electrode 20 are formed on the N layer 28, and RTA is performed at 800° C. for 60 seconds in a N2 gas atmosphere, thereby bonding the source electrode 19 and the drain electrode 20 to the undoped Al x Ga 1-x N layer 28 ohm contact.

[0194] Then, if Fig.35 As shown, the SiO2 films 27, 28, and 29 are removed by etching, and then the first gate electrode 15 and the second gate electrode 18 are formed on the p-type GaN layer 14 and the p-type GaN layer 23, respectively, in the same manner as in Example 2, and ohmic contacts are made therebetween.

[0195] Then, if Fig.36 As shown, a resist pattern (not shown) is formed, which has an opening at a portion corresponding to a region spanning the source electrode 19 and the second gate electrode 18. Subsequently, a Ti film (5 nm) and an Au film (200 nm) are sequentially formed on the entire surface of the substrate by vacuum evaporation, and then the resist pattern and the Ti / Au stacked film formed thereon are removed together, thereby forming an electrode 22 that electrically connects the source electrode 19 to the second gate electrode 18.

[0196] Thus, the target PSJ-GaN diode was manufactured.

[0197] As described above, according to this embodiment, the PSJ-GaN diode is composed of a dual-gate PSJ-GaN FET, so that it can be used as a high-voltage power diode capable of high-speed high-power switching, and the threshold voltage V of the second gate electrode 18, which is the on-state voltage of the diode, can be made thCompared with the conventional GaN-based Schottky diode, the voltage is lower than 0V or more and lower than 0.9V, for example, 0.3V, so that energy loss can be reduced. By being able to reduce energy loss in this way, a PSJ-GaN-based diode with low power consumption and low heat generation can be obtained, thereby enabling miniaturization of the PSJ-GaN-based diode. Furthermore, high-performance electrical devices can be realized using this excellent PSJ-GaN-based diode.

[0198] As mentioned above, although one embodiment and an example of the present invention have been specifically described, the present invention is not limited to the above-mentioned embodiment and examples, and various modifications can be made based on the technical idea of ​​the present invention.

[0199] For example, the numerical values, structures, shapes, materials, etc. listed in the above-mentioned embodiments and examples are merely examples, and different numerical values, structures, shapes, materials, etc. may be used as needed.

[0200] Explanation of symbols

[0201] 10 Base substrate

[0202] 11 GaN layer

[0203] 12 Undoped Al x Ga 1-x N-tier

[0204] 13 Undoped GaN layer

[0205] 14 p-type GaN layer

[0206] 15. First gate electrode

[0207] 16 slots

[0208] 17 Gate insulation film

[0209] 18. Second gate electrode

[0210] 19 Source electrode

[0211] 20 Drain electrode

Claims

1. A diode, wherein: The diode is composed of a double-gate superjunction GaN field effect transistor. The dual-gate super-junction GaN field effect transistor has: an undoped first GaN layer; Al x Ga 1-x N layer, the Al x Ga 1-x The N layer is on the first GaN layer, and 0<x<1; The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape; a p-type GaN layer on the second GaN layer and having a second island shape; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor; a first gate electrode electrically connected to the p-type GaN layer; and A second gate electrode is provided on a gate insulating film provided inside a groove provided at the Al2O3 layer between the source electrode and the second GaN layer. x Ga 1-x Among the N layers, The threshold voltage of the second gate electrode is greater than 0V, The control by the first gate electrode is a normally-on type, and the control by the second gate electrode is a normally-off type, The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, the source electrode, the first gate electrode, and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode. or The source electrode and the second gate electrode are electrically connected to each other, a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode, the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, When no voltage is applied to the anode electrode and the cathode electrode, x Ga 1-x Two-dimensional hole gas is formed in the second GaN layer at a portion near the heterointerface between the N layer and the second GaN layer, and in the first GaN layer and the AlN layer except for a portion below the second gate electrode. x Ga 1-x A two-dimensional electron gas is formed in the first GaN layer at a portion near the heterointerface between the N layers.

2. The diode according to claim 1, wherein The threshold voltage of the second gate electrode is greater than or equal to 0V and less than or equal to 0.9V.

3. The diode according to claim 1, wherein An electrode is provided in a manner covering the source electrode, the first gate electrode, and the second gate electrode so that the source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other.

4. The diode according to claim 1, wherein An electrode is provided in a manner covering the source electrode and the second gate electrode so that the source electrode and the second gate electrode are electrically connected to each other.

5. The diode according to claim 1, wherein The Al x Ga 1-x The thickness of the N layer is greater than or equal to 3 nm and less than or equal to 100 nm.

6. The diode according to claim 1, wherein The gate insulating film includes a p-type semiconductor or an insulator.

7. The diode according to claim 6, wherein The p-type semiconductor is p-type GaN, p-type InGaN or NiO x .

8. The diode according to claim 6, wherein The insulator is an inorganic oxide, an inorganic nitride or an inorganic oxynitride.

9. The diode according to claim 6, wherein The insulator is Al2O3, SiO2, AlN, SiN x or SiON.

10. A method for manufacturing a diode, wherein the diode is composed of a double-gate super-junction GaN field effect transistor, The dual-gate super-junction GaN field effect transistor has: an undoped first GaN layer; Al x Ga 1-x N layer, the Al x Ga 1-x The N layer is on the first GaN layer, and 0<x<1; The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape; a p-type GaN layer on the second GaN layer and having a second island shape; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor; a first gate electrode electrically connected to the p-type GaN layer; and A second gate electrode is provided on a gate insulating film provided inside a groove provided at the Al2O3 layer between the source electrode and the second GaN layer. x Ga 1-x Among the N layers, The threshold voltage of the second gate electrode is greater than 0V, The control by the first gate electrode is a normally-on type, and the control by the second gate electrode is a normally-off type, The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, the source electrode, the first gate electrode, and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode. or The source electrode and the second gate electrode are electrically connected to each other, a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode, the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, When no voltage is applied to the anode electrode and the cathode electrode, x Ga 1-x Two-dimensional hole gas is formed in the second GaN layer at a portion near the heterointerface between the N layer and the second GaN layer, and in the first GaN layer and the AlN layer except for a portion below the second gate electrode. x Ga 1-x A two-dimensional electron gas is formed in the first GaN layer at a portion near the heterointerface between the N layers, characterized in that The method for manufacturing the diode comprises: The first GaN layer, the Al layer, and the x Ga 1-x N layer, the second GaN layer and the p-type GaN layer; By forming the p-type GaN layer, the second GaN layer, and the Al x Ga 1-x The N layer is etched to the Al x Ga 1-x A step of forming the groove to a depth halfway through the N layer; A step of growing a p-type GaN layer for forming a gate insulating film on the p-type GaN layer so as to fill the groove; The step of patterning the gate insulating film forming p-type GaN layer and the p-type GaN layer by etching to form the second island shape and forming the gate insulating film; In the Al x Ga 1-x A process of forming the source electrode and the drain electrode on the N layer; forming the first gate electrode and the second gate electrode on the gate insulating film-forming p-type GaN layer formed into the second island shape and the gate insulating film, respectively; and A step of forming an electrode covering the source electrode, the first gate electrode, and the second gate electrode, or an electrode covering the source electrode and the second gate electrode.

11. A method for manufacturing a diode, wherein the diode is composed of a dual-gate superjunction GaN field effect transistor, The dual-gate super-junction GaN field effect transistor has: an undoped first GaN layer; Al x Ga 1-x N layer, the Al x Ga 1-x The N layer is on the first GaN layer, and 0<x<1; The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape; a p-type GaN layer on the second GaN layer and having a second island shape; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor; a first gate electrode electrically connected to the p-type GaN layer; and A second gate electrode is provided on a gate insulating film provided inside a groove provided at the Al2O3 layer between the source electrode and the second GaN layer. x Ga 1-x Among the N layers, The threshold voltage of the second gate electrode is greater than 0V, The control by the first gate electrode is a normally-on type, and the control by the second gate electrode is a normally-off type, The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, the source electrode, the first gate electrode, and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode. or The source electrode and the second gate electrode are electrically connected to each other, a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode, the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, When no voltage is applied to the anode electrode and the cathode electrode, x Ga 1-x Two-dimensional hole gas is formed in the second GaN layer at a portion near the heterointerface between the N layer and the second GaN layer, and in the first GaN layer and the AlN layer except for a portion below the second gate electrode. x Ga 1-x A two-dimensional electron gas is formed in the first GaN layer at a portion near the heterointerface between the N layers, characterized in that The method for manufacturing the diode comprises: The first GaN layer, the Al layer, and the x Ga 1-x N layer, the second GaN layer and the p-type GaN layer; The step of patterning the p-type GaN layer and the second GaN layer into the second island shape and the first island shape respectively by etching; In the Al x Ga 1-x A process of forming the source electrode and the drain electrode on the N layer; By forming the Al x Ga 1-x The N layer is etched to the Al x Ga 1-x A step of forming the groove to a depth halfway through the N layer; forming the gate insulating film inside the groove; forming the first gate electrode and the second gate electrode on the p-type GaN layer and the gate insulating film, respectively; and A step of forming an electrode covering the source electrode, the first gate electrode, and the second gate electrode, or an electrode covering the source electrode and the second gate electrode.

12. A method for manufacturing a diode, wherein the diode is composed of a double-gate super-junction GaN field effect transistor. The dual-gate super-junction GaN field effect transistor has: an undoped first GaN layer; Al x Ga 1-x N layer, the Al x Ga 1-x The N layer is on the first GaN layer, and 0<x<1; The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape; a p-type GaN layer on the second GaN layer and having a second island shape; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor; a first gate electrode electrically connected to the p-type GaN layer; and A second gate electrode is provided on a gate insulating film provided inside a groove provided at the Al2O3 layer between the source electrode and the second GaN layer. x Ga 1-x Among the N layers, The threshold voltage of the second gate electrode is greater than 0V, The control by the first gate electrode is a normally-on type, and the control by the second gate electrode is a normally-off type, The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, the source electrode, the first gate electrode, and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode. or The source electrode and the second gate electrode are electrically connected to each other, a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode, the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, When no voltage is applied to the anode electrode and the cathode electrode, x Ga 1-x Two-dimensional hole gas is formed in the second GaN layer at a portion near the heterointerface between the N layer and the second GaN layer, and two-dimensional hole gas is formed in the first GaN layer and the AlN layer except for a portion below the second gate electrode. x Ga 1-x A two-dimensional electron gas is formed in the first GaN layer at a portion near the heterointerface between the N layers, characterized in that The method for manufacturing the diode comprises: The first GaN layer, the first Al layer, and the x Ga 1-x The step of forming a p-type GaN layer for the N layer and the gate insulating film; forming a first mask on the p-type GaN layer for forming a gate insulating film, wherein the first mask includes an inorganic insulator having the same shape as the groove; A step of using the first mask as an etching mask to pattern the p-type GaN layer for forming a gate insulating film by etching, thereby forming the gate insulating film; The first mask is used as a growth mask, and the first Al x Ga 1-x The second Al x Ga 1-x N layer, the second GaN layer and the p-type GaN layer; forming a second mask on the p-type GaN layer, the second mask comprising an inorganic insulator having the same shape as the second island shape; A step of using the second mask as an etching mask to pattern the p-type GaN layer by etching; forming a third mask so as to cover the second mask, the third mask including an inorganic insulator having the same shape as the first island shape; A step of using the third mask as an etching mask to pattern the second GaN layer by etching; In the second Al x Ga 1-x A process of forming the source electrode and the drain electrode on the N layer; forming the first gate electrode and the second gate electrode on the p-type GaN layer and the gate insulating film, respectively; A step of forming an electrode covering the source electrode, the first gate electrode, and the second gate electrode, or an electrode covering the source electrode and the second gate electrode.

13. An electrical device comprising at least one diode, The diode is composed of a double-gate superjunction GaN field effect transistor. The dual-gate super-junction GaN field effect transistor has: an undoped first GaN layer; Al x Ga 1-x N layer, the Al x Ga 1-x The N layer is on the first GaN layer, and 0<x<1; The undoped second GaN layer is formed on the Al x Ga 1-x on the N layer and having a first island shape; a p-type GaN layer on the second GaN layer and having a second island shape; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged on the Al layer in a manner of sandwiching the second GaN layer. x Ga 1-x On the Nth floor; a first gate electrode electrically connected to the p-type GaN layer; and A second gate electrode is provided on a gate insulating film provided inside a groove provided at the Al2O3 layer between the source electrode and the second GaN layer. x Ga 1-x Among the N layers, The threshold voltage of the second gate electrode is greater than 0V, The control by the first gate electrode is a normally-on type, and the control by the second gate electrode is a normally-off type, The source electrode, the first gate electrode, and the second gate electrode are electrically connected to each other, the source electrode, the first gate electrode, and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode. or The source electrode and the second gate electrode are electrically connected to each other, a positive voltage relative to the source electrode and the second gate electrode is applied to the first gate electrode, the source electrode and the second gate electrode constitute an anode electrode, and the drain electrode constitutes a cathode electrode, When no voltage is applied to the anode electrode and the cathode electrode, x Ga 1-x Two-dimensional hole gas is formed in the second GaN layer at a portion near the heterointerface between the N layer and the second GaN layer, and two-dimensional hole gas is formed in the first GaN layer and the AlN layer except for a portion below the second gate electrode. x Ga 1-x A two-dimensional electron gas is formed in the first GaN layer at a portion near the heterointerface between the N layers.

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