Capacitor and method of manufacturing capacitor and semiconductor device

Abstract

A capacitor includes first and second electrodes spaced apart from each other, a dielectric layer disposed between the first and second electrodes, the dielectric layer including at least one of hafnium and zirconium, a first insertion layer disposed between the first electrode and the dielectric layer, and a second insertion layer disposed between the dielectric layer and the second electrode. The first insertion layer includes a first conductive material different from the hafnium or zirconium forming the dielectric layer. The second insertion layer includes a second conductive material different from the hafnium or zirconium forming the dielectric layer. The first and second conductive materials each have a lattice constant with a lattice mismatch of 2% or less from a horizontal lattice constant of a dielectric material of the dielectric layer.

Description

[0001] This application is a divisional application of invention patent application 201810369447.4, filed on April 23, 2018, and therefore claims priority to Korean patent applications No. 10-2017-0053872 and No. 10-2017-0118877, filed with the Korean Intellectual Property Office on April 26, 2017 and September 15, 2017, respectively, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present invention relate to capacitors, semiconductor devices, and methods of manufacturing capacitors and semiconductor devices. For example, this disclosure relates to a capacitor including a high-k dielectric layer and a method of manufacturing the same. For example, this disclosure relates to a semiconductor device including a high-k dielectric layer and a method of manufacturing such a semiconductor device. Background Technology

[0003] With the increasing integration of semiconductor devices, there is a demand for capacitors with sufficient capacitance within a limited area. The capacitance of a capacitor can be directly proportional to the surface area of ​​the electrodes constituting the capacitor and the dielectric constant of the dielectric layer disposed between the two electrodes, and inversely proportional to the equivalent oxide thickness (EOT) of the dielectric layer. Therefore, to increase the capacitance of a capacitor in a limited area, a three-dimensional structure can be formed to increase the surface area of ​​the electrodes, the equivalent oxide thickness of the dielectric layer can be reduced, and / or a material with a high dielectric constant can be used as the dielectric layer. Summary of the Invention

[0004] Embodiments of the present invention can provide capacitors with increased capacitance.

[0005] Embodiments of the present invention may also provide a method for manufacturing a capacitor with increased capacitance, which simplifies the manufacturing process.

[0006] Embodiments of the present invention may also include semiconductor devices with improved reliability.

[0007] In one aspect, the capacitor may include: a first electrode and a second electrode spaced apart from each other; a dielectric layer disposed between the first electrode and the second electrode; and a first seed layer disposed between the first electrode and the dielectric layer. The dielectric layer may include a dielectric material having a tetragonal crystal structure. The first seed layer may include a first seed material. The lattice constant of the first seed material may have a lattice mismatch of 2% or less with the horizontal lattice constant of the dielectric material.

[0008] In one aspect, the capacitor may include: a first electrode and a second electrode spaced apart from each other; a dielectric layer disposed between the first electrode and the second electrode; and a metal seed layer disposed between the first electrode and the dielectric layer. The dielectric layer may include a dielectric material having a tetragonal crystal structure. The metal seed layer may include a seed material. The mismatch between the bond lengths between the metal atoms of the seed material and the bond lengths between the oxygen atoms of the dielectric material may be 5% or less.

[0009] In one aspect, the capacitor may include: a first electrode and a second electrode spaced apart from each other; a dielectric layer disposed between the first electrode and the second electrode; and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer may include hafnium oxide having a tetragonal crystal structure or zirconium oxide having a tetragonal crystal structure. The seed layer may include a cobalt layer, a nickel layer, a copper layer, or a Co layer. x N layers (where 3.5 < x < 4.5).

[0010] In one aspect, a method of manufacturing a capacitor may include: sequentially forming a first electrode, a dielectric layer, and a second electrode on a substrate; and forming a seed layer between the first electrode and the dielectric layer, or between the dielectric layer and the second electrode. The dielectric layer may include hafnium oxide or zirconium oxide. The seed layer may include a seed material. The lattice constant of the seed material may have a lattice mismatch of 2% or less with the horizontal lattice constant of the tetragonal crystal structure of the oxide included in the dielectric layer.

[0011] In one aspect, a method of manufacturing a capacitor may include: sequentially forming a first electrode, a dielectric layer, and a second electrode on a substrate; and forming a metal seed layer between the first electrode and the dielectric layer, or between the dielectric layer and the second electrode. The dielectric layer may include hafnium oxide or zirconium oxide. The metal seed layer may include a seed material. The mismatch between the bond lengths between the metal atoms of the seed material and the bond lengths between the oxygen atoms of the tetragonal crystal structure of the oxide included in the dielectric layer may be 5% or less.

[0012] In some embodiments, a method of manufacturing a semiconductor device includes: forming a dielectric layer, a first metal layer, and a first electrode on a substrate, wherein the first metal layer is disposed between the dielectric layer and the first electrode, wherein the first metal layer comprises a first metal having a cubic crystal structure, and wherein the dielectric layer comprises a material having a tetragonal crystal structure. Attached Figure Description

[0013] The inventive concept will become clear from the accompanying drawings and detailed embodiments.

[0014] Figure 1 This is a cross-sectional view of a capacitor illustrating some embodiments of the concept according to the present invention.

[0015] Figure 2A The tetragonal crystal structure of a dielectric material according to some embodiments of the present invention is shown.

[0016] Figure 2B The cubic crystal structure of the seed crystal material according to some embodiments of the present invention is shown.

[0017] Figure 3 This is a flowchart illustrating a method for manufacturing a capacitor according to some embodiments of the present invention.

[0018] Figures 4A to 4C This is a cross-sectional view illustrating a method for manufacturing a capacitor according to some embodiments of the present invention.

[0019] Figure 5 This is a cross-sectional view of a capacitor illustrating some embodiments of the concept according to the present invention.

[0020] Figure 6 This is a flowchart illustrating a method for manufacturing a capacitor according to some embodiments of the present invention.

[0021] Figures 7A to 7C This is a cross-sectional view illustrating a method for manufacturing a capacitor according to some embodiments of the present invention.

[0022] Figure 8 This is a cross-sectional view of a capacitor illustrating some embodiments of the concept according to the present invention.

[0023] Figure 9 This is a flowchart illustrating a method for manufacturing a capacitor according to some embodiments of the present invention.

[0024] Figures 10A to 10C This is a cross-sectional view illustrating a method for manufacturing a capacitor according to some embodiments of the present invention.

[0025] Figure 11A This is a graph showing the X-ray diffraction analysis results of the crystal structure of hafnium oxide formed on a general electrode (e.g., an electrode without a seed layer between hafnium oxide and the electrode).

[0026] Figure 11B This is a graph showing the X-ray diffraction analysis results of the crystal structure of hafnium oxide formed on a seed layer according to some embodiments of the present invention.

[0027] Figure 11C The graph shows the X-ray diffraction analysis results of the crystal structures of zirconium oxide layers formed on general electrodes (e.g., electrodes without seed layers between hafnium oxide and the electrode) and having different thicknesses from each other.

[0028] Figure 11D This is a graph showing the X-ray diffraction analysis results of a crystal structure with zirconium oxide layers of different thicknesses according to an embodiment of the present invention.

[0029] Figure 11E This is a graph showing the X-ray diffraction analysis results of a crystal structure with zirconium oxide layers of different thicknesses according to an embodiment of the present invention.

[0030] Figure 11F The graphs show the X-ray diffraction analysis results of the crystal structures of zirconia layers formed on general electrodes (e.g., electrodes without seed layers between hafnium oxide and the electrode) at different temperatures.

[0031] Figure 11G The graph shows the X-ray diffraction analysis results of the crystal structures of the zirconia layers formed on the seed crystal layer at different temperatures.

[0032] Figure 11H The graph shows the X-ray diffraction analysis results of the crystal structures of the zirconia layers formed on the seed crystal layer at different temperatures.

[0033] Figures 12A to 12C This is a cross-sectional view illustrating an example of the shape of a capacitor in a semiconductor device according to some embodiments of the present invention.

[0034] Figure 13A This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention.

[0035] Figure 13B This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention. Detailed Implementation

[0036] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout this disclosure, the same reference numerals or the same reference numerals may denote the same elements.

[0037] Figure 1 This is a cross-sectional view of a capacitor illustrating some embodiments of the concept according to the present invention. Figure 2A The tetragonal crystal structure of a dielectric material according to some embodiments of the present invention is shown. Figure 2B The cubic crystal structure of the seed crystal material according to some embodiments of the present invention is shown.

[0038] refer to Figure 1 A substrate 100 may be provided. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0039] A selection element (not shown) may be disposed on the substrate 100. In some embodiments, the selection element may be a transistor. In these embodiments, some components of the transistor (e.g., source and drain regions) may be disposed in the substrate 100.

[0040] Interlayer insulating layer 110 may be disposed on substrate 100. Interlayer insulating layer 110 may cover selected elements. For example, interlayer insulating layer 110 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0041] Contact plug 112 may be disposed in interlayer insulating layer 110. Contact plug 112 may be electrically connected to a selection element. Contact plug 112 may include a conductive material. For example, contact plug 112 may include at least one of the following: a doped semiconductor (e.g., doped silicon, doped germanium, or doped silicon-germanium), a metal (e.g., titanium, tantalum, or tungsten), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and / or a metal semiconductor compound (e.g., a metal silicide).

[0042] Capacitor CA1 can be disposed on interlayer insulating layer 110. Capacitor CA1 may include a first electrode E1, a second electrode E2, a dielectric layer DL, and a seed layer SL.

[0043] The first electrode E1 may be disposed on the interlayer insulating layer 110. The first electrode E1 may be electrically connected to the selection element via the contact plug 112. The first electrode E1 may include a conductive material. For example, the first electrode E1 may include at least one of the following: a semiconductor, a metal, a conductive metal nitride, and / or a metal semiconductor compound doped with a dopant (e.g., an impurity). For example, the dopant of the semiconductor may be one or more of boron, phosphorus, arsenic, antimony, gallium, aluminum, etc.

[0044] The second electrode E2 can be spaced apart from the first electrode E1. For example, the second electrode E2 can be spaced apart from the first electrode E1 in the vertical direction, such as... Figure 1 As shown. However, embodiments of the present invention are not limited thereto. The second electrode E2 may include a conductive material. For example, the second electrode E2 may include at least one of the following: a semiconductor doped with a dopant, a metal, a conductive metal nitride, and / or a metal semiconductor compound.

[0045] A dielectric layer DL can be disposed between the first electrode E1 and the second electrode E2. The dielectric layer DL may include materials with a tetragonal crystal structure (e.g., Figure 2AThe dielectric material (shown) may be used. For example, the dielectric layer DL may include hafnium oxide (i.e., HfO2) or zirconium oxide (i.e., ZrO2) having a tetragonal crystal structure. Two of the lattice constants of the dielectric material having a tetragonal crystal structure may be equal to each other. For example, the tetragonal crystal structure of the dielectric layer DL may have three lattice constants, and two of the three lattice constants may be equal, while the third lattice constant may be different from the two equal lattice constants. For example, the tetragonal crystal structure of the dielectric layer DL may be a simple / primitive tetragonal crystal structure. In this disclosure, two identical lattice constants a1 of the dielectric material having a tetragonal crystal structure are defined as horizontal lattice constants, and another lattice constant c1 of the dielectric material is defined as a vertical lattice constant.

[0046] Compared to hafnium oxide (m-HfO2) with a monoclinic crystal structure, hafnium oxide (t-HfO2) with a tetragonal crystal structure can have a higher dielectric constant. For example, the dielectric constant of hafnium oxide with a tetragonal crystal structure can be in the range of about 40 to about 60, while the dielectric constant of hafnium oxide with a monoclinic crystal structure can be about 20. Similarly, compared to zirconium oxide (m-ZrO2) with a monoclinic crystal structure, zirconium oxide (t-ZrO2) with a tetragonal crystal structure can have a higher dielectric constant. For example, the dielectric constant of zirconium oxide with a tetragonal crystal structure can be about 40, while the dielectric constant of zirconium oxide with a monoclinic crystal structure can be about 20.

[0047] Some properties of hafnium oxide (t-HfO2) and zirconium oxide (t-ZrO2) with tetragonal crystal structures according to some embodiments are shown in Table 1 below.

[0048] [Table 1]

[0049]

[0050] The seed layer SL can be disposed between the first electrode E1 and the dielectric layer DL. The thickness of the seed layer SL can be approximately... up to approximately Within the range.

[0051] The seed layer SL may include a seed material that facilitates the crystallization of the dielectric material into a tetragonal crystal structure. The seed material may satisfy at least one of the following lattice constant conditions or the following bond length conditions.

[0052] [Lattice constant condition]

[0053] The lattice constant of the seed material can have a lattice mismatch of about 2% or less with the horizontal lattice constant of the dielectric material (e.g., at room temperature). The seed material can have a cubic crystal structure (e.g., Figure 2B As shown), the lattice constants a2 of the seed crystal materials can be equal to each other. For example, the seed crystal material can have a face-centered cubic crystal structure. In some embodiments, the seed crystal material can have a simple cubic crystal structure or a body-centered cubic crystal structure. In this disclosure, the lattice mismatch between the lattice constant of the seed crystal material and the horizontal lattice constant of the dielectric material (i.e., the lattice mismatch between the lattice constant of the seed crystal material and the horizontal lattice constant of the dielectric material) is defined by the following Equation 1.

[0054] [Equation 1]

[0055]

[0056] In Equation 1, “LS” represents lattice mismatch, “a1” is the horizontal lattice constant of the dielectric material with a tetragonal crystal structure, and “a2” is the lattice constant of the seed material. For example, a1 can be two equal lattice constants of the tetragonal crystal structure of the dielectric material.

[0057] When the lattice constant condition is met (e.g., 2% or less of lattice mismatch), the lattice mismatch between the lattice constant of the seed material and the horizontal lattice constant of the dielectric material with a tetragonal crystal structure can be smaller than the lattice mismatch between the lattice constant of the seed material and the lattice constant a1, b1, or c1 of the dielectric material with a monoclinic crystal structure. For example, when the lattice constant condition is met, the lattice mismatch between the lattice constant of the seed material and each (or the average value) of the lattice constant (or horizontal lattice constant) of the monoclinic crystal structure of the dielectric material can be smaller than the lattice mismatch between the lattice constant of the seed material and the horizontal lattice constant of the tetragonal crystal structure of the dielectric material.

[0058] [Key length condition]

[0059] The seed material can be a metal. The mismatch between the bond lengths between the metal atoms included in the seed material and the bond lengths between the oxygen atoms included in the dielectric material having a tetragonal crystal structure can be about 5% or less (e.g., at room temperature). In this disclosure, the mismatch between the bond lengths between the metal atoms included in the seed material and the bond lengths between the oxygen atoms included in the dielectric material having a tetragonal crystal structure is defined by the following Equation 2.

[0060] [Equation 2]

[0061]

[0062] In Equation 2, “BM” represents the bond mismatch, “BL1” represents the bond length between oxygen atoms in a dielectric material with a tetragonal crystal structure, and “BL2” represents the bond length between metal atoms in a seed material.

[0063] When the bond length condition is met (e.g., 5% or less of bond length mismatch), the bond length mismatch between the metal atoms in the seed material and the bond length mismatch between the oxygen atoms in the dielectric material with a monoclinic crystal structure can be smaller.

[0064] When the bond length condition is met, the metal atoms in the seed material can interact with the oxygen atoms in the dielectric material. In this case, the metal atoms in the seed material can be those exposed on the top surface of the seed layer SL. For example, when the bond length condition is met, the metal atoms in the seed layer SL can (e.g., through electrodynamic forces and / or through combinations of atoms) influence the arrangement of oxygen atoms in the dielectric layer at the boundary between the seed layer SL and the dielectric layer DL. For example, the seed material can crystallize the dielectric material into a tetragonal crystal structure under predetermined temperature conditions (e.g., 240 degrees Celsius or higher).

[0065] According to some embodiments, the seed crystal material can satisfy the following conductivity conditions, the following work function conditions, and / or the following oxide bandgap conditions.

[0066] [Conductivity conditions]

[0067] The seed material can be conductive. For example, the seed material included in the seed layer can be a conductor.

[0068] [Oxide band gap conditions]

[0069] The band gap (e.g., energy band gap) of the oxide of the seed crystal material can be about 3 eV or less.

[0070] [Conditions for the work function]

[0071] The work function of the seed crystal material can be approximately 4.7 eV or greater.

[0072] When the seed material meets the conductivity condition, the seed layer SL can be used as an electrode in the capacitor CA1, which can help reduce or suppress the increase in the equivalent oxide thickness of the capacitor CA1. For example, in some embodiments, the seed material can be a conductor, and the seed layer SL is used as an electrode of the capacitor CA1. Therefore, the capacitor CA1 can have a thin insulating layer, which is beneficial for obtaining a capacitor CA1 with a larger capacitance. For example, the seed layer SL and the electrode E1 or E2 in contact with the seed layer SL can be used together as an electrode of the capacitor CA1. For example, in some embodiments, the electrode can include a doped semiconductor layer and a metal layer in contact with each other.

[0073] In some embodiments, capacitor CA1 may include a secondary oxide layer SOL disposed between the seed layer SL and the dielectric layer DL, such as Figure 1 As shown. The thickness of the secondary oxide layer SOL can be approximately... up to approximately Within the specified range, a portion of the seed layer SL can be oxidized to form the secondary oxide layer SOL. For example, the secondary oxide layer SOL may include the same metal as the metal included in the seed layer SL. When the seed material satisfies the oxide bandgap condition, the secondary oxide layer SOL can be used as an electrode in the capacitor CA1, which can help reduce or suppress the increase in the equivalent oxide thickness of the capacitor CA1.

[0074] In some embodiments, with Figure 1 Unlike other capacitors, CA1 may not include the secondary oxide layer SOL.

[0075] When the seed crystal material satisfies the work function condition, the seed crystal layer SL can suppress leakage current in capacitor CA1 or reduce leakage current in capacitor CA1.

[0076] In some embodiments, the seed layer SL may have approximately up to approximately The thickness. When the thickness of the seed layer SL is greater than... When the thickness of the seed layer SL is less than a certain value, it may be difficult to reduce the size of the capacitor CA1. At times, it may be difficult to crystallize the dielectric layer DL into a tetragonal crystal structure. However, according to some embodiments of the present invention, the seed layer SL can crystallize the dielectric layer DL into a tetragonal crystal structure, and therefore the dielectric layer DL can have high k dielectric properties. For example, according to some embodiments of the present disclosure, the size of the capacitor CA1 can be reduced or minimized.

[0077] Seed materials can include cobalt, nickel, copper, or cobalt nitride. Cobalt nitride can be Co4N, or can have a composition ratio similar to that of Co4N. For example, seed materials can include Co... x N, where 3.5 < x < 4.5. Each of cobalt, nickel, copper, and Co4N can satisfy at least one of the above conditions. Cobalt, nickel, copper, and Co4N can have the properties shown in Table 2 below.

[0078] [Table 2]

[0079]

[0080] Referring to Table 2, it can be seen that, relative to hafnium oxide (t-HfO2) with a tetragonal crystal structure, each of cobalt, nickel, copper, and Co4N satisfies at least one of the lattice constant condition or the bond length condition. For example, relative to hafnium oxide (t-HfO2) with a tetragonal crystal structure, cobalt, nickel, and copper satisfy the lattice constant condition. Relative to hafnium oxide (t-HfO2) with a tetragonal crystal structure, cobalt, nickel, and copper satisfy the bond length condition.

[0081] The lattice mismatch between the lattice constants of each of cobalt, nickel, copper, and Co4N and the horizontal lattice constant of hafnium oxide (t-HfO2) with a monoclinic crystal structure is smaller than the lattice mismatch between the lattice constants of each of cobalt, nickel, copper, and Co4N and the horizontal lattice constant of hafnium oxide (t-HfO2) with a tetragonal crystal structure. The bond length mismatch between the metal atoms of each of cobalt, nickel, and copper and the bond length between oxygen atoms in hafnium oxide (t-HfO2) with a tetragonal crystal structure is also smaller than the bond length mismatch between the metal atoms of each of cobalt, nickel, and copper and the bond length between oxygen atoms in hafnium oxide (t-HfO2) with a tetragonal crystal structure.

[0082] It can be recognized that, relative to zirconium oxide (t-ZrO2) with a tetragonal crystal structure, each of cobalt, nickel, copper, and Co4N satisfies at least one of the lattice constant condition or the bond length condition. For example, copper and Co4N satisfy the lattice constant condition relative to zirconium oxide (t-ZrO2) with a tetragonal crystal structure. Cobalt, nickel, and copper satisfy the bond length condition relative to zirconium oxide (t-ZrO2) with a tetragonal crystal structure.

[0083] The lattice mismatch between the lattice constants of each of cobalt, nickel, copper, and Co4N and the horizontal lattice constant of zirconium oxide (t-ZrO2) with a monoclinic crystal structure is smaller than the lattice mismatch between the lattice constants of each of cobalt, nickel, copper, and Co4N and the horizontal lattice constant of zirconium oxide (t-ZrO2) with a tetragonal crystal structure. The bond length mismatch between the metal atoms of each of cobalt, nickel, and copper and the bond length between oxygen atoms in zirconium oxide (t-ZrO2) with a tetragonal crystal structure is also smaller than the bond length mismatch between the metal atoms of each of cobalt, nickel, and copper and the bond length between oxygen atoms in zirconium oxide (t-ZrO2) with a tetragonal crystal structure.

[0084] Each of cobalt, nickel, copper, and Co4N can be conductive and can have a work function of 4.7 eV or higher. The oxides of each of cobalt, nickel, copper, and Co4N can have a band gap of 3 eV or less. For example, each of cobalt, nickel, copper, and Co4N can satisfy the conductivity condition, the oxide band gap condition, and the work function condition.

[0085] In this disclosure, cobalt, nickel, copper, and Co4N are described as examples of seed materials. However, embodiments of the invention are not limited thereto. In some embodiments, other materials satisfying the above conditions may be used as seed materials.

[0086] Conductive interconnects (not shown) may be disposed on capacitor CA1. The conductive interconnects may be electrically connected to the second electrode E2. For example, the conductive interconnects may include at least one of the following: a semiconductor doped with a dopant, a metal, a conductive metal nitride, and / or a metal-semiconductor compound.

[0087] According to some embodiments of the present invention, the dielectric layer DL may comprise hafnium oxide or zirconium oxide with a tetragonal crystal structure having a high dielectric constant. Therefore, the capacitance of capacitor CA1 can be increased.

[0088] According to some embodiments of the present invention, the seed layer SL and the secondary oxide layer SOL formed by oxidizing a portion of the seed layer SL can be used as electrodes, which can help reduce or suppress the increase in the equivalent oxide thickness of the capacitor CA1.

[0089] According to some embodiments of the present invention, the seed layer SL may comprise a seed material with a work function of approximately 4.7 eV or greater. For example, the seed layer SL may suppress or reduce leakage current in capacitor CA1.

[0090] According to some embodiments of the present invention, the dielectric layer DL can have approximately up to approximately The thickness. When the thickness of the dielectric layer DL is less than When the thickness of the dielectric layer DL is greater than a certain value, leakage current can occur through the dielectric layer DL. At that time, it may be difficult to reduce the size of capacitor CA1.

[0091] Figure 3 This is a flowchart illustrating a method for manufacturing a capacitor according to some embodiments of the present invention. Figures 4A to 4C This is a cross-sectional view illustrating a method of manufacturing a capacitor according to some embodiments of the present invention. For example, Figure 3 and Figures 4A to 4C It may be that a manufacturing reference is shown. Figure 1 A diagram describing the method of using a capacitor. See below for reference. Figure 1 The same elements or components described may be indicated by the same reference numerals or the same reference numerals, and for ease of explanation, their description will be omitted or briefly mentioned.

[0092] refer to Figure 3 and Figure 4AAn interlayer insulating layer 110 can be formed on the substrate 100. The interlayer insulating layer 110 can cover a selection element (not shown) formed on the substrate 100. For example, with respect to... Figure 1 Similarly, the selected element can be a transistor.

[0093] Contact plugs 112 may be formed in the interlayer insulating layer 110. Contact plugs 112 may be electrically connected to a selection element. Forming contact plugs 112 may include: forming contact holes 110a in the interlayer insulating layer 110; forming a conductive layer (not shown) to fill the contact holes 110a; and performing a planarization process on the conductive layer.

[0094] The first electrode E1 and the seed layer SL (S10) can be formed sequentially on the interlayer insulating layer 110.

[0095] A first electrode E1 can be formed on the interlayer insulating layer 110. The first electrode E1 can be electrically connected to the contact plug 112. For example, the first electrode E1 can be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0096] A seed layer SL can be formed on the first electrode E1. For example, a CVD process or an ALD process can be used to form the seed layer SL.

[0097] The seed layer SL may include a seed material that facilitates the crystallization of the dielectric material included in the dielectric layer DL to be formed in subsequent processes into a tetragonal crystal structure. The seed material may be related to the above references. Figure 1 The described seed materials are substantially the same. For example, the seed material may satisfy at least one of the above-described lattice constant conditions or bond length conditions. For example, the seed material may satisfy the above-described conductivity conditions, work function conditions, and / or oxide band gap conditions. For example, the seed material may include cobalt, nickel, copper, or cobalt nitride. Cobalt nitride may be Co4N, or may have a composition ratio similar to that of Co4N. For example, the seed material may include Co. x N, where 3.5 < x < 4.5. The seed layer SL can be formed with approximately up to approximately The thickness.

[0098] refer to Figure 3 and Figure 4BA dielectric layer DL (E11) can be formed on the seed layer SL. For example, the dielectric layer DL can be formed using a CVD or ALD process. In some embodiments, immediately after the formation of the dielectric layer DL on the seed layer SL, the dielectric layer DL may comprise an amorphous dielectric material. For example, when the dielectric layer is formed on the seed layer SL, the dielectric layer DL may be at least partially amorphous. For example, the dielectric layer DL may comprise amorphous hafnium oxide or amorphous zirconium oxide.

[0099] The amorphous dielectric material included in the dielectric layer DL can be influenced by the seed layer SL, thus allowing the amorphous dielectric material to be crystallized into a tetragonal crystal structure at a relatively low temperature, for example, about 240 degrees Celsius or higher. For example, the amorphous dielectric material can be crystallized at temperatures ranging from about 240 degrees Celsius to about 600 degrees Celsius. Alternatively, the amorphous dielectric material can be crystallized at temperatures ranging from about 240 degrees Celsius to about 400 degrees Celsius.

[0100] In some embodiments, at least a portion of the dielectric layer DL can crystallize into a tetragonal crystal structure during the deposition process. The dielectric layer DL can be formed or deposited at a temperature of approximately 240 degrees Celsius or higher. For example, the dielectric layer DL can be formed or deposited at a temperature of approximately 240 degrees Celsius to approximately 290 degrees Celsius. Under these temperature conditions, the seed layer SL can help or induce the dielectric material to crystallize into a tetragonal crystal structure. Immediately following the formation of the dielectric layer DL, the dielectric layer DL can include a dielectric material having a tetragonal crystal structure and an amorphous dielectric material. For example, the dielectric layer DL can be formed into a tetragonal crystal structure during a CVD process or an ALD process. For example, the seed layer SL can help to give the dielectric layer DL a tetragonal crystal structure during and / or immediately following a CVD process or an ALD process.

[0101] In some embodiments, the secondary oxide layer SOL can be formed by the process of forming the dielectric layer DL, such as... Figure 4B As shown. In the process of forming the dielectric layer DL, a portion of the seed layer SL can be oxidized to form a secondary oxide layer SOL. For example, the secondary oxide layer SOL may include the same metal as the metal included in the seed layer SL. The thickness of the secondary oxide layer SOL can be approximately... up to approximately Within the range.

[0102] In some embodiments, with Figure 4B Unlike other methods, a secondary oxide layer SOL may not be formed. For example, in some embodiments, the seed layer SL may contact the dielectric layer DL.

[0103] refer to Figure 3 and Figure 4CA second electrode E2 (Si2) can be formed on the dielectric layer DL. The second electrode E2 can be formed spaced apart from the first electrode E1, with the dielectric layer DL and the seed layer SL between them. For example, the second electrode E2 can be formed using CVD or ALD processes.

[0104] The process of forming the second electrode E2 can be performed at a temperature of approximately 240 degrees Celsius or higher (e.g., temperatures from approximately 240 degrees Celsius to approximately 400 degrees Celsius). At least a portion of the dielectric layer DL can crystallize during the process of forming the second electrode E2. For example, the temperature at which the second electrode E2 is formed can facilitate the crystallization of the dielectric layer DL. Since the seed layer SL, which includes the aforementioned seed material, is adjacent to the dielectric layer DL, the dielectric material can be crystallized into a tetragonal crystal structure. When the process of forming the second electrode E2 is performed at a temperature below approximately 240 degrees Celsius, it may be difficult to form the second electrode E2 or crystallize the dielectric layer DL. However, according to some embodiments, the process of forming the second electrode E2 can be performed at a temperature of approximately 240 degrees Celsius or higher to crystallize the dielectric layer DL during the formation of the second electrode E2. For example, the process of forming the second electrode E2 can be performed at a temperature of approximately 400 degrees Celsius or lower, which is beneficial for reducing or preventing leakage current from flowing through the dielectric layer DL.

[0105] refer to Figure 1 and Figure 3 A subsequent heat treatment process (S13) can be performed. For example, the subsequent heat treatment process can induce further crystallization in the dielectric layer DL. In some embodiments, the dielectric material can be crystallized into a tetragonal crystal structure by a subsequent heat treatment process. For example, the subsequent heat treatment process can correspond to the process of forming conductive interconnects (not shown) on capacitor CA1, and can be performed at a temperature of about 240 degrees Celsius or higher (e.g., a temperature from about 240 degrees Celsius to about 400 degrees Celsius). For example, the dielectric material can be crystallized into a tetragonal crystal structure when forming conductive interconnects electrically connected to the second electrode E2. In some embodiments, the subsequent heat treatment process can be a different process than forming conductive interconnects.

[0106] According to embodiments of the present invention, the amorphous dielectric material can be influenced by the seed layer SL, thus allowing the amorphous dielectric material to be crystallized into a tetragonal crystal structure at relatively low temperatures. For example, the amorphous dielectric material can be crystallized at temperatures of approximately 240 degrees Celsius or higher. For example, the amorphous dielectric material can be crystallized at temperatures ranging from approximately 240 degrees Celsius to approximately 600 degrees Celsius. For example, the amorphous dielectric material can be crystallized at temperatures ranging from approximately 240 degrees Celsius to approximately 400 degrees Celsius. The crystallization temperature of the dielectric material can correspond to the following: the deposition temperature of the dielectric material, the temperature of the process for forming the second electrode E2, and / or the temperature of subsequent heat treatment processes (e.g., the process for forming subsequent conductive interconnects (not shown)). For example, the dielectric material can be crystallized into a tetragonal crystal structure without additional high-temperature heat treatment processes, which is beneficial for simplifying the manufacturing process of capacitor CA1 and / or semiconductor devices including capacitor CA1. When the dielectric layer DL, the second electrode E2, and the subsequent conductive interconnects are formed at high temperatures, thermal stress may be applied to the dielectric layer DL. However, according to embodiments of the present invention, the dielectric layer DL, the second electrode E2, and the subsequent conductive interconnects can be formed at low temperatures, which can help reduce, suppress, or prevent leakage current through the dielectric layer DL due to thermal stress. Furthermore, the process for manufacturing the capacitor CA1 can be simplified.

[0107] Figure 5 This is a cross-sectional view of a capacitor illustrating some embodiments of the concept according to the present invention. In the following, reference is made to... Figure 1 The same elements or components described may be indicated by the same reference numerals or the same reference numerals, and for ease of explanation, their description will be omitted or briefly mentioned.

[0108] refer to Figure 5 The interlayer insulating layer 110 can be disposed on the substrate 100, and the contact plug 112 can be disposed in the interlayer insulating layer 110.

[0109] Capacitor CA2 can be disposed on interlayer insulating layer 110. Capacitor CA2 may include a first electrode E1, a second electrode E2, a dielectric layer DL, and a seed layer SL. The first electrode E1, the second electrode E2, and the dielectric layer DL can be connected to a reference... Figure 1 The components described are essentially the same.

[0110] A seed layer SL can be disposed between the dielectric layer DL and the second electrode E2. The seed layer SL may include a seed material that facilitates the crystallization of the dielectric material included in the dielectric layer DL into a tetragonal crystal structure. The seed material may be used in conjunction with a reference... Figure 1 The seed materials described are essentially the same. The mechanism for inducing a tetragonal crystal structure in the dielectric layer DL is similar to that described above. Figure 1The mechanisms described are the same.

[0111] In some embodiments, the seed layer SL can be in contact with the dielectric layer DL, such as... Figure 5 As shown. For example, see reference. Figure 1 The described secondary oxide layer may not be disposed between the seed layer SL and the dielectric layer DL. In some embodiments, the secondary oxide layer may be very thin, and therefore may not be observable between the seed layer SL and the dielectric layer DL.

[0112] In some embodiments, with Figure 5 Different, see reference Figure 1 The described secondary oxide layer SOL can be disposed between the seed layer SL and the dielectric layer DL.

[0113] Figure 6 This is a flowchart illustrating a method for manufacturing a capacitor according to some embodiments of the present invention. Figures 7A to 7C This is a cross-sectional view illustrating a method of manufacturing a capacitor according to some embodiments of the present invention. For example, Figure 6 and Figures 7A to 7C It may be that a manufacturing reference is shown. Figure 5 A diagram describing the method of using a capacitor. See below for reference. Figure 1 and Figure 5 The same elements or components described may be indicated by the same reference numerals or the same reference numerals, and for ease of explanation, their description will be omitted or briefly mentioned.

[0114] refer to Figure 6 and Figure 7A An interlayer insulating layer 110 and a contact plug 112 can be formed on the substrate 100. The formation of the interlayer insulating layer 110 and the contact plug 112 can be related to a reference. Figure 3 and Figure 4A The two items described are essentially the same in formation.

[0115] The first electrode E1 and the dielectric layer DL (S20) can be sequentially formed on the interlayer insulating layer 110.

[0116] A first electrode E1 can be formed on the interlayer insulating layer 110. The first electrode E1 can be electrically connected to the contact plug 112. For example, the first electrode E1 can be formed using a CVD process or an ALD process.

[0117] A dielectric layer DL can be formed on the first electrode E1. Immediately following the formation of the dielectric layer DL, the dielectric layer DL may include an amorphous dielectric material. For example, the dielectric layer DL may include amorphous hafnium oxide or amorphous zirconium oxide. The dielectric layer DL can be formed, for example, by a CVD process or an ALD process.

[0118] refer to Figure 6 and Figure 7B A seed layer SL (S21) can be formed on the dielectric layer DL. For example, the seed layer SL can be formed using CVD or ALD processes.

[0119] The seed layer SL may include a seed material that facilitates the crystallization of the dielectric material included in the dielectric layer DL into a tetragonal crystal structure. The seed material may be related to the above-mentioned references. Figure 1 The described seed materials are substantially the same. For example, the seed material may satisfy at least one of the above-described lattice constant conditions or bond length conditions. For example, the seed material may satisfy the above-described conductivity conditions, work function conditions, and / or oxide band gap conditions. For example, the seed material may include cobalt, nickel, copper, or Co4N. Alternatively, the seed material may include cobalt nitride with a compositional ratio similar to that of Co4N. For example, the seed material may include Co x N, where 3.5 < x < 4.5.

[0120] Reference Figure 4B Depending on the described process, an auxiliary oxide layer may not form between the seed layer SL and the dielectric layer DL. Alternatively, a very thin auxiliary oxide layer may be formed between the seed layer SL and the dielectric layer DL, so that this auxiliary oxide layer may not be observed. This may be because the process temperature for forming the seed layer SL is lower than the process temperature for forming the dielectric layer DL.

[0121] refer to Figure 6 and Figure 7C A second electrode E2 (S22) can be formed on the seed layer SL. The second electrode E2 can be formed spaced apart from the first electrode E1, with the seed layer SL and the dielectric layer DL between them. For example, the second electrode E2 can be formed using a CVD process or an ALD process.

[0122] The amorphous dielectric material included in the dielectric layer DL can be influenced by the seed layer SL, thus allowing the amorphous dielectric material to be crystallized into a tetragonal crystal structure at relatively low temperatures. For example, the amorphous dielectric material can be crystallized at temperatures of approximately 240 degrees Celsius or higher (e.g., temperatures from approximately 240 degrees Celsius to approximately 400 degrees Celsius).

[0123] The process for forming the second electrode E2 can be performed at a temperature of approximately 240 degrees Celsius or higher (e.g., a temperature from approximately 240 degrees Celsius to approximately 400 degrees Celsius). For example, at least a portion of the dielectric layer DL can be crystallized during the process of forming the second electrode E2. Since the seed layer SL, which includes the aforementioned seed material, is adjacent to the dielectric layer DL, the dielectric material can be crystallized into a tetragonal crystal structure.

[0124] refer to Figure 5 and Figure 6 A subsequent heat treatment process (S23) can be performed. For example, the subsequent heat treatment process can induce further crystallization in the dielectric layer DL. In some embodiments, the dielectric material can be crystallized into a tetragonal crystal structure by a subsequent heat treatment process. For example, the subsequent heat treatment process can correspond to the process of forming conductive interconnects (not shown) on capacitor CA2, and can be performed at a temperature of about 240 degrees Celsius or higher (e.g., about 240 degrees Celsius to about 400 degrees Celsius). For example, the dielectric material can be crystallized into a tetragonal crystal structure when forming conductive interconnects electrically connected to the second electrode E2. In some embodiments, the subsequent heat treatment process can be a different process than forming conductive interconnects.

[0125] Figure 8 This is a cross-sectional view of a capacitor illustrating some embodiments of the concept according to the present invention. In the following, reference is made to... Figure 1 and / or Figure 5 The same elements or components described may be indicated by the same reference numerals or the same reference numerals, and for ease of explanation, their description will be omitted or briefly mentioned.

[0126] refer to Figure 8 The interlayer insulating layer 110 can be disposed on the substrate 100, and the contact plug 112 can be disposed in the interlayer insulating layer 110.

[0127] Capacitor CA3 can be disposed on interlayer insulating layer 110. Capacitor CA3 may include a first electrode E1, a second electrode E2, a dielectric layer DL, a first seed layer SL1, and a second seed layer SL2. The first electrode E1, the second electrode E2, and the dielectric layer DL can be disposed with reference to... Figure 1 The components described are essentially the same.

[0128] The first seed layer SL1 can be disposed between the first electrode E1 and the dielectric layer DL. The first seed layer SL1 can be disposed with respect to the reference layer. Figure 1 The seed layer SL described is essentially the same.

[0129] The second seed layer SL2 can be disposed between the second electrode E2 and the dielectric layer DL. The second seed layer SL2 can be disposed with respect to the reference layer. Figure 5 The seed layer SL described is essentially the same.

[0130] In some embodiments, capacitor CA3 may include a secondary oxide layer SOL disposed between the first seed layer SL1 and the dielectric layer DL, such as Figure 8 As shown. The secondary oxide layer SOL can be compared with the reference. Figure 1 The described secondary oxide layer SOL is essentially the same.

[0131] In some embodiments, with Figure 8 Unlike other capacitors, CA3 may not include the secondary oxide layer SOL.

[0132] Figure 9 This is a flowchart illustrating a method for manufacturing a capacitor according to some embodiments of the present invention. Figures 10A to 10C This is a cross-sectional view illustrating a method of manufacturing a capacitor according to some embodiments of the present invention. For example, Figure 9 and Figures 10A to 10C It may be that a manufacturing reference is shown. Figure 8 A diagram describing the method of using a capacitor. See below for reference. Figure 1 , Figure 5 and Figure 8 The same elements or components described may be indicated by the same reference numerals or the same reference numerals, and for ease of explanation, their description will be omitted or briefly mentioned.

[0133] refer to Figure 9 and Figure 10A An interlayer insulating layer 110 and a contact plug 112 can be formed on the substrate 100. The formation of the interlayer insulating layer 110 and the contact plug 112 can be related to a reference. Figure 3 and Figure 4A The two items described are essentially the same in formation.

[0134] A first electrode E1 and a first seed layer SL1 can be sequentially formed on the interlayer insulating layer 110 (S30). The process for forming the first electrode E1 and the first seed layer SL1 can be the same as that described in the reference. Figure 3 and Figure 4A The processes for forming the first electrode E1 and the seed layer SL are substantially the same. The first seed layer SL1 may include a seed material that facilitates the crystallization of the dielectric material included in the dielectric layer DL to be formed in subsequent processes into a tetragonal crystal structure. For example, the dielectric material in the dielectric layer DL can be formed into a tetragonal crystal structure through interaction with the seed material.

[0135] A dielectric layer DL (S31) can be formed on the first seed layer SL1. The process for forming the dielectric layer DL can be compared with the reference. Figure 3 and Figure 4BThe described process for forming the dielectric layer DL is substantially the same. Immediately following the formation of the dielectric layer DL, the dielectric layer DL may comprise an amorphous dielectric material. For example, the dielectric layer DL may comprise amorphous hafnium oxide or amorphous zirconium oxide. In some embodiments, at least a portion of the dielectric layer DL may crystallize into a tetragonal crystal structure during the deposition process. In this case, immediately following the formation of the dielectric layer DL, the dielectric layer DL may comprise both an amorphous dielectric material and a dielectric material having a tetragonal crystal structure. The dielectric layer DL can be formed at a temperature of approximately 240 degrees Celsius or higher (e.g., temperatures from approximately 240 degrees Celsius to 290 degrees Celsius).

[0136] refer to Figure 9 and Figure 10B A second seed layer SL2 (S32) can be formed on the dielectric layer DL. The process for forming the second seed layer SL2 can be the same as the reference. Figure 6 and Figure 7B The process for forming the seed layer SL is substantially the same as described. The second seed layer SL2 may include a seed material that helps to crystallize the dielectric material included in the dielectric layer DL into a tetragonal crystal structure.

[0137] refer to Figure 9 and Figure 10C A second electrode E2 (S33) can be formed on the second seed layer SL2. The process for forming the second electrode E2 can be the same as that described in the reference. Figure 6 and Figure 7C The process for forming the second electrode E2 is substantially the same as described. At least a portion of the dielectric layer DL can be crystallized using the process for forming the second electrode E2. Since the first seed layer SL1 and the second seed layer SL2, which include the aforementioned seed materials, are adjacent to the dielectric layer DL, the dielectric material can be crystallized into a tetragonal crystal structure.

[0138] refer to Figure 8 and Figure 9 A subsequent heat treatment process (S34) can be performed. For example, the subsequent heat treatment process can induce further crystallization in the dielectric layer DL. In some embodiments, the dielectric material can be crystallized into a tetragonal crystal structure by a subsequent heat treatment process. For example, the subsequent heat treatment process can correspond to the process of forming conductive interconnects (not shown) on capacitor CA3, and can be performed at a temperature of about 240 degrees Celsius or higher (e.g., about 240 degrees Celsius to about 400 degrees Celsius). For example, the dielectric material can be crystallized into a tetragonal crystal structure when forming conductive interconnects electrically connected to the second electrode E2. In some embodiments, the subsequent heat treatment process can be a different process than forming the conductive interconnects.

[0139] [Analysis results of the crystal structure of hafnium oxide]

[0140] Figure 11A This is a graph showing the X-ray diffraction analysis results of the crystal structure of hafnium oxide formed on a general electrode. For example, the general electrode may be substantially the same as one of the electrodes E1 and E2 described in this disclosure, but without a seed layer between the electrode and the hafnium oxide layer. For example, the hafnium oxide is formed on titanium nitride and subjected to heat treatment (or annealing) at a certain temperature. Subsequently, the hafnium oxide is analyzed by X-ray diffraction analysis. For example, Figure 11A The distribution of hafnium oxide structures in the hafnium oxide layer formed on the titanium nitride electrode is shown in the absence of a seed layer between the hafnium oxide layer and the titanium nitride electrode. Before measuring the hafnium oxide structure, the titanium nitride electrode and the hafnium oxide layer formed on the titanium nitride were heat-treated (or annealed) at different temperatures.

[0141] refer to Figure 11A It can be recognized that when a hafnium oxide layer is formed on a general electrode and heat-treated (or annealed) at a temperature of about 240 degrees Celsius to about 600 degrees Celsius, hafnium oxide with a monoclinic crystal structure (m-HfO2) and hafnium oxide with a tetragonal crystal structure (t-HfO2) coexist in the hafnium oxide layer.

[0142] Figure 11B This is a graph illustrating the X-ray diffraction analysis results of the crystal structure of a hafnium oxide layer formed on a seed layer according to some embodiments of the present invention. For example, the hafnium oxide layer is formed on Co4N and subjected to heat treatment (or annealing) at a certain temperature. Subsequently, the hafnium oxide is analyzed by X-ray diffraction analysis.

[0143] refer to Figure 11B It can be recognized that when a hafnium oxide layer is formed on a seed layer in certain embodiments of the present invention and heat-treated (or annealed) at a temperature of about 240 degrees Celsius to about 600 degrees Celsius, hafnium oxide (t-HfO2) with a tetragonal crystal structure is mainly formed in the hafnium oxide layer.

[0144] [The crystal structure of zirconium oxide based on thickness analysis results]

[0145] Figure 11C This is a graph showing the X-ray diffraction analysis results of zirconia layers formed on general electrodes and having different thicknesses from each other. For example, each general electrode may be substantially the same as one of the electrodes E1 and E2 described in this disclosure, but without a seed layer between the electrode and the zirconia layer. For example, layers with thicknesses of different thicknesses are formed on titanium nitride electrodes. and A zirconium oxide layer was formed, and the titanium nitride electrode and the zirconium oxide layer formed on the titanium nitride electrode were heat-treated (i.e., annealed) at a certain temperature. Subsequently, the zirconium oxide layer was analyzed by X-ray diffraction. Figure 11C In the diagram, samples c1, c2, c3, c4, and c5 show thicknesses of... and Analysis results of the zirconium oxide layer.

[0146] refer to Figure 11C When the thickness of the zirconium oxide layer is relatively small, such as in samples c1, c2, and c3 (e.g., When the thickness of the zirconia layer is relatively large (e.g., greater than or smaller than the thickness of samples c4 and c5), zirconia (t-ZrO2) with a tetragonal crystal structure does not form. However, when the thickness of the zirconia layer is relatively large, such as in samples c4 and c5 (e.g., greater than the thickness of samples c4 and c5), zirconia does not form. When ), zirconium oxide (t-ZrO2) with a tetragonal crystal structure is formed.

[0147] Figure 11D This is a graph illustrating the X-ray diffraction analysis results of a crystal structure with zirconium oxide layers of varying thicknesses according to an embodiment of the present invention. Figure 11D In this process, zirconium oxide layers are formed on seed layers. For example, zirconium oxide layers with thicknesses of [thickness values ​​missing] are formed on cobalt (Co) layers. and A zirconia layer was formed, and the cobalt layer and the zirconia layer formed on the cobalt layer were heat-treated (i.e., annealed). The zirconia layer on the cobalt layer was then analyzed by X-ray diffraction. Here, the thickness of each cobalt layer is approximately [missing information]. exist Figure 11D In the sample diagram, samples e11, e12, and e13 show thicknesses of respectively. and Analysis results of the zirconium oxide layer.

[0148] refer to Figure 11D When zirconia is formed on the seed layer, regardless of the thickness of the zirconia, a tetragonal zirconia (t-ZrO2) crystal structure is formed. For example, in samples with relatively small zirconia layers, such as sample e11 (e.g., (or smaller) and the relatively large thickness of the zirconia layer, such as in samples e12 and e13 (e.g., greater than). In both cases, zirconium oxide (t-ZrO2) with a tetragonal crystal structure was observed.

[0149] Figure 11E This is a graph illustrating the X-ray diffraction analysis results of a crystal structure with zirconium oxide layers of varying thicknesses according to an embodiment of the present invention. Figure 11EIn this process, a zirconium oxide layer is formed on a seed layer. For example, a zirconium oxide layer with thicknesses of [thickness values ​​missing] is formed on a nickel (Ni) layer. and A zirconium oxide layer was formed on the nickel layer, and both the nickel layer and the zirconium oxide layer formed on the nickel layer were heat-treated (i.e., annealed). The zirconium oxide layer on the nickel layer was then analyzed by X-ray diffraction. Here, the thickness of each nickel layer is... exist Figure 11E In the sample diagram, samples e21, e22, and e23 show thicknesses of respectively. and Analysis results of the zirconium oxide layer.

[0150] refer to Figure 11E When zirconia is formed on the seed layer, regardless of the thickness of the zirconia, a tetragonal zirconia (t-ZrO2) crystal structure is formed. For example, in samples e21 and e22 with relatively small zirconia layer thicknesses (e.g., ...), ... (or smaller) and the relatively large thickness of the zirconia layer, such as in sample e23 (e.g., greater than). In both cases, zirconium oxide (t-ZrO2) with a tetragonal crystal structure was observed.

[0151] [Analysis of the crystal structure of zirconium oxide based on temperature conditions]

[0152] Figure 11F This is a graph showing the X-ray diffraction analysis results of the crystal structures of zirconia layers formed on general electrodes at different temperatures. For example, each general electrode may be substantially the same as one of electrodes E1 and E2 described in this disclosure, but without a seed layer between the electrode and the zirconia. For example, zirconia layers were formed (deposited) on titanium nitride electrodes at 250°C, 275°C, and 300°C, and the formed zirconia layers were analyzed by X-ray diffraction analysis. Here, the thickness of each zirconia layer is... No seed crystal layer was formed. Figure 11F In the figures, samples c11, c12, and c13 show the analytical results of the zirconia layers formed at 250℃, 275℃, and 300℃, respectively.

[0153] refer to Figure 11F When the zirconia layer is formed at a relatively low temperature (e.g., 290°C or lower), as in samples c11 and c12, zirconia with a tetragonal crystal structure (t-ZrO2) is not formed in the zirconia layer. However, when the zirconia layer is formed at a relatively high temperature (e.g., greater than 290°C), as in sample c13, zirconia with a tetragonal crystal structure (t-ZrO2) is formed.

[0154] Figure 11GThese are X-ray diffraction (XRD) graphs showing the crystal structures of zirconia layers formed on seed layers at different temperatures. For example, zirconia layers were formed (deposited) on cobalt (Co) layers at 250°C, 275°C, and 300°C, respectively, and the formed zirconia layers were analyzed by XRD. In samples e31, e32, and e33, the thickness of each cobalt layer is... Samples e31, e32, and e33 show the results at 250°C, 275°C, and 300°C respectively, with a thickness of [missing information]. The analysis results show the zirconium oxide layer formed on the cobalt layer. In samples e41, e42, and e43, the thickness of each cobalt layer is... Samples e41, e42, and e43 show the results at 250°C, 275°C, and 300°C respectively, with a thickness of [missing information]. The analysis results show the zirconium oxide layers formed on the cobalt layer. Here, the thicknesses of the zirconium oxide layers in samples e31, e32, e33, e41, e42, and e43 are respectively... and

[0155] refer to Figure 11G When the zirconia layer is formed at a relatively low temperature (e.g., 290°C or less), as in samples e31, e32, e41, and e42, zirconia with a tetragonal crystal structure (t-ZrO2) is formed. When the zirconia layer is formed at a relatively high temperature (e.g., greater than 290°C), as in samples e33 and e43, zirconia with a tetragonal crystal structure (t-ZrO2) is formed. For example, even when the seed layer (i.e., the cobalt layer) is relatively thin, as in samples e41, e42, and e43, zirconia with a tetragonal crystal structure (t-ZrO2) is formed.

[0156] Figure 11H These are X-ray diffraction (XRD) graphs showing the crystal structures of zirconia layers formed on seed layers at different temperatures. For example, zirconia layers were formed (deposited) on nickel (Ni) layers at 250°C, 275°C, and 300°C, respectively, and the formed zirconia layers were analyzed by XRD. In samples e51, e52, and e53, the thickness of each nickel layer is... Samples e51, e52, and e53 demonstrate the results at 250°C, 275°C, and 300°C, respectively, with a thickness of [missing information]. The analysis results show the zirconium oxide layer formed on the nickel layer. In samples e61, e62, and e63, the thickness of each nickel layer is... Samples e61, e62, and e63 demonstrate the results at 250°C, 275°C, and 300°C, respectively, with a thickness of [missing information]. The analysis results show the zirconium oxide layer formed on the nickel layer. Here, the thicknesses of the zirconium oxide layers in samples e51, e52, e53, e61, e62, and e63 are respectively... and

[0157] refer to Figure 11H When the zirconia layer is formed at a relatively low temperature (e.g., 290°C or less), as in samples e51, e52, e61, and e62, zirconia with a tetragonal crystal structure (t-ZrO2) is formed. When the zirconia layer is formed at a relatively high temperature (e.g., greater than 290°C), as in samples e53 and e63, zirconia with a tetragonal crystal structure (t-ZrO2) is formed. Furthermore, even when the seed layer (i.e., the nickel layer) is relatively thin, as in samples e61, e62, and e63, zirconia with a tetragonal crystal structure (t-ZrO2) is formed.

[0158] Figures 12A to 12C This is a cross-sectional view illustrating an example of the shape of a capacitor in a semiconductor device according to some embodiments of the present invention. The capacitor can be compared with a reference... Figure 1 , Figure 5 and / or Figure 8 The capacitors described are essentially the same, except for their shape.

[0159] refer to Figures 12A to 12C An interlayer insulating layer 110 may be disposed on a substrate 100. The interlayer insulating layer 110 may cover a selection element (not shown) disposed on the substrate 100.

[0160] Contact plugs 112 may be disposed in the interlayer insulation layer 110. Contact plugs 112 may be electrically connected to the selection element.

[0161] Capacitor CA3 can be disposed on interlayer insulation layer 110. Capacitor CA3 can be electrically connected to contact plug 112. Figures 12A to 12C References are shown Figure 8 The capacitor CA3 is described. However, embodiments of the present invention are not limited thereto. In some embodiments, references may be used. Figure 1 The capacitor CA1 described or the reference Figure 5 The capacitor CA2 is used instead of each capacitor CA3. Each capacitor CA3 may include a first electrode E1, a second electrode E2, a dielectric layer DL, a first seed layer SL1, a second seed layer SL2, and a sub-oxide layer SOL. The first electrode E1 may be disposed in each capacitor CA3 and may be spaced apart from each other. On the other hand, the second electrode E2, the dielectric layer DL, the first seed layer SL1, the second seed layer SL2, and the sub-oxide layer SOL may be shared by multiple capacitors CA3.

[0162] In some embodiments, each first electrode E1 may be columnar, such as Figure 12A As shown. The first seed layer SL1, the secondary oxide layer SOL, the dielectric layer DL, the second seed layer SL2, and the second electrode E2 conformally cover the sidewalls and top surface of the first electrode E1 and the top surface of the interlayer insulating layer 110.

[0163] In some embodiments, the first electrode E1 may be disposed in the upper insulating layer 120 formed on the interlayer insulating layer 110, such as... Figure 12B As shown. Each first electrode E1 can be a hollow column with a closed bottom, and the outer wall of the first electrode E1 can be in contact with the upper insulating layer 120. The first seed layer SL1, the secondary oxide layer SOL, the dielectric layer DL, the second seed layer SL2, and the second electrode E2 can conformally cover the inner surface of the first electrode E1 and the top surface of the upper insulating layer 120.

[0164] In some embodiments, each first electrode E1 may be a hollow cylindrical shape with a closed bottom, such as... Figure 12C As shown. The first seed layer SL1, the secondary oxide layer SOL, the dielectric layer DL, the second seed layer SL2, and the second electrode E2 conformally cover the inner surface and outer sidewall of the first electrode E1 and the top surface of the interlayer insulating layer 110.

[0165] Figure 13A This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention. In the following text, for ease of explanation, descriptions of the same technical features as those in the above embodiments will be omitted or briefly mentioned.

[0166] refer to Figure 13A Semiconductor device 1 may include a substrate 100, a dielectric layer DL, a seed layer SL, and a gate electrode layer EL. Substrate 100 may be a semiconductor substrate. For example, substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, substrate 100 may be a silicon-on-insulator (SOI) substrate. Substrate 100 may have source / drain regions SDR and a channel region. The source / drain regions SDR of substrate 100 may be regions doped with dopant. The dielectric layer DL, the seed layer SL, and the gate electrode layer EL may expose the source / drain regions SDR of substrate 100. A portion of substrate 100 disposed below the gate electrode layer EL may be used as a channel region. The channel region of substrate 100 may be disposed between the source / drain regions SDR.

[0167] A dielectric layer DL can be formed on the substrate 100. The dielectric layer DL may include zirconium oxide and / or hafnium oxide. The dielectric layer DL may have approximately up to approximately The thickness of the dielectric layer DL is specified. The dielectric layer DL can be deposited amorphously on the substrate 100. The dielectric layer DL can be formed using, for example, CVD or ALD processes. The dielectric layer DL can be used as a gate insulating layer.

[0168] A seed layer SL can be formed on the dielectric layer DL. For example, the seed layer SL can be formed using CVD or ALD processes. The seed layer SL may include a seed material that facilitates the crystallization of the dielectric material included in the dielectric layer DL into a tetragonal crystal structure. The seed material may be related to a reference... Figure 1 The described seed materials are substantially the same. For example, the seed material may satisfy at least one of the above-described lattice constant conditions or bond length conditions. For example, the seed material may satisfy the above-described conductivity conditions, work function conditions, and / or oxide band gap conditions. For example, the seed material may include cobalt, nickel, copper, and Co4N.

[0169] A gate electrode layer EL can be formed on a seed layer SL. For example, the gate electrode layer EL can be formed by a CVD process or an ALD process. The gate electrode layer EL can include a conductive material. For example, the gate electrode layer EL can include at least one of the following: a doped semiconductor material, a metal, a conductive metal nitride, and / or a metal semiconductor compound. The process of forming the gate electrode layer EL can be performed at a temperature of approximately 240 degrees Celsius or higher (e.g., temperatures from approximately 240 degrees Celsius to approximately 400 degrees Celsius). The amorphous dielectric material included in the dielectric layer DL can be affected by the temperature conditions of the seed layer SL, and the dielectric layer DL can be crystallized, for example, during the process of forming the gate electrode layer EL. Since the seed layer SL is adjacent to the dielectric layer DL, the dielectric material can be crystallized into a tetragonal crystal structure.

[0170] Subsequently, a subsequent heat treatment process can be performed. This subsequent heat treatment process can be used to crystallize the dielectric material in the dielectric layer DL into a tetragonal crystal structure. The subsequent heat treatment process can correspond to, for example, the process of forming conductive interconnects (not shown) on the gate electrode layer EL, and can be performed at a temperature of about 240 degrees Celsius or higher (e.g., about 240 degrees Celsius to about 400 degrees Celsius).

[0171] Figure 13B This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention. In the following text, for ease of explanation, descriptions of the same technical features as those in the above embodiments will be omitted or briefly mentioned.

[0172] refer to Figure 13B The semiconductor device 2 may include a substrate 100, a dielectric layer DL, a seed layer SL, and a gate electrode layer EL. Figure 13BThe dielectric layer DL, seed layer SL, and gate electrode layer EL can be respectively connected to Figure 13A The dielectric layer DL, seed layer SL, and gate electrode layer EL are essentially the same. However, Figure 13B The gate electrode layer EL can be embedded in the substrate 100.

[0173] According to some embodiments of the present invention, a trench 101 may be formed in a substrate 100. A dielectric layer DL may be conformally formed on the inner surface of the trench 101. The dielectric layer DL may include a reference... Figure 1 The dielectric layer DL described is made of substantially the same material. The dielectric layer DL may be deposited amorphously on the substrate 100. For example, immediately after the dielectric layer DL is deposited on the substrate 100, at least a portion of the dielectric material included in the dielectric layer DL may be in an amorphous state. In some embodiments, the dielectric material included in the dielectric layer DL may be substantially amorphous when the dielectric material is deposited on the substrate 100. A seed layer SL may be formed on the dielectric layer DL. The seed layer SL may include a seed material that facilitates the crystallization of the dielectric material included in the dielectric layer DL into a tetragonal crystal structure. The seed material may be similar to the reference material. Figure 1 The seed material described is substantially the same. A gate electrode layer EL can be formed on the seed layer SL to fill trench 101. The process for forming the gate electrode layer EL can be performed at a temperature of approximately 240 degrees Celsius or higher (e.g., a temperature from approximately 240 degrees Celsius to approximately 400 degrees Celsius). For example, the dielectric layer DL can be crystallized into a tetragonal crystal structure during the process of forming the gate electrode layer EL. Source / drain regions SDR can be formed on both sides of the gate electrode layer EL in the substrate 100.

[0174] Subsequently, a subsequent heat treatment process can be performed. This subsequent heat treatment process can be used to crystallize the dielectric material in the dielectric layer DL into a tetragonal crystal structure. The subsequent heat treatment process can correspond to, for example, the process of forming conductive interconnects (not shown) on the gate electrode layer EL, and can be performed at a temperature of approximately 240 degrees Celsius or higher (e.g., approximately 240 degrees Celsius to approximately 400 degrees Celsius). The subsequent heat treatment process can be a process of forming conductive interconnects electrically connected to the gate electrode layer EL, or it can be a process different from forming conductive interconnects. A temperature between 240 degrees Celsius and 400 degrees Celsius can be applied in the subsequent heat treatment process to induce a tetragonal crystal structure in the dielectric layer DL.

[0175] According to some embodiments of the present invention, the dielectric layer may comprise hafnium oxide or zirconium oxide with a tetragonal crystal structure having a high dielectric constant. Therefore, the capacitance of the capacitor can be increased.

[0176] According to some embodiments of the present invention, dielectric materials can be crystallized into a tetragonal crystal structure without additional high-temperature heat treatment processes. Therefore, the process for manufacturing capacitors can be simplified.

[0177] According to some embodiments of the present invention, dielectric materials can be crystallized into a tetragonal crystal structure at low temperatures. Therefore, the process for manufacturing capacitors can be simplified, and leakage current flowing through the dielectric layer can be reduced or prevented.

[0178] According to some embodiments of the present invention, the dielectric layer can have a relatively thin thickness, and the size of the capacitor can be reduced or minimized while maintaining adequate capacitance so that the capacitor and / or semiconductor device can operate properly.

[0179] Although the inventive concept has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes and modifications can be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative.

Claims

1. A capacitor, comprising: The first and second electrodes are spaced apart from each other; A dielectric layer is disposed between the first electrode and the second electrode, the dielectric layer comprising hafnium oxide having a tetragonal crystal structure or zirconium oxide having a tetragonal crystal structure; A first seed crystal layer is disposed between the first electrode and the dielectric layer; as well as A second seed layer is disposed between the dielectric layer and the second electrode. The first seed layer comprises a first conductive material that is different from the hafnium or zirconium element included in the dielectric layer. The second seed layer comprises a second conductive material that is different from the hafnium or zirconium element included in the dielectric layer, and Wherein, the lattice constants of the first conductive material and the second conductive material are 2% or less of a lattice mismatch with the horizontal lattice constant of the dielectric material of the dielectric layer.

2. The capacitor according to claim 1, wherein, The first electrode comprises titanium nitride, and The second electrode comprises titanium nitride.

3. The capacitor according to claim 1, wherein, At least one of the first seed layer and the second seed layer includes a conductor.

4. The capacitor according to claim 1, wherein, The first conductive material has a cubic crystal structure.

5. The capacitor according to claim 4, wherein, The second conductive material has a cubic crystal structure.

6. The capacitor according to claim 1, wherein, The first conductive material and the second conductive material include cobalt, nickel, copper or Co. x N, where 3.5 < x < 4.

5.

7. The capacitor according to claim 1, wherein, The first seed layer and the second seed layer comprise the same material.

8. A capacitor, comprising: The first and second electrodes are spaced apart from each other; A dielectric layer is disposed between the first electrode and the second electrode, the dielectric layer comprising hafnium oxide having a tetragonal crystal structure or zirconium oxide having a tetragonal crystal structure; A first seed crystal layer is disposed between the first electrode and the dielectric layer; A second seed crystal layer is disposed between the dielectric layer and the second electrode; as well as A secondary oxide layer is disposed between the dielectric layer and the first seed layer. The first seed crystal layer comprises a first material. The second seed layer comprises a second material. Wherein, the lattice constants of the first material and the second material respectively have a lattice mismatch of 2% or less with the horizontal lattice constant of the dielectric material of the dielectric layer, and The secondary oxide layer comprises the same metal as the metal included in the first seed crystal layer.

9. The capacitor according to claim 8, wherein, The thickness of the secondary oxide layer is in the range of 5 Å to 10 Å.

10. A capacitor, comprising: The first and second electrodes are spaced apart from each other; A dielectric layer is disposed between the first electrode and the second electrode, the dielectric layer comprising hafnium oxide having a tetragonal crystal structure or zirconium oxide having a tetragonal crystal structure; A first conductive seed layer is disposed between the first electrode and the dielectric layer; as well as A second conductive seed layer is disposed between the dielectric layer and the second electrode. Wherein, the first conductive seed layer comprises a first material, and the second conductive seed layer comprises a second material. Wherein, the first conductive seed layer and the second conductive seed layer comprise the same material, and Wherein, the lattice constants of the first material and the second material are 2% or less of a lattice mismatch with the horizontal lattice constant of the dielectric material of the dielectric layer.

11. The capacitor according to claim 10, wherein, The first material and the second material have a cubic crystal structure.

12. The capacitor according to claim 10, wherein, The first electrode comprises titanium nitride, and the second electrode comprises titanium nitride.

13. The capacitor according to claim 10, wherein, The first material and the second material include cobalt, nickel, copper or Co. x N, where 3.5 < x < 4.

5.

14. The capacitor according to claim 10, wherein, The dielectric layer includes a first metal element, and the first conductive seed layer and the second conductive seed layer include metal elements different from the first metal element.

15. A capacitor, comprising: Interlayer insulating layer on substrate; The contact plug in the interlayer insulation layer; The first electrode, which is on the interlayer insulating layer and electrically connected to the contact plug, comprises titanium nitride. A second electrode spaced apart from the first electrode, the second electrode comprising titanium nitride; A dielectric layer is disposed between the first electrode and the second electrode; A first seed crystal layer is disposed between the first electrode and the dielectric layer, and the first seed crystal layer comprises a first material; as well as A second seed layer is disposed between the dielectric layer and the second electrode, and the second seed layer comprises a second material. The first seed layer and the second seed layer are made of the same material. The dielectric layer comprises hafnium oxide with a tetragonal crystal structure or zirconium oxide with a tetragonal crystal structure, and The lattice constants of the first material and the second material are respectively mismatched with the horizontal lattice constant of the dielectric material of the dielectric layer by 0.28% and 2%.

16. The capacitor according to claim 15, wherein, The first material and the second material include conductors.

17. The capacitor according to claim 16, wherein, The conductor is cobalt, nickel, copper, or Co. x One of N, where 3.5 < x < 4.5.

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