Frequency Tunable Loop Oscillator

Abstract

The present invention discloses a frequency-tunable loop oscillator, which includes: an LDO unit and a VCO loop oscillation unit. The LDO unit includes an LDO power supply circuit and an LDO bias current trimming circuit. The LDO power supply circuit and the LDO bias current trimming circuit cooperate to provide a voltage and a preset bias current for the VCO loop oscillation unit. The VCO loop oscillation unit generates an oscillation clock signal according to the voltage and the preset bias current. By the cooperation of the LDO power supply circuit and the LDO bias current trimming circuit to provide a voltage and a preset bias current for the VCO loop oscillation unit, trimming is performed on the loop oscillator to eliminate the non-linear influence brought by power supply noise and modulation effect.

Description

Technical Field

[0001] This application relates to the field of ring oscillators, and particularly to a frequency-tunable ring oscillator. Background Art

[0002] Voltage-controlled oscillators are widely used in analog circuits to provide clock signals for local oscillator frequencies. This system includes both analog and digital circuits, as well as high-frequency and low-frequency parts. Therefore, quality indicators such as the frequency stability and phase stability of its output signals are very important. The implementation structures of CMOS oscillators often focus on two types: LC oscillators and ring oscillators. Among them, ring oscillators are mainly composed of several delay units. When the output signal of a certain unit passes through the entire loop and returns to the input of this unit, the signal flips. Therefore, the circuit generates a periodic oscillation signal. However, because ring oscillators do not have high-quality filters, their phase noise is worse than that of LC oscillators and is more susceptible to PVT effects. Therefore, in terms of reducing the phase noise of ring oscillators and improving reliability. The existing ring oscillator applied to the internal clock startup module of the chip can generate a clock signal with a frequency of 500 MHz. In actual applications, it is always inevitable to be affected by power supply noise, and the non-linearity brought by the channel length modulation effect under the existing process is becoming more and more obvious. Therefore, it is necessary to design a circuit module to provide voltage and bias current for the ring oscillator to adjust the ring oscillator. Summary of the Invention

[0003] This application provides a frequency-tunable ring oscillator to eliminate the problem of the non-linear influence caused by power supply noise and modulation effect of the ring oscillator in the internal clock startup module of the chip.

[0004] To solve the above technical problems, a technical solution adopted in this application is: to provide a frequency-tunable ring oscillator, which includes: an LDO unit and a VCO loop oscillation unit. The LDO unit includes an LDO power supply circuit and an LDO bias current adjustment circuit. The LDO power supply circuit and the LDO bias current adjustment circuit cooperate to provide voltage and a preset bias current for the VCO loop oscillation unit. The VCO loop oscillation unit generates an oscillation clock signal according to the voltage and the preset bias current. The LDO power supply circuit and the LDO bias current adjustment circuit are respectively used to supply voltage and provide a preset bias current for the VCO loop oscillation unit, so that the VCO loop oscillation unit has a good power supply noise suppression ratio. Further, the programmable MOS transistor array of the LDO bias current adjustment circuit can be programmed to adjust the startup frequency of the VCO loop oscillation unit, overcoming the non-linear influence brought by the short-channel effect under the MOS transistor process.

[0005] Furthermore, the operational amplifier AMP1 in the LDO power supply circuit copies the VREF1 buffer voltage to the resistor divider network for voltage division via the series resistor R0 and the ground resistor R1. The VREF1 buffer voltage is then divided by the operational amplifier AMP2 and the ground resistor R2 to obtain a target voltage for powering the VCO loop oscillation unit. The operational amplifiers at the two stages of AMP1 and AMP2 have the function of amplifying voltage. A clean voltage source is obtained through layer-by-layer voltage division via the series resistor and the ground resistor to provide power for the VCO loop oscillation unit. The VCO loop oscillation unit is powered after the original power supply noise is eliminated.

[0006] Further specifically, the LDO bias current trimming circuit includes an LDO of an operational amplifier AMP3, wherein the operational amplifier AMP3 first drives the connected PMOS tube PM1 with the VREF2 buffer voltage output, and then copies the current to the PMOS tube PM0 connected to the PMOS tube PM1 in the form of a current mirror, the leakage current of the PMOS tube PM0 provides a bias current for the VCO loop oscillation unit, the leakage end of the PMOS tube PM1 is connected to the grounding resistor R3 and the positive electrode of the operational amplifier AMP3, the leakage current of the PMOS tube PM0 provides a bias current for the VCO loop oscillation unit, the operational amplifier AMP3 first drives the connected PMOS tube PM1 with the VREF2 buffer voltage output, and then copies the current of the PMOS tube PM1 to the connected PMOS tube PM0 in the form of a current mirror, so that the bias current from the LDO bias current trimming circuit can be fully accepted, and the programmable MOS tube array of the LDO bias current trimming circuit can realize programming to trim the bias current of the starting frequency of the VCO loop oscillation unit, thereby restraining the nonlinear influence caused by the short channel effect of the MOS tube under the existing process.

[0007] Furthermore, the LDO bias current trimming circuit also includes an LDO buffer circuit, which drives the PMOS tube PM5 with the output voltage to convert the voltage into current, and converts the current at the drain end of the PMOS tube PM5 into voltage by connecting the connected PMOS tube NM2 in a diode connection manner, and then outputs it to the gate ends of the two parallel P / N MOS tube arrays of the connected PMOS tube PM6 array and the PMOS tube NM3 array in a current mirror manner through the PMOS tube PM5 and the PMOS tube NM2, and uses the PMOS tube PM6 array and the PMOS tube NM3 array to implement programming, and trim the bias current of the starting frequency of the VCO loop oscillation unit.

[0008] Further, the LDO buffer circuit further includes that the gate terminals of PMOS transistor PM5 and PMOS transistor PM4 are connected, the drain terminal of PMOS transistor PM4 is connected to the grounding resistor R4, the drain terminal of PMOS transistor PM4 is serially connected to the gate terminal of PMOS transistor NM0, the drain terminals of PMOS transistor NM0 and PMOS transistor NM1 are connected in parallel to the source terminal of PMOS transistor NM4, and the drain terminal of PMOS transistor NM4 is connected in parallel to the drain terminals of PMOS transistor NM2 and the PMOS transistor NM3 array, thereby constructing an LDO buffer circuit that provides a buffer voltage for the PMOS transistor PM6 array and the PMOS transistor NM3 array to generate a bias current through programming.

[0009] Further, the LDO buffer circuit further includes that the gate terminals of PMOS transistor PM2 and PMOS transistor PM3 are connected, the source terminals of PMOS transistor NM0 and PMOS transistor PM2 are connected, and an interconnecting wire is provided on the connection line of the gate terminals of PMOS transistor PM2 and PMOS transistor PM3 and is connected to the source terminals of PMOS transistor NM0 and PMOS transistor PM2, and the source terminals of PMOS transistor PM3 and PMOS transistor NM1 are connected in parallel to the gate terminal of PMOS transistor PM4.

[0010] Further specifically, the current-carrying terminals of the P / N MOS transistor array are connected in parallel between the drain terminal of PMOS transistor PM1 and the grounding resistor R3.

[0011] Further specifically, the LDO buffer circuit further includes a decoder module. The decoder module is used to select the path of the P / N MOS transistor array switch P / NMOS. The decoder module is programmable and configured for selection using codes from 0 to 255 to generate different bias currents. The decoder module using codes from 0 to 255 for programmable configuration of selection corresponds to 256 different bias current relationships. The bias current that meets the startup frequency of the VCO loop oscillation unit can be adjusted according to needs for the 256 bias currents. The advantages of this tunable frequency oscillator include a good power supply rejection ratio; the programmable MOS transistor array can realize programming to adjust the startup frequency of the VCO oscillation unit, overcoming the nonlinear influence brought by the short-channel effect under the MOS transistor process.

[0012] Further specifically, the decoder module programmably selects the P / N MOS transistor array, thereby adjusting the node current and the current flow direction.

[0013] The beneficial effects of the present application are as follows: An adjustable-frequency loop oscillator of the present application includes an LDO unit and a VCO loop oscillation unit. The LDO unit includes an LDO power supply circuit and an LDO bias current trimming circuit. The LDO power supply circuit and the LDO bias current trimming circuit cooperate to provide a voltage and a preset bias current for the VCO loop oscillation unit, and the VCO loop oscillation unit generates an oscillation clock signal according to the voltage and the preset bias current. By the cooperation of the LDO power supply circuit and the LDO bias current trimming circuit to provide a voltage and a preset bias current for the VCO loop oscillation unit to trim the loop oscillator, the decoder module generates different bias currents. The decoder module uses 0 to 255 encoding programmable configuration to select and enable corresponding 256 different bias current relationships, and can trim 256 bias currents according to needs to achieve a bias current that meets the starting frequency of the VCO loop oscillation unit, eliminating the non-linear effects brought by power supply noise and modulation effects. Description of the Drawings

[0014] Figure 1 It is a schematic diagram of an adjustable-frequency loop oscillator according to an embodiment of the present invention;

[0015] Figure 2 It is a schematic diagram of the main body module of the adjustable-frequency loop oscillator according to an embodiment of the present invention;

[0016] Figure 3 It is a schematic diagram of the overall circuit of the adjustable-frequency loop oscillator according to an embodiment of the present invention. Detailed Embodiments

[0017] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0018] The terms "first", "second", and "third" in this application are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0019] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0020] Figures 1 - 3 This application provides a frequency-adjustable loop oscillator, which includes: an LDO unit and a VCO loop oscillation unit. The LDO unit includes an LDO power supply circuit and an LDO bias current trimming circuit. The LDO power supply circuit and the LDO bias current trimming circuit cooperate to provide voltage and a preset bias current for the VCO loop oscillation unit. The VCO loop oscillation unit generates an oscillation clock signal according to the voltage and the preset bias current. The LDO power supply circuit and the LDO bias current trimming circuit are respectively used to supply voltage and provide a preset bias current for the VCO loop oscillation unit, so that the VCO loop oscillation unit has a good power supply noise suppression ratio. Further, the programmable MOS transistor array of the LDO bias current trimming circuit can be programmed to trim the starting frequency of the VCO loop oscillation unit, overcoming the nonlinear influence brought by the short-channel effect in the MOS transistor process.

[0021] Furthermore, the operational amplifier AMP1 in the LDO power supply circuit copies the VREF1 buffer voltage to the resistor divider network for voltage division via the series resistor R0 and the ground resistor R1. The VREF1 buffer voltage is then divided by the operational amplifier AMP2 and the ground resistor R2 to obtain a target voltage for powering the VCO loop oscillation unit. The operational amplifiers at the two stages of AMP1 and AMP2 have the function of amplifying voltage. A clean voltage source is obtained through layer-by-layer voltage division via the series resistor and the ground resistor to provide power for the VCO loop oscillation unit. The VCO loop oscillation unit is powered after the original power supply noise is eliminated.

[0022] Further specifically, the LDO bias current trimming circuit includes an LDO of an operational amplifier AMP3, wherein the operational amplifier AMP3 first drives the connected PMOS tube PM1 with the VREF2 buffer voltage output, and then copies the current to the PMOS tube PM0 connected to the PMOS tube PM1 in the form of a current mirror, the leakage current of the PMOS tube PM0 provides a bias current for the VCO loop oscillation unit, the leakage end of the PMOS tube PM1 is connected to the grounding resistor R3 and the positive electrode of the operational amplifier AMP3, the leakage current of the PMOS tube PM0 provides a bias current for the VCO loop oscillation unit, the operational amplifier AMP3 first drives the connected PMOS tube PM1 with the VREF2 buffer voltage output, and then copies the current of the PMOS tube PM1 to the connected PMOS tube PM0 in the form of a current mirror, so that the bias current from the LDO bias current trimming circuit can be fully accepted, and the programmable MOS tube array of the LDO bias current trimming circuit can realize programming to trim the bias current of the starting frequency of the VCO loop oscillation unit, thereby restraining the nonlinear influence caused by the short channel effect of the MOS tube under the existing process.

[0023] Please refer to Figure 3 Further, the LDO bias current trimming circuit also includes an LDO buffer circuit, wherein the LDO buffer circuit drives the PMOS tube PM5 with the output voltage to convert the voltage into current, and the current at the drain end of the PMOS tube PM5 is connected to the connected PMOS tube NM2 in a diode connection manner to be converted into voltage, and then outputted to the gate ends of the two parallel P / N MOS tube arrays of the connected PMOS tube PM6 array and the PMOS tube NM3 array in a current mirror manner through the PMOS tube PM5 and the PMOS tube NM2, and the programming is realized by using the PMOS tube PM6 array and the PMOS tube NM3 array to trim the bias current of the starting frequency of the VCO loop oscillation unit.

[0024] Further, the LDO buffer circuit further includes that the gate terminals of PMOS transistor PM5 and PMOS transistor PM4 are connected, the drain terminal of PMOS transistor PM4 is connected to the ground resistor R4, the drain terminal of PMOS transistor PM4 is serially connected to the gate terminal of PMOS transistor NM0, the drain terminals of PMOS transistor NM0 and PMOS transistor NM1 are connected in parallel to the source terminal of PMOS transistor NM4, and the drain terminal of PMOS transistor NM4 is connected in parallel to the drain terminals of PMOS transistor NM2 and the PMOS transistor NM3 array, thereby constructing an LDO buffer circuit that provides a buffer voltage for the PMOS transistor PM6 array and the PMOS transistor NM3 array to generate a bias current through programming. The programmable MOS transistor array of the LDO bias current trimming circuit can realize programming to trim the bias current of the starting frequency of the VCO loop oscillation unit, and overcome the non-linear influence brought by the short-channel effect of MOS transistors under the existing process.

[0025] Further, the LDO buffer circuit further includes that the gate terminals of PMOS transistor PM2 and PMOS transistor PM3 are connected, the source terminals of PMOS transistor NM0 and PMOS transistor PM2 are connected, an interconnection line is provided on the connection line of the gate terminals of PMOS transistor PM2 and PMOS transistor PM3 and is connected to the source terminals of PMOS transistor NM0 and PMOS transistor PM2, and the source terminals of PMOS transistor PM3 and PMOS transistor NM1 are connected in parallel to the gate terminal of PMOS transistor PM4, thereby realizing the buffering function of the LDO buffer circuit to provide a buffer voltage for the PMOS transistor PM6 array and the PMOS transistor NM3 array through programming. The programmable MOS transistor array of the LDO bias current trimming circuit can realize programming to trim the bias current of the starting frequency of the VCO loop oscillation unit, and overcome the non-linear influence brought by the short-channel effect of MOS transistors under the existing process.

[0026] Further specifically, the current-carrying ends of the P / N MOS transistor array are connected in parallel between the drain terminal of PMOS transistor PM1 and the ground resistor R3, thereby guiding the trimmed bias current to PMOS transistor PM1. The ground resistor R3 plays a voltage-dividing role, and a clean voltage source is obtained through series voltage division of the ground resistor R3 to supply power to the VCO loop oscillation unit, and the VCO loop oscillation unit is powered after eliminating the original power supply noise.

[0027] Further specifically, the LDO buffer circuit further includes a decoder module. The decoder module is used to select the path of the P / N MOS transistor array switch P / NMOS. The decoder module is programmable and configured for selection using 0 to 255 encoding. The PMOS transistor PM6 array and the PMOS transistor NM3 array are selected by the decoder module to generate different bias currents. The decoder module is programmable and configured for selection using 0 to 255 encoding corresponding to 256 different bias current relationships, and the 256 bias currents can be trimmed according to needs to achieve the bias current that meets the starting frequency of the VCO loop oscillation unit.

[0028] More specifically, please refer to Figure 3 The decoder module can programmably gate the P / N MOS transistor array to adjust the node current and the current flow direction. Figure 3 In Figure 3 , the D terminals of the respective P / N array transistors of the PMOS transistor PM6 array and the PMOS transistor NM3 array are the A and B nodes. The D terminal is the current-carrying terminal, and they are jointly shorted to the X node. When the decoder module encodes and gates the N array transistors, the B node will draw current from the drain terminal of PM1, thereby reducing the voltage of the X node. The drain current copied to the drain terminal of the PMOS transistor PM0 will also decrease, thereby reducing the oscillation frequency of the VCO loop oscillation unit. When the P array transistors are encoded and gated, the A node will inject current into the X node, thereby increasing the voltage of the X node. The drain current copied to the drain terminal of the PMOS transistor PM0 will also increase, thereby increasing the VCO oscillation frequency. The step values for the decoder module to decrease and increase can be customized by the engineer according to specific requirements by specifying how many P / N array transistors are turned on for each coding value of the respective P / N array transistors.

[0029] The beneficial effects of this application are as follows: An adjustable-frequency loop oscillator of this application includes an LDO unit and a VCO loop oscillation unit. The LDO unit includes an LDO power supply circuit and an LDO bias current trimming circuit. The LDO power supply circuit and the LDO bias current trimming circuit cooperate to provide voltage and a preset bias current for the VCO loop oscillation unit. The VCO loop oscillation unit generates an oscillation clock signal based on the voltage and the preset bias current. By the cooperation of the LDO power supply circuit and the LDO bias current trimming circuit to provide voltage and a preset bias current for the VCO loop oscillation unit for trimming the loop oscillator, the power supply circuit and the LDO bias current trimming circuit are respectively used to cooperate to provide voltage and a preset bias current for the VCO loop oscillation unit, which has a good power supply rejection ratio; the decoder module generates different bias currents. The decoder module uses 0 to 255 encoding for programmable configuration to gate 256 different bias current relationships. The bias current can be trimmed according to needs to reach the bias current that meets the starting frequency of the VCO loop oscillation unit. The programmable MOS transistor array can realize programming to trim the starting frequency of the VCO loop oscillation unit, overcoming the non-linear influence brought by the short-channel effect under the MOS transistor process.

[0030] In several embodiments provided in the present application, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0031] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units. The above is only the implementation mode of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A frequency-adjustable ring oscillator, comprising an LDO unit and a VCO ring oscillation unit, wherein the LDO unit comprises an LDO power supply circuit and an LDO bias current adjustment circuit, wherein the LDO power supply circuit and the LDO bias current adjustment circuit cooperate to provide a voltage and a preset bias current for the VCO ring oscillation unit, wherein the VCO ring oscillation unit generates an oscillation clock signal according to the voltage and the preset bias current, and wherein the LDO power supply circuit comprises an operational amplifier; The LDO bias current adjustment circuit includes an LDO of an operational amplifier AMP3, in, The operational amplifier AMP3 first drives the connected PMOS tube PM1 with the VREF2 buffer voltage output, and then copies the current to the PMOS tube PM0 connected to the PMOS tube PM1 in the form of a current mirror. The leakage current of the PMOS tube PM0 provides a bias current for the VCO loop oscillation unit. The leakage end of the PMOS tube PM1 is connected to the ground resistor R3 and the positive electrode of the operational amplifier AMP3. The LDO bias current trimming circuit also includes an LDO buffer circuit, which drives the PMOS tube PM5 with the output voltage to convert the voltage into current, and converts the current at the drain end of the PMOS tube PM5 into voltage through the connected PMOS tube NM2 in a diode connection manner, and then outputs it to the gate ends of two parallel P / N MOS tube arrays, namely, the connected PMOS tube PM6 array and the PMOS tube NM3 array, in a current mirror manner through the PMOS tube PM5 and the PMOS tube NM2.

2. The frequency-adjustable ring oscillator according to claim 1, It is characterized in that The operational amplifier AMP1 in the LDO power supply circuit copies the VREF1 buffer voltage to the resistor divider network and divides it through the series resistor R0 and the ground resistor R1. The VREF1 buffer voltage is then divided by the operational amplifier AMP2 and the ground resistor R2 to obtain the target voltage to power the VCO loop oscillation unit.

3. The frequency-adjustable ring oscillator according to claim 1, It is characterized in that The LDO buffer circuit also includes a gate end of a PMOS tube PM5 connected to a gate end of a PMOS tube PM4, a drain end of the PMOS tube PM4 connected to a grounding resistor R4, a drain end of the PMOS tube PM4 connected in series to a gate end of a PMOS tube NM0, drain ends of the PMOS tube NM0 and the PMOS tube NM1 connected in parallel to a source of the PMOS tube NM4, and a drain end of the PMOS tube NM4 connected in parallel to drain ends of an array of PMOS tubes NM2 and NM3.

4. The frequency-adjustable ring oscillator according to claim 3, It is characterized in that The LDO buffer circuit also includes a PMOS tube PM2 connected to the gate end of the PMOS tube PM3, a PMOS tube NM0 connected to the source of the PMOS tube PM2, an interconnection line is provided on the gate end connection line of the PMOS tube PM2 and the PMOS tube PM3 to connect to the source of the PMOS tube NM0 and the PMOS tube PM2, and the source of the PMOS tube PM3 and the PMOS tube NM1 are connected in parallel to the gate end of the PMOS tube PM4.

5. The frequency-adjustable ring oscillator according to claim 1, It is characterized in that the current-carrying end of the P / N MOS transistor array is connected in parallel between the leakage end of the PMOS transistor PM1 and the grounding resistor R3.

6. The frequency-tunable loop oscillator according to claim 5, It is characterized in that the LDO buffer circuit further includes a decoder module, and the decoder module is used to select the path of the P / N MOS transistor array switch P / NMOS.

7. The frequency-tunable loop oscillator according to claim 6, It is characterized in that the decoder module is programmed with 0 to 255 encoding for selectable configuration.

8. The frequency-tunable loop oscillator according to claim 7, It is characterized in that the decoder module can be programmed to select the P / N MOS transistor array, thereby adjusting the node current and the current flow direction.

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