LDMOS with enhanced safe operating area and method of manufacturing the same

Abstract

The present disclosure relates to LDMOS with enhanced safe operating area and methods of manufacturing the same. An integrated circuit, comprising: an n-type drift region; a gate structure directly on a first portion of the n-type drift region; a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure separated by a length of the drift region; a resistive protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure; a field plate contact providing a direct electrical connection to the resistive protective oxide.

Description

Technical Field

[0001] This disclosure relates to an LDMOS having an enhanced safe operating region and a method for manufacturing the same. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are planar double-diffused MOSFETs (metal-oxide-semiconductor field-effect transistors) commonly used in amplifiers, including microwave power amplifiers, RF (radio frequency) power amplifiers, and audio power amplifiers. The fabrication of LDMOS devices typically involves a series of ion implantation processes and annealing cycles to produce a doping profile sufficient to withstand the electric fields generated within the LDMOS device during operation.

[0003] RF LDMOS (Radio Frequency LDMOS) devices are widely used in high-voltage, high-power RF power amplifier applications ranging from 1MHz to over 3.5GHz, and are an important RF power device technology for expanding and maintaining cellular infrastructure. RF LDMOS devices are widely used power amplifiers in mobile networks (e.g., 4G and 5G cellular networks) and typically offer a desirable combination of high output power and corresponding drain-source breakdown voltages exceeding 60V to allow their use in high-voltage applications. Summary of the Invention

[0004] According to one embodiment of this disclosure, an integrated circuit is provided, comprising: an n-type drift region; a gate structure on a first portion of the n-type drift region; a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being spaced apart by a drift region length (Lds); a resist protective oxide (RPO) situated above the n-type drift region between the gate structure and the drain structure; and a field plate contact directly electrically connected to the resist protective oxide, the field plate contact being configured to apply a voltage to the resist protective oxide.

[0005] According to another embodiment of this disclosure, a method of manufacturing an integrated circuit is provided, comprising: implanting a deep P-well in a P-type substrate; implanting an n-type drift region in the deep P-well; depositing a gate structure on a first portion of the n-type drift region; implanting a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being spaced apart by a drift region length (Lds); depositing a resist protective oxide (RPO) on a third portion of the n-type drift region between the gate structure and the drain structure; etching field plate contact openings to expose surface portions of the resist protective oxide; and depositing field plate contacts in the field plate contact openings to provide direct electrical connections to the resist protective oxide.

[0006] According to another embodiment of this disclosure, a method for improving high-voltage performance in an LDMOS integrated circuit is provided, comprising: depositing an insulating field plate over a portion disposed in an n-type drift region between a gate structure and a drain structure; and applying a field plate voltage to the field plate during device operation. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cross-sectional view of an LDMOS device structure according to some embodiments.

[0009] Figures 2A to 2E This is a cross-sectional view during the fabrication of an LDMOS device structure according to some embodiments.

[0010] Figures 3A to 3B This is a graph of comparative electron density data for an LDMOS structure based on some embodiments.

[0011] Figures 4A to 4C This is a graph of comparative parameter data for an LDMOS structure based on some embodiments.

[0012] Figures 5A to 5G It is based on Figure 2E The graphs show the analog parameter data for various LDMOS structures from some embodiments of the LDMOS device.

[0013] Figure 6 This is a flowchart of a method for manufacturing an LDMOS device according to some embodiments.

[0014] Figure 7 This is a schematic diagram of a system for manufacturing LDMOS devices according to some embodiments.

[0015] Figure 8 It is a flowchart of IC device design, manufacturing, and programming. Detailed Implementation

[0016] This description, intended to be read in conjunction with the accompanying drawings, is considered an integral part of the entire written description. The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. The drawings are not drawn to scale, and the relative dimensions and positions of the structures have been modified for clarity rather than dimensional accuracy. To simplify this disclosure, specific examples of components, values, operations, materials, arrangements, etc., are described below.

[0017] Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features so that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, spatially related terms (such as "below," "under," "below," "above," "upper," "vertical," "horizontal," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). Spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. Devices and structures may be oriented in other ways (e.g., rotated 90 degrees, 180 degrees, or mirrored about a horizontal or vertical axis), and the spatially related descriptors used herein may be interpreted accordingly.

[0019] The structures and methods detailed below typically relate to the structures, design, and fabrication methods for LDMOS devices, including high-voltage LDMOS devices. These structures and methods can produce improved LDMOS output characteristics, such as on-state Id-Vd tailing, which are associated with a higher drain-side electric field, in order to achieve an appropriate combination of improved breakdown voltage (BVoff), resistance spread (Rsp), and safe operating area (SOA) performance in the off-state. Previous efforts have included, for example, adding additional well injections to the drain side to suppress high electric fields and achieve improved Id-Vd tailing; however, well injections with small tilt, high dose, and high energy tend to reduce BVoff, and often increase handling, manufacturing costs, and defect risks due to the addition of additional injection mask layers to an already complex fabrication process.

[0020] Figure 1 This is a cross-sectional view of a finished LDMOS structure 100 according to some embodiments. According to some embodiments, the LDMOS structure 100 includes: a P-type substrate (P substrate) 102, a field oxide (FOX) region 124 for defining an active region, a deep P-well (DPW) 104 formed in the P-type substrate 102, a high-voltage P-type implantation (HVPB) region 108 in the DPW, an N-type drift region doped (NDD) region 110 in the DPW adjacent to the HVPB region, a masked N-well (SHN) region 112 in the DPW adjacent to the NDD region, and a masked P-well (SHP) region 114 in the P substrate.

[0021] According to some embodiments, the LDMOS structure 100 further includes a P-type source contact region 116 and an N-type source contact region 118 in the HVPB, an N+ drain contact region 120 in the SHN, and a P+P substrate contact region 122 in the SHP. According to some embodiments, the LDMOS structure 100 also includes a gate oxide (Gox) 126 and a gate conductor (POLY) 128 disposed over adjacent portions of the HVPB and NDD regions, collectively referred to as a gate stack 129. According to some embodiments, the gate stack 129 will include sidewall structures (not shown) and / or portions of the original polysilicon gate conductor that have undergone silicide or self-aligned silicide processes to reduce the resistivity of the gate conductor.

[0022] In some embodiments, portions of the gate stack and NDD regions are protected during manufacturing by a resist-protected oxide (RPO) layer 125 comprising alternating layers of silicon dioxide (SiO2) and silicon nitride (Si3N4) arranged in a layered configuration, such as oxide / nitride (ON) or oxide / nitride / oxide / nitride (ONON). In some embodiments, an interlayer dielectric (ILD) (140) is then deposited, patterned, and etched to form a series of contact holes that expose portions of the top surfaces of the P+ / N+ source contact regions 116, 118, the gate stack 129, the N+ drain contact 120, and the P+P substrate contact 122. In some embodiments, an initial metal layer (MO) (not shown) is then deposited on the ILD to fill the contact openings, and after chemical mechanical planarization (CMP), source contacts 130, gate contacts 132, drain contacts 134, and P-substrate contacts 136 are formed, which will provide electrical contact with subsequent metal layers. In some embodiments, configurations of various structures including the LDMOS structure 100 will generate a stronger electric field in operation in the high-field region 138 adjacent to the SHN region 112 and the P-substrate region 102 and / or the DPW region 104.

[0023] Figure 2A This is a cross-sectional view of an intermediate structure during the fabrication process of an LDMOS structure 200 according to some embodiments. The LDMOS structure 200 includes: a P-type substrate (P substrate) 202, a field oxide (FOX) region 224 for defining an active region, a deep P-well (DPW) 204 formed in the P-type substrate 202, a high-voltage P-type implantation (HVPB) region 208 in the DPW, an N-type drift-doped (NDD) region 210 adjacent to the HVPB region in the DPW, and an SHP region 214 in the P substrate.

[0024] Figure 2BThis is a cross-sectional view of another intermediate structure during the fabrication process of the LDMOS structure 200 according to some embodiments, which also includes the formation of P-type source contact regions 216 and N-type source contact regions 218 in the HVPB, an N+ drain contact region 220 adjacent to the field oxide region 224 in the NDD, and a P+P substrate contact region 222 in the SHP. According to some embodiments, the LDMOS structure 200 also includes the formation of gate oxide (Gox) 226 and gate conductor (POLY) 228 (collectively referred to as gate stack 229) disposed over adjacent portions of the HVPB and NDD regions. According to some embodiments, the gate stack 229 will include sidewall structures (not shown) and / or portions of the original polysilicon gate conductor that have undergone silicide or self-aligned silicide processes to reduce the resistivity of the gate conductor. In some embodiments, during manufacturing, portions of the gate stack and NDD region are protected by a resist-protected oxide (RPO) layer 225 comprising alternating layers of silicon dioxide (SiO2) and silicon nitride (Si3N4) arranged, for example, in a two-layer oxide / nitride (ON) layer configuration or a four-layer oxide / nitride / oxide / nitride (ONON) layer configuration.

[0025] Figure 2C This is a cross-sectional view of another intermediate structure during the fabrication process of the LDMOS structure 200, in which an interlayer dielectric layer 240 is then deposited, patterned, and etched to form a series of contact holes 242 that expose the top surface of the P+ / N+ source contact regions 216, 218, the gate stack 229, the N+ drain contact 220, the P+P substrate contact 222, and the RPO layer 226.

[0026] Figure 2D This is a cross-sectional view of another intermediate structure during the fabrication of the LDMOS structure 200, wherein an initial metal layer (M0) (not shown) is deposited on the ILD to fill the contact openings, and after chemical mechanical planarization (CMP), source contact 230, gate contact 232, drain contact 234, P-substrate contact 236, and field plate contact 244 are formed, with the field plate contact closer to the drain contact (compared to the gate contact). These contacts will provide electrical contact with subsequent metal layers (e.g., metal 1 (M1) layer).

[0027] Figure 2EThis is a cross-sectional view of another intermediate structure during the fabrication of the LDMOS structure 200, wherein a second interlayer dielectric layer 248 is deposited on the contacts. In some embodiments, the second ILD 248 is etched to expose the top surface of specific contacts, including, for example, drain contact 234 and field plate contact (CFP) 244, and portions of the second ILD layer between the exposed contacts are removed. A metal layer (M1) (not shown) is then deposited on the second ILD to fill the openings(s) between the exposed contacts, and after chemical mechanical planarization (CMP), a metal pattern 246 is formed that establishes an electrical connection between the drain contact 234 and the field plate contact 244. The metal pattern 246 ensures that the same drain voltage (Vd or Vdd) is applied simultaneously to both the drain contact and the field plate contact. Additional operations, including depositing ILD layers, contact / via patterning, contact / via etching, metal deposition, metal patterning, and metal etching and / or CMP, will be used to complete the integrated circuit (IC) device.

[0028] According to some embodiments, Figure 1 and Figure 2E Some structural elements shown in the structure are configured and doped according to a set of design rules associated with the manufacturing process used to create and manufacture LDMOS devices. Some embodiments of LDMOS devices include regions of size and doping defined within specific ranges, which include, for example, in some embodiments, an initial P-substrate doping concentration of 10. 14 -10 15 / cm 3 The doping concentration of DPW was set to 10. 15 -10 17 / cm 3 The doping concentration of the NDD is 10 μm, and the depth is 2-3 μm. 16 -10 17 / cm 3 The HVPB doping concentration was set to 10 at a depth of 0.5-1.0 μm. 17 -10 18 / cm 3 The SHN doping concentration is 10 at a depth of 1.5-2.5 μm. 17 -10 18 / cm 3 The SHP doping concentration was set to 10 at a depth of 1-2 μm. 17 -10 18 / cm 3 The depth is 1-2 μm; the doping concentration of the N+ region is formed to be 10. 20 -10 21 / cm3 The depth is 0.2-0.3 μm; and the doping concentration of the P+ region is formed to be 10. 20 -10 21 / cm 3 The dimensions and doping values ​​provided are intended to guide those skilled in the art only and should not be construed as values ​​essential or necessary for fabricating functional integrated circuit devices according to some embodiments. In practice, those skilled in the art will be able to fabricate functional semiconductor devices in which one or more parameters fall outside the stated range without excessive experimentation.

[0029] According to some embodiments, in Figure 1 and Figure 2E Some structural elements shown in the structure are configured and deposited / grown according to a set of design rules associated with the manufacturing process used to create and manufacture LDMOS devices. Some embodiments of LDMOS devices include deposited regions and elements with dimensions falling within a specific range, which includes, for example, in some embodiments, a depth of 0.3-0.5 μm for the FOX and a thickness of [missing information - likely a missing element]. In some embodiments, the gate conductor (POLY) has a thickness of 0.2-0.3 μm, and cobalt (Co) and / or titanium (Ti) silicides are formed on the gate conductor; the total thickness of the RPO layers is 0.05-0.2 μm; wherein the O / N / O / N layer in the four RPO layers comprises 0.03-0.09 μm oxide / 0.01-0.03 μm nitride / 0.03-0.09 μm oxide / 0.01-0.03 μm nitride, and the O / N layer in the two RPO layers comprises 0.03-0.12 μm oxide / 0.02-0.08 μm nitride; and the ILD thickness is 0.5-1.5 μm. The thickness values ​​provided above are intended only to guide those skilled in the art and should not be construed as values ​​critically important or necessary for manufacturing functional integrated circuit devices according to some embodiments. In practice, those skilled in the art will be able to manufacture functional semiconductor devices where one or more parameters fall outside the stated ranges without excessive experimentation.

[0030] Figure 3A It comes from using device simulation software to generally correspond to Figure 2E The simulated electron density curves were prepared based on the IC device structure. Figure 3B It comes from using device simulation software to generally correspond to Figure 1 The simulated electron density curve was prepared based on the IC device structure, which lacks [a specific feature / structure]. Figure 2E The field plate contact structure 244 was discovered. (Comparison) Figure 3A and Figure 3BThe graphs presented show that a reduction in electron density is achieved in the portion of NDD region 338 near the drain contact, which tends to improve the high-voltage (HV) performance of the IC device, especially relative to BVoff performance. Device simulation software includes, for example, Sentaurus Device, multi-dimensional (1D / 2D / 3D) device simulators, or Taurus Medici, two-dimensional device simulators; both simulators can be used to model the electrical, thermal, and / or optical characteristics of various semiconductor devices.

[0031] Figure 4A This shows the results from using device simulation software, which generally corresponds to... Figure 2E The IC device structure (wf1md - blue) and its overall correspondence Figure 1 IC device structure (wf2md-red) (This IC device structure lacks in) Figure 2E The relative electron density curve was prepared based on the field plate contact structure 244 found in the simulation. (Comparison) Figure 4A The lines drawn on the graph show the overall correspondence to... Figure 2E Higher electron density is achieved in the IC structure.

[0032] Figure 4B This shows the results from using device simulation software, which generally corresponds to... Figure 2E The IC device structure (wf1md - blue) and its overall correspondence Figure 1 IC device structure (wf2md-red) (This IC device structure lacks in) Figure 2E The relative electric field strength curves were prepared based on the field plate contact structure 244 found in the simulation. (Comparison) Figure 4B The lines drawn on the graph show the overall correspondence to... Figure 2E A lower electric field strength is achieved in the IC structure.

[0033] Figure 4C This shows the results from using device simulation software, which generally corresponds to... Figure 2E The IC device structure (wf1md - blue) and its overall correspondence Figure 1 IC device structure (wf2md-red) (This IC device structure lacks in) Figure 2E The simulation results show the functional relationship between relative drain current and drain voltage (based on the field plate contact structure discovered in the study). Comparison Figure 4C The line plotted on the graph shows the overall performance for operating voltages above 14V. Figure 2E A lower drain current amplitude is achieved in the IC structure. For an operating voltage of approximately 20V, the Id-Vd tail is improved by approximately 10%.

[0034] Figure 5A It comes from using device simulation software (also known as technical computer-aided design (TCAD)) to generally correspond to Figure 2E The simulated electron density plot was prepared for the IC device structure, which has certain relevant dimensions marked, including: D1, the distance from the field plate contact (CFP) to the gate polysilicon; D2, the distance from the field plate contact to the silicon surface (i.e., the remaining thickness of the RPO structure after contact etching); D3, the width of the field plate contact (CFP); and Lds, the length of the drift region between the gate and drain structures. Figures 5B-5G It shows Figure 5A The various relationships between device performance and dimensional elements (specifically, dimensions Lds, D1, D2, and D3) shown are described in detail below.

[0035] Figure 5B This is a graph showing the functional relationship between the saturated drain current (Idsat) ratio and the D1 / Lds ratio. For example... Figure 5B As shown, the Idsat current decreases as the D1 / Lds ratio decreases, until it reaches a ratio of approximately 0.45, after which the Idsat value remains relatively constant. Therefore, D1 / Lds ratios between approximately 0.35 and 0.7 maintain the Idsat ratio within the range of approximately 0.92 and 0.96. Figure 5B As shown, the Idsat ratio is sensitive to the positioning of the field plate contact 244 relative to the gate structure 226 / 228 and the drain structure 220. Specifically, if the field plate contact 244 is positioned too close to the gate structure 226 / 228, i.e., the D1 / Lds ratio is less than about 0.35, the Idsat ratio will exceed the target value of 0.96. Therefore, ensuring that the field plate contact 244 is positioned to provide sufficient spacing between the field plate contact 244 and the gate structure 226 / 228 will tend to improve the performance of the resulting semiconductor device.

[0036] Overall corresponding to Figure 2E Furthermore, TCAD simulations using LDMOS structures with various D1 / Lds ratios show that... Figure 4C The improved Id-Vd tail reflected in the NDD 210 can be attributed to the increased electron concentration near the drain side, which acts as a buffer for the depletion region of the on-state adjacent to the drain-side N+ contact 220, and thus reduces the drain-side electric field. This reduced electric field, in turn, suppresses impact ionization and impact ionization current near the drain side of the NDD 210, thereby improving the Id-Vd tail performance.

[0037] The D1 / Lds ratio is crucial for achieving a significant improvement in the Id-Vd tail performance of LDMOS devices according to some embodiments, especially those operating at voltages exceeding 14V. The lower limit of the D1 / Lds ratio will depend on the target maximum Idsat ratio value associated with a particular design, but for the overall... Figure 2E For LDMOS device designs aiming for a maximum Idsat ratio of 0.96, the D1 / Lds ratio should be no less than 0.35, and preferably at least 0.40. The upper limit of the D1 / Lds ratio will depend on the design rules applicable to the specific manufacturing process used to manufacture the semiconductor device, but it should be at least 0.7. If the D1 / Lds ratio is too low, the variability of the Idsat ratio will increase and tend to exceed the predetermined target value. Conversely, if the D1 / Lds ratio is too high, the placement of the field plate contacts 244 will be more likely to violate the minimum contact-to-contact pitch requirements of the applicable manufacturing process design rules.

[0038] Figure 5C This is a graph showing the relationship between the saturated drain current (Idsat) ratio and D2. For example... Figure 5C As shown, the Idsat current increases with the increase of the length of D2 (RPO thickness). A D2 value between approximately 0.05 and 0.2 μm maintains the Idsat ratio within the range of approximately 0.92 to 0.96. If the D2 value is too low, the Idsat ratio will drop below the lower target value of 0.92. If the D2 value is too high, the Idsat ratio will drop above the upper target value of 0.96.

[0039] Figure 5D This is a graph showing the functional relationship between the saturated drain current (Idsat) ratio and the D3 / Lds ratio. For example... Figure 5D As shown, for a range of D3 / Lds ratios, the Idsat current ratio is relatively constant (0.94–0.96). A D3 / Lds ratio in the range of approximately 0.07 to 0.37 keeps the Idsat ratio in the range of approximately 0.94 to 0.96. If the D3 / Lds ratio is too low, the field plate contact 244 will be difficult to pattern and etch consistently. If the D3 / Lds ratio is too high, the effect of the field plate contact 244 will not be concentrated on the portion of the NDD region 338 used to reduce the electric field to improve the HV performance of the device.

[0040] Figure 5E It is a graph showing the functional relationship between the decrease in breakdown voltage turn-off (BVoff) and the D1 / Lds ratio. For example... Figure 5EAs shown, the reduction in BVoff is improved as the field plate contacts move away from the gate structure and toward the drain structure. D1 / Lds values ​​between 0.4 and 0.7 keep the Idsat ratio in the range of approximately 0.92 to 0.96, while D1 / Lds values ​​below approximately 0.35 show an Idsat ratio greater than 0.96.

[0041] Figure 5F This is a graph showing the functional relationship between the breakdown voltage turn-off (BVoff) and D2. For example... Figure 5F As shown, the reduction in BVoff is generally insensitive to the thickness of the RPO structure.

[0042] Figure 5G This is a graph showing the functional relationship between the reduction in breakdown voltage turn-off (BVoff) and the ratio of D3 / Lds. For example... Figure 5G As shown, the decrease in BVoff slows down as the D3 / Lds ratio increases. Therefore, the D3 / Lds ratio will generally remain in the range of 0.1 to 0.3.

[0043] Figure 6 It is manufactured according to the corresponding Figure 2E A flowchart of a method 600 for an LDMOS device according to some embodiments is provided, which includes a series of successive operations, including step 602, during which an active region is defined on a P-type substrate 202, and a field oxide (FOX) region 224 is formed to isolate the active region. According to some embodiments, a deep P-well (DPW) 204 is then formed in the P-type substrate 202.

[0044] According to some embodiments of method 600, during operation 604, a high-voltage P-type implantation (HVPB) region 208 is formed in the DPW, an N-type drift-doped (NDD) region 210 adjacent to the HVPB region is formed in the DPW, and an SHP region 214 is formed in the P substrate 202, the SHP region being separated from the NDD region 210 by a FOX.

[0045] According to some embodiments of method 600, operation 606 includes forming a gate stack 229 comprising a layer of gate oxide 226 on adjacent surfaces of the HVPB and NDD regions and a polysilicon layer on the gate oxide 226 serving as a gate conductor 228. According to some embodiments, a portion of the gate conductor is used to form a silicide with cobalt (Co), titanium (Ti), or (one or more) other suitable metals and suitable alloys and mixtures thereof, thereby reducing the resistance of the gate conductor 228. In some embodiments, a gate sidewall structure (not shown) is formed adjacent to the gate stack 229.

[0046] According to some embodiments of method 600, operation 608 includes forming a P-type source contact region 216 and an N-type source contact region 218 in the HVPB, an N+ drain contact region 220 adjacent to the field oxide region 224 in the NDD, and a P+P substrate contact region 222 in the SHP. In some embodiments, operation 608 includes forming a resist protective oxide (RPO) layer 225 comprising alternating layers of silicon dioxide (SiO2) and silicon nitride (Si3N4) arranged, for example, in a two-layer oxide / nitride (ON) layer configuration or a four-layer oxide / nitride / oxide / nitride (ONON) layer configuration. Although ON and ONON configurations have been successfully utilized in the fabrication of semiconductor devices, those skilled in the art will be able to form the RPO 225 structure using one or more other dielectric materials without excessive experimentation to fabricate functional semiconductor devices.

[0047] According to some embodiments of method 600, operation 610 includes forming an interlayer dielectric layer 240, and then patterning and etching the interlayer dielectric layer 240 to form a series of contact holes 242 that expose the P+ / N+ source contact regions 216, 218, gate stack 229, N+ drain contact 220, P+P substrate contact 222 and exposed portions of the top surface of the RPO layer 226.

[0048] According to some embodiments of method 600, operation 612 includes depositing an initial metal layer (MO) (not shown) on the patterned and etched ILD layer 240 to fill the contact openings, and after chemical mechanical planarization (CMP), forming source contact 230, gate contact 232, drain contact 234, P-substrate contact 236, and field plate contact 244, with the field plate contact closer to the drain contact than the gate contact. These contacts will provide electrical contact with subsequent metal layers (e.g., metal 1 (M1) layer). In some embodiments, configurations including various structures of LDMOS structure 200 will generate a stronger electric field (and thus exhibit a lower BVoff value) in operation in the high field region 138 of SHN region 112 adjacent to P-substrate region 102 and / or DPW region 104.

[0049] According to some embodiments of method 600, optional operation 614 includes forming a second interlayer dielectric layer 248 on the contacts. In some embodiments, the second ILD 248 is then patterned and etched to expose the top surface of specific contacts, including, for example, drain contact 234 and field plate contact 244, and the portion of the second ILD layer between the exposed contacts is removed. A metal layer (M1) (not shown) is then deposited on the second ILD 248 to fill the opening(s) between the exposed contacts, and after chemical mechanical planarization (CMP), a metal pattern 246 is formed that establishes an electrical connection between the drain contact 234 and the field plate contact 244. The metal pattern 246 ensures that the same drain voltage (Vd or Vdd) is applied simultaneously to both the drain contact 234 and the field plate contact 244.

[0050] According to some embodiments of method 600, optional operation 616 includes depositing an additional ILD layer, applying a contact / via pattern to the ILD layer, etching the contact / via pattern, depositing a metal layer, and using metal patterning and etching and / or CMP to remove portions of the metal layer to form additional interconnect patterns that will produce an IC device with designed functionality. According to some embodiments of method 600, optional operation 618 includes packaging the completed IC device in a format suitable for use in an electronic device. In embodiments of method 600, operations 612 and 614 form field plate contacts 244 and provide electrical connections between field plate contacts 244 and drain contacts 234. The formation of these structures allows drain voltage to be applied to field plate contacts 224 to achieve improved HV performance of the resulting IC device, for example, in Figure 3A and Figure 4C As shown in the image.

[0051] Figure 7 This is a block diagram of an electronic process control (EPC) system 700 according to some embodiments. According to some embodiments of such a system, for example using EPC system 700, methods for generating cell layout diagrams corresponding to some embodiments of the LDMOS structure detailed above can be implemented, particularly regarding methods for adding and placing field plate contacts on an RPO structure. In some embodiments, EPC system 700 is a general-purpose computing device including a hardware processor 702 and a non-transitory computer-readable storage medium 704. The computer-readable storage medium 704 is encoded, in particular, with computer program code (or instructions) 706 (i.e., an executable instruction set), i.e., storing the computer program code (or instructions) 706. Execution of the computer program code 706 by the hardware processor 702 (at least partially) represents an EPC tool that implements some or all of the methods described herein according to one or more (hereinafter referred to as processes and / or methods).

[0052] Hardware processor 702 is electrically coupled to computer-readable storage medium 704 via bus 718. Hardware processor 702 is also electrically coupled to I / O interface 712 via bus 718. Network interface 714 is also electrically connected to hardware processor 702 via bus 718. Network interface 714 is connected to network 716, enabling hardware processor 702 and computer-readable storage medium 704 to be connected to external components via network 716. Hardware processor 702 is configured to execute computer program code 706 encoded in computer-readable storage medium 704 so that EPC system 700 can be used to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, hardware processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0053] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 704 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD R / W), and / or digital video disc (DVD).

[0054] In one or more embodiments, computer-readable storage medium 704 stores computer program code 706 configured to enable EPC system 700 (where such execution (at least partially) represents an EPC tool) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 704 also stores information that facilitates the execution of some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 704 stores process control data 708, which in some embodiments includes control algorithms, process variables and constants, target ranges, setpoints, programmed control data, and code for enabling statistical process control (SPC) and / or various process controls based on model predictive control (MPC).

[0055] EPC system 700 includes an I / O interface 712. The I / O interface 712 is coupled to external circuitry. In one or more embodiments, the I / O interface 712 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to hardware processor 702.

[0056] EPC system 700 also includes a network interface 714 coupled to hardware processor 702. Network interface 714 allows EPC system 700 to communicate with network 716, which is connected to one or more other computer systems. Network interface 714 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE 1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EPC systems 700.

[0057] EPC system 700 is configured to receive information via I / O interface 712. The information received via I / O interface 712 includes one or more of instructions, data, programming data, and design rules specifying, for example, layer thickness, spacing, structure and layer resistivity, as well as feature dimensions, process performance history, target range, setpoint, and / or other parameters for processing by hardware processor 702. The information is transmitted to hardware processor 702 via bus 718. EPC system 700 is also configured to receive information related to the user interface (UI) via I / O interface 712. This information is stored as user interface (UI) 710 on computer-readable medium 704.

[0058] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EPC tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by the EPC system 700.

[0059] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, etc.

[0060] Figure 8This is a block diagram of an integrated circuit (IC) manufacturing system 800 according to some embodiments of an LDMOS device incorporating the field plate contact structure detailed above, and the associated IC manufacturing process. In some embodiments, based on the layout diagram, the manufacturing system 800 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0061] exist Figure 8 In this IC manufacturing system 800, entities such as design studio 820, mask room 830, and IC manufacturer / factory (“foundry”) 850 interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of IC device 860. The entities in the manufacturing system 800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet.

[0062] The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 820, mask room 830, and IC foundry 850 are owned by a single, larger company. In some embodiments, two or more of the design room 820, mask room 830, and IC foundry 850 coexist in a shared facility and use shared resources.

[0063] The design company (or design team) 820 generates an IC design layout diagram 822. The IC design layout diagram 822 includes various geometric patterns designed for the IC device 860. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 860 to be manufactured. These layers are combined to form various IC features.

[0064] For example, a portion of the IC design layout diagram 822 includes various IC features, such as active regions to be formed in a semiconductor substrate (e.g., a silicon wafer), gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads, as well as various material layers disposed on the semiconductor substrate. Design room 820 implements appropriate design processes to form the IC design layout diagram 822. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout diagram 822 is presented in one or more data files containing geometric pattern information. For example, the IC design layout diagram 822 may be represented in GDSII or DFII file format.

[0065] Although the pattern of a modified IC design layout is adjusted using appropriate methods to reduce, for example, the parasitic capacitance of the integrated circuit compared to an unmodified IC design layout, the modified IC design layout reflects the result of changing the position of the wires in the layout, and in some embodiments, features associated with capacitive isolation structures are inserted into the IC design layout to further reduce parasitic capacitance compared to an IC structure having a modified IC design layout (which does not have features for forming the capacitive isolation structures located therein).

[0066] Mask chamber 830 includes mask data preparation 832 and mask fabrication 844. Mask chamber 830 uses an IC design layout 822 to fabricate one or more masks 845 for fabricating various layers of an IC device 860 according to the IC design layout 822. Mask chamber 830 performs mask data preparation 832, in which the IC design layout 822 is converted into a representative data file (“RDF”). Mask data preparation 832 provides the RDF to mask fabrication 844. Mask fabrication 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (mask plate) 845 or a semiconductor wafer 853). The IC design layout 822 is manipulated by mask data preparation 832 to conform to the specific characteristics of the mask writer and / or the requirements of the IC foundry 850. Figure 8 In this design, mask data preparation 832 and mask manufacturing 844 are shown as separate elements. In some embodiments, mask data preparation 832 and mask manufacturing 844 may be collectively referred to as mask data preparation.

[0067] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout (Figure 822). In some embodiments, mask data preparation 832 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assistance, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0068] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks an IC design layout 822 that has undergone an OPC process, wherein the OPC process has a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 822 to compensate for constraints during mask fabrication 844, which can undo portions of the modifications performed by the OPC to satisfy the mask creation rules.

[0069] In some embodiments, mask data preparation 832 includes a Lithography Process Check (LPC) simulation, which is performed by an IC foundry 850 to simulate the process for manufacturing an IC device 860. The LPC simulates the process based on an IC design layout 822 to create a simulated fabricated device, such as IC device 860. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after creating a simulated fabricated device via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 822.

[0070] It should be understood that, for clarity, the above description of mask data preparation 832 has been simplified. In some embodiments, mask data preparation 832 includes additional features such as logic operations (LOPs) to modify the IC design layout 822 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 822 during mask data preparation 832 can be performed in various different sequences.

[0071] Following mask data preparation 832 and during mask fabrication 844, a mask 845 or a set of masks 845 is fabricated based on a modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more photolithographic exposures based on the IC design layout 822. In some embodiments, an electron beam (e-beam) or multiple e-beams mechanism is used to form a pattern on the mask (photomask or photomask plate) 845 based on the modified IC design layout 822. The mask 845 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 845. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (e.g., ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask.

[0072] In another example, a phase-shifting technique is used to form mask 845. In the phase-shifting mask (PSM) version of mask 845, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be a decaying PSM or an alternating PSM. The mask(s) generated by mask fabrication 844 are used in a variety of processes. For example, such a mask(s) is used in ion implantation processes to form various doped regions in semiconductor wafer 853, in etching processes to form various etched regions in semiconductor wafer 853, and / or in other suitable processes.

[0073] IC foundry 850 includes wafer fabrication 852. IC foundry 850 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC foundry 850 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end line-of-sale (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end line-of-sale (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility may provide other services for foundry operations.

[0074] Wafer fabrication 852 includes forming a patterned layer of mask material on a semiconductor substrate, wherein the semiconductor material is made of one or more layers of mask material comprising photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4, SiON, SiC, SiOC), or combinations thereof. In some embodiments, mask 845 comprises a single layer of mask material. In some embodiments, mask 845 comprises a multilayer of mask material.

[0075] In some embodiments, the mask material is patterned by exposing it to an illumination source. In some embodiments, the illumination source is an electron beam source. In some embodiments, the illumination source is a light-emitting lamp. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the illumination source emits combinations of different (ultraviolet, visible, and / or infrared) light.

[0076] Following the mask patterning operation, areas not covered by the mask are etched, such as fins in open areas of the pattern, to alter the dimensions of one or more structures within the exposed areas(s). In some embodiments, etching is performed using plasma etching or a liquid chemical etching solution, according to several examples. The chemical composition of the liquid chemical etching solution includes one or more etchants, such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F), potassium hydroxide (KOH), ethylenediamine catechol (EDP), TMAH (tetramethylammonium hydroxide), or combinations thereof.

[0077] In some embodiments, the etching process is a dry etching or plasma etching process. Plasma etching of the substrate material is performed using a halogen-containing reactive gas excited by an electromagnetic field to dissociate into ions. Reactive or etchant gases include, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or combinations thereof; however, other semiconductor etchant gases are contemplated within the scope of this disclosure. According to plasma etching methods known in the art, ions are accelerated to bombard the exposed material by means of an alternating electromagnetic field or a fixed bias voltage.

[0078] In some embodiments, the etching process includes exposing the exposed structure in one or more functional regions in an oxygen-containing atmosphere to oxidize the outer portion of the exposed structure, followed by a chemical trimming process, such as plasma etching or liquid chemical etching, as described above, to remove the oxidized material and leave a modified structure. In some embodiments, oxidation is followed by chemical trimming to provide greater dimensional selectivity for the exposed material and reduce the likelihood of accidental material removal during the manufacturing process. In some embodiments, the exposed structure may include the fin structure of a fin field-effect transistor (FinFET), wherein the fin is embedded in a dielectric support medium covering the sides of the fin. In some embodiments, the exposed portion of the fin in the functional region is the top surface and sides of the fin, which are located above the top surface of the dielectric support medium, wherein the top surface of the dielectric support medium is recessed below the level of the top surface of the fin, but still covers the lower portion of the sides of the fin.

[0079] IC foundry 850 uses one or more masks 845 manufactured by mask chamber 830 to manufacture IC device 860. Therefore, IC foundry 850 uses IC design layout 822 at least indirectly to manufacture IC device 860. In some embodiments, semiconductor wafer 853 is manufactured by IC foundry 850 using one or more masks 845 to form IC device 860. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based at least indirectly on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 853 also includes one or more of the following: various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0080] Discovered related to integrated circuit (IC) manufacturing systems (e.g., Figure 8 The manufacturing system 800) and details relating to the IC manufacturing process associated with the following: for example, U.S. Patent 9,256,709, granted February 9, 2016; U.S. Pre-Principal Grant Notice 20150278429, published October 1, 2015; U.S. Pre-Principal Grant Notice 20140040838, published February 6, 2014; and U.S. Patent 7,260,442, granted August 21, 2007, each of which is incorporated herein by reference in its entirety.

[0081] In some embodiments, wires are created within an integrated circuit by depositing a dielectric material layer on a layer of the integrated circuit having a gate structure therein, followed by forming an opening in the dielectric material at the location of at least one track. In some embodiments, a metal seed material is added to the exposed surface within the opening in the dielectric material, and a conductive material layer is added to the opening above the seed layer. In some embodiments, the conductive material layer is added by electroplating. In some embodiments, the conductive material layer is added, for example, by sputtering from a metal target. In some embodiments, the conductive material layer is added by chemical vapor deposition, which includes one or more of the following: chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the conductive material on top of the dielectric material layer is removed by chemical mechanical polishing (CMP) and / or plasma etching to isolate portions of the conductive material within the opening in the dielectric material layer.

[0082] In some embodiments, the conductors along the individual traces of the integrated circuit layout or the manufactured integrated circuit are separated from each other by removing the length of the conductor between two other conductors and filling the volume of the removed length of the conductor with a dielectric material (e.g., forming a trench isolation structure between the two conductors, wherein the trench isolation structure and the conductor each extend along a first direction). In some embodiments, portions of one or more adjacent conductors are isolated by etching through the conductors to form an insulating structure that extends in a second direction different from the direction in which the conductors extend through the layers of the integrated circuit.

[0083] An integrated circuit according to some embodiments includes: an n-type drift region; a gate structure on a first portion of the n-type drift region; a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being spaced apart by a drift region length (Lds); a resist protective oxide (RPO) situated above the n-type drift region between the gate structure and the drain structure; and a field plate contact directly electrically connected to the resist protective oxide, the field plate contact being configured to apply a voltage to the resist protective oxide. Other embodiments of the integrated circuit include a conductive structure that is directly electrically connected between a drain contact and a field plate contact, wherein the applied voltage will be the drain voltage, the field plate contact is spaced from the gate structure by a first distance (D1), wherein the first distance is at least 40% of Lds, the first distance being between 40% and 70% of Lds, the contact width (D3) of the field plate contact is between 10% and 30% of Lds, the field plate contact includes a first field plate contact having a first contact width and a second field plate contact having a second contact width, wherein the first contact width and the second contact width are at least 10% of Lds, the RPO thickness (D2) of the resist protective oxide is at least 10% of Lds, the RPO thickness (D2) of the resist protective oxide is between 0.05 μm and 0.2 μm, and / or Lds is at least 0.5 μm.

[0084] The manufacturing method according to some embodiments includes a series of sequential operations, including implanting a deep P-well in a P-type substrate, implanting an n-type drift region in the deep P-well, depositing a gate structure on a first portion of the n-type drift region, implanting a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being spaced apart by a drift region length (Lds), depositing a resist protective oxide (RPO) on a third portion of the n-type drift region between the gate structure and the drain structure, etching field plate contact openings to expose surface portions of the resist protective oxide, and depositing field plate contacts in the field plate contact openings to provide direct electrical connection to the resist protective oxide.

[0085] Other embodiments of the manufacturing method include additional or modified operations, including forming drain contacts for providing direct electrical connection to the drain structure, forming a metal jumper between field plate contacts and drain contacts, forming a resist protective oxide (RPO) over a portion of the gate structure, forming a sidewall structure adjacent to the gate structure, defining a plurality of active regions on a P-type substrate, forming a field oxide (FOX) structure between adjacent active regions, positioning the field plate contacts closer to the drain structure than to the gate structure, positioning the field plate contacts on the resist protective oxide (RPO) at a distance of 40% to 70% from the gate structure offset by Lds, positioning the field plate contacts at contact points on the resist protective oxide (RPO) at a distance of 40% to 70% from the gate structure offset by Lds, and / or forming a plurality of field plate contacts on the resist protective oxide (RPO), wherein the field plate contacts are offset by at least 40% from the gate structure offset by Lds.

[0086] A method for improving LDMOS performance according to some embodiments includes the following operations: depositing an insulating field plate over a portion disposed in an n-type drift region between a gate structure and a drain structure, and applying a field plate voltage to the field plate during device operation, applying a field plate voltage of at least 14V, and / or applying a field plate voltage equal to the drain voltage (Vdd) applied to the drain of the LDMOS integrated circuit during device operation.

[0087] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or realizing the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0088] Example 1 is an integrated circuit comprising: an n-type drift region; a gate structure on a first portion of the n-type drift region; a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being spaced apart by a drift region length (Lds); a resist protective oxide (RPO) situated above the n-type drift region between the gate structure and the drain structure; and a field plate contact directly electrically connected to the resist protective oxide, the field plate contact being configured to apply a voltage to the resist protective oxide.

[0089] Example 2 is the integrated circuit described in Example 1, further comprising: a conductive structure that is directly electrically connected between the drain contact and the field plate contact, wherein the applied voltage will be the drain voltage.

[0090] Example 3 is the integrated circuit described in Example 2, wherein: the field plate contact is separated from the gate structure by a first distance (D1), wherein the first distance is at least 35% of Lds.

[0091] Example 4 is the integrated circuit described in Example 3, wherein the first distance is between 40% and 70% of the Lds.

[0092] Example 5 is the integrated circuit described in Example 1, wherein: the field plate contact has a contact width (D3), and the contact width is between 10% and 30% of Lds.

[0093] Example 6 is the integrated circuit described in Example 1, wherein: the field plate contact includes a first field plate contact having a first contact width and a second field plate contact having a second contact width, the first contact width being at least 10% of the Lds, and the second contact width being at least 10% of the Lds.

[0094] Example 7 is the integrated circuit described in Example 1, wherein: the resist protective oxide has an RPO thickness (D2), and the RPO thickness is at least 10% of the Lds.

[0095] Example 8 is the integrated circuit described in Example 1, wherein: the resist protective oxide has an RPO thickness (D2); and the RPO thickness is between 0.05 μm and 0.2 μm.

[0096] Example 9 is the integrated circuit described in Example 1, wherein the Lds is at least 0.5 μm.

[0097] Example 10 is a method of manufacturing an integrated circuit, comprising: implanting a deep P-well in a P-type substrate; implanting an n-type drift region in the deep P-well; depositing a gate structure on a first portion of the n-type drift region; implanting a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being spaced apart by a drift region length (Lds); depositing a resist-protected oxide (RPO) on a third portion of the n-type drift region between the gate structure and the drain structure; etching field plate contact openings to expose surface portions of the resist-protected oxide; and depositing field plate contacts in the field plate contact openings to provide direct electrical connections to the resist-protected oxide.

[0098] Example 11 is a method of manufacturing an integrated circuit as described in Example 10, further comprising: forming a drain contact for providing a direct electrical connection to the drain structure; and forming a metal jumper between the field plate contact and the drain contact.

[0099] Example 12 is a method of manufacturing an integrated circuit as described in Example 10, further comprising: forming the resist protective oxide (RPO) over a portion of the gate structure.

[0100] Example 13 is a method of manufacturing an integrated circuit as described in Example 10, further comprising: forming a sidewall structure adjacent to the gate structure.

[0101] Example 14 is a method of manufacturing an integrated circuit as described in Example 10, further comprising: defining a plurality of active regions on the P-type substrate; forming a field oxide (FOX) structure between adjacent active regions; and positioning the field plate contacts closer to the drain structure than to the gate structure.

[0102] Example 15 is a method of manufacturing an integrated circuit as described in Example 10, further comprising: positioning the field plate contact on the resist protective oxide (RPO) at an offset of 40% to 70% from the gate structure of the Lds.

[0103] Example 16 is a method of manufacturing an integrated circuit as described in Example 10, further comprising: positioning the field plate contact at a contact point on the resist protective oxide (RPO) that is spaced from the gate structure at a distance between 40% and 70% of the Lds.

[0104] Example 17 is a method of manufacturing an integrated circuit as described in Example 10, further comprising: forming a plurality of field plate contacts on the resist protective oxide (RPO), wherein the field plate contacts are offset from the gate structure by at least 40% of the Lds.

[0105] Example 18 is a method for improving high-voltage performance in an LDMOS integrated circuit, comprising: depositing an insulating field plate over a portion disposed in an n-type drift region between a gate structure and a drain structure; and applying a field plate voltage to the field plate during device operation.

[0106] Example 19 is a method for improving high-voltage performance in an LDMOS integrated circuit as described in Example 18, wherein the field plate voltage is at least 14V.

[0107] Example 20 is a method for improving high-voltage performance in an LDMOS integrated circuit as described in Example 18, wherein the field plate voltage is equal to the drain voltage (Vdd) applied to the drain of the LDMOS integrated circuit.

Claims

1. An integrated circuit, comprising: n-type drift region; A gate structure, the gate structure being located on a first portion of the n-type drift region; A drain structure, wherein the drain structure is located in the second portion of the n-type drift region, and the gate structure and the drain structure are separated by a drift region length Lds; A resist-protected oxide RPO is located above the n-type drift region between the gate structure and the drain structure; as well as A field plate contact, which is directly electrically connected to the resist protective oxide, is configured to apply a voltage to the resist protective oxide. The field plate contact is separated from the gate structure by a first distance D1, and the first distance is between 40% and 70% of Lds. The integrated circuit further includes a conductive structure that is directly electrically connected between the drain contact and the field plate contact, wherein the applied voltage is the drain voltage.

2. The integrated circuit according to claim 1, wherein: The field plate contact element has a contact element width D3, and The width of the contact element is between 10% and 30% of the Lds.

3. The integrated circuit according to claim 1, wherein: The field plate contact includes a first field plate contact with a first contact width and a second field plate contact with a second contact width. The width of the first contact element is at least 10% of the width of Lds, and The width of the second contact is at least 10% of the width of Lds.

4. The integrated circuit according to claim 1, wherein: The resist protects the oxide with a thickness D2, and The thickness is at least 10% of the Lds.

5. The integrated circuit according to claim 1, wherein: The corrosion resist protects the oxide with a thickness D2; and The thickness is between 0.05 µm and 0.2 µm.

6. The integrated circuit according to claim 1, wherein: The Lds is at least 0.5 µm.

7. A method for manufacturing an integrated circuit, comprising: Deep P-wells are implanted in P-type substrates; An n-type drift region is injected into the deep P-well; A gate structure is deposited on the first portion of the n-type drift region; A drain structure is injected into the second part of the n-type drift region, wherein the gate structure and the drain structure are separated by a drift region length Lds; In the n-type drift region, a resist protective oxide RPO is deposited on the third portion between the gate structure and the drain structure; The etching field plate contacts are opened to expose the surface portion of the resist-protected oxide; as well as Field plate contacts are deposited in the field plate contact openings to provide a direct electrical connection to the resist-protected oxide. The method further includes: The field plate contacts are positioned on the resist-protected oxide RPO at contact points that are 40% to 70% of the distance between the Lds and the gate structure. The method further includes: Forming drain contacts to provide a direct electrical connection to the drain structure; and A metal jumper is formed between the field plate contact and the drain contact.

8. The method for manufacturing an integrated circuit according to claim 7, further comprising: The resist protective oxide RPO is formed on a portion of the gate structure.

9. The method for manufacturing an integrated circuit according to claim 7, further comprising: A sidewall structure is formed adjacent to the gate structure.

10. The method for manufacturing an integrated circuit according to claim 7, further comprising: Multiple active regions are defined on the P-type substrate; A field oxide FOX structure is formed between adjacent active regions; as well as The field plate contact is positioned closer to the drain structure than to the gate structure.

11. The method for manufacturing an integrated circuit according to claim 7, further comprising: A plurality of field plate contacts are formed on the resist-protected oxide RPO, wherein the field plate contacts are offset from the gate structure by at least 40% of the Lds.

12. A method for improving the high-voltage performance in LDMOS integrated circuits, comprising: A resist-protected oxide RPO is deposited on the portion of the n-type drift region between the gate structure and the drain structure, and a field plate contact is directly formed on the resist-protected oxide RPO. as well as During device operation, a field plate voltage is applied to the field plate contacts. Wherein, the field plate contact is separated from the gate structure by a first distance D1, the gate structure and the drain structure are separated by a drift region length Lds, and the first distance is between 40% and 70% of Lds. Wherein, the field plate voltage is equal to the drain voltage Vdd applied to the drain of the LDMOS integrated circuit.

13. The method for improving high-voltage performance in LDMOS integrated circuits according to claim 12, wherein: The voltage of the field plate is at least 14V.

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