Non-integer frequency divider and flash memory controller

Abstract

The present invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency divider includes a plurality of registers, a counter, a control signal generator, and a clock gating circuit. With respect to the plurality of registers, at least a portion of the plurality of registers is set to have a value. The counter is configured to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator is configured to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is configured to mask or unmask an input clock signal based on the control signal to generate an output clock signal.

Description

Technical Field

[0001] The present invention relates to a non-integer frequency divider, and in particular to a non-integer frequency divider for a flash memory controller. Background Art

[0002] Conventional frequency dividers are implemented using multiple flip-flops connected in series. These flip-flops receive an input clock signal and generate an output clock signal with a frequency lower than that of the input clock signal. In such conventional frequency dividers, the frequency of the output clock signal must be equal to (1 / 2^n) times the frequency of the input clock signal, where "n" is an integer determined by the number of flip-flops. Alternatively, non-integer frequency dividers can be designed to generate an output clock signal with a specific frequency. However, these typically require a relatively complex circuit design. Summary of the Invention

[0003] An object of the present invention is to provide a non-integer frequency divider that can have different frequencies by changing the configuration, and the non-integer frequency divider has a simpler circuit design to solve the above-mentioned problem.

[0004] One embodiment of the present invention discloses a non-integer frequency divider comprising a plurality of registers, a counter, a control signal generator, and a clock gating circuit. At least a portion of the registers is set to have values. The counter sequentially generates a plurality of count values, wherein the plurality of count values ​​correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator generates a control signal based on the received count values ​​and the corresponding register values. The clock gating circuit uses the control signal to mask or unmask an input clock signal to generate an output clock signal.

[0005] Another embodiment of the present invention discloses a flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module includes at least one flash memory chip, and the flash memory controller includes a memory, a microprocessor, a first digital circuit, a second digital circuit, a clock signal generator, and a non-integer frequency divider. The memory is used to store a program code, and the microprocessor is used to execute the program code to access the flash memory module. The clock signal generator is used to generate a clock signal and an input clock signal. The non-integer frequency divider includes multiple registers, a counter, a control signal generator, and a clock gating circuit. At least a portion of the multiple registers is set to have a value. The counter is used to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers and the plurality of count values ​​are repeatedly generated. The control signal generator is used to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is used to mask or unmask an input clock signal with reference to the control signal to generate an output clock signal. The first digital circuit operates by using the clock signal, and the second digital circuit operates by using the output clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 4 is a schematic diagram of a non-integer frequency divider according to an embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a timing diagram of signals of the non-integer frequency divider according to an embodiment of the present invention.

[0008] Figure 3 A schematic diagram of an electronic device according to an embodiment of the present invention.

[0009]

Explanation of symbols

[0010] 30: Electronic devices

[0011] 100: Non-integer frequency divider

[0012] 110: Clock gate control circuit

[0013] 120: Controller

[0014] 122: Control signal generator

[0015] 130: Counter

[0016] 300: Memory device

[0017] 310: Memory controller

[0018] 312: Microprocessor

[0019] 312C: Program code

[0020] 312M: Read-only memory

[0021] 314: Control logic circuit

[0022] 331: Encoder

[0023] 332:Decoder

[0024] 333:Randomizer

[0025] 334:Derandomizer

[0026] 335: Interface circuit

[0027] 336:Clock Signal Generator

[0028] 316: Buffer

[0029] 318: Transmission interface circuit

[0030] 320: Flash memory module

[0031] 350: Host device DETAILED DESCRIPTION

[0032] Figure 1 FIG. 1 is a schematic diagram of a fractional frequency divider 100 according to an embodiment of the present invention. Figure 1 As shown, the non-integer frequency divider 100 includes a clock gating circuit 110, a controller 120, and a counter 130. The controller 120 includes a control signal generator 122 and a plurality of registers R1-RN. In this embodiment, the non-integer frequency divider 100 is a configurable frequency divider, i.e., the non-integer frequency divider 100 can use different divisors to divide the frequency of an input clock signal CK_in to generate an output clock signal CK_out.

[0033] In the non-integer frequency divider 100, at least a portion of registers R1-RN are set based on register setting information provided by another circuit to determine the divisor of the non-integer frequency divider 100. For example, if the non-integer frequency divider 100 is controlled to generate an output clock signal CK_out having a frequency 7 / 9 times that of the input clock signal CK_in (i.e., a divisor of 9 / 7), the nine registers R1-R9 can be selected to set various values ​​based on the register setting information provided by the other circuit. For example, registers R1-R9 can be set to have seven 1s and two 0s. In other words, the values ​​of registers R1-R9 can be represented in binary as 9'b1_1101_1101.

[0034] The counter 130 can be used to repeatedly generate a count value CV for the controller 120 based on the register setting information. In this embodiment, the count value ranges from zero to a value equal to the number of registers set by the register setting information. For example, if nine registers R1-R9 are selected for setting values ​​based on the register setting information, the counter 130 can sequentially generate count values ​​from "1" to "9," with count values ​​CV=1 to CV=9 being repeatedly generated. Furthermore, the counter 130 generates a count value CV during one clock cycle of the input clock signal CK_in. For example, the counter 130 generates a count value "1" during the first clock cycle of the input clock signal CK_in, a count value "2" during the second clock cycle of the input clock signal CK_in, a count value "3" during the third clock cycle of the input clock signal CK_in, and so on.

[0035] The control signal generator 122 can be configured to generate a control signal Vc based on a count value CV and at least a portion of the values ​​of registers R1-RN. Specifically, when the control signal generator 122 receives the count value CV, the control signal generator 122 references the value of a register corresponding to the received count value CV to determine the level of the control signal Vc. For example, assuming that the design values ​​"1" to "9" correspond to registers R1 to R9, respectively, when the control signal generator 122 receives a count value CV equal to "1," if the value of register R1 is "1," the control signal generator 122 generates a control signal Vc having a first logic value (e.g., a logic value "1" or a high voltage level). If the value of register R1 is "0," the control signal generator 122 generates a control signal Vc having a second logic value (e.g., a logic value "0" or a low voltage level). When the control signal generator 122 receives a count value CV equal to "2," if the value of register R2 is "1," the control signal generator 122 generates a control signal Vc having the first logic value. If the value of register R2 is "0," the control signal generator 122 generates a control signal Vc having the second logic value. When the control signal generator 122 receives a count value CV equal to "3," if the value of register R3 is "1," the control signal generator 122 generates a control signal Vc having the first logic value. If the value of register R3 is "0," the control signal generator 122 generates a control signal Vc having the second logic value. In view of the above, the control signal generator 122 continuously generates the control signal Vc based on the received count value CV and the corresponding register value.

[0036] The clock gating circuit 110 can be used to output the input clock signal CK_in or not output the input clock signal CK_in based on a control signal Vc to generate an output clock signal CK_out. Specifically, the clock gating circuit 110 can be implemented as a switch. When the control signal Vc has a first logic value, the clock gating circuit 110 is enabled to output the input clock signal CK_in to generate the output clock signal CK_out. When the control signal Vc has a second logic value, the clock gating circuit 110 is disabled, such that the input clock signal CK_in is masked and the output clock signal CK_out is not toggled.

[0037] Figure 2 FIG. 1 is a timing diagram of signals of a non-integer frequency divider 100 according to an embodiment of the present invention. Figure 2 As shown, each clock cycle of the input clock signal CK_in has a high voltage level period and a low voltage level period, and when the control signal Vc has a first logic value such as the high voltage level (for example, Figure 2 When the control signal Vc has the second logic value, such as a low voltage level (for example, the second clock cycle and the sixth clock cycle), the output clock signal CK_out is at a low voltage level during the entire clock cycle. Figure 2 In the embodiment shown, in nine cycles, the input clock signal CK_in has nine enabled periods (i.e., periods with a high voltage level), but the output clock signal CK_out has only seven enabled periods (i.e., periods with a high voltage level). Therefore, the frequency of the output clock signal CK_out can be regarded as 7 / 9 times the frequency of the input clock signal CK_in.

[0038] exist Figure 2 In the embodiment shown, to make the output clock signal CK_out have evenly distributed enable periods, the distance between two clock cycles without enable periods is as far as possible. In one embodiment, the output clock signal CK_out does not have two adjacent clock cycles without enable periods.

[0039] A non-integer frequency divider 100 can be used in an electronic device to provide an output clock signal CK_out to a digital circuit. The frequency of the output clock signal CK_out can be changed in real time during the operation of the electronic device. Specifically, the non-integer frequency divider 100 can continuously output the output clock signal CK_out without temporarily suspending the generation of the output clock signal CK_out. Specifically, assuming that registers R1-R9 each have the values ​​9'b1_1101_1101, and the divisor of the non-integer frequency divider 100 is controlled to change from 9 / 7 to 9 / 6, registers R1-R9 can refer to the register setting information to have the values ​​9'b1_1011_0110, and the frequency of the output clock signal CK_out can be quickly changed to 6 / 9 times the frequency of the input clock signal CK_in. In another embodiment, assuming that registers R1-R9 respectively have values ​​9'b1_1101_1101, and the divisor of the non-integer frequency divider 100 is controlled to change from 9 / 7 to 7 / 6, registers R1-R7 can refer to the register setting information to set their values ​​to 9'b111_0111. The counter 130 sequentially and repeatedly generates count values ​​from "1" to "7" according to the register setting information, and quickly changes the frequency of the output clock signal CK_out to 6 / 7 times the frequency of the input clock signal CK_in.

[0040] Figure 3FIG2 is a schematic diagram of an electronic device 30 according to an embodiment of the present invention, wherein the electronic device 30 may include a host device 350 and a memory device 300. The memory device 300 may be used to provide storage space for the host device 350 and obtain one or more driving voltages from the host device 350 as a power source for the memory device 300. Examples of the host device 350 may include, but are not limited to, a multifunctional mobile phone, a wearable device, a tablet, and a personal computer such as a desktop or laptop computer. Examples of the memory device 300 may include, but are not limited to, a solid state drive (SSD) and various types of embedded memory devices, such as embedded memory devices compliant with the Peripheral Component Interconnect Express (PCIe) standard. According to this embodiment, the memory device 300 may include a flash memory controller 310 and a flash memory module 320. The flash memory controller 310 may be used to control the operation of the memory device 300 and access the flash memory module 320. The flash memory module 320 is used to store information. The flash memory module 320 may include at least one flash memory chip.

[0041] like Figure 3As shown, the flash memory controller 310 may include a processing circuit (e.g., a microprocessor 312), a storage unit (e.g., a read-only memory (ROM) 312M), a control logic circuit 314, a buffer 316, and a transmission interface circuit 118, wherein the above components may be coupled to each other via a bus. The buffer 316 is implemented as a static random access memory (SRAM), but the present invention is not limited to this. The buffer 316 can be used to provide internal storage space for the flash memory controller 110. In addition, the ROM 312M of this embodiment can be used to store a program code 312C, and the microprocessor 312 can be used to execute the program code 312C to control access to the flash memory module 320. Please note that in some examples, the program code 312C can be stored in the buffer 316 or any other type of memory. Furthermore, the control logic circuit 314 may be used to control the flash memory module 320 and may include an encoder 331, a decoder 332, a randomizer 333, a de-randomizer 334, and an interface circuit 335, wherein the interface circuit 335 is coupled to the flash memory module 320. The transmission interface circuit 318 may comply with a specific communication standard (such as the Serial Advanced Technology Attachment (SATA) standard, the Peripheral Component Interconnect (PCI) standard, the Peripheral Component Interconnect Express (PCIe) standard, the Universal Flash Storage (UFS) standard, etc.) and may communicate according to the specific communication standard. For example, the host device 350 may communicate with the memory device 300, wherein the host device 350 may include a corresponding transmission interface circuit that complies with the specific communication standard to communicate with the memory device 300.

[0042] In this embodiment, the host device 350 can transmit a host command and a corresponding logical address to the flash memory controller 310 to access the memory device 300. The flash memory controller 310 receives the host command and the logical address, converts the host command into a memory operation command (hereinafter referred to as an operation command), and further uses the operation command to control the flash memory module 320 to perform operations such as read, write, or program on certain memory cells (e.g., data pages) in the flash memory module 320 that have physical addresses corresponding to the logical addresses.

[0043] exist Figure 3 In the embodiment shown, each circuit block requires a clock signal to operate, and the non-integer frequency divider 100 can be used in any digital circuit except the transmission interface circuit 318, the microprocessor 312, and the interface circuit 335. Figure 3 For example, the control logic circuit 314 further includes a clock signal generator 336 and a non-integer frequency divider 100. The clock signal generator 336 can be used to generate a clock signal CK to the interface circuit 335. The clock signal CK is a normal clock signal and does not mask any enable period within a clock cycle. That is, each clock cycle of the clock signal CK has a high voltage level period and a low voltage level period. In addition, the clock signal generator 336 can also generate an input clock signal CK_in to the non-integer frequency divider 100, so that the non-integer frequency divider 100 generates an output clock signal CK_out to the encoder 331, the decoder 332, the randomizer 333, and / or the de-randomizer 334. The non-integer frequency divider 100 can receive register setting information from the microprocessor 312 to determine the divisor to be used.

[0044] In one embodiment of the present invention, the flash memory controller 310 can operate in at least a normal mode and a power saving mode. When the flash memory controller 310 operates in the normal mode, the non-integer frequency divider 100 can be disabled, and the encoder 331, the decoder 332, the randomizer 333, and / or the derandomizer 334 operate using the clock signal CK generated by the clock signal generator 336. In another embodiment, when the flash memory controller 310 operates in the normal mode, the microprocessor 112 generates the register setting information to the non-integer frequency divider 100 to set the values ​​of the registers R1-RN to "1". Since each of the registers R1-RN has a value of "1", the control signal Vc is always enabled, so that the output clock signal CK_out is equal to the input clock signal CK_in. Therefore, the output clock signal CK_out can be regarded as a normal clock signal without any masked enable period, and the encoder 331, the decoder 332, the randomizer 333 and / or the de-randomizer 334 operate by using the output clock signal CK_out generated by the non-integer frequency divider 100.

[0045] When the flash memory controller 310 operates in power saving mode, it can operate at a slower speed to reduce power consumption. In this case, the interface circuit 335 still operates using the clock signal CK, but the encoder 331, decoder 332, randomizer 333, and / or derandomizer 334 use the lower frequency output clock signal CK_out. Specifically, when the flash memory controller 310 operates in power saving mode, the non-integer frequency divider 100 is enabled, and the microprocessor 312 sends register setting information to the non-integer frequency divider 100 to set at least a portion of registers R1-RN, further causing the portion of registers R1-RN to have one or more "0" values. As a result, some enable periods of the input clock signal CK_in are masked by the clock signal gating circuit 110, generating a lower frequency output clock signal CK_out.

[0046] In short, in the non-integer frequency divider of the present invention, it can use simple circuits, such as counters, registers, and clock gating circuits to divide the frequency of the input clock signal to generate an output clock signal, and the non-integer frequency divider can be simply controlled by a processor to generate output clock signals with different frequencies. Therefore, the non-integer frequency divider of the present invention can be used in many digital circuits to provide appropriate clock signals.

[0047] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A non-integer frequency divider, comprising: a plurality of registers, wherein at least a portion of the plurality of registers are set to have values; a counter for sequentially generating a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the plurality of registers, and the plurality of count values ​​are repeatedly generated; a control signal generator for generating a control signal according to the received count value and the corresponding register value; and A clock gating circuit is used to shield or not shield an input clock signal with reference to the control signal to generate an output clock signal.

2. The non-integer frequency divider according to claim 1, wherein: The number of the plurality of count values ​​is the same as the number of the at least a portion of the plurality of registers. If the register corresponding to the count value received by the control signal generator has a first value, the control signal generated by the control signal generator has a first logic value. If the register corresponding to the count value received by the control signal generator has a second value, the control signal generated by the control signal generator has a second logic value.

3. The non-integer frequency divider according to claim 2, wherein: When the control signal has the first logic value, the clock gating circuit shields the input clock signal so that the output clock signal does not have a consistent enable period; when the control signal has the second logic value, the clock gating circuit does not shield the input clock signal so that the output clock signal is generated by the input clock signal.

4. The non-integer frequency divider according to claim 3, wherein: The counter generates only one count value to the control signal generator in one clock cycle of the input clock signal. For each clock cycle of the input clock signal, when the control signal has the first logic value, the clock gating circuit masks the input clock signal so that the output clock signal does not have the enable period in the clock cycle, and when the control signal has the second logic value, the clock gating circuit does not mask the input clock signal so that the output clock signal is the same as the input clock signal in the clock cycle.

5. A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, the flash memory module includes at least one flash memory chip, and the flash memory controller includes: a memory for storing a program code; a microprocessor, configured to execute the program code to access the flash memory module; a first digital circuit and a second digital circuit; a clock signal generator for generating a clock signal and an input clock signal; as well as A non-integer frequency divider comprising: a plurality of registers, wherein at least a portion of the plurality of registers are set to have values; a counter for sequentially generating a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the plurality of registers, and the plurality of count values ​​are repeatedly generated; a control signal generator for generating a control signal according to the received count value and the corresponding register value; as well as a clock gating circuit for shielding or not shielding the input clock signal with reference to the control signal to generate an output clock signal; The first digital circuit operates by using the clock signal, and the second digital circuit operates by using the output clock signal.

6. The flash memory controller according to claim 5, wherein: The number of the plurality of count values ​​is the same as the number of the at least a portion of the plurality of registers. If the register corresponding to the count value received by the control signal generator has a first value, the control signal generated by the control signal generator has a first logic value. If the register corresponding to the count value received by the control signal generator has a second value, the control signal generated by the control signal generator has a second logic value.

7. The flash memory controller according to claim 6, wherein: When the control signal has the first logic value, the clock gating circuit shields the input clock signal so that the output clock signal does not have a consistent enable period; when the control signal has the second logic value, the clock gating circuit does not shield the input clock signal so that the output clock signal is generated by the input clock signal.

8. The flash memory controller according to claim 7, wherein: The counter generates only one count value to the control signal generator within one clock cycle of the input clock signal; and for each clock cycle of the input clock signal, when the control signal has the first logic value, the clock gating circuit masks the input clock signal so that the output clock signal does not have the enable period within the clock cycle, and when the control signal has the second logic value, the clock gating circuit does not mask the input clock signal so that the output clock signal is the same as the input clock signal within the clock cycle.

9. The flash memory controller according to claim 5, wherein: The non-integer frequency divider is a frequency divider with changeable configuration, and the microprocessor generates a register setting information for the non-integer frequency divider to set the plurality of registers to change a divisor of the non-integer frequency divider.

10. The flash memory controller according to claim 9, wherein: The microprocessor generates the register setting information for the non-integer frequency divider to set the plurality of registers so as to instantly change the divisor of the non-integer frequency divider during an operation period of the non-integer frequency divider.

11. The flash memory controller according to claim 5, wherein: The flash memory controller can selectively operate in a normal mode or a power-saving mode. When the flash memory controller operates in the normal mode, the first digital circuit and the second digital circuit both operate using the clock signal, and the non-integer frequency divider is disabled. When the flash memory controller operates in the power-saving mode, the first digital circuit operates using the clock signal, and the second digital circuit operates using the output clock signal generated by the non-integer frequency divider.

12. The flash memory controller according to claim 5, wherein: The first digital circuit is an interface circuit coupled to the flash memory controller, and the second digital circuit is an encoder, a decoder, a randomizer, or a derandomizer.

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