A two-dimensional AMR sensor switch chip signal detection architecture and detection method

Abstract

The present invention discloses a two-dimensional AMR sensor switch chip signal architecture and detection method. In the signal circuit architecture, the clock signal output terminal of the fast clock circuit is connected to the clock signal input terminal of the first combinational logic operation module and the clock signal input terminal of the second combinational logic operation module, and the clock signal output terminal of the slow clock circuit is connected to the clock signal input terminal of the first combinational logic operation module; the first combinational logic operation module outputs an X-direction sampling signal, a Y-direction sampling signal, and a detection enable signal, and the second combinational logic operation module outputs a comparator enable signal, a chopping signal, and an XY-direction switching signal. Chopping offset cancellation technology is used to improve detection accuracy, and time-division multiplexing technology is used to share a processing signal chain, achieving low-power two-dimensional signal acquisition and detection in the X and Y directions, and flexible switching of directions according to actual needs.

Description

Technical Field

[0001] The present invention relates to the technical field of sensor control circuits, and in particular to a two-dimensional AMR sensor switch chip signal detection architecture and detection method. Background Art

[0002] The anisotropic magnetoresistance (AMR) effect is a phenomenon in which the resistivity of ferromagnetic materials changes with changes in magnetization intensity (applied magnetic field) and current direction. Magnetoresistive sensors based on this effect are widely used due to their high sensitivity and ease of integration. In a typical signal detection circuit architecture, the oscillator's output signal is processed by a frequency divider, which then feeds the processed signal into a combinational logic unit. This output signals the AMR switch chip's detection enable clock signal and a comparator's output sampling clock signal, which are used to control the AMR switch chip's detection of the magnetic field.

[0003] Conventional signal detection circuit architectures have the following drawbacks: First, for applications with many frequency divisions and long counting cycles, the combinational logic circuits required to control the operation of the AMR switch chip using the aforementioned signal detection circuit architecture are large in scale, require large computational load, and consume high power. Second, glitches are easily generated during the computation process. Third, the AMR signal output is directly fed to the comparator, and the comparator offset is greatly affected by the process (auto-zero comparators cannot be used without chopping signals), resulting in low signal detection accuracy. Fourth, traditional implementations of two-dimensional signal acquisition require two sets of signal processing links, resulting in poor consistency and high power consumption.

[0004] In view of this, this application is hereby filed. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that conventional timing control circuit architectures consume high power when controlling AMR switch chips to detect magnetic fields, are prone to glitches during calculations, have low detection accuracy, and utilize two sets of signal processing links for two-dimensional signal acquisition, resulting in poor consistency and high power consumption. The present invention aims to provide a two-dimensional AMR sensor switch chip signal detection architecture and method. By using a digital control circuit, the chip's high-power analog circuits, such as the magnetoresistive bridge and comparator, are periodically switched between active-sleep-active states. The presence or absence of a magnetic field is determined through sampling, effectively reducing the chip's power consumption. Furthermore, a two-phase chopping signal is introduced to eliminate the offset voltage of the instrumentation amplifier, thereby improving the detection accuracy of the magnetoresistive switch chip. Furthermore, an X-direction sampling signal, a Y-direction sampling signal, and an XY-direction switching signal are generated to achieve two-dimensional signal acquisition, with switching capabilities required to enhance signal sampling flexibility.

[0006] The present invention is achieved through the following technical solutions: On the one hand, the present invention proposes a two-dimensional AMR sensor switch chip signal detection architecture, including: a fast clock circuit, a slow clock circuit, a first combinational logic operation module, and a second combinational logic operation module; the F_CLK output terminal of the fast clock circuit is connected to the CLK_1 input terminal of the first combinational logic operation module and the CLK input terminal of the second combinational logic operation module, and the S_CLK output terminal of the slow clock circuit is connected to the CLK_2 input terminal of the first combinational logic operation module; the XY_SW input terminal of the first combinational logic operation module is connected to the XY_SW output terminal of the second combinational logic operation module, the Sampling_X output terminal outputs an X-direction sampling signal, the Sampling_Y output terminal outputs a Y-direction sampling signal, and the EN output terminal is connected to the EN input terminal of the second combinational logic operation module and outputs a detection enable signal; the XY_SW output terminal of the second combinational logic operation module outputs an XY direction switching signal, the EN_comp output terminal outputs a comparator enable signal, and the chopping output terminal outputs a two-phase chopping signal. The POR input terminal of the first combinational logic operation module receives a power-on reset signal, and the chopping output terminal of the second combinational logic operation module includes a chopping PH1 output terminal and a chopping PH2 output terminal.

[0007] To address the large size, computational complexity, and power consumption of the combinational logic circuits required by conventional timing control circuit architectures to control AMR switch chips detecting magnetic fields when multiple frequency divisions are applied and counting cycles are long, this present invention proposes a digital circuit composed of a slow clock, a fast clock, and a combinational logic module to periodically control the chip's power-hungry analog circuits, such as the magnetoresistive bridge and comparator, to cycle between active and passive states. The circuit then determines the presence of a magnetic field through sampling, eliminating the need for real-time detection and effectively reducing chip energy consumption. The chip's active-sleep time cycle is determined by the slow clock circuit, while the chip's active and sampling times are derived from the slow and fast clock circuits and the combinational logic module.

[0008] Among them, the slow clock circuit is used to set the chip's work-sleep cycle, and its clock cycle is long and the current consumption is low; the fast clock circuit is used to generate a fast clock signal, and its working time is short and the current consumption is low; the combinational logic operation is used to perform logical operations on the fast clock signal and the slow clock signal, and its internal circuit logic is clear and the amount of calculation is small, which can generate the chip's detection enable signal, comparator output sampling signal and comparator enable signal; when the chip's detection enable signal is high and the comparator output sampling signal lasts, the comparator compares the differential output of the instrumentation amplifier, and the sampling signal samples the comparator output result, and the sampling result is sent to the chip's output drive. Therefore, the present invention adopts two sets of fast and slow clock circuits, and cooperates with the combinational logic operation module to control the chip to complete signal detection work in a shorter working time at a lower working current, with a small amount of calculation, which can effectively reduce the chip's power consumption.

[0009] To address the problem of glitches easily generated during the calculation process of conventional signal detection circuit architectures, the present invention improves the detection accuracy of magnetic field signals by introducing a two-phase chopping signal to offset the offset voltage. Specifically, the combinational logic operation module outputs chopping signals PH1 and PH2 to eliminate the offset voltage of the instrumentation amplifier. An auto-zeroing comparator is used to eliminate comparator offset, thereby reducing glitches during the calculation process and improving the detection accuracy of the magnetoresistive switch chip.

[0010] To address the shortcomings of conventional signal detection circuit architectures, which use two sets of signal processing links to achieve poor consistency in signal acquisition in two-dimensional directions and high power consumption, the present invention uses a digital control circuit to generate X-direction sampling signals and Y-direction sampling signals respectively, for implementing signal sampling in two-dimensional directions on a single signal processing link. Compared with conventional signal detection circuit architectures, this increases the dimensionality of signal sampling; and generates an XY-direction switching signal for switching the signal sampling direction according to actual needs, thereby improving sampling flexibility.

[0011] As a further description of the present invention, the first combinational logic operation module includes: a detection enable signal generation unit, an XY direction sampling signal generation unit and a reset signal generation unit; the input end of the detection enable signal generation unit is connected to the S_CLK output end of the slow clock circuit and receives the POR signal, and the output end outputs the detection enable signal; the input end of the XY direction sampling signal generation unit is connected to the F_CLK output end of the fast clock circuit and receives the POR signal, and the output end outputs the X direction sampling signal and the Y direction sampling signal; the input end of the reset signal generation unit is connected to the output end of the XY direction sampling signal generation unit and receives the POR signal, and the output end is connected to the detection enable signal generation unit and the XY direction sampling signal generation unit.

[0012] As a further description of the present invention, the detection enable signal generation unit includes: a two-input NAND gate A1, a trigger B6, and a driver buffer D1, connected in sequence; one input of A1 is connected to the S_CLK output of the slow clock circuit, and the other input receives a POR signal; the output of D1 outputs the detection enable signal. The XY direction sampling signal generation unit includes: two-input NAND gates A2 and A3, a first counter, and a second counter; one input of A2 is connected to the F_CLK output of the fast clock circuit, the other input receives a POR signal, and the output is connected to the input of the first counter, the output of the first counter is connected to one input of A3; the other input of A3 receives an XY direction switching signal, and the output outputs an X direction sampling signal; the input of the second counter is connected to the output of A2, and the output outputs a Y direction sampling signal.

[0013] As a further description of the present invention, the reset signal generating unit includes: a first reset signal generating circuit and a second reset signal generating circuit; the first reset signal generating circuit includes: delay buffers E1 and E2, a two-input NAND gate A4 and an inverter N1; E1 and E2 are connected in series between the output end of the first counter and one input end of A4, the other input end of A4 receives a POR signal, and the output end of N1 is connected to the reset end of the first counter; the second reset signal generating circuit includes: delay buffers E3 and E4, a two-input NAND gate A5 and an inverter N2; E3 and E4 are connected in series between the output end of the second counter and one input end of A5, the other input end of A5 receives a POR signal, and the output end of N2 is connected to the reset end of the second counter and B6.

[0014] As a further description of the present invention, the first counter includes: cascaded triggers B1, B2, B3, B4 and B5, and a two-input AND gate A6; the D input terminals of B1, B2, B3, B4 and B5 are connected to The output terminal of B1 is connected to the output terminal of A2, the Q output terminal of B3 is connected to one input terminal of A6, the Q output terminal of B5 is connected to the other input terminal of A6, and the output terminal of A6 is connected to one input terminal of A3; the reset terminals of B1, B2, B3, B4 and B5 are connected to the reset signal; the second counter includes: cascaded flip-flops B7, B8, B9, B10, B11 and B12, and a two-input AND gate A7; the D input terminals of B7, B8, B9, B10, B11 and B12 are connected Output end, the CK input end of B7 is connected to the output end of A2, the Q output end of B10 is connected to one input end of A7, the Q output end of B12 is connected to the other input end of A7, and the output end of A7 outputs the Y direction sampling signal; the reset terminals of B7, B8, B9, B10, B11 and B12 are connected to the reset signal.

[0015] As a further description of the present invention, the second combinational logic operation module includes: an XY direction switching signal generation unit, a comparator enable signal generation unit and a two-phase chopping signal generation unit; the input end of the XY direction switching signal generation unit receives a fast clock signal and an EN signal, and the output end outputs the XY direction switching signal; the input end of the comparator enable signal generation unit receives an EN signal, and the output end outputs a comparator enable signal; the input end of the two-phase chopping signal generation unit receives an EN signal, and the output end outputs a two-phase chopping signal.

[0016] As a further description of the present invention, the XY direction switching signal generating unit includes: a third counter, delay buffers E5 and E6, two-input AND gates A8 and A9, inverters N3 and N4, and a flip-flop B13; one input terminal of A8 is connected to the F_CLK output terminal of the fast clock circuit, the other input terminal receives the EN signal, and the output terminal is connected to the input terminal of the third counter;

[0017] The output of the third counter is connected to E5 and E6 in sequence, and the reset terminal is connected to the output terminal of N3; the output terminal of E6 is connected to one input terminal of A9 and the CK input terminal of B13; the other input terminal of A9 is connected to the reset terminal of B13, and the output terminal is connected to the input terminal of N3;

[0018] B13's D input terminal Output end, Q output end is connected to the input end of N4, and the output end of N4 outputs XY direction switching signal.

[0019] As a further description of the present invention, the comparator enable signal generating unit includes: cascaded triggers B14, B15, B16 and B17, two-input AND gates A10, A11 and A12, three-input NAND gate A13, delay buffer E7, and inverter N5; the CK input terminal of B14 is connected to the output terminal of A8, the Q output terminal of B14 is connected to one input terminal of A10, the Q output terminal of B15 is connected to one input terminal of A11, and the Q output terminal of B17 is connected to the other input terminal of A10 and the other input terminal of A11; the output terminal of A11 is connected to E7 and N5 in sequence; the output terminal of N5 is connected to one input terminal of A12; the other input terminal of A12 is connected to the reset terminal of B13 and receives the EN signal, and the output terminal is connected to the reset terminals of B14, B15, B16 and B17; the D input terminals of B14, B15, B16 and B17 are connected Output terminal; Two-phase chopping signal generating unit includes: trigger B18 and two-phase non-overlapping clock generator; B18 CK input terminal is connected to the output terminal of A11, D input terminal is connected to The output end, the Q output end is connected to the input end of the two-phase non-overlapping clock generator; the reset end of B18 receives the EN signal; the output end of the two-phase non-overlapping clock generator outputs a two-phase chopping signal; the output ends of A8 and A10, and the PH2 output end of the two-phase non-overlapping clock generator are connected to the input end of A13, and the output end of A13 outputs a comparator enable signal.

[0020] As a further description of the present invention, a two-phase non-overlapping clock generator includes: inverters N6, N7, N8, N9, N10 and N11, two-input NAND gates A14 and A15, and delay buffers E8, E9, E10 and E11; N6 and N7 are connected in series and then connected to one input terminal of A14, and the input terminal of N6 is connected to the Q output terminal of B18; the output terminal of A14 is connected to E8, E9, N8 and N9 in sequence, and the output terminal of N9 outputs the PH1 chopping signal; one input terminal of A15 is connected to the output terminal of N9, the other input terminal is connected to the output terminal of N6, and the output terminal is connected to E10, E11, N10 and N11 in sequence. The output terminal of N11 is connected to the other input terminal of A14 and outputs the PH2 chopping signal.

[0021] On the other hand, the present invention provides a detection method for a two-dimensional AMR sensor switch chip signal detection architecture, comprising the following steps: a slow clock circuit sends an S_CLK signal to a first combinational logic operation module;

[0022] The fast clock circuit sends an F_CLK signal to the first combinational logic operation module;

[0023] The first logic operation module performs a logic operation according to the S_CLK signal and the F_CLK signal, and outputs a detection enable signal and a sampling signal;

[0024] The fast clock circuit sends an F_CLK signal to the second combinational logic operation module;

[0025] The first combinational logic operation module sends an EN signal to the second combinational logic operation module;

[0026] The second combinational logic operation module performs a logic operation according to the F_CLK signal and the EN signal, and outputs an XY direction switching signal, a comparator enable signal and a two-phase chopping signal;

[0027] The control chip performs signal detection according to the detection enable signal, the sampling signal, the XY direction switching signal, the output comparator enable signal and the two-phase chopping signal.

[0028] Compared with the prior art, the present invention has the following advantages and beneficial effects: 1. The embodiment of the present invention provides a two-dimensional AMR sensor switch chip signal detection architecture and detection method, which uses a digital circuit composed of a slow clock, a fast clock, and a combinational logic operation module to control the chip's high-power analog circuits such as the magnetoresistive bridge and comparator to periodically enter a work-sleep-work state. The presence or absence of a magnetic field is determined by sampling, eliminating the need for real-time detection and reducing chip operating energy consumption.

[0029] 2. The present invention provides a two-dimensional AMR sensor switch chip signal detection architecture and detection method. This architecture introduces a two-phase chopping signal to offset the offset voltage of the instrumentation amplifier, thereby reducing glitches during the calculation process and improving the detection accuracy of the magnetoresistive switch chip.

[0030] 3. The signal detection architecture and detection method of a two-dimensional AMR sensor switch chip provided by the embodiments of the present invention can flexibly adjust the chip's work-sleep-work duty cycle to meet different practical application requirements;

[0031] 4. The embodiment of the present invention provides a two-dimensional AMR sensor switch chip signal detection architecture and detection method, which can collect signals in the X direction and the Y direction, and can flexibly switch directions according to actual needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without making any creative efforts.

[0033] Figure 1 A schematic diagram of the structure of a common signal detection circuit provided in Example 1 of the present invention;

[0034] Figure 2 Schematic diagram of the signal detection architecture of a two-dimensional AMR sensor switch chip provided in Example 1 of the present invention;

[0035] Figure 3 A schematic diagram of the internal circuit wiring relationship of the first combinational logic operation module provided in Example 1 of the present invention;

[0036] Figure 4 This is an internal circuit wiring diagram of the first counter in the first combinational logic operation module provided in Example 1 of the present invention;

[0037] Figure 5This is an internal circuit wiring diagram of the second counter in the first combinational logic operation module provided in Example 1 of the present invention;

[0038] Figure 6 A schematic diagram of the internal circuit wiring relationship of the second combinational logic operation module provided in Example 1 of the present invention;

[0039] Figure 7 A diagram showing the internal circuit connection relationship of a two-phase non-overlapping clock generator in the second combinational logic operation module provided in Example 1 of the present invention;

[0040] Figure 8 This is a schematic diagram of the logical relationship of the timing control circuit architecture provided in Example 2 of the present invention.

[0041] Markings and corresponding component names in the accompanying drawings: 1-fast clock circuit, 2-slow clock circuit, 3-first combinational logic operation module, 4-second combinational logic operation module, 31-detection enable signal generation unit, 32-XY direction sampling signal generation unit, 33-reset signal generation unit, 41-XY direction switching signal generation unit, 42-comparator enable signal generation unit, 43-two-phase chopping signal generation unit. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0043] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not necessarily required to practice the present invention. In other embodiments, well-known structures, circuits, materials, or methods are not described in detail to avoid obscuring the present invention.

[0044] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Therefore, appearances of the phrases "one embodiment," "an embodiment," "an example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combinations and / or subcombinations. Furthermore, it will be understood by those of ordinary skill in the art that the figures provided herein are for illustrative purposes only and are not necessarily drawn to scale. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] In the description of the present invention, the terms "front", "back", "left", "right", "up", "down", "vertical", "horizontal", "high", "low", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the scope of protection of the present invention.

[0046] Example 1

[0047] Figure 1 A schematic diagram of a typical signal detection circuit architecture is shown. The signal output by the oscillator enters a frequency divider for processing, which then inputs the processed signal into a combinational logic unit. This unit ultimately outputs an AMR switch chip detection enable clock signal and a comparator to determine the output sampling clock signal, which is used to control the AMR switch chip's ability to detect the presence of a magnetic field. However, for applications with a high number of frequency divisions and long counting cycles, using this timing control circuit architecture to control the operation of the AMR switch chip requires a large combinational logic circuit, requiring a large amount of computation and consuming high power. This process is prone to glitches and makes it impossible to acquire signals in two dimensions.

[0048] In view of the defects of the above-mentioned common timing control circuit architecture, this embodiment provides a two-dimensional AMR sensor switch chip signal detection architecture, such as Figure 2 The signal detection circuit frame includes: a fast clock circuit 1, a slow clock circuit 2, a first combinational logic operation module 3, and a second combinational logic operation module 4; the F_CLK output terminal of the fast clock circuit 1 is connected to the CLK_1 input terminal of the first combinational logic operation module 3 and the CLK input terminal of the second combinational logic operation module 4, and the S_CLK output terminal of the slow clock circuit 2 is connected to the CLK_2 input terminal of the first combinational logic operation module 3; the XY_SW input terminal of the first combinational logic operation module 3 is connected to the XY_SW output terminal of the second combinational logic operation module 4, the Sampling_X output terminal outputs the X-direction sampling signal, the Sampling_Y output terminal outputs the Y-direction sampling signal, and the EN output terminal is connected to the EN input terminal of the second combinational logic operation module 4 and outputs a detection enable signal; the XY_SW output terminal of the second combinational logic operation module 4 outputs the XY direction switching signal, the EN_comp output terminal outputs the comparator enable signal, and the chopping output terminal outputs the two-phase chopping signal.

[0049] Slow clock circuit 2 can be constructed using an RC charge-discharge unit and a comparator architecture, generating a slow clock signal to set the chip's active-sleep cycle. This circuit features a long clock cycle and low current consumption. The cycle of slow clock circuit 2 is determined by the active-sleep-active cycle requirements of the magnetoresistive switch chip. In this embodiment, the chip's active-sleep cycle is set to 10 slow clock cycles, and the active state is 40 fast clock cycles.

[0050] The fast clock circuit 1 may be composed of an RC charge-discharge unit and a comparator architecture, and is used to generate a fast clock signal (compared to a slow clock signal). During its working period, the current consumption is low.

[0051] The first combinational logic operation module 3 is used to perform logical operations on the fast clock signal and the slow clock signal to generate the chip's detection enable signal, the fast clock enable signal, and the comparator output sampling Sampling_X signal and Sampling_Y signal, thereby controlling the chip's high-power analog circuits such as the magnetoresistive bridge and comparator to periodically be in a work-sleep-work state, and determine the presence or absence of a magnetic field by sampling in two-dimensional directions (X direction and Y opposite direction). The sampling time is set by the delay unit time in the timing control circuit architecture.

[0052] The second combinational logic operation module 4 is used to perform logical operations on the fast clock signal to generate an XY direction switching signal, a two-phase chopping signal and a comparator enable signal. It is used to flexibly switch between the X and Y directions according to actual needs during the signal sampling process and control the comparator. The chopping signal is used by the instrument amplifier to eliminate the offset signal and improve the detection accuracy.

[0053] Under the control of the signal detection circuit architecture of this embodiment, when the chip detects a high-level enable signal and the comparator outputs a sampling signal, the comparator compares the differential output of the instrumentation amplifier. The sampling signal samples the comparator's output, and the sampling result is sent to the chip's output driver. Because this embodiment utilizes two sets of fast and slow clock circuits, combined with a combinational logic operation module, the chip can complete signal detection within a short operating time at a low operating current, resulting in a small amount of computation and effectively reducing chip power consumption. Furthermore, the combinational logic operation module outputs a chopping signal to eliminate the offset voltage of the instrumentation amplifier, thereby improving the detection accuracy of the magnetoresistive switch chip and resolving the problem of glitches that are common in conventional sequential control circuit architectures during the operation process. Furthermore, the output Sampling_X and Sampling_Y signals enable signal acquisition in two dimensions, and the output XY_SW signal allows for flexible switching between the X and Y directions according to actual needs during the signal sampling process.

[0054] Next, the internal structures of the first combinational logic operation module 3 and its counter, and the second combinational logic operation module 4 and its two-phase non-overlapping clock generator in the timing control circuit architecture are described in detail.

[0055] The internal circuit connection relationship of the first combinational logic operation module 3 is as follows: Figure 3 As shown, it includes: a detection enable signal generating unit 31, an XY direction sampling signal generating unit 32 and a reset signal generating unit 33; the input end of the detection enable signal generating unit 31 is connected to the S_CLK output end of the slow clock circuit 2 and receives the POR signal, and the output end outputs the detection enable signal; the input end of the XY direction sampling signal generating unit 32 is connected to the F_CLK output end of the fast clock circuit 1 and receives the POR signal, and the output end outputs the X direction sampling signal and the Y direction sampling signal; the input end of the reset signal generating unit 33 is connected to the output end of the XY direction sampling signal generating unit 32 and receives the POR signal, and the output end is connected to the detection enable signal generating unit 31 and the XY direction sampling signal generating unit 32.

[0056] Furthermore, in the first combinational logic operation module 3, the detection enable signal generation unit 31 includes: a two-input AND gate A1, a trigger B6 and a driving buffer D1 connected in sequence; one input end of A1 is connected to the S_CLK end of the slow clock circuit 2, and the other input end receives the POR signal; the output end of D1 outputs the detection enable signal.

[0057] The XY direction sampling signal generating unit 32 includes: a two-input AND gate A2 and A3, a first counter and a second counter;

[0058] One input terminal of A2 is connected to the F_CLK terminal of the fast clock circuit 1, the other input terminal receives the POR signal, and the output terminal is connected to the input terminal of the first counter. The output terminal of the first counter is connected to one input terminal of A3; the other input terminal of A3 receives the XY direction switching signal, and the output terminal outputs the X direction sampling signal; the input terminal of the second counter is connected to the output terminal of A2, and the output terminal outputs the Y direction sampling signal.

[0059] The reset signal generating unit 33 includes a first reset signal generating circuit and a second reset signal generating circuit. The first reset signal generating circuit includes delay buffers E1 and E2, a two-input AND gate A4, and an inverter N1. E1 and E2 are connected in series between the output of the first counter and one input of A4, the other input of A4 receives a POR signal, and the output of N1 is connected to the reset terminal of the first counter. The second reset signal generating circuit includes delay buffers E3 and E4, a two-input AND gate A5, and an inverter N2. E3 and E4 are connected in series between the output of the second counter and one input of A5, the other input of A5 receives a POR signal, and the output of N2 is connected to the reset terminal of the second counter and B6.

[0060] Furthermore, in the XY direction sampling signal generating unit 32,

[0061] The first counter includes: cascaded triggers B1, B2, B3, B4 and B5, and a two-input AND gate A6; the D input terminals of B1, B2, B3, B4 and B5 are connected to At the output end, the CK input of B1 is connected to the output of A2, the Q output of B3 is connected to one input of A6, the Q output of B5 is connected to the other input of A6, and the output of A6 is connected to one input of A3;

[0062] The reset terminals of B1, B2, B3, B4 and B5 are connected to the reset signal. Figure 4 .

[0063] The second counter includes: cascaded flip-flops B7, B8, B9, B10, B11 and B12, and a two-input AND gate A7;

[0064] D input terminals for B7, B8, B9, B10, B11, and B12 Output terminal, CK input terminal of B7 is connected to output terminal of A2, Q output terminal of B10 is connected to one input terminal of A7, Q output terminal of B12 is connected to the other input terminal of A7, and output terminal of A7 outputs Y direction sampling signal; reset terminal of B7, B8, B9, B10, B11 and B12 is connected to reset signal. For the internal circuit wiring relationship of the second counter, please refer to Figure 5 .

[0065] The internal circuit connection relationship of the second combinational logic operation module 4 is as follows: Figure 6 As shown, it includes: an XY direction switching signal generating unit 41, a comparator enable signal generating unit 42 and a two-phase chopping signal generating unit 43; the input end of the XY direction switching signal generating unit 41 receives the fast clock signal and the EN signal, and the output end outputs the XY direction switching signal; the input end of the comparator enable signal generating unit 42 receives the EN signal, and the output end outputs the comparator enable signal; the input end of the two-phase chopping signal generating unit 43 receives the EN signal, and the output end outputs the two-phase chopping signal.

[0066] In the second combinational logic operation module 4, the XY direction switching signal generation unit 41 includes: a third counter, delay buffers E5 and E6, two-input AND gates A8 and A9, inverters N3 and N4, and a flip-flop B13. One input of A8 is connected to the F_CLK output of the fast clock circuit 1, the other input receives the EN signal, and the output is connected to the input of the third counter. The output of the third counter is connected to E5 and E6 in sequence, and the reset terminal is connected to the output of N3. The output of E6 is connected to one input of A9 and the CK input of B13.

[0067] The other input terminal of A9 is connected to the reset terminal of B13, and the output terminal is connected to the input terminal of N3; the D input terminal of B13 is connected to Output end, Q output end is connected to the input end of N4, and the output end of N4 outputs XY direction switching signal.

[0068] The comparator enable signal generating unit 42 includes: cascaded flip-flops B14, B15, B16 and B17, two-input AND gates A10, A11 and A12, three-input NAND gate A13, delay buffer E7, and inverter N5; the CK input terminal of B14 is connected to the output terminal of A8, the Q output terminal of B14 is connected to one input terminal of A10, the Q output terminal of B15 is connected to one input terminal of A11, and the Q output terminal of B17 is connected to the other input terminal of A10 and the other input terminal of A11; the output terminal of A11 is connected to E7 and N5 in sequence; the output terminal of N5 is connected to one input terminal of A12; the other input terminal of A12 is connected to the reset terminal of B13 and receives the EN signal, and the output terminal is connected to the reset terminals of B14, B15, B16 and B17; the D input terminals of B14, B15, B16 and B17 are connected Output terminal;

[0069] The two-phase chopping signal generating unit 43 includes: a trigger B18 and a two-phase non-overlapping clock generator; the CK input terminal of B18 is connected to the output terminal of A11, and the D input terminal is connected to The output end, the Q output end is connected to the input end of the two-phase non-overlapping clock generator; the reset end of B18 receives the EN signal; the output end of the two-phase non-overlapping clock generator outputs a two-phase chopping signal; the output ends of A8 and A10, and the PH2 output end of the two-phase non-overlapping clock generator are connected to the input end of A13, and the output end of A13 outputs a comparator enable signal.

[0070] The two-phase non-overlapping clock generator includes: inverters N6, N7, N8, N9, N10 and N11, two-input NAND gates A14 and A15, and delay buffers E8, E9, E10 and E11; N6 and N7 are connected in series and connected to one input terminal of A14, and the input terminal of N6 is connected to the Q output terminal of B18; the output terminal of A14 is connected to E8, E9, N8 and N9 in sequence, and the output terminal of N9 outputs the PH1 chopping signal; one input terminal of A15 is connected to the output terminal of N9, the other input terminal is connected to the output terminal of N6, and the output terminal is connected to E10, E11, N10 and N11 in sequence. The output terminal of N11 is connected to the other input terminal of A14 and outputs the PH2 chopping signal.

[0071] For the internal circuit connection relationship of the two-phase non-overlapping clock generator, please refer to Figure 7 .

[0072] It should be noted that, in the first combinational logic operation module 3 and the second combinational logic operation module 4, the delay buffer includes: a plurality of cascaded even-numbered inverters, and the driving buffer includes: a plurality of cascaded odd-numbered inverters.

[0073] Example 2

[0074] This embodiment provides a detection method for the signal detection circuit architecture of the two-dimensional AMR sensor switch chip as described in Example 1, wherein the logical relationship of the signal detection circuit architecture is as follows: Figure 8 As shown, the timing control method includes the following steps: Step 1: the slow clock circuit sends an S_CLK signal to the first combinational logic operation module;

[0075] Step 2: The fast clock circuit sends an F_CLK signal to the first combinational logic operation module;

[0076] Step 3: The first logic operation module performs a logic operation according to the S_CLK signal and the F_CLK signal, and outputs a detection enable signal and a sampling signal;

[0077] Step 4: The fast clock circuit sends an F_CLK signal to the second combinational logic operation module;

[0078] Step 5: The first combinational logic operation module sends an EN signal to the second combinational logic operation module;

[0079] Step 6: The second combinational logic operation module performs a logic operation according to the F_CLK signal and the EN signal, and outputs an XY direction switching signal, a comparator enable signal, and a two-phase chopping signal;

[0080] Step 7: Controlling the chip to perform signal detection according to the detection enable signal, the sampling signal, the XY direction switching signal, the output comparator enable signal, and the two-phase chopping signal.

[0081] However, it should be noted that the clock generating circuits, counters, delay devices, two-phase non-overlapping clock generators, etc. in this embodiment may also have many other embodiments. Without departing from the spirit and essence of the present invention, technical personnel familiar with this field can make various corresponding changes and / or deformations based on the present invention.

[0082] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A two-dimensional AMR sensor switch chip signal detection architecture, characterized in that: include: A fast clock circuit (1), a slow clock circuit (2), a first combinational logic operation module (3) and a second combinational logic operation module (4); The F_CLK output terminal of the fast clock circuit (1) is connected to the CLK_1 input terminal of the first combinational logic operation module (3) and the CLK input terminal of the second combinational logic operation module (4), and the S_CLK output terminal of the slow clock circuit (2) is connected to the CLK_2 input terminal of the first combinational logic operation module (3); The XY_SW input terminal of the first combination logic operation module (3) is connected to the XY_SW output terminal of the second combination logic operation module (4), the Sampling_X output terminal outputs an X-direction sampling signal, the Sampling_Y output terminal outputs a Y-direction sampling signal, and the EN output terminal is connected to the EN input terminal of the second combination logic operation module (4) and outputs a detection enable signal; The first combinational logic operation module (3) includes: a detection enable signal generation unit (31), an XY direction sampling signal generation unit (32) and a reset signal generation unit (33); The XY direction sampling signal generating unit (32) comprises: a two-input AND gate A2 and A3, a first counter and a second counter; one input end of A2 is connected to the F_CLK output end of the fast clock circuit, the other input end receives the POR signal, the output end is connected to the input end of the first counter, and the output end of the first counter is connected to one input end of A3; the other input end of A3 receives the XY direction switching signal, and the output end outputs the X direction sampling signal; the input end of the second counter is connected to the output end of A2, and the output end outputs the Y direction sampling signal; The input end of the reset signal generating unit (33) is connected to the output end of the XY direction sampling signal generating unit (32) and receives the POR signal, and the output end is connected to the detection enable signal generating unit (31) and the XY direction sampling signal generating unit; The XY_SW output terminal of the second combinational logic operation module (4) outputs an XY direction switching signal, the EN_comp output terminal outputs a comparator enable signal, and the chopping output terminal outputs a two-phase chopping signal; The second combinational logic operation module (4) includes: an XY direction switching signal generating unit (41), a comparator enable signal generating unit (42) and a two-phase chopping signal generating unit (43); The XY direction switching signal generating unit (41) comprises: a third counter, delay buffers E5 and E6, two-input AND gates A8 and A9, inverters N3 and N4, and a trigger B13; one input terminal of A8 is connected to the F_CLK output terminal of the fast clock circuit (1), the other input terminal receives the EN signal, and the output terminal is connected to the input terminal of the third counter; the output terminal of the third counter is connected to E5 and E6 in sequence, and the reset terminal is connected to the output terminal of N3; the output terminal of E6 is connected to one input terminal of A9 and the CK input terminal of B13; the other input terminal of A9 is connected to the reset terminal of B13, and the output terminal is connected to the input terminal of N3; the D input terminal of B13 is connected to Output end, Q output end is connected to the input end of N4, and the output end of N4 outputs XY direction switching signal; The comparator enable signal generating unit (42) receives an EN signal at its input terminal and outputs a comparator enable signal at its output terminal; The input end of the two-phase chopping signal generating unit (43) receives the EN signal, and the output end outputs the two-phase chopping signal.

2. A two-dimensional AMR sensor switch chip signal detection architecture according to claim 1, characterized in that: The detection enable signal generating unit (31) comprises: a two-input AND gate A1, a trigger B6 and a driving buffer D1 connected in sequence; one input end of A1 is connected to the S_CLK output end of the slow clock circuit, and the other input end receives a POR signal; and the output end of D1 outputs a detection enable signal.

3. The two-dimensional AMR sensor switch chip signal detection architecture according to claim 1, characterized in that: The reset signal generating unit (33) includes: a first reset signal generating circuit and a second reset signal generating circuit; The first reset signal generating circuit includes: delay buffers E1 and E2, a two-input AND gate A4, and an inverter N1; E1 and E2 are connected in series between the output terminal of the first counter and one input terminal of A4, the other input terminal of A4 receives the POR signal, and the output terminal of N1 is connected to the reset terminal of the first counter; The second reset signal generating circuit includes: delay buffers E3 and E4, a two-input AND gate A5 and an inverter N2; E3 and E4 are connected in series between the output terminal of the second counter and one input terminal of A5, the other input terminal of A5 receives the POR signal, and the output terminal of N2 is connected to the reset terminal of the second counter and B6.

4. The two-dimensional AMR sensor switch chip signal detection architecture according to claim 1, characterized in that: The first counter includes: cascaded triggers B1, B2, B3, B4 and B5, and a two-input AND gate A6; the D input terminals of B1, B2, B3, B4 and B5 are connected to Output terminal: the CK input terminal of B1 is connected to the output terminal of A2, the Q output terminal of B3 is connected to one input terminal of A6, the Q output terminal of B5 is connected to the other input terminal of A6, and the output terminal of A6 is connected to one input terminal of A3; the reset terminals of B1, B2, B3, B4 and B5 are connected to the reset signal; The second counter includes: cascaded triggers B7, B8, B9, B10, B11 and B12, and a two-input AND gate A7; the D input terminals of B7, B8, B9, B10, B11 and B12 are connected to Output end, the CK input end of B7 is connected to the output end of A2, the Q output end of B10 is connected to one input end of A7, the Q output end of B12 is connected to the other input end of A7, and the output end of A7 outputs the Y direction sampling signal; the reset terminals of B7, B8, B9, B10, B11 and B12 are connected to the reset signal.

5. The two-dimensional AMR sensor switch chip signal detection architecture according to claim 1, characterized in that: The comparator enable signal generating unit (42) comprises: cascaded triggers B14, B15, B16 and B17, two-input AND gates A10, A11 and A12, three-input NAND gate A13, delay buffer E7, and inverter N5; the CK input terminal of B14 is connected to the output terminal of A8, the Q output terminal of B14 is connected to one input terminal of A10, the Q output terminal of B15 is connected to one input terminal of A11, and the Q output terminal of B17 is connected to the other input terminal of A10 and the other input terminal of A11; the output terminal of A11 is connected to E7 and N5 in sequence; the output terminal of N5 is connected to one input terminal of A12; the other input terminal of A12 is connected to the reset terminal of B13 and receives the EN signal, and the output terminal is connected to the reset terminals of B14, B15, B16 and B17; the D input terminals of B14, B15, B16 and B17 are connected Output terminal; two-phase chopping signal generating unit (43) includes: trigger B18 and two-phase non-overlapping clock generator; B18 CK input terminal connected to the output terminal of A11, D input terminal connected The output end, the Q output end is connected to the input end of the two-phase non-overlapping clock generator; the reset end of B18 receives the EN signal; the output end of the two-phase non-overlapping clock generator outputs a two-phase chopping signal; the output ends of A8 and A10, and the PH2 output end of the two-phase non-overlapping clock generator are connected to the input end of A13, and the output end of A13 outputs a comparator enable signal.

6. The two-dimensional AMR sensor switch chip signal detection architecture according to claim 5, characterized in that: The two-phase non-overlapping clock generator includes: inverters N6, N7, N8, N9, N10 and N11, two-input NAND gates A14 and A15, and delay buffers E8, E9, E10 and E11; N6 and N7 are connected in series and connected to one input terminal of A14, and the input terminal of N6 is connected to the Q output terminal of B18; the output terminal of A14 is connected to E8, E9, N8 and N9 in sequence, and the output terminal of N9 outputs the PH1 chopping signal; one input terminal of A15 is connected to the output terminal of N9, the other input terminal is connected to the output terminal of N6, and the output terminal is connected to E10, E11, N10 and N11 in sequence. The output terminal of N11 is connected to the other input terminal of A14 and outputs the PH2 chopping signal.

7. A detection method for a signal detection architecture according to any one of claims 1 to 6, characterized in that: The following steps are involved: The slow clock circuit sends an S_CLK signal to the first combinational logic operation module; The fast clock circuit sends an F_CLK signal to the first combinational logic operation module; The first logic operation module performs a logic operation according to the S_CLK signal and the F_CLK signal, and outputs a detection enable signal and a sampling signal; The fast clock circuit sends an F_CLK signal to the second combinational logic operation module; The first combinational logic operation module sends an EN signal to the second combinational logic operation module; The second combinational logic operation module performs a logic operation according to the F_CLK signal and the EN signal, and outputs an XY direction switching signal, a comparator enable signal and a two-phase chopping signal; The control chip performs signal detection according to the detection enable signal, the sampling signal, the XY direction switching signal, the output comparator enable signal and the two-phase chopping signal.

Images