memory chip

Abstract

This application provides a memory chip, comprising: a one-time programmable region including a first SOT unit, a switching unit, and a data read unit, wherein a first terminal of the first SOT unit is electrically connected to a bit line, a second terminal of the first SOT unit is electrically connected to a first terminal of the switching unit, a second terminal of the switching unit is electrically connected to a source line, and a third terminal of the switching unit is electrically connected to a word line; the first SOT unit includes a first MTJ and a first spin-orbit matrix layer disposed by contacts; and a data storage region including a second SOT unit, a read unit, and a write unit, wherein a first terminal of the read unit and a first terminal of the write unit are respectively electrically connected to a source line, a second terminal of the read unit is electrically connected to a first terminal of the second SOT unit, a second terminal of the write unit is electrically connected to a second terminal of the second SOT unit, and a third terminal of the second SOT unit is electrically connected to a bit line; the second SOT unit includes at least one second MTJ and a second spin-orbit matrix layer disposed by contacts.

Description

Technical Field

[0001] This application relates to the field of memory, and more specifically, to a memory chip. Background Technology

[0002] Compared to traditional STT-MRAM (Spin-Torque Magnetic Random Access Memory), SOT-MRAM (Spin-Orbit Magnetic Random Access Memory) retains the excellent characteristics of MRAM, such as high speed and low power consumption, while achieving low write voltage and read / write path separation. It is expected to replace STT-MRAM, utilizing spin-orbit moments to achieve fast and reliable magnetization switching. Memory chips typically have a one-time programmable module to store the chip's configuration information (such as read and write conditions). Volatile chips usually use an eFuse as the one-time programmable module. MRAM, as a non-volatile memory, can use its memory cells (MTJs) to store configuration information, but applications often require it to withstand reflow soldering. Existing technologies for memory chips with configuration information storage capabilities have complex manufacturing processes and high production costs.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a memory chip to solve the problems of complex manufacturing process and high manufacturing cost of memory chips with storage configuration information function in the prior art.

[0005] To achieve the above objectives, according to one aspect of this application, a memory chip is provided, the memory chip including a one-time programmable region and a data storage region, wherein the one-time programmable region includes a first SOT unit, a switching unit, and a data read unit, a first terminal of the first SOT unit is electrically connected to a bit line, a second terminal of the first SOT unit is electrically connected to a first terminal of the switching unit, a second terminal of the switching unit is electrically connected to a source line, a third terminal of the switching unit is electrically connected to a word line, and the data read unit is electrically connected to either the first terminal of the switching unit or the third terminal of the first SOT unit, the first SOT unit including a first MTJ and a first spin-orbit matrix layer disposed in contact; the data storage region includes a second SOT unit, a read unit, and a write unit, the first terminals of the read unit and the write unit are respectively electrically connected to the source line, the second terminal of the read unit is electrically connected to the first terminal of the second SOT unit, the second terminal of the write unit is electrically connected to the second terminal of the second SOT unit, the third terminal of the second SOT unit is electrically connected to a bit line, and the second SOT unit includes at least one second MTJ and a second spin-orbit matrix layer disposed in contact.

[0006] Optionally, the second end of the first MTJ is the first end of the first SOT unit, the second end of the first spin-orbit moment layer is the second end of the first SOT unit, the third end of the first spin-orbit moment layer is the third end of the first SOT unit, the data reading unit is electrically connected to the third end of the first SOT unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer; there is one second MTJ, the second end of the second MTJ is the first end of the second SOT unit, the second end of the second spin-orbit moment layer is the second end of the second SOT unit, the third end of the second spin-orbit moment layer is the third end of the second SOT unit, and the first end of the second MTJ is electrically connected to the first end of the second spin-orbit moment layer.

[0007] Optionally, the second end of the first spin-orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, the data reading unit is electrically connected to the first end of the switching unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer; there is one second MTJ, the second end of the second spin-orbit moment layer is the first end of the second SOT unit, the second end of the second MTJ is the second end of the second SOT unit, and the first end of the second MTJ is electrically connected to the first end of the second spin-orbit moment layer.

[0008] Optionally, the second end of the first MTJ is the first end of the first SOT unit, the second end of the first spin-orbit moment layer is the second end of the first SOT unit, the third end of the first spin-orbit moment layer is the third end of the first SOT unit, the data reading unit is electrically connected to the third end of the first SOT unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer; there are multiple second MTJs, the second end of the multiple second MTJs is the first end of the second SOT unit, the second end of the second spin-orbit moment layer is the second end of the second SOT unit, the third end of the second spin-orbit moment layer is the third end of the second SOT unit, and the first end of the second MTJ is electrically connected to the first end of the second spin-orbit moment layer.

[0009] Optionally, the second end of the first spin-orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, the data reading unit is electrically connected to the first end of the switching unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer; the second end of the second spin-orbit moment layer is the first end of the second SOT unit, there are multiple second MTJs, the second ends of the multiple second MTJs are the second ends of the second SOT unit, and the first ends of the second MTJs are electrically connected to the first end of the second spin-orbit moment layer.

[0010] Optionally, the first SOT unit further includes a through-hole structure and an insulating dielectric layer. The through-hole structure penetrates the insulating dielectric layer perpendicularly. The insulating dielectric layer contacts the surface of the first spin orbital moment layer away from the first MTJ. The first end of the through-hole structure contacts the surface of the first spin orbital moment layer away from the first MTJ. The second end of the through-hole structure is the second end of the first SOT unit. The projection of the through-hole structure onto a predetermined plane is located in the structural layer of the first MTJ. The predetermined plane is the plane where the first MTJ is located.

[0011] Optionally, the read unit includes at least one read word line and at least one first transistor, the gate of the first transistor and the read word line are connected in a one-to-one correspondence, the source of the first transistor is electrically connected to the source line, and the drain of the first transistor is electrically connected to the second MTJ in a one-to-one correspondence. The write unit includes a second transistor and a write word line, the gate of the second transistor and the write word line are electrically connected, the source of the second transistor is electrically connected to the source line, and the drain of the second transistor is electrically connected to the second spin-orbit matrix.

[0012] Optionally, the switching unit is a third transistor, the gate of the third transistor is electrically connected to the word line, the source of the third transistor is electrically connected to the source line, and the drain of the third transistor is electrically connected to the through-hole structure.

[0013] Optionally, the first spin orbital moment layer and the second spin orbital moment layer have the same structure. The material of the first spin orbital moment layer in contact with the first MTJ is a heavy metal material layer, and the material of the second spin orbital moment layer in contact with the second MTJ is a heavy metal material layer. The heavy metal material layer includes any one of platinum, tantalum, tungsten, iridium, hafnium, ruthenium, thallium, bismuth, gold, titanium, and osmium.

[0014] Optionally, the first MTJ includes a first free layer, a first barrier layer and a first pinning layer stacked in sequence, and the second MTJ includes a second free layer, a second barrier layer and a second pinning layer stacked in sequence, wherein the first free layer is in contact with the first spin-orbit moment layer, and the second free layer is in contact with the second spin-orbit moment layer.

[0015] Optionally, the first MTJ further includes a first top electrode or a first bottom electrode. When the second end of the first MTJ is the first end of the first SOT unit, the first MTJ includes the first top electrode, which is electrically connected to the bit line. When the second end of the first MTJ is the second end of the first SOT unit, the first MTJ includes the first bottom electrode, which is electrically connected to the switching unit. The second MTJ further includes a second top electrode or a second bottom electrode. When the second end of the second MTJ is the first end of the second SOT unit, the second MTJ includes the second top electrode, which is electrically connected to the read unit. When the second end of the second MTJ is the second end of the second SOT unit, the second MTJ includes the second bottom electrode, which is electrically connected to the write unit.

[0016] Optionally, the through-hole structure includes a conductive through-hole and a filling material, wherein the filling material is a low-resistance conductive material.

[0017] This application provides a memory chip, comprising a one-time programmable region and a data storage region. The one-time programmable region includes a first SOT unit, a switching unit, and a data reading unit. The first SOT unit includes a first MTJ and a first spin-orbit moment layer (SMT) with contact settings. The data storage region includes a second SOT unit, a read unit, and a write unit. The second SOT unit includes at least one second MTJ and a second SMT layer with contact settings. The memory chip can store chip configuration information through the one-time programmable region and the data storage region. The one-time programmable region and the data storage region share the same basic SOT unit structure. Compared to existing technologies, this memory chip, while possessing the function of storing configuration information, does not require an additional photomask. Both the one-time programmable region and the data storage region can be manufactured simultaneously, resulting in a simpler manufacturing process. This effectively controls the chip's manufacturing cost and alleviates the problems of complex manufacturing processes and high manufacturing costs associated with existing memory chips that have configuration information storage capabilities. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 A schematic diagram of the structure of a memory chip according to an embodiment of this application is shown;

[0020] Figures 2 to 4 Schematic diagrams of the structure of memory chips according to three specific embodiments of this application are shown respectively;

[0021] Figure 5(a) shows a side view of the structure of a memory chip according to a specific embodiment of this application;

[0022] Figure 5(b) shows a top view of the structure of a memory chip according to a specific embodiment of this application;

[0023] Figure 6 A schematic diagram of the structure of a memory chip according to a specific embodiment of this application is shown.

[0024] The above figures include the following reference numerals:

[0025] 10. One-time programmable area; 20. Data storage area; 100. First SOT unit; 101. Switching unit; 102. Data reading unit; 103. First MTJ; 104. First spin-orbit layer; 105. Insulating dielectric layer; 106. Conductive via; 107. First pinning layer; 108. First barrier layer; 109. First free layer; 110. First bottom electrode; 111. First top electrode; 200. Second SOT unit; 201. First transistor; 202. Second transistor; 203. Second MTJ; 204. Second spin-orbit layer; 205. Second pinning layer; 206. Second barrier layer; 207. Second free layer; 208. Second bottom electrode; 209. Second top electrode. Detailed Implementation

[0026] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0027] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0029] As described in the background section, the manufacturing process of existing memory chips with configuration information storage functions is complex and the manufacturing cost is high. In order to solve the above problems, this application proposes a memory chip.

[0030] According to a typical embodiment of this application, a memory chip is provided. Figure 1 A schematic diagram of the structure of a memory chip according to an embodiment of this application is shown, such as... Figure 1As shown, the memory chip includes a one-time programmable region 10 and a data storage region 20. The one-time programmable region 10 includes a first SOT unit 100, a switching unit 101, and a data read unit 102. The first terminal of the first SOT unit 100 is electrically connected to a bit line, the second terminal of the first SOT unit 100 is electrically connected to the first terminal of the switching unit 101, the second terminal of the switching unit 101 is electrically connected to a source line, and the third terminal of the switching unit 101 is electrically connected to a word line. The data read unit 102 is electrically connected to either the first terminal of the switching unit 101 or the third terminal of the first SOT unit 100. That is, the data read unit 102 can be connected in two ways: firstly, the data read unit 102 is electrically connected to the first terminal of the switching unit 101, such as... Figure 1 As shown; secondly, the data reading unit 102 is electrically connected to the third terminal of the first SOT unit 100. Figure 1 (Not shown in the diagram); the first SOT unit 100 includes a first MTJ 103 and a first spin-orbit layer 104 that are contacted together; the data storage area 20 includes a second SOT unit 200, a read unit, and a write unit. The first end of the read unit and the first end of the write unit are electrically connected to the source line, respectively. The second end of the read unit is electrically connected to the first end of the second SOT unit 200. The second end of the write unit is electrically connected to the second end of the second SOT unit 200. The third end of the second SOT unit 200 is electrically connected to the bit line. The second SOT unit 200 includes at least one second MTJ 203 and a second spin-orbit layer 204 that are contacted together.

[0031] The aforementioned memory chip includes a primary programmable region and a data storage region. The primary programmable region includes a first SOT unit, a switching unit, and a data read unit 102. The first SOT unit includes a first MTJ and a first spin-orbit matrix layer with contact settings. The data storage region includes a second SOT unit, a read unit, and a write unit. The second SOT unit includes at least one second MTJ and a second spin-orbit matrix layer with contact settings. The aforementioned memory chip can store chip configuration information through the primary programmable region and the data storage region. Furthermore, the primary programmable region and the data storage region share the same basic SOT unit structure. Compared to existing technologies, this memory chip, while possessing the function of storing configuration information, does not require an additional photomask and can simultaneously manufacture the primary programmable region and the data storage region. The manufacturing process is relatively simple, effectively controlling the chip manufacturing cost and alleviating the problems of complex manufacturing processes and high manufacturing costs associated with existing memory chips that have configuration information storage functions.

[0032] Of course, the positional relationship between the first MTJ and the first spin-orbit moment layer is not limited to the above. Figure 1 The positional relationships shown above, including the positional relationships of the second MTJ and the second spin-orbit moment layer, are not limited to those described above. Figure 1 The positional relationships shown are illustrated.

[0033] According to a specific embodiment of this application, the second end of the first MTJ is the first end of the first SOT unit, the second end of the first spin-orbit matrix layer is the second end of the first SOT unit, the third end of the first spin-orbit matrix layer is the third end of the first SOT unit, the data reading unit 102 is electrically connected to the third end of the first SOT unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit matrix layer; there is one second MTJ, the second end of the second MTJ is the first end of the second SOT unit, the second end of the second spin-orbit matrix layer is the second end of the second SOT unit, the third end of the second spin-orbit matrix layer is the third end of the second SOT unit, and the first end of the second MTJ is electrically connected to the first end of the second spin-orbit matrix layer. In this memory chip, the first SOT unit and the second SOT unit have the same structure, which further ensures that the manufacturing process of the memory chip is relatively simple, further ensures that the manufacturing cost of the memory chip is low, and further alleviates the problem of complex manufacturing process and high manufacturing cost of existing memory chips with storage configuration information functions.

[0034] According to another specific embodiment of this application, the second end of the first spin-orbit matrix layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, the data reading unit 102 is electrically connected to the first end of the switching unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit matrix layer; there is one second MTJ, the second end of the second spin-orbit matrix layer is the first end of the second SOT unit, the second end of the second MTJ is the second end of the second SOT unit, and the first end of the second MTJ is electrically connected to the first end of the second spin-orbit matrix layer. In the above-mentioned memory chip, the first SOT unit and the second SOT unit have the same structure, which further ensures that the manufacturing process of the memory chip is relatively simple, further ensures that the manufacturing cost of the memory chip is low, and further alleviates the problem of complex manufacturing process and high manufacturing cost of existing memory chips with storage configuration information functions.

[0035] In practical applications, the sizes of the first MTJ and the second MTJ can be the same or different, and the widths of the first spin orbital moment layer and the second spin orbital moment layer can be the same or different.

[0036] In another specific embodiment of this application, the second end of the first MTJ is the first end of the first SOT unit, the second end of the first spin-orbit moment layer is the second end of the first SOT unit, the third end of the first spin-orbit moment layer is the third end of the first SOT unit, the data reading unit 102 is electrically connected to the third end of the first SOT unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer. There are multiple second MTJs, with the second end of each second MTJ being the first end of a second SOT unit, the second end of the second spin-orbit moment layer being the second end of the second SOT unit, the third end of the second spin-orbit moment layer being the third end of the second SOT unit, and the first end of each second MTJ being electrically connected to the first end of the second spin-orbit moment layer. The memory chip includes multiple second MTJs. While ensuring a relatively simple manufacturing process, the multiple second MTJs enable better performance of the storage configuration information in the data storage area, ensuring that the chip has a good ability to store configuration information.

[0037] According to another specific embodiment of this application, the second end of the first spin-orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, the data reading unit is electrically connected to the first end of the switching unit, and the first end of the first MTJ is electrically connected to the first end of the first spin-orbit moment layer; the second end of the second spin-orbit moment layer is the first end of the second SOT unit, and there are multiple second MTJs, with the second ends of the multiple second MTJs being the second ends of the second SOT units, and the first ends of the second MTJs being electrically connected to the first end of the second spin-orbit moment layer. The memory chip includes multiple second MTJs, which, while ensuring a relatively simple manufacturing process, improves the performance of the storage configuration information in the data storage area, thus ensuring that the chip has a good ability to store configuration information.

[0038] In practical applications, the first SOT unit further includes a through-hole structure and an insulating dielectric layer. The through-hole structure penetrates the insulating dielectric layer vertically. The insulating dielectric layer contacts the surface of the first spin orbital moment layer that is away from the first MTJ. The first end of the through-hole structure contacts the surface of the first spin orbital moment layer that is away from the first MTJ. The second end of the through-hole structure is the second end of the first SOT unit. The projection of the through-hole structure onto a predetermined plane is located in the structural layer of the first MTJ. The predetermined plane is the plane where the first MTJ is located. The aforementioned first SOT unit includes a via structure and an insulating dielectric layer, with the via structure perpendicularly penetrating the insulating dielectric layer. The projection of the via structure onto a predetermined plane is located within the structural layer of the aforementioned first MTJ. The via structure provides a conductive path perpendicular to the aforementioned first spin orbital layer, thereby ensuring that the read / write current of the aforementioned primary programmable region is perpendicular to the aforementioned first spin orbital layer. This effectively avoids the read window disturbance caused by the lateral resistance of the aforementioned first spin orbital layer. Simultaneously, through the via structure and the breakdown characteristics of the aforementioned first MTJ, the aforementioned primary programmable region can possess good reflow soldering resistance, thereby effectively mitigating the problem of data loss in the aforementioned primary programmable region after reflow soldering.

[0039] Of course, the first end of the aforementioned through-hole structure can also contact the surface of the first MTJ that is away from the first spin orbital moment layer, the second end of the aforementioned through-hole structure is the second end of the aforementioned first SOT unit, and the projection of the aforementioned through-hole structure on a predetermined plane is located in the structural layer of the aforementioned first MTJ, the aforementioned predetermined plane being the plane where the aforementioned first MTJ is located.

[0040] In order to further reduce the impact of read window disturbance on the memory chip and further enhance the memory chip's ability to withstand reflow soldering, in actual applications, the projection of the via structure on the plane where the first MTJ is located is located at the center of the structural layer of the first MTJ, and the distance from the center of the projection to the center of the structural layer of the first MTJ is less than 50nm.

[0041] According to another specific embodiment of this application, the read unit includes at least one read word line and at least one first transistor. The gate of the first transistor is connected to the read word line in a one-to-one correspondence. The source of the first transistor is electrically connected to the source line in a one-to-one correspondence. The drain of the first transistor is electrically connected to the second MTJ in a one-to-one correspondence. The write unit includes a second transistor and a write word line. The gate of the second transistor is electrically connected to the write word line. The source of the second transistor is electrically connected to the source line in a one-to-one correspondence. The drain of the second transistor is electrically connected to the second spin orbital layer.

[0042] Of course, the above-mentioned read unit may also include read word lines and other devices, and the above-mentioned write unit may also include write word lines and other devices.

[0043] In practical applications, the aforementioned switching unit may include any device with switching function. Those skilled in the art can select according to actual needs. In another specific embodiment of this application, the aforementioned switching unit is a third transistor. The gate of the aforementioned third transistor is electrically connected to the aforementioned word line, the source of the aforementioned third transistor is electrically connected to the source line, and the drain of the aforementioned third transistor is electrically connected to the aforementioned through-hole structure.

[0044] The memory chip in this application utilizes the high resistance value (typically greater than 5 × 10⁻⁶) of the MTJ device before breakdown. 3 The first programmable region (SOT) exhibits low resistance (typically less than 200 ohms) after breakdown, allowing information to be read from the memory cell. In practical applications, the state of the first MTJ must be changed by a current parallel to the interface between the heavy metal layer and the first MTJ. When a voltage is applied across the SOT, the resistances of the first SOT cell and the switching unit form a voltage divider. When the voltage across the first SOT cell is sufficiently large, it causes the barrier layer to break down. After breakdown, the first SOT cell is short-circuited, and the SOT is in a programming state with a resistance of approximately 100 ohms. The on-resistance of the switching unit is approximately 500 ohms, and the output data state is state 1. During the reading process, the pinned layer and free layer of the first MTJ in the first SOT cell are not short-circuited, and the magnetization directions of the two layers are the same or opposite, with corresponding resistances of Rp or Rap, respectively. The on-resistance of the transistor is approximately 500 ohms, and the data read unit outputs data in state 0. During the reading process of the programmable region, the current passes through the first MTJ and then vertically through the first spin orbital layer. With the through-hole structure, the spin orbital and through-hole structures pass vertically, which makes the high resistivity heavy metal layer material contribute very little series resistance, and its impact on the voltage divider circuit is negligible.

[0045] In practical applications, both the first and second spin-orbit spacers are multi-layered structures in the vertical direction. The first and second spin-orbit spacers have identical structures. The material in contact with the first MTJ in the first spin-orbit spacer is a heavy metal layer, and the material in contact with the second MTJ in the second spin-orbit spacer is also a heavy metal layer. These heavy metal layers include any one of platinum, tantalum, tungsten, iridium, hafnium, ruthenium, thallium, bismuth, gold, titanium, and osmium. This ensures that both the first and second spin-orbit spacers have relatively high surface resistivity in contact with the first and second MTJs, facilitating the generation of the spin-orbit distance effect and enabling relatively rapid and reliable magnetization reversal between the first and second MTJs.

[0046] Of course, the material of the first spin orbital layer that is in contact with the first MTJ can also be other heavy metal materials, and the material of the second spin orbital layer that is in contact with the second MTJ can also be other heavy metal materials.

[0047] In one specific embodiment, the second bottom electrode first MTJ includes a first free layer, a first barrier layer, and a first pinned layer stacked sequentially. The second bottom electrode second MTJ includes a second free layer, a second barrier layer, and a second pinned layer stacked sequentially. The first free layer of the second bottom electrode is in contact with the first spin-orbit moment layer of the second bottom electrode, and the second free layer of the second bottom electrode is in contact with the second spin-orbit moment layer of the second bottom electrode. Through the contact between the first free layer of the first MTJ and the first spin-orbit moment layer, and the contact between the second free layer of the second MTJ and the second spin-orbit moment layer, the generation of the spin-orbit moment effect is further ensured, thereby achieving rapid magnetization reversal of the first MTJ and the second MTJ.

[0048] In another specific embodiment of this application, the second bottom electrode first MTJ further includes a first top electrode or a first bottom electrode. When the second end of the second bottom electrode first MTJ is the first end of the second bottom electrode first SOT unit, the second bottom electrode first MTJ includes a second bottom electrode first top electrode, which is electrically connected to the bit line. When the second end of the second bottom electrode first MTJ is the second end of the second bottom electrode first SOT unit, the second bottom electrode first MTJ includes a second bottom electrode first bottom electrode, which is electrically connected to the second bottom electrode switching unit. This ensures that when the first MTJ is electrically connected to the bit line, the first MTJ is electrically connected to the bit line through the top electrode; and when the first MTJ is electrically connected to the switching unit, the first MTJ is electrically connected to the switching unit through the bottom electrode. The second bottom electrode, the second MTJ, also includes a second top electrode or a second bottom electrode. When the second end of the second bottom electrode, the second MTJ, is the first end of the second SOT unit, the second bottom electrode, the second MTJ, includes a second bottom electrode and a second top electrode, which are electrically connected to the second bottom electrode read unit. When the second end of the second bottom electrode, the second MTJ, is the second end of the second bottom electrode, the second MTJ, the second bottom electrode, the second bottom electrode, is electrically connected to the write unit. This ensures that when the second MTJ is electrically connected to the read unit, it is electrically connected to the read unit through the second top electrode. When the second MTJ is electrically connected to the write unit, it is electrically connected to the write unit through the second bottom electrode.

[0049] In practical applications, when the first SOT unit includes a through-hole structure and the through-hole structure is in contact with the first MTJ, the first MTJ is electrically connected to the switching unit through the through-hole structure. The through-hole structure is equivalent to the bottom electrode of the first MTJ. At this time, the first MTJ may not include the first bottom electrode.

[0050] According to another specific embodiment of this application, the via structure includes a conductive via and a filling material, wherein the filling material is a low-resistance conductive material. The use of a low-resistance conductive material as the filling material ensures better accuracy in reading data from the programmable area.

[0051] In one specific embodiment, the filler includes copper (Cu) and / or tungsten (W). Of course, the filler may also include other low-resistivity metal materials.

[0052] To enable those skilled in the art to better understand the technical solution of this application, specific embodiments will be used for illustration below.

[0053] Example 1

[0054] Generated as Figure 2 The diagram shows the structure of a memory chip. The first MTJ includes a first top electrode 111, a first pinning layer 107, a first barrier layer 108, and a first free layer 109. The second MTJ includes a second top electrode 209, a second pinning layer 205, a second barrier layer 206, and a second free layer 207. The write unit includes a second transistor 202 and a write word line WWL. The read unit includes a read word line RWL and a first transistor 201. The first spin-orbit layer 104 is electrically connected to the data read unit 102. The switching unit 101 is a third transistor. The first SOT unit includes a via structure and an insulating dielectric layer 105. The via structure includes a conductive via 106 and a filling material. The second spin-orbit layer 204 is electrically connected to the second transistor 202. Data read and write operations in the primary programmable area are performed through two independent channels, while data read and write operations in the data storage area are performed through a single channel.

[0055] By creating the conductive via 106 on the first spin orbital layer 104 and connecting it to the data readout unit 102, when a programming voltage V is applied to the bit line BL... BL When crossing the aforementioned programmable region, the voltage V across the first SOT unit... SOT It is determined by the following equation:

[0056]

[0057] Among them, R HM Rvia is the resistance of the first spin orbital layer 104 perpendicular to the direction of the first SOT unit, and Rvia is the resistance of the via structure. MOS R is the resistance when the third transistor is turned on. SOT The resistor is the first SOT unit mentioned above.

[0058] Because the first spin orbital moment layer 104 is very thin in the direction perpendicular to the first SOT unit, R HM If the resistance is low (approximately 10 ohms), and the conductive via 106 is filled with a low-resistance metallic material such as Cu or W, with a resistance of only a few ohms, then:

[0059]

[0060] When V SOT When the value is lower than the breakdown voltage of the first SOT cell, the output data status is 0; when V... SOT When the voltage is large enough, the device breaks down, and the output data state becomes 1.

[0061] Of course, the aforementioned switching unit may also include other devices, and the aforementioned first transistor and the aforementioned second transistor may also be other devices.

[0062] Example 2

[0063] Generated as Figure 3 The diagram shows the structure of a memory chip. The first MTJ includes a first top electrode 111, a first pinning layer 107, a first barrier layer 108, and a first free layer 109. The second MTJ includes a second top electrode 209, a second pinning layer 205, a second barrier layer 206, and a second free layer 207. The write unit includes a second transistor 202 and a write word line WWL. The read unit includes a read word line RWL and a first transistor 201. The switching unit 101 is a third transistor and is electrically connected to the data read unit 102, meaning data is read from the drain of the third transistor. The first SOT unit includes a via structure and an insulating dielectric layer 105. The via structure includes a conductive via 106 and a filling material. The second spin-orbit layer 204 is electrically connected to the second transistor 202. Data read and write operations in the primary programmable area are performed through two independent channels, while data read and write operations in the data storage area are performed through a single channel.

[0064] The conductive via 106 is filled with a low-resistance metal material such as Cu or W, with a resistance of only a few ohms, which does not affect the accuracy of data reading. At the same time, the conductive via 106 of the first MTJ and the conductive via 106 of the data reading unit can be integrated in the same process, which can reduce the difficulty and cost of process integration.

[0065]

[0066] Of course, the aforementioned switching unit may also include other devices, and the aforementioned first transistor and the aforementioned second transistor may also be other devices.

[0067] Example 3

[0068] Generated as Figure 4The diagram shows the structure of a memory chip. The first MTJ includes a first pinning layer 107, a first barrier layer 108, a first free layer 109, and a first bottom electrode 110. The second MTJ includes a second pinning layer 205, a second barrier layer 206, a second free layer 207, and a second bottom electrode 208. The write unit includes a second transistor 202 and a write word line WWL. The read unit includes a read word line RWL and a first transistor 201. The first spin orbital layer 104 is electrically connected to the bit line and is located above the first MTJ. The switching unit 101... The third transistor is used. The data read unit 102 is electrically connected to the switching unit 101, meaning data is read from the drain of the third transistor. The second spin-orbit layer 204 is located above the second MTJ. One end of the second spin-orbit layer 204 is electrically connected to the bit line, and the other end is electrically connected to the first transistor 201. The first SOT cell includes a via structure and an insulating dielectric layer 105. The via structure includes a conductive via 106 and a filling material. The second spin-orbit layer 204 is electrically connected to the second transistor 202. Data read and write operations in the primary programmable area are performed through two independent channels, while data read and write operations in the data storage area are performed through a single channel.

[0069] When the first spin-orbit layer 104 is above the first MTJ device, the first pinning layer 107 is electrically connected to the first bottom electrode 110. When the first MTJ does not include the first bottom electrode 110, the first pinning layer 107 is electrically connected to the conductive via 106. The first free layer 109 is above the first barrier layer 108, and the first spin-orbit layer 104 is connected to the bit line BL. The data readout unit 102 is connected from the drain of the third transistor or from the first bottom electrode 110 of the first MTJ, and determines the state of the first SOT unit through an amplifier. The voltage divider expression of the first SOT unit is:

[0070]

[0071] Of course, the aforementioned switching unit may also include other devices, and the aforementioned first transistor and the aforementioned second transistor may also be other devices. In the case that the aforementioned first SOT unit includes the aforementioned through-hole structure, the aforementioned first MTJ may not include the aforementioned first bottom electrode.

[0072] Example 4

[0073] A memory chip structure diagram as shown in Figure 5 is generated. Figure 5(a) is a top view of the memory chip, and Figure 5(b) is a side view of the memory chip. The first MTJ103 includes a first top electrode 111, a first pinning layer 107, a first barrier layer 108, and a first free layer 109. The second MTJ203 includes a second top electrode 209, a second pinning layer 205, a second barrier layer 206, and a second free layer 207. In the primary programmable region unit, the switching unit 101 is a third transistor. The drain of the third transistor is connected to the first spin-orbit layer 104, and the source of the third transistor is connected to the source line SL. The gate is connected to the word line WL. The data read unit 102 is connected to one end of the first spin-orbit matrix layer 104. The first MTJ 103 is located above the first spin-orbit matrix layer 104. The width of the first spin-orbit matrix layer 104 is greater than the size of the first MTJ 103, such that the resistance per unit length of the first spin-orbit matrix layer 104 is much lower than the resistance per unit length of the second spin-orbit matrix layer 204, and the total resistance of the first spin-orbit matrix layer 104 is much lower than the resistance of the first MTJ 103. The first spin-orbit matrix layer 104 is connected to the first free layer 109 of the first MTJ 103, and the first MTJ 103 is connected to the bit line BL. Preferably, the width of the first spin-orbit layer 104 of the primary programmable region is approximately twice the width of the second spin-orbit layer 204 of the data storage region, such that the resistance per unit length of the first spin-orbit layer 104 is more than 50% smaller than the resistance per unit length of the second spin-orbit layer 204, and the device dimensions of the primary programmable region and the data storage region are consistent. The read unit includes a read word line RWL and a first transistor 201, and the write unit includes a second transistor 202 and a write word line WWL.

[0074] For the aforementioned programmable region cell, the voltage V of the first SOT cell is... SOT The expression is:

[0075]

[0076] Among them, R HM R is the resistor of the first spin-orbit layer 104 between the data reading unit and the first SOT unit. MOS R is the resistance when the third transistor is turned on. SOT V is the resistance of the first SOT unit mentioned above. BL This refers to the voltage applied to the bit line.

[0077] In the aforementioned programmable region, R HM The resistance is approximately 500 ohms, RMOS The resistance is approximately 500 ohms, and the voltage V of the first SOT unit mentioned above is... SOT As the value increases, the aforementioned programmable area unit is more prone to breakdown. When the aforementioned first SOT unit does not break down, it is in a parallel or antiparallel state, with a resistance of 5000 or 10000 ohms, an output voltage of low level, and a state of "0"; when the aforementioned first SOT unit breaks down, its resistance is approximately 100 ohms, the output level is high level, and the state is "1".

[0078] Compared with Embodiment 3, the memory chip in this embodiment does not include a through-hole structure. The data reading unit 102 is directly electrically connected to the first spin orbital layer 104. By making the resistance per unit length of the first spin orbital layer 104 much lower than the resistance per unit length of the second spin orbital layer 204, and the total resistance of the first spin orbital layer 104 much lower than the resistance of the first MTJ 103, the one-time programmable area can work well, thereby ensuring good performance of the memory chip.

[0079] Of course, the aforementioned switching unit may also include other devices, and the aforementioned first transistor and the aforementioned second transistor may also be other devices.

[0080] Example 5

[0081] A memory chip structure diagram as shown in Figure 5 was generated. Figure 5(a) is a top view of the memory chip, and Figure 5(b) is a side view of the memory chip. The switching unit 101 is a third transistor. In the primary programmable region, the drain of the third transistor is connected to the first spin-orbit matrix 104, the source of the third transistor is connected to the source line SL, and the gate of the third transistor is connected to the word line WL. The data read unit 102 is connected to one end of the first spin-orbit matrix 104. The first MTJ 103 is located above the first spin-orbit matrix 104. The width of the first spin-orbit matrix 104 is greater than the size of the first MTJ 103, resulting in a resistance per unit length of the first spin-orbit matrix 104 that is much lower than the resistance per unit length of the second spin-orbit matrix 204, and the total resistance of the first spin-orbit matrix 104 is much smaller than the resistance of the first MTJ 103. The first spin-orbit layer 104 is connected to the first free layer 109 of the first MTJ 103, and the first MTJ 103 is connected to the bit line BL. Preferably, the size of the first MTJ 103 in the primary programmable region is about 20% smaller than the size of the second MTJ 203 in the data storage region, such that the device resistance of the primary programmable region is more than 40% greater than the device resistance of the data storage region; the size of the first spin-orbit layer 104 in the primary programmable region is the same as that of the second spin-orbit layer 204 in the data storage region. The read unit includes a read word line RWL and the first transistor 201, and the write unit includes the second transistor 202 and the write word line WWL.

[0082] For the aforementioned programmable region, the voltage V of the first SOT unit SOT The expression is:

[0083]

[0084] Where R HM R is the resistor of the first spin-orbit layer 104 between the data reading unit and the first SOT unit. MOS R is the resistance when the third transistor is turned on. SOT V is the resistance of the first SOT unit mentioned above. BL This refers to the voltage applied to the bit line.

[0085] The above-mentioned one-time programmable region R HM The resistance is approximately 1000 ohms, and the resistance of the first SOT unit is approximately 7800 or 15600 ohms. The voltage divider V of the first SOT unit... SOTAs the value increases, the aforementioned programmable area is more prone to breakdown. When the first SOT unit is not broken down, it is in a parallel or antiparallel state, the output voltage is low, and the state is "0"; when the first SOT unit breaks down, its resistance is approximately 100 ohms, the output level is high, and the state is "1".

[0086] Compared with Embodiment 3, the memory chip in this embodiment does not include a through-hole structure. The data reading unit 102 is directly electrically connected to the first spin orbital layer 104. By making the resistance per unit length of the first spin orbital layer 104 much lower than the resistance per unit length of the second spin orbital layer 204, and the total resistance of the first spin orbital layer 104 much lower than the resistance of the first MTJ 103, the one-time programmable area can work well, thereby ensuring good performance of the memory chip.

[0087] Of course, the aforementioned switching unit may also include other devices, and the aforementioned first transistor and the aforementioned second transistor may also be other devices.

[0088] Example 6

[0089] Generate as Figure 6 The diagram shows a memory chip structure where there are multiple second MTJs, a read unit includes multiple read word lines (RWLs) and multiple first transistors (201s), a switch unit (101) is a third transistor, and a write unit includes a second transistor (202) and a write word line (WWL). Each second MTJ is connected to a corresponding first transistor (201). The data storage area can be implemented using a NAND-like SOT (NAND flash memory transistor) array. The primary programmable area can be implemented using any of the above embodiments, including using the conductive via structure, increasing the width of the first spin orbital layer, or reducing the size of the first MTJ in the primary programmable area. The data read unit (102) can be connected to the drain of the third transistor or to the first spin orbital layer (104).

[0090] Of course, the aforementioned switching unit may also include other devices, and the aforementioned first transistor and the aforementioned second transistor may also be other devices.

[0091] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0092] This application provides a memory chip, which includes a primary programmable region and a data storage region. The primary programmable region includes a first SOT unit, a switching unit, and a data reading unit. The first SOT unit includes a first MTJ and a first spin-orbit layer with contacts. The data storage region includes a second SOT unit, a read unit, and a write unit. The second SOT unit includes at least one second MTJ and a second spin-orbit layer with contacts. This memory chip can store chip configuration information through the primary programmable region and the data storage region. The primary programmable region and the data storage region share the same basic SOT unit structure. Compared to existing technologies, this memory chip, while possessing the function of storing configuration information, does not require an additional photomask and can simultaneously manufacture the primary programmable region and the data storage region. The manufacturing process is relatively simple, effectively controlling the chip manufacturing cost and alleviating the problems of complex manufacturing processes and high manufacturing costs associated with existing memory chips with configuration information storage functions.

[0093] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory chip, characterized by, The application relates to a memory cell, comprising: a one-time programmable region, comprising a first SOT unit, a switch unit and a data reading unit, a first end of the first SOT unit being electrically connected with a bit line, a second end of the first SOT unit being electrically connected with a first end of the switch unit, a second end of the switch unit being electrically connected with a source line, a third end of the switch unit being electrically connected with a word line, the data reading unit being electrically connected with the first end of the switch unit or the third end of the first SOT unit, the first SOT unit comprising a first MTJ and a first spin-orbit torque layer arranged in contact; when a voltage is applied across the one-time programmable region, the resistance of the first SOT unit and the switch unit forms a voltage divider, when the voltage across the first SOT unit is higher than a preset threshold, the barrier layer of the first SOT unit is broken down, after the breakdown, the first SOT unit is short-circuited, the one-time programmable region is in a programming state, the one-time programmable region has a first resistance value, the on-resistance of the switch unit has a second resistance value, the first resistance value is smaller than the second resistance value, and the one-time programmable region outputs a data state as state 1; applying a voltage V across the first SOT cell SOT is determined by the equation: wherein R HM is the resistance of the first spin orbit torque layer perpendicular to the first SOT cell direction, Rvia is the resistance of the via structure in the first SOT cell, R MOS is the resistance of the switch unit when conducting, R SOT is the resistance of the first SOT cell; a data storage region, comprising a second SOT unit, a reading unit and a writing unit, a first end of the reading unit and a first end of the writing unit being electrically connected with a source line respectively, a second end of the reading unit being electrically connected with a first end of the second SOT unit, a second end of the writing unit being electrically connected with a second end of the second SOT unit, a third end of the second SOT unit being electrically connected with a bit line, the second SOT unit comprising at least one second MTJ and a second spin-orbit torque layer arranged in contact; the second MTJ has a plurality of second ends, the second ends of the plurality of second MTJs being the first end of the second SOT unit, the second end of the second spin-orbit torque layer being the second end of the second SOT unit, the third end of the second spin-orbit torque layer being the third end of the second SOT unit, the first end of the second MTJ being electrically connected with the first end of the second spin-orbit torque layer.

2. The memory chip of claim 1, wherein, the second end of the first MTJ being the first end of the first SOT unit, the second end of the first spin-orbit torque layer being the second end of the first SOT unit, the third end of the first spin-orbit torque layer being the third end of the first SOT unit, the data reading unit being electrically connected with the third end of the first SOT unit, the first end of the first MTJ being electrically connected with the first end of the first spin-orbit torque layer, the second MTJ has one, the second end of the second MTJ being the first end of the second SOT unit, the second end of the second spin-orbit torque layer being the second end of the second SOT unit, the third end of the second spin-orbit torque layer being the third end of the second SOT unit, the first end of the second MTJ being electrically connected with the first end of the second spin-orbit torque layer.

3. The memory chip of claim 1, wherein, The second end of the first spin orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, the data reading unit is electrically connected with the first end of the switch unit, and the first end of the first MTJ is electrically connected with the first end of the first spin orbit moment layer.

4. The memory chip of claim 1, wherein, The second end of the first spin orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, the data reading unit is electrically connected with the first end of the switch unit, and the first end of the first MTJ is electrically connected with the first end of the first spin orbit moment layer.

5. The memory chip of claim 1, wherein, The second end of the first spin orbit moment layer is the first end of the first SOT unit, the second end of the first MTJ is the second end of the first SOT unit, the data reading unit is electrically connected with the first end of the switch unit, and the first end of the first MTJ is electrically connected with the first end of the first spin orbit moment layer.

6. The memory chip of claim 2, wherein, The first SOT unit further comprises a via structure and an insulating dielectric layer, the via structure vertically penetrates the insulating dielectric layer, the insulating dielectric layer is in contact with a surface of the first spin orbit moment layer away from the first MTJ, a first end of the via structure is in contact with the surface of the first spin orbit moment layer away from the first MTJ, a second end of the via structure is the second end of the first SOT unit, and a projection of the via structure on a predetermined plane is located in a structure layer of the first MTJ, the predetermined plane being a plane where the first MTJ is located.

7. The memory chip according to any one of claims 1 to 6, characterized in that, The reading unit comprises at least one reading word line and at least one first transistor, the gate of the first transistor is connected with the reading word line one by one, the source of the first transistor is electrically connected with the source line respectively, and the drain of the first transistor is electrically connected with the second MTJ one by one.

8. The memory chip according to any one of claims 1 to 6, characterized in that, The switch unit is a third transistor, the gate of the third transistor is electrically connected with the word line, the source of the third transistor is electrically connected with the source line, and the drain of the third transistor is electrically connected with the via structure.

9. The memory chip of claim 1, wherein, The first spin-orbit torque layer and the second spin-orbit torque layer are of the same structure, a material of the first spin-orbit torque layer in contact with the first MTJ is a heavy metal material layer, a material of the second spin-orbit torque layer in contact with the second MTJ is a heavy metal material layer, and the heavy metal material layer includes any one of platinum, tantalum, tungsten, iridium, hafnium, ruthenium, thallium, bismuth, gold, titanium, and osmium.

10. The memory chip of claim 1, wherein, The first MTJ includes a first free layer, a first barrier layer, and a first pinned layer stacked in sequence, and the second MTJ includes a second free layer, a second barrier layer, and a second pinned layer stacked in sequence, the first free layer is in contact with the first spin-orbit torque layer, and the second free layer is in contact with the second spin-orbit torque layer.

11. The memory chip of claim 1, wherein, The first MTJ further includes a first top electrode or a first bottom electrode, in a case where the second end of the first MTJ is the first end of the first SOT cell, the first MTJ includes the first top electrode, the first top electrode is electrically connected with a bit line, in a case where the second end of the first MTJ is the second end of the first SOT cell, the first MTJ includes the first bottom electrode, the first bottom electrode is electrically connected with the switch unit, the second MTJ further includes a second top electrode or a second bottom electrode, in a case where the second end of the second MTJ is the first end of the second SOT cell, the second MTJ includes the second top electrode, the second top electrode is electrically connected with the read unit, in a case where the second end of the second MTJ is the second end of the second SOT cell, the second MTJ includes the second bottom electrode, and the second bottom electrode is electrically connected with the write unit.

12. The memory chip of claim 6, wherein, The via structure includes a conductive via and a filling substance, and the filling substance is a low-resistance conductive material.

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