A pipeline instruction allocation method, system, device and medium

Abstract

The application provides a pipeline instruction distribution method, comprising the following steps: calculating the load time of each pipeline, and sorting the pipelines according to the load time, and setting the pipeline priority according to the sorting result; calculating the waiting time of each instruction, and sorting the instructions according to the waiting time, and setting the instruction priority according to the sorting result; and distributing the instructions to the corresponding pipelines according to the instruction priority and the pipeline priority. The pipeline instruction distribution method provided by the application can realize the dynamic balance of the waiting time and the instruction selection range by several simple judgment logics according to the current real-time instruction emission condition and the pipeline load execution condition, and can realize the instruction scheduling in a short time by using as few hardware resources as possible, and complete the load balance in the asymmetric pipeline.

Description

Technical Field

[0001] This invention belongs to the field of computer science, and specifically relates to a pipeline instruction allocation method, system, device, and medium. Background Technology

[0002] Superscalar processors leverage parallelism by increasing the instruction window and fully utilizing computational units. Typically, multiple computational clusters can be configured, each containing computational units with different instruction types. By comprehensively considering instruction characteristics, hardware overhead, and other performance requirements, an appropriate issue strategy can be developed to better utilize the performance of the computational clusters. Software compilation methods for allocation and scheduling are static optimizations and cannot consider real-time runtime information.

[0003] Although the hardware issue unit cannot know the global instruction and register usage information, it can grasp the real-time component usage and instruction load requirements, and provide dynamic instruction load classification and issue scheduling schemes.

[0004] Simple static allocation methods, such as round-robin, are easy to implement but have poor performance. Complex allocation methods consider more factors but incur significant overhead in terms of hardware area and time. One study proposed a greedy allocation strategy for fine-grained automatic allocation of computing resources, which can fully utilize buffers and computing resources to achieve better balance. However, this scheme simply multiplies the selectable range of instructions by the instruction waiting time as a comprehensive index for instruction sorting, without fully considering the characteristics of instructions and arithmetic clusters. Furthermore, the index uses multiplication, consuming logical area and requiring considerable computation time. Additionally, this index is fixed and cannot dynamically change according to the actual execution of instructions, making it inflexible. Summary of the Invention

[0005] To address the above problems, this invention proposes a pipeline instruction allocation method, comprising:

[0006] Calculate the load time for each pipeline, sort the pipelines according to the load time, and set the pipeline priority based on the sorting result;

[0007] Calculate the waiting time for each instruction, sort the instructions according to the waiting time, and set the instruction priority according to the sorting result;

[0008] Instructions are assigned to the corresponding pipelines according to the instruction priority and the pipeline priority.

[0009] In some embodiments of the present invention, the method further includes:

[0010] The pipeline selectable range of the instructions to be allocated is determined based on the arithmetic cluster, and the instructions to be allocated are sorted according to the pipeline selectable range.

[0011] The instructions are assigned to the corresponding pipelines from low to high according to the selectable range of the pipeline.

[0012] In some embodiments of the present invention, the method further includes:

[0013] In response to the fact that the pipeline selectable range of the instructions to be assigned is the same, the instructions are assigned according to the instruction priority and the pipeline priority.

[0014] In some embodiments of the present invention, the method further includes:

[0015] In response to the absence of a selectable pipeline for the instruction to be assigned, no pipeline is assigned.

[0016] In some embodiments of the present invention, the method further includes:

[0017] The system calculates the waiting time of an instruction, and in response to the waiting time exceeding a first predetermined time, allocates the instruction according to pipeline priority.

[0018] In some embodiments of the present invention, calculating the waiting time for the instruction includes:

[0019] A time stamp variable is set for the instruction, the value of the time stamp variable is increased in units of a second predetermined time, and it is determined whether the value of the time stamp variable exceeds the value of a first predetermined time.

[0020] In response to the value of the time stamp variable exceeding the value of the first predetermined time, the instruction is allocated according to pipeline priority.

[0021] In some embodiments of the invention, the method further includes clearing the time stamp variable of the instruction in response to the instruction being executed on the pipeline.

[0022] Another aspect of the present invention provides a pipeline instruction allocation system, comprising:

[0023] A first calculation module is configured to calculate the load time of each pipeline, sort the pipelines according to the load time, and set pipeline priorities according to the sorting results.

[0024] The second calculation module is configured to calculate the waiting time for each instruction, sort the instructions according to the waiting time, and set the instruction priority according to the sorting result.

[0025] The allocation module is configured to allocate instructions to the corresponding pipelines according to the instruction priority and the pipeline priority.

[0026] Another aspect of the present invention provides a computer device comprising:

[0027] At least one processor; and

[0028] A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of any of the methods described in the above embodiments.

[0029] Another aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods described in the above embodiments. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A flowchart of a pipeline instruction allocation method provided in an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a pipeline instruction allocation system provided in an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of a computer-readable storage medium provided in an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0036] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0037] This invention proposes a pipeline instruction allocation method, comprising:

[0038] Step S1: Calculate the load time of each pipeline, sort the pipelines according to the load time, and set the pipeline priority according to the sorting result;

[0039] Step S2: Calculate the waiting time for each instruction, sort the instructions according to the waiting time, and set the instruction priority according to the sorting result;

[0040] Step S3: Assign instructions to the corresponding pipelines according to the instruction priority and the pipeline priority.

[0041] In an embodiment of the present invention, in step S1, the pipeline load time refers to the total time required to execute the instructions allocated to each pipeline. The execution time of an instruction on the pipeline is fixed because, given sufficient computational data, the computational performance is determined by the hardware circuitry on the pipeline. Therefore, in step S1, the execution time of each instruction on each pipeline is determined based on the performance of the computational unit or cluster on that pipeline. Then, the number of instructions allocated to each pipeline is multiplied by the execution time to obtain the load time of each pipeline. The pipelines are then sorted according to their load times. Pipelines with smaller or lower load times are designated as priority pipelines. That is, the pipelines are sorted from low to high priority, with higher priority pipelines listed earlier. In some embodiments, the highest priority pipeline is designated as 0 (in computer science, ordered sequences start from 0), and other pipelines are sorted accordingly.

[0042] In step S2, the instruction wait time refers to the waiting time for each instruction to be executed on the pipeline. The instruction wait time can be calculated in multiple ways, such as according to the order in which the instructions are generated, i.e., in a first-in, first-out manner. Theoretically, the later the instruction arrives, the longer the wait time. The calculation of the instruction wait time is still related to the execution time of the instruction on the pipeline. When calculating the instruction wait time, the load time of each pipeline needs to be taken into account.

[0043] Specifically, assume there are m pipelines, issuing n instructions, with a fixed instruction execution time, and the issue latency of instruction i assigned to pipeline j is w. ij If i cannot be assigned to j, let w ij =max_Lat, there is already an instruction on j that needs to wait for Lat. j Upon successful launch, I(i,j) = 1 indicates that instruction i is assigned to pipeline j, while 0 indicates the opposite. After this round of allocation, the production line needs... Launch complete.

[0044] In some embodiments of the present invention, the waiting time of the computation instruction also includes the delay time of the instruction in the pipeline due to the time for the instruction to fetch data, etc., as the maximum execution time of each instruction in the pipeline. That is, the execution time of each instruction in the pipeline under normal and unobstructed conditions plus the maximum delay time of the pipeline for the instruction (the maximum time for the instruction to fetch data in the pipeline. If this time is exceeded, the pipeline triggers a "flushing" mechanism, that is, if an instruction fails to execute and cannot continue, the entire pipeline is cleared.

[0045] Furthermore, if no delay occurs during instruction execution on the pipeline, the waiting time for subsequent instructions is reduced by one unit of the maximum delay time. If a delay exists but the "flushing" mechanism is not triggered, the waiting time for subsequent unexecuted instructions is reduced by the delay time.

[0046] After calculating the waiting time for each instruction, the instructions are sorted from highest to lowest waiting time. The instruction with the highest waiting time (the unallocated instruction) is assigned as the highest priority instruction, and its sorting priority is also marked as 0.

[0047] In step S3, the instruction that is assigned first after sorting is assigned to the pipeline with the highest priority.

[0048] In some embodiments of the present invention, after allocating one or more instructions to the highest priority pipeline, the load time of the pipeline after the instruction allocation is determined. If the load time is still less than the load time of pipelines with lower priority than the pipelines below it, then the pipeline is still regarded as the highest priority pipeline.

[0049] In some embodiments of the present invention, the method further includes:

[0050] The pipeline selectable range of the instructions to be allocated is determined based on the arithmetic cluster, and the instructions to be allocated are sorted according to the pipeline selectable range.

[0051] The instructions are assigned to the corresponding pipelines from low to high according to the selectable range of the pipeline.

[0052] In this embodiment, when assigning instructions to the corresponding pipeline, the system also determines whether to assign the instruction based on whether the type of the pipeline's arithmetic clusters satisfies the instruction's computation type. Each time an instruction is assigned to a pipeline, the number of instructions that can be assigned to that pipeline is known; that is, the total number of instructions that can be assigned to the current pipeline is known. Instructions are selected in descending order of their latency, representing the pipeline's allowed number of assignments (i.e., the instructions to be assigned). Then, the instructions are reordered based on the pipelines available for selection in this allocation. Selectable pipelines refer to those whose computation type can be satisfied by the arithmetic clusters on the pipeline. In some cases, multiple pipelines may be able to satisfy the execution needs of an instruction; these pipelines are the selectable pipelines for the instruction. Therefore, the instructions to be assigned are sorted in ascending order based on the selectable pipelines, with instructions having a smaller pipeline selection range prioritized for allocation. Instructions with a larger selection range are assigned with lower priority.

[0053] In some embodiments of the present invention, if an instruction cannot be assigned to a pipeline, the waiting time of that instruction includes the maximum waiting time of a pipeline, i.e., when i cannot be assigned to j, let w ij =max_Lat. If an instruction has multiple pipelines that cannot be allocated, its latency will include multiple wait times. ij =max_Lat time.

[0054] In some embodiments of the present invention, the method further includes:

[0055] In response to the fact that the pipeline selectable range of the instructions to be assigned is the same, the instructions are assigned according to the instruction priority and the pipeline priority.

[0056] In this embodiment, if the pipelines of the instructions to be assigned have the same selectable range, or if the operation types of the instructions to be assigned are the same, then the instructions are directly assigned according to the priority of the waiting time corresponding to the instructions to be assigned.

[0057] In some embodiments of the present invention, the method further includes:

[0058] In response to the absence of a selectable pipeline for the instruction to be assigned, no pipeline is assigned.

[0059] In this embodiment, if the operation type of a certain instruction to be allocated is not satisfied by the currently available pipeline, then the instruction will not be processed in this allocation.

[0060] In some embodiments of the present invention, the method further includes:

[0061] The system calculates the waiting time of an instruction, and in response to the waiting time exceeding a first predetermined time, allocates the instruction according to pipeline priority.

[0062] In this embodiment, the waiting time of a computation instruction refers to the time during which the instruction has not been executed after it was generated, or the waiting time of the instruction exceeds the set maximum waiting time because the pipeline for the required operation type is always busy. In this case, the instruction is allocated with priority. As long as there is a selectable pipeline, the allocation is performed directly according to the pipeline priority.

[0063] In some embodiments of the present invention, for an assigned instruction, if the pipeline to which it was assigned becomes inefficient due to significant execution delays or other reasons, causing the instruction to wait for an extended period exceeding the set maximum waiting time, the instruction's assignment is cancelled, it is reassigned as a pending instruction, and reallocated according to the highest priority. This applies when the pipeline's issue buffer queue or list is not a first-in-first-out (FIFO) storage structure and can be modified.

[0064] In some embodiments of the present invention, calculating the waiting time for the instruction includes:

[0065] A time stamp variable is set for the instruction, the value of the time stamp variable is increased in units of a second predetermined time, and it is determined whether the value of the time stamp variable exceeds the value of a first predetermined time.

[0066] In response to the value of the time stamp variable exceeding the value of the first predetermined time, the instruction is allocated according to pipeline priority.

[0067] In this embodiment, a predetermined bit space for a flag is set when each instruction is generated, for example, 4 bits, which can be incremented 16 times, or 8 bits, which can be incremented 256 times, and can be flexibly configured according to the needs of the hardware circuit space. The value of this flag is increased periodically, for example, by a clock cycle or by the number of instruction allocations. Specifically, the value of the time flag variable is increased by 1 (binary) by the clock cycle or by one instruction allocation. When the increased value exceeds the space limit of the time flag variable, for example, the maximum allowed number for a 4-bit time flag is 16, and when the value of the time flag variable is 15, it is considered that a predetermined time has been exceeded. The instruction corresponding to this time flag variable is then designated as the highest priority instruction to be allocated, and the highest priority pipeline is selected for allocation.

[0068] In some embodiments of the invention, the method further includes clearing the time stamp variable of the instruction in response to the instruction being executed on the pipeline.

[0069] In this embodiment, when an instruction is sent to the pipeline for execution, the timestamp variable of that instruction is cleared.

[0070] In some embodiments of the present invention, the arithmetic clusters are configured according to the following principles: arithmetic clusters are classified and configured according to integer, floating point, and memory access; each type of instruction corresponds to only one type of arithmetic unit; the number of units is positively correlated with the frequency of use; and the computing units are configured in a complementary manner according to the length of execution time.

[0071] The transmit delay originates from the arithmetic clusters and arithmetic units. Each arithmetic cluster transmit channel can only transmit one instruction per cycle, corresponding to one cycle transmit delay. Furthermore, the arithmetic unit must complete its current instruction and be idle before it can execute a new instruction, corresponding to the arithmetic unit transmit delay.

[0072] Each arithmetic cluster corresponds to several instruction types using the same arithmetic unit, and also to an issue buffer. Decoded and renamed instructions are placed in the wait buffer. Under the condition that the hardware design is completed, the types and number of instructions issued per cycle are fixed. The conditions for instruction issuance and execution are that the operands are ready, the arithmetic cluster is idle, and the computing unit is idle.

[0073] After an instruction is issued, the arithmetic cluster and computation unit become busy; in the next clock cycle, the arithmetic cluster becomes free, and the computation unit becomes free after execution. Therefore, operand dependency, the range of arithmetic clusters that can be selected by the instruction, and instruction latency affect the execution state.

[0074] Assume there are m pipelines, issuing n instructions, with a fixed instruction execution time. The issue latency of instruction i assigned to pipeline j is w. ij If i cannot be assigned to j, let w ij =max_Lat, there is already an instruction on j that needs to wait for Lat. j Upon successful launch, I(i,j) = 1 indicates that instruction i is assigned to pipeline j, while 0 indicates the opposite. After this round of allocation, the production line needs... Launch complete.

[0075] The effectiveness of load balancing is represented by variance:

[0076]

[0077] in,

[0078] The equilibrium objective is to find the pipeline allocation strategy I(i,j) corresponding to each instruction i under the condition of minimizing the variance Var.

[0079] This nonlinear programming problem can be solved using an ergonomic approach, but this is time-consuming and cannot be implemented in hardware. For the processor, all known states are the decoded and allocated n instructions. A greedy approach that finds local optima can be used, where a series of local optima ensure that the system finds a globally relatively optimal solution as quickly as possible.

[0080] For instruction i, all computational pipeline loads Initial load

[0081] A symmetric greedy algorithm is used to find the pipeline j allocated to the i-th instruction, satisfying the objective min j＝0,…,m-1 Var ij Assume the optimal solution for the current j is k. i If there are multiple solutions, they are allocated in rotation.

[0082] at this time,

[0083] Average pipeline load after assigning instruction i

[0084] variance

[0085] but

[0086] In asymmetric scenarios, instruction issuance latency varies across different pipelines. However, according to the arithmetic cluster configuration principle—arithmetic clusters are categorized by integer, floating-point, and memory access, and each instruction type corresponds to only one arithmetic unit—each instruction h, in addition to the latency w allocated to the pipeline l' that does not have its arithmetic unit, also experiences latency. hl’ =max_Lat, where the number of pipelines l (l≠l') that can be allocated have the same waiting time, denoted as w. hl = h Assume that instruction h can be allocated to a finite number of pipelines l, namely p.

[0087] Because, when scheduling instructions h and i, Lat h w hl Lat i w ij All of them are known constants.

[0088]

[0089] Where C is a constant.

[0090] In a symmetrical pipeline, instruction i selects L in the corresponding pipeline. i-1,j The smallest pipeline is k i The variance is minimized, and because L ijIt increases with increasing i, so the load of different instructions... It also increases as i increases. To achieve Var n Minimize, and combine different instructions w i Sort from largest to smallest, and take each instruction... This allows the allocation strategy to be determined.

[0091] In asymmetric pipelines, some literature directly incorporates the instruction issue latency and pipeline selection range into the construction of the sorting key, using w h (m+1-p) is used as the key to sort instructions by size. However, simple multiplication cannot accurately reflect the rationality of the weight between the launch latency and the selection range, nor can it be dynamically adjusted according to the operating conditions, which has great limitations.

[0092] The pipeline instruction allocation method proposed in this paper uses a few simple judgment logics to achieve dynamic balance between the launch waiting time and the instruction selection range based on the current real-time instruction issuance status and pipeline load execution status. It achieves instruction scheduling in a short time with minimal hardware resources, thus completing load balancing in asymmetric pipelines.

[0093] Another aspect of the present invention provides a pipeline instruction allocation system, comprising:

[0094] A first calculation module is configured to calculate the load time of each pipeline, sort the pipelines according to the load time, and set pipeline priorities according to the sorting results.

[0095] The second calculation module is configured to calculate the waiting time for each instruction, sort the instructions according to the waiting time, and set the instruction priority according to the sorting result.

[0096] The allocation module is configured to allocate instructions to the corresponding pipelines according to the instruction priority and the pipeline priority.

[0097] Another aspect of the present invention provides a computer device comprising:

[0098] At least one processor; and

[0099] A memory storing computer instructions executable on the processor, the instructions, when executed by the processor, implementing a pipelined instruction allocation method, including:

[0100] Calculate the load time for each pipeline, sort the pipelines according to the load time, and set the pipeline priority based on the sorting result;

[0101] Calculate the waiting time for each instruction, sort the instructions according to the waiting time, and set the instruction priority according to the sorting result;

[0102] Instructions are assigned to the corresponding pipelines according to the instruction priority and the pipeline priority.

[0103] In some embodiments of the present invention, the method further includes:

[0104] The pipeline selectable range of the instructions to be allocated is determined based on the arithmetic cluster, and the instructions to be allocated are sorted according to the pipeline selectable range.

[0105] The instructions are assigned to the corresponding pipelines from low to high according to the selectable range of the pipeline.

[0106] In some embodiments of the present invention, the method further includes:

[0107] In response to the fact that the pipeline selectable range of the instructions to be assigned is the same, the instructions are assigned according to the instruction priority and the pipeline priority.

[0108] In some embodiments of the present invention, the method further includes:

[0109] In response to the absence of a selectable pipeline for the instruction to be assigned, no pipeline is assigned.

[0110] In some embodiments of the present invention, the method further includes:

[0111] The system calculates the waiting time of an instruction, and in response to the waiting time exceeding a first predetermined time, allocates the instruction according to pipeline priority.

[0112] In some embodiments of the present invention, calculating the waiting time for the instruction includes:

[0113] A time stamp variable is set for the instruction, the value of the time stamp variable is increased in units of a second predetermined time, and it is determined whether the value of the time stamp variable exceeds the value of a first predetermined time.

[0114] In response to the value of the time stamp variable exceeding the value of the first predetermined time, the instruction is allocated according to pipeline priority.

[0115] In some embodiments of the invention, the method further includes clearing a timestamp variable of the instruction in response to pipeline execution of the instruction. Another aspect of the invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements...

[0116] A pipeline instruction allocation method includes:

[0117] Calculate the load time for each pipeline, sort the pipelines according to the load time, and set the pipeline priority based on the sorting result;

[0118] Calculate the waiting time for each instruction, sort the instructions according to the waiting time, and set the instruction priority according to the sorting result;

[0119] Instructions are assigned to the corresponding pipelines according to the instruction priority and the pipeline priority.

[0120] In some embodiments of the present invention, the method further includes:

[0121] The pipeline selectable range of the instructions to be allocated is determined based on the arithmetic cluster, and the instructions to be allocated are sorted according to the pipeline selectable range.

[0122] The instructions are assigned to the corresponding pipelines from low to high according to the selectable range of the pipeline.

[0123] In some embodiments of the present invention, the method further includes:

[0124] In response to the fact that the pipeline selectable range of the instructions to be assigned is the same, the instructions are assigned according to the instruction priority and the pipeline priority.

[0125] In some embodiments of the present invention, the method further includes:

[0126] In response to the absence of a selectable pipeline for the instruction to be assigned, no pipeline is assigned.

[0127] In some embodiments of the present invention, the method further includes:

[0128] The system calculates the waiting time of an instruction, and in response to the waiting time exceeding a first predetermined time, allocates the instruction according to pipeline priority.

[0129] In some embodiments of the present invention, calculating the waiting time for the instruction includes:

[0130] A time stamp variable is set for the instruction, the value of the time stamp variable is increased in units of a second predetermined time, and it is determined whether the value of the time stamp variable exceeds the value of a first predetermined time.

[0131] In response to the value of the time stamp variable exceeding the value of the first predetermined time, the instruction is allocated according to pipeline priority.

[0132] In some embodiments of the invention, the method further includes clearing the time stamp variable of the instruction in response to the instruction being executed on the pipeline.

[0133] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The embodiments of the computer program can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0134] Furthermore, typically, the devices and equipment disclosed in the embodiments of this invention can be various electronic terminal devices, such as mobile phones, personal digital assistants (PDAs), tablet computers (PADs), smart TVs, etc., or they can be large terminal devices, such as servers. Therefore, the scope of protection disclosed in the embodiments of this invention should not be limited to a specific type of device or equipment. The client disclosed in the embodiments of this invention can be applied to any of the above-mentioned electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.

[0135] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0136] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0137] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM may be available in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0138] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of the various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0139] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0140] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0141] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0142] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of the different aspects of the invention as described above exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A pipeline instruction allocation method, characterized in that, include: Calculate the load time of each pipeline, sort the pipelines according to the load time, set pipeline priorities according to the sorting results, and set pipelines with smaller or lower load times as priority pipelines. Calculate the waiting time for each instruction, sort the instructions according to the waiting time, set the instruction priority according to the sorting result, and sort the waiting time of the instructions from high to low. Instructions are assigned to the corresponding pipelines according to the instruction priority and the pipeline priority. The pipeline selectable range of the instructions to be allocated is determined based on the arithmetic cluster, and the instructions to be allocated are sorted according to the pipeline selectable range. The instructions to be assigned are distributed to the corresponding pipelines in ascending order of the pipeline selectability range, with instructions with a smaller pipeline selectability range being given priority for assignment.

2. The method according to claim 1, characterized in that, Also includes: In response to the fact that the pipeline selectable range of the instructions to be assigned is the same, the instructions to be assigned are assigned according to the instruction priority and the pipeline priority.

3. The method according to claim 1, characterized in that, Also includes: In response to the absence of a selectable pipeline for the instruction to be assigned, the instruction to be assigned is not assigned.

4. The method according to claim 1, characterized in that, Also includes: The system calculates the waiting time of an instruction, and in response to the waiting time exceeding a first predetermined time, allocates the instruction according to pipeline priority.

5. The method according to claim 4, characterized in that, The calculation of the waiting time for the instruction includes: A time stamp variable is set for the instruction, the value of the time stamp variable is increased in units of a second predetermined time, and it is determined whether the value of the time stamp variable exceeds the value of a first predetermined time. In response to the value of the time stamp variable exceeding the value of the first predetermined time, the instruction is allocated according to pipeline priority.

6. The method according to claim 5, characterized in that, In response to the instruction being executed on the pipeline, the time stamp variable of the instruction is cleared.

7. A pipeline instruction allocation system, characterized in that, include: The first calculation module is configured to calculate the load time of each pipeline, sort the pipelines according to the load time, set pipeline priority according to the sorting result, and set pipelines with small or low load times as priority pipelines. The second calculation module is configured to calculate the waiting time of each instruction, sort the instructions according to the waiting time, set the instruction priority according to the sorting result, and sort the waiting time of the instructions from high to low. An allocation module is configured to allocate instructions to corresponding pipelines according to the instruction priority and the pipeline priority. And modules for performing the following functions: The pipeline selectable range of the instructions to be allocated is determined based on the arithmetic cluster, and the instructions to be allocated are sorted according to the pipeline selectable range. The instructions to be assigned are distributed to the corresponding pipelines in ascending order of the pipeline selectability range, with instructions with a smaller pipeline selectability range being given priority for assignment.

8. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-6.

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