Automatic bi-directional conversion method and device for instruction set in heterogeneous multi-core project

Abstract

The application relates to an automatic bidirectional conversion method and device for an instruction set in a heterogeneous multi-core project, computer equipment and a storage medium. The method comprises the following steps: obtaining an operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one core in the heterogeneous multi-core project; using a compiler to compile the operation instruction to be converted to obtain machine code corresponding to the operation instruction; using a decoder to analyze the machine code to obtain an instruction type and an operand; scheduling the instruction type and the operand to an instruction set execution library different from the core where the operation instruction is located to perform matching to obtain machine code after instruction conversion; and performing disassembly on the machine code after instruction exchange to obtain converted instructions. The method can improve verification incentive efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an automatic bidirectional conversion method and device for instruction sets in a heterogeneous multi-core project, a computer device and a storage medium. BACKGROUND

[0002] With the continuous promotion of heterogeneous multi-core projects in integrated circuits, in the process of application development, different types of instructions commonly used by R&D and verification personnel include DSP, ARM, etc. More often, different instruction formats exist on different versions of each type of instruction. These problems will bring obstacles to the writing of test stimuli by verification personnel in the development process of heterogeneous multi-core projects.

[0003] In the development process of heterogeneous multi-core projects, when writing verification stimuli for different cores, the use of different instruction sets requires R&D and verification personnel to be proficient in using multiple instruction sets, or to learn related functions by searching and consulting various instruction set documents each time other instructions are used. However, due to the large difference in instruction formats supported by different cores, and the difficulty in quickly understanding due to habit problems when learning two types of instructions. For example, in the DSP 66x instruction set, the instruction format for reading data to a fixed address is LDW*A3, A4, which means reading data from the A3 address and placing it in A4. However, the instruction format for performing this task in the ARM v5 instruction set is LDR R4, [R3]. From the two instruction formats, the most intuitive feeling is that the positions of the address and data are obviously opposite. However, for an engineer who has been proficient in using DSP instructions for a long time, it is difficult to accept the change in habit when suddenly learning ARM instructions. Therefore, this greatly increases the development difficulty of R&D and verification personnel, increases the time and labor cost in the verification process, and reduces the efficiency of verification stimuli. SUMMARY

[0004] Therefore, it is necessary to provide an automatic bidirectional conversion method, device, computer device and storage medium for instruction sets in a heterogeneous multi-core project, which can improve the efficiency of verification stimuli.

[0005] An automatic bidirectional conversion method for instruction sets in a heterogeneous multi-core project, the method comprising:

[0006] Obtaining an operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one core in the heterogeneous multi-core project;

[0007] Compiling the operation instruction to be converted by using a compiler to obtain machine code corresponding to the operation instruction;

[0008] Analyzing the machine code by using a decoder to obtain an instruction type and an operand;

[0009] scheduling the instruction type and the operand to an instruction set execution library different from the core where the operation instruction is located to match, to obtain the machine code after the instruction conversion;

[0010] disassembling the machine code after the instruction exchange to obtain the converted instruction.

[0011] In one of the embodiments, the method further comprises: constructing the instruction execution library in advance according to the requirement of the instruction set conversion; the instruction execution library comprises an instruction type library and a condition code library.

[0012] In one of the embodiments, the operand comprises a source register and a destination register.

[0013] scheduling the instruction type and the operand to an instruction set execution library different from the core where the operation instruction is located to match, to obtain the machine code after the instruction conversion, comprising:

[0014] scheduling the instruction type, the source register and the destination register to an instruction set execution library different from the core where the operation instruction is located, and finding the machine code corresponding to the meaning in the instruction set execution library according to the meaning of the instruction type, the source register and the destination register, to obtain the machine code after the instruction conversion.

[0015] In one of the embodiments, the machine code after the instruction conversion further comprises a condition code.

[0016] In one of the embodiments, the heterogeneous multi-core project represents a multi-core heterogeneous project using different instruction sets in the IC verification stage of the integrated circuit chip development process.

[0017] An automatic bidirectional conversion device for instruction sets in a heterogeneous multi-core project, the device comprising:

[0018] a receiving operation instruction module for obtaining an operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one of the cores in the heterogeneous multi-core project;

[0019] a compiling and parsing module for compiling the operation instruction to be converted by using a compiler to obtain the machine code corresponding to the operation instruction, and parsing the machine code by using a decoder to obtain an instruction type and an operand;

[0020] a bidirectional conversion module for scheduling the instruction type and the operand to an instruction set execution library different from the core where the operation instruction is located to match, to obtain the machine code after the instruction conversion; and disassembling the machine code after the instruction exchange to obtain the converted instruction.

[0021] A computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0022] An operation instruction to be converted is acquired, and the operation instruction to be converted is an operation instruction supported by any one of the cores in the heterogeneous multi-core project;

[0023] The operation instruction to be converted is compiled by using a compiler to obtain machine code corresponding to the operation instruction;

[0024] The machine code is parsed by using a decoder to obtain an instruction type and an operand;

[0025] The instruction type and the operand are dispatched to an instruction set execution library different from the core where the operation instruction is located to be matched, and machine code after instruction conversion is obtained;

[0026] The machine code after instruction exchange is disassembled to obtain converted instructions.

[0027] A computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0028] An operation instruction to be converted is acquired, and the operation instruction to be converted is an operation instruction supported by any one of the cores in the heterogeneous multi-core project;

[0029] The operation instruction to be converted is compiled by using a compiler to obtain machine code corresponding to the operation instruction;

[0030] The machine code is parsed by using a decoder to obtain an instruction type and an operand;

[0031] The instruction type and the operand are dispatched to an instruction set execution library different from the core where the operation instruction is located to be matched, and machine code after instruction conversion is obtained;

[0032] The machine code after instruction exchange is disassembled to obtain converted instructions.

[0033] The automatic bidirectional conversion method, device, computer equipment and storage medium for the instruction set in the heterogeneous multi-core project have the advantages that the operation instruction to be converted is compiled into machine code, the machine code is then parsed, the instruction type and the operand of the machine code are analyzed, the instruction type and the operand are dispatched to the instruction set execution library different from the kernel where the operation instruction is located for matching, the machine code after the instruction conversion is obtained, the converted instruction is obtained through disassembly, the accurate matching of various different instruction sets is realized by extracting the instruction type and the operand, the dynamic switching between different instruction sets is realized through the rapid dispatching of the instruction parameters, the automatic translation is realized, the reuse of the verification excitation in different instruction sets is realized, and the efficiency of the verification excitation is improved. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 An application scenario diagram of an embodiment of the automatic bidirectional conversion method for the instruction set in the heterogeneous multi-core project is shown in the figure.

[0035] Figure 2 A structure block diagram of an embodiment of the automatic bidirectional conversion device for the instruction set in the heterogeneous multi-core project is shown in the figure.

[0036] Figure 3 An internal structure diagram of the computer equipment in an embodiment is shown in the figure. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0038] In an embodiment, as shown in Figure 1 An automatic bidirectional conversion method for the instruction set in the heterogeneous multi-core project is provided, including the following steps:

[0039] Step 102, obtaining an operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one of the kernels in the heterogeneous multi-core project.

[0040] In the heterogeneous multi-core project, due to the differences in the kernel structure, the instruction formats of the instruction sets supported by different kernels also have many differences.

[0041] Step 104, using a compiler to compile the operation instruction to be converted to obtain the machine code corresponding to the operation instruction; using a decoder to parse the machine code to obtain the instruction type and the operand.

[0042] Step 106: Schedule the instruction type and operands to an instruction set execution library that is different from the kernel where the operation instruction is located for matching, and obtain the machine code after instruction conversion; disassemble the machine code after instruction exchange to obtain the converted instruction.

[0043] The process involves compiling operation instructions into machine code, parsing the machine code to obtain the instruction type and operands corresponding to the operation instructions, and defining the source register, destination register, addressing mode, and offset. The meaning of the instruction type and operands is then determined; for example, an instruction type of LDW means reading data. The process then involves finding the instruction type and operands of another instruction set in a different kernel's execution library, performing parameter matching to obtain the machine code of that instruction set, and finally disassembling it to obtain the converted instructions.

[0044] In the aforementioned automatic bidirectional instruction set conversion method for heterogeneous multi-core projects, this invention compiles the operation instructions to be converted into machine code, then parses the machine code to analyze its instruction type and operands, schedules the instruction type and operands to an instruction set execution library different from the kernel where the operation instructions reside for matching, obtains the machine code after instruction conversion, and then disassembles it to obtain the converted instructions. By extracting the instruction type and operands, accurate matching of multiple different instruction sets is achieved. Dynamic switching between different instruction sets is achieved through rapid scheduling of instruction parameters. Automatic translation enables the reuse of verification stimuli in different instruction sets, thereby improving the efficiency of verification stimuli.

[0045] In one embodiment, the method further includes: pre-constructing an instruction execution library according to the requirements of instruction set conversion; the instruction execution library includes an instruction type library and a condition code library.

[0046] The instruction execution library needs to be built in advance according to the requirements of instruction set conversion. Instruction type libraries and condition code libraries should be built separately according to the required important parameters. Important parameters refer to the source operand, destination operand, instruction type, and condition code. The principle for building the library is to cover basic operation instructions. When parameter information such as the instruction type 011001 of a DSP instruction is obtained, the instruction type of the current ARM instruction can be determined by comparing it with the called library. Then, the obtained ARM instruction parameter information is integrated to obtain the correct machine code.

[0047] In one embodiment, the operands include a source register and a destination register;

[0048] The instruction type and operands are scheduled to an instruction set execution library different from the kernel where the operation instruction is located for matching, resulting in the machine code after instruction translation, including:

[0049] The instruction type, the source register and the destination register are dispatched to an instruction set execution library different from the kernel where the operation instruction is located, and the machine code corresponding to the meaning of the instruction type, the source register and the destination register is found in the instruction set execution library according to the meaning of the instruction type, the source register and the destination register, and the converted machine code is the machine code of the instruction.

[0050] In one of the embodiments, the converted machine code of the instruction further comprises a condition code.

[0051] Taking the conversion from the DSP instruction set to the ARM instruction set as an example:

[0052] Compilation: the machine code corresponding to the DSP instruction LDW *A3, A4 is 0x020C0264, which indicates that the binary is 'b0000_0010_0000_1100_0000_0010_0110_0100

[0053] The machine code corresponding to the ARM instruction LDR R4, [R3] is 0xE5934000, which indicates that the binary is 'b1110_0101_1001_0011_0100_0000_0000_0000

[0054] Analysis:

[0055] DSP instruction:

[0056] [7:2]011001, indicating the instruction type, which is currently LDW, word read (other bytes, half words, double words have different instruction codes)

[0057] [17:8]0000000010, indicating the offset and addressing mode, whether to increment, etc. The current is register address increment addressing, and the offset is 0

[0058] [22:18]00011, SRC source register, register is 3

[0059] [27:23]00100, DST destination register, register is 4

[0060] [31:28]0000, condition code

[0061] ARM instruction:

[0062] [11:0]00000000000, indicating the addressing mode and offset, which currently indicates that no offset addressing is needed, and the increment is 0

[0063] [15:12]0100, DST destination register, register is 4

[0064] [19:16]0011, SRC source register, register is 3

[0065] [27:20] 01011001, instruction type, word read

[0066] [31:28] 1110, condition code, unconditional execution

[0067] Matching: in the current case, the instruction type is word read, the source register is 3, the destination register is 4, and no offset addressing is required. Therefore, we can match the parameters according to the parameters, put the parameters of the ARM instruction into the corresponding position, and obtain the converted instruction through disassembly.

[0068] According to the above analysis, the characteristic parameters attached in the machine code are the source register, the destination register, and the instruction type. According to the matching in the two instruction sets, a new instruction execution code can be generated. By adding the condition code, the correctness of the instruction translation is increased. The verifier only needs to master one instruction set to conveniently verify the processors of the DSP and ARM two architectures. The two instruction sets can be directly converted, which greatly improves the efficiency of the verification personnel and reduces the time overhead of the third-party tool.

[0069] In one embodiment, the heterogeneous multi-core project represents a multi-core heterogeneous project using different instruction sets in the IC verification stage of the integrated circuit chip development process.

[0070] It should be understood that, although Figure 1 the steps in the flowchart of the method are shown in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified in this article, the execution of these steps has no strict sequence restriction, and these steps can be executed in other orders. Moreover, Figure 1 at least part of the steps in the method can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0071] In one embodiment, as shown in Figure 2 , an automatic bidirectional conversion device for instruction sets in a heterogeneous multi-core project is provided, comprising: a receiving operation instruction module 202, a compilation and analysis module 204, and a bidirectional conversion module 206, wherein:

[0072] The receiving operation instruction module 202 is used to obtain the operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one core in the heterogeneous multi-core project;

[0073] The compiling and parsing module 204 is configured to compile the operation instruction to be converted by using a compiler to obtain machine code corresponding to the operation instruction; and parse the machine code by using a decoder to obtain an instruction type and an operand;

[0074] The bidirectional conversion module 206 is configured to schedule the instruction type and the operand to an instruction set execution library different from a kernel where the operation instruction is located to perform matching to obtain machine code after conversion of the instruction; and deassemble the machine code after exchange of the instruction to obtain a converted instruction.

[0075] In one of the embodiments, the method further includes: constructing an instruction execution library in advance according to a requirement of instruction set conversion; and the instruction execution library includes an instruction type library and a condition code library.

[0076] In one of the embodiments, the operand includes a source register and a destination register.

[0077] The bidirectional conversion module 206 is further configured to schedule the instruction type and the operand to an instruction set execution library different from a kernel where the operation instruction is located to perform matching to obtain machine code after conversion of the instruction, and includes:

[0078] The instruction type, the source register and the destination register are scheduled to an instruction set execution library different from a kernel where the operation instruction is located, and machine code corresponding to the meaning of the instruction type, the source register and the destination register is found in the instruction set execution library to obtain machine code after conversion of the instruction.

[0079] In one of the embodiments, the machine code after conversion of the instruction further includes a condition code.

[0080] In one of the embodiments, the heterogeneous multi-core project represents a multi-core heterogeneous project using different instruction sets in an IC verification stage of an integrated circuit chip research and development process.

[0081] For specific limitations of the apparatus for automatic bidirectional conversion of instruction sets in a heterogeneous multi-core project, refer to the limitations of the method for automatic bidirectional conversion of instruction sets in a heterogeneous multi-core project, which will not be repeated here. Each module in the apparatus for automatic bidirectional conversion of instruction sets in a heterogeneous multi-core project can be realized by software, hardware and a combination thereof, in whole or in part. Each module can be embedded in or independent of a processor in a computer device in a hardware form, or can be stored in a memory in a computer device in a software form, so as to be called and executed by a processor to perform operations corresponding to each module.

[0082] In one embodiment, a computer device is provided, which can be a terminal, and an internal structure diagram of the computer device can be as shown in Figure 3As shown in the figure. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is used to communicate with the external terminal through the network connection. The computer program is executed by the processor to implement a kind of automatic bidirectional conversion method for instruction set in heterogeneous multi-core project. The display screen of the computer device can be liquid crystal display screen or electronic ink display screen, the input device of the computer device can be the touch layer covered on the display screen, also can be the key, trackball or touchpad arranged on the shell of computer device, also can be external keyboard, touchpad or mouse etc.

[0083] Those skilled in the art can understand that, Figure 3 The skilled in the art can understand that,

[0084] In one embodiment, a computer device is provided, comprising a memory and a processor, the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in the above embodiments.

[0085] In one embodiment, a computer storage medium is provided, which stores a computer program, and the computer program is executed by the processor to implement the steps of the method in the above embodiments.

[0086] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0087] The technical features of the above embodiments can be combined in any way. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0088] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent protection of the present application should be subject to the appended claims.

Claims

1. A method for automatic bi-directional conversion of instruction sets in a heterogeneous multi-core project, characterized in that, The method comprises: acquiring an operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one core in a heterogeneous multi-core project; the operation instruction is a DSP instruction or an ARM instruction; compiling the operation instruction to be converted by using a compiler to obtain machine code corresponding to the operation instruction; a flag parameter attached in the machine code is a source register, a destination register, and an instruction type; analyzing the machine code by using a decoder to obtain an instruction type and an operand; the operand includes the source register and the destination register; scheduling the instruction type, the source register, and the destination register to an instruction set execution library different from a core where the operation instruction is located, finding machine code corresponding to a meaning of the instruction type, the source register, and the destination register in the instruction set execution library as machine code after instruction conversion according to the meaning; and disassembling the machine code after instruction conversion to obtain a converted instruction.

2. The method of claim 1, wherein, The method further comprises: pre-constructing an instruction execution library according to a requirement of instruction set conversion; the instruction execution library includes an instruction type library and a condition code library.

3. The method of claim 1, wherein, The machine code after instruction conversion further includes a condition code.

4. The method of claim 3, wherein, The heterogeneous multi-core project indicates a multi-core heterogeneous project using different instruction sets in an IC verification stage in a process of researching and developing an integrated circuit chip.

5. An apparatus for automatic bi-directional conversion of instruction sets in a heterogeneous multi-core project, characterized in that, The apparatus comprises: a receiving operation instruction module configured to acquire an operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one core in a heterogeneous multi-core project; the operation instruction is a DSP instruction or an ARM instruction; a compiling and analyzing module configured to compile the operation instruction to be converted by using a compiler to obtain machine code corresponding to the operation instruction, and analyze the machine code by using a decoder to obtain an instruction type and an operand; a flag parameter attached in the machine code is a source register, a destination register, and an instruction type; the operand includes the source register and the destination register; a bidirectional conversion module configured to schedule the instruction type, the source register, and the destination register to an instruction set execution library different from a core where the operation instruction is located, find machine code corresponding to a meaning of the instruction type, the source register, and the destination register in the instruction set execution library as machine code after instruction conversion according to the meaning, and disassemble the machine code after instruction conversion to obtain a converted instruction. 6.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-5 when the computer program is executed by the processor. The processor executes the computer program to implement steps of the method in any one of claims 1 to 4.

7. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement steps of the method in any one of claims 1 to 4.

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