Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method comprising: providing a substrate, forming a plurality of active layers and a plurality of sacrificial layers on the substrate, the active layers and the sacrificial layers being arranged alternately; two adjacent active layers constituting an active group; the active layers in the active group having a first interval, adjacent active groups having a second interval, the first interval being greater than the second interval; forming an isolation layer, the isolation layer penetrating all the active layers and all the sacrificial layers, and each active layer being divided into a plurality of active structures; removing the isolation layer and the sacrificial layer in a word line region; forming a first dielectric layer in the word line region, the first dielectric layer covering the surface of the active layer and also being located between the active structures in the same layer and between the active groups; forming a word line in the word line region, the word line being located between the active layers in the active group, and each word line crossing the active structures in the same layer. The embodiment of the present disclosure can at least improve the performance of the semiconductor structure.

Claims

1. A method for manufacturing a semiconductor structure, said semiconductor structure comprising bit line regions, word line regions, and capacitor regions arranged sequentially in a first direction, characterized in that, The manufacturing method includes: A substrate is provided, on which multiple active layers and multiple sacrificial layers are formed, the active layers and the sacrificial layers being alternately arranged; two adjacent active layers constitute an active group; the active layers within the active group have a first spacing, and adjacent active groups have a second spacing, the first spacing being greater than the second spacing; Multiple isolation layers are formed, each of which penetrates all active layers and all sacrificial layers, dividing each active layer into multiple active structures, and the isolation layers extend along the first direction; Remove the isolation layer and the sacrificial layer located in the word line region; A first dielectric layer is formed in the word line area. The first dielectric layer covers the surface of the active layer and is also located between adjacent active structures in the same layer and between adjacent active groups. Multiple word lines are formed in the word line area, the word lines are located between the active layers in the active group, and each word line spans multiple active structures located in the same layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The ratio of the first spacing to the second spacing is 1.8 to 3.5; The ratio of the second spacing to the width of the isolation layer is 0.8 to 1.

2.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The first spacing is 15nm~30nm; the second spacing is 8nm~14nm.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: An insulating layer is formed on the sidewall of the word line area near the capacitor area; The sacrificial layer located in the capacitor region is removed to expose the insulating layer, and the active structure, the isolation layer, and the insulating layer formed in the same active group surround a capacitor aperture; A lower electrode is formed on the inner wall of the capacitor hole, and a filling layer is formed between adjacent active groups; A capacitor dielectric layer is formed on the surface of the lower electrode; An upper electrode is formed on the surface of the capacitor dielectric layer, and the upper electrodes located at different capacitor holes are interconnected.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The steps of forming the lower electrode and the filling layer include: An initial lower electrode is formed in the capacitor region. The initial lower electrode is located on the surface of the active structure, the surface of the insulating layer, and the surface of the isolation layer, and fills the space between adjacent active groups. The active structure located in the capacitor region has an end face away from the word line region, and the initial lower electrode located on the end face is removed; the initial lower electrode filled between adjacent active groups serves as a filler layer, and the initial lower electrode located in the capacitor hole serves as the lower electrode.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, Removing the initial lower electrode located on the end face includes: A capacitor protection layer is filled into the capacitor hole, the capacitor protection layer covering the initial lower electrode located on the inner wall and exposing the initial lower electrode located on the end face; The initial lower electrode located on the end face is removed using a wet etching process; Remove the capacitor protection layer.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a step region, which is located in a second direction of the word line region and connected to the word line region; the second direction is perpendicular to the first direction. The active layer and the sacrificial layer are also located in the step region; The process of removing the isolation layer and the sacrificial layer located in the word line area also includes: removing the sacrificial layer located in the step area; The first dielectric layer and the word line are also located in the stepped region; After the word line is formed, the step area is graphically processed to form multiple steps; the active layer, the first dielectric layer, and the word line within the same active group are used to constitute the steps; in the direction from the word line area to the step area, the height of the multiple steps decreases sequentially. Multiple connecting columns are formed, each corresponding to one of the steps and connected to one of the letter lines.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes an initial step region, which is located in a second direction of the bit line region, the word line region, and the capacitor region; Before forming the steps, the process further includes: graphically processing the initial step area to form the step area.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, Forming multiple of the connecting posts includes: A filling medium layer is formed, the filling medium layer covering the steps in the step region; Multiple through holes are formed in the filling medium layer, and the multiple through holes correspond one-to-one with the steps. The through holes also penetrate the active structure and the first medium layer located at the upper part of the steps, and expose the upper surface of the word lines. A connecting post is formed to fill the through hole.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, After the step is formed, and before the filling medium layer is formed, the method further includes: A protective layer is formed covering the surface of the step; The through-hole also penetrates the protective layer.

11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After the first dielectric layer is formed, the method further includes: A second dielectric layer is formed, which covers the surface of the first dielectric layer and is located between the first dielectric layer and the word line; The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer.

12. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After the isolation layer is formed, the method further includes: Remove the sacrificial layer located in the bit line region; A bit line conductive layer is formed in the bit line region. The bit line conductive layer is located between active structures in the same active group and between adjacent active groups, and also between adjacent isolation layers. Multiple spaced bit lines are formed in the bit line region. The bit lines extend perpendicularly to the surface of the substrate, and the bit lines are connected to the end face of the active structure located in the bit line region away from the word line region.

13. A semiconductor structure, characterized in that, The semiconductor structure includes a bit line region, a word line region, and a capacitor region arranged sequentially in a first direction, and the semiconductor structure further includes: Base; The substrate of the bit line region, the word line region, and the capacitor region has multiple active layers spaced apart. Two adjacent active layers form an active group. The active layers within the active group have a first spacing, and adjacent active groups have a second spacing. The first spacing is greater than the second spacing. Multiple isolation layers, each of which penetrates all of the active layers, dividing each of the active layers into multiple active structures, the isolation layers extending along the first direction; A first dielectric layer covers the surface of the active layer and is also located between adjacent active structures in the same layer and between adjacent active groups. Word lines, wherein the word lines are located between adjacent active layers within the active group, and each word line spans multiple active structures located on the same layer.

14. The semiconductor structure according to claim 13, characterized in that, Also includes: An insulating layer is located on the sidewall of the word line area near the capacitor area; The active structure, the isolation layer, and the insulating layer formed by the same active group enclose a capacitor aperture; The lower electrode is located on the inner wall of the capacitor hole; A capacitor dielectric layer is located on the surface of the lower electrode; The upper electrode is located on the surface of the capacitor dielectric layer, and the upper electrodes located at different capacitor holes are interconnected. The lower electrode, the capacitor dielectric layer, and the upper electrode constitute a capacitor; A filling layer is located between adjacent active groups and also between adjacent isolation layers.

15. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure further includes a step region, which is located in a second direction of the word line region and connected to the word line region; the second direction is perpendicular to the first direction. The active layer, the first dielectric layer, and the word line are also located in the step region; The step area has multiple steps, and the active layer, the first dielectric layer and the word line in the same active group are used to form the steps; in the direction from the word line area to the step area, the height of the multiple steps decreases sequentially. The connecting column corresponds one-to-one with the step and is connected one-to-one with the letter line.

Images